sbin/fsck_hammer2: Allow -l to take multiple PFS names
[dragonfly.git] / sys / kern / kern_intr.c
CommitLineData
984263bc 1/*
033a4603 2 * Copyright (c) 2003 Matthew Dillon <dillon@backplane.com> All rights reserved.
ef0fdad1 3 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> All rights reserved.
984263bc
MD
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/kern/kern_intr.c,v 1.24.2.1 2001/10/14 20:05:50 luigi Exp $
27 *
28 */
29
984263bc
MD
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/malloc.h>
33#include <sys/kernel.h>
34#include <sys/sysctl.h>
ef0fdad1
MD
35#include <sys/thread.h>
36#include <sys/proc.h>
7e071e7a 37#include <sys/random.h>
477d3c1c 38#include <sys/serialize.h>
a7231bde 39#include <sys/interrupt.h>
477d3c1c 40#include <sys/bus.h>
37e7efec 41#include <sys/machintr.h>
984263bc 42
477d3c1c 43#include <machine/frame.h>
984263bc 44
684a93c4
MD
45#include <sys/thread2.h>
46#include <sys/mplock2.h>
47
c83c147e 48struct intr_info;
9d522d14 49
ef0fdad1
MD
50typedef struct intrec {
51 struct intrec *next;
9d522d14 52 struct intr_info *info;
ef0fdad1
MD
53 inthand2_t *handler;
54 void *argument;
477d3c1c 55 char *name;
ef0fdad1 56 int intr;
477d3c1c
MD
57 int intr_flags;
58 struct lwkt_serialize *serializer;
59} *intrec_t;
60
61struct intr_info {
62 intrec_t i_reclist;
877d4511 63 struct thread *i_thread; /* don't embed struct thread */
477d3c1c 64 struct random_softc i_random;
862f2618 65 long i_count; /* interrupts dispatched */
1169d35d 66 int i_running;
7bdce293
SZ
67 short i_mplock_required;
68 short i_flags;
477d3c1c
MD
69 int i_fast;
70 int i_slow;
f33e9c1c 71 int i_state;
b560de96
MD
72 int i_errorticks;
73 unsigned long i_straycount;
c83c147e
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74 int i_cpuid;
75 int i_intr;
76};
77
d8f4ebf4
CR
78struct intr_info_block {
79 struct intr_info ary[MAXCPU][MAX_INTS];
80};
81
82static struct intr_info_block *intr_block;
c83c147e 83static struct intr_info *swi_info_ary[MAX_SOFTINTS];
5f456c40 84
ff52cb5b 85static int max_installed_hard_intr[MAXCPU];
477d3c1c 86
d8f4ebf4
CR
87MALLOC_DEFINE(M_INTRMNG, "intrmng", "interrupt management");
88
89
a9d00ec1
MD
90#define EMERGENCY_INTR_POLLING_FREQ_MAX 20000
91
250ce837
MD
92/*
93 * Assert that callers into interrupt handlers don't return with
94 * dangling tokens, spinlocks, or mp locks.
95 */
3933a3ab 96#ifdef INVARIANTS
149a3d9e
VS
97
98#define TD_INVARIANTS_DECLARE \
149a3d9e
VS
99 int spincount; \
100 lwkt_tokref_t curstop
101
102#define TD_INVARIANTS_GET(td) \
103 do { \
0846e4ce 104 spincount = (td)->td_gd->gd_spinlocks; \
149a3d9e
VS
105 curstop = (td)->td_toks_stop; \
106 } while(0)
107
108#define TD_INVARIANTS_TEST(td, name) \
109 do { \
0846e4ce 110 KASSERT(spincount == (td)->td_gd->gd_spinlocks, \
149a3d9e
VS
111 ("spincount mismatch after interrupt handler %s", \
112 name)); \
113 KASSERT(curstop == (td)->td_toks_stop, \
114 ("token count mismatch after interrupt handler %s", \
115 name)); \
149a3d9e 116 } while(0)
250ce837
MD
117
118#else
119
b5d16701 120/* !INVARIANTS */
3933a3ab
MD
121
122#define TD_INVARIANTS_DECLARE
123#define TD_INVARIANTS_GET(td)
149a3d9e 124#define TD_INVARIANTS_TEST(td, name)
3933a3ab 125
149a3d9e 126#endif /* ndef INVARIANTS */
3933a3ab 127
a9d00ec1
MD
128static int sysctl_emergency_freq(SYSCTL_HANDLER_ARGS);
129static int sysctl_emergency_enable(SYSCTL_HANDLER_ARGS);
96d52ac8 130static void emergency_intr_timer_callback(systimer_t, int, struct intrframe *);
a9d00ec1
MD
131static void ithread_handler(void *arg);
132static void ithread_emergency(void *arg);
c83c147e 133static void report_stray_interrupt(struct intr_info *info, const char *func);
6355d931 134static void int_moveto_destcpu(int *, int);
4c846371 135static void int_moveto_origcpu(int, int);
c83c147e 136static void sched_ithd_intern(struct intr_info *info);
37d44089 137
ff52cb5b 138static struct systimer emergency_intr_timer[MAXCPU];
df0cd41c 139static struct thread *emergency_intr_thread[MAXCPU];
a9d00ec1 140
f33e9c1c
MD
141#define ISTATE_NOTHREAD 0
142#define ISTATE_NORMAL 1
143#define ISTATE_LIVELOCKED 2
37d44089 144
b560de96 145static int livelock_limit = 40000;
6ad84740 146static int livelock_limit_hi = 120000;
0e6beaa3 147static int livelock_lowater = 20000;
b560de96 148static int livelock_debug = -1;
37d44089
MD
149SYSCTL_INT(_kern, OID_AUTO, livelock_limit,
150 CTLFLAG_RW, &livelock_limit, 0, "Livelock interrupt rate limit");
6ad84740
SZ
151SYSCTL_INT(_kern, OID_AUTO, livelock_limit_hi,
152 CTLFLAG_RW, &livelock_limit_hi, 0,
153 "Livelock interrupt rate limit (high frequency)");
f33e9c1c
MD
154SYSCTL_INT(_kern, OID_AUTO, livelock_lowater,
155 CTLFLAG_RW, &livelock_lowater, 0, "Livelock low-water mark restore");
b560de96
MD
156SYSCTL_INT(_kern, OID_AUTO, livelock_debug,
157 CTLFLAG_RW, &livelock_debug, 0, "Livelock debug intr#");
984263bc 158
a9d00ec1
MD
159static int emergency_intr_enable = 0; /* emergency interrupt polling */
160TUNABLE_INT("kern.emergency_intr_enable", &emergency_intr_enable);
161SYSCTL_PROC(_kern, OID_AUTO, emergency_intr_enable, CTLTYPE_INT | CTLFLAG_RW,
162 0, 0, sysctl_emergency_enable, "I", "Emergency Interrupt Poll Enable");
163
164static int emergency_intr_freq = 10; /* emergency polling frequency */
165TUNABLE_INT("kern.emergency_intr_freq", &emergency_intr_freq);
166SYSCTL_PROC(_kern, OID_AUTO, emergency_intr_freq, CTLTYPE_INT | CTLFLAG_RW,
167 0, 0, sysctl_emergency_freq, "I", "Emergency Interrupt Poll Frequency");
168
169/*
170 * Sysctl support routines
171 */
172static int
173sysctl_emergency_enable(SYSCTL_HANDLER_ARGS)
174{
1acf7492 175 int error, enabled, cpuid, freq, origcpu;
a9d00ec1
MD
176
177 enabled = emergency_intr_enable;
178 error = sysctl_handle_int(oidp, &enabled, 0, req);
179 if (error || req->newptr == NULL)
180 return error;
181 emergency_intr_enable = enabled;
ff52cb5b
SZ
182 if (emergency_intr_enable)
183 freq = emergency_intr_freq;
184 else
185 freq = 1;
186
1acf7492
SZ
187 origcpu = mycpuid;
188 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
189 lwkt_migratecpu(cpuid);
ff52cb5b 190 systimer_adjust_periodic(&emergency_intr_timer[cpuid], freq);
1acf7492
SZ
191 }
192 lwkt_migratecpu(origcpu);
a9d00ec1
MD
193 return 0;
194}
195
196static int
197sysctl_emergency_freq(SYSCTL_HANDLER_ARGS)
198{
1acf7492 199 int error, phz, cpuid, freq, origcpu;
a9d00ec1
MD
200
201 phz = emergency_intr_freq;
202 error = sysctl_handle_int(oidp, &phz, 0, req);
203 if (error || req->newptr == NULL)
204 return error;
205 if (phz <= 0)
206 return EINVAL;
207 else if (phz > EMERGENCY_INTR_POLLING_FREQ_MAX)
208 phz = EMERGENCY_INTR_POLLING_FREQ_MAX;
209
210 emergency_intr_freq = phz;
ff52cb5b
SZ
211 if (emergency_intr_enable)
212 freq = emergency_intr_freq;
213 else
214 freq = 1;
215
1acf7492
SZ
216 origcpu = mycpuid;
217 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
218 lwkt_migratecpu(cpuid);
ff52cb5b 219 systimer_adjust_periodic(&emergency_intr_timer[cpuid], freq);
1acf7492
SZ
220 }
221 lwkt_migratecpu(origcpu);
a9d00ec1
MD
222 return 0;
223}
984263bc 224
45d76888
MD
225/*
226 * Register an SWI or INTerrupt handler.
45d76888 227 */
477d3c1c
MD
228void *
229register_swi(int intr, inthand2_t *handler, void *arg, const char *name,
1da8d52f 230 struct lwkt_serialize *serializer, int cpuid)
984263bc 231{
5f456c40 232 if (intr < FIRST_SOFTINT || intr >= MAX_INTS)
ef0fdad1 233 panic("register_swi: bad intr %d", intr);
1da8d52f
SZ
234
235 if (cpuid < 0)
236 cpuid = intr % ncpus;
237 return(register_int(intr, handler, arg, name, serializer, 0, cpuid));
984263bc
MD
238}
239
8619d09d
AH
240void *
241register_swi_mp(int intr, inthand2_t *handler, void *arg, const char *name,
1da8d52f 242 struct lwkt_serialize *serializer, int cpuid)
8619d09d
AH
243{
244 if (intr < FIRST_SOFTINT || intr >= MAX_INTS)
245 panic("register_swi: bad intr %d", intr);
1da8d52f
SZ
246
247 if (cpuid < 0)
248 cpuid = intr % ncpus;
249 return(register_int(intr, handler, arg, name, serializer,
5a4bb8ec 250 INTR_MPSAFE, cpuid));
8619d09d
AH
251}
252
477d3c1c
MD
253void *
254register_int(int intr, inthand2_t *handler, void *arg, const char *name,
6355d931 255 struct lwkt_serialize *serializer, int intr_flags, int cpuid)
984263bc 256{
477d3c1c
MD
257 struct intr_info *info;
258 struct intrec **list;
7bdce293 259 intrec_t rec = NULL;
6355d931
SZ
260 int orig_cpuid;
261
262 KKASSERT(cpuid >= 0 && cpuid < ncpus);
ef0fdad1 263
5f456c40 264 if (intr < 0 || intr >= MAX_INTS)
ef0fdad1 265 panic("register_int: bad intr %d", intr);
477d3c1c
MD
266 if (name == NULL)
267 name = "???";
d8f4ebf4 268 info = &intr_block->ary[cpuid][intr];
477d3c1c 269
7bdce293
SZ
270 int_moveto_destcpu(&orig_cpuid, cpuid);
271
272 /*
273 * This intr has been registered as exclusive one, so
274 * it can't shared.
275 */
276 if (info->i_flags & INTR_EXCL)
277 goto done;
278
279 /*
280 * This intr has been registered as shared one, so it
281 * can't be used for exclusive handler.
282 */
283 list = &info->i_reclist;
284 if ((intr_flags & INTR_EXCL) && *list != NULL)
285 goto done;
286
9d522d14
MD
287 /*
288 * Construct an interrupt handler record
289 */
efda3bd0
MD
290 rec = kmalloc(sizeof(struct intrec), M_DEVBUF, M_INTWAIT);
291 rec->name = kmalloc(strlen(name) + 1, M_DEVBUF, M_INTWAIT);
477d3c1c 292 strcpy(rec->name, name);
ef0fdad1 293
9d522d14 294 rec->info = info;
ef0fdad1
MD
295 rec->handler = handler;
296 rec->argument = arg;
ef0fdad1 297 rec->intr = intr;
477d3c1c 298 rec->intr_flags = intr_flags;
ef0fdad1 299 rec->next = NULL;
477d3c1c 300 rec->serializer = serializer;
ef0fdad1 301
a9d00ec1
MD
302 /*
303 * Create an emergency polling thread and set up a systimer to wake
b9e35f5a
MD
304 * it up. objcache isn't operational yet so use kmalloc.
305 *
306 * objcache may not be operational yet, use kmalloc().
a9d00ec1 307 */
df0cd41c 308 if (emergency_intr_thread[cpuid] == NULL) {
b9e35f5a
MD
309 emergency_intr_thread[cpuid] = kmalloc(sizeof(struct thread), M_DEVBUF,
310 M_INTWAIT | M_ZERO);
311 lwkt_create(ithread_emergency, NULL, NULL,
312 emergency_intr_thread[cpuid],
c83c147e 313 TDF_NOSTART | TDF_INTTHREAD, cpuid, "ithreadE %d",
ff52cb5b
SZ
314 cpuid);
315 systimer_init_periodic_nq(&emergency_intr_timer[cpuid],
316 emergency_intr_timer_callback,
df0cd41c 317 emergency_intr_thread[cpuid],
a9d00ec1
MD
318 (emergency_intr_enable ? emergency_intr_freq : 1));
319 }
320
ef0fdad1
MD
321 /*
322 * Create an interrupt thread if necessary, leave it in an unscheduled
45d76888 323 * state.
ef0fdad1 324 */
f33e9c1c
MD
325 if (info->i_state == ISTATE_NOTHREAD) {
326 info->i_state = ISTATE_NORMAL;
877d4511 327 info->i_thread = kmalloc(sizeof(struct thread), M_DEVBUF,
b9e35f5a 328 M_INTWAIT | M_ZERO);
fdce8919 329 lwkt_create(ithread_handler, (void *)(intptr_t)intr, NULL,
877d4511 330 info->i_thread, TDF_NOSTART | TDF_INTTHREAD, cpuid,
c83c147e 331 "ithread%d %d", intr, cpuid);
5f456c40 332 if (intr >= FIRST_SOFTINT)
877d4511 333 lwkt_setpri(info->i_thread, TDPRI_SOFT_NORM);
4b5f931b 334 else
877d4511
SZ
335 lwkt_setpri(info->i_thread, TDPRI_INT_MED);
336 info->i_thread->td_preemptable = lwkt_preempt;
ef0fdad1
MD
337 }
338
339 /*
9d522d14 340 * Keep track of how many fast and slow interrupts we have.
862f2618
MD
341 * Set i_mplock_required if any handler in the chain requires
342 * the MP lock to operate.
ef0fdad1 343 */
5a4bb8ec 344 if ((intr_flags & INTR_MPSAFE) == 0) {
862f2618 345 info->i_mplock_required = 1;
5a4bb8ec
MD
346 kprintf("interrupt uses mplock: %s\n", name);
347 }
f8a09be1 348 if (intr_flags & INTR_CLOCK)
9d522d14
MD
349 ++info->i_fast;
350 else
351 ++info->i_slow;
6ad84740 352
7bdce293 353 info->i_flags |= (intr_flags & INTR_EXCL);
6ad84740
SZ
354 if (info->i_slow + info->i_fast == 1 && (intr_flags & INTR_HIFREQ)) {
355 /*
356 * Allow high frequency interrupt, if this intr is not
357 * shared yet.
358 */
359 info->i_flags |= INTR_HIFREQ;
360 } else {
361 info->i_flags &= ~INTR_HIFREQ;
362 }
9d522d14 363
8b3ec75a
MD
364 /*
365 * Enable random number generation keying off of this interrupt.
366 */
367 if ((intr_flags & INTR_NOENTROPY) == 0 && info->i_random.sc_enabled == 0) {
368 info->i_random.sc_enabled = 1;
369 info->i_random.sc_intr = intr;
370 }
371
9d522d14
MD
372 /*
373 * Add the record to the interrupt list.
374 */
375 crit_enter();
ef0fdad1
MD
376 while (*list != NULL)
377 list = &(*list)->next;
378 *list = rec;
379 crit_exit();
5f456c40
MD
380
381 /*
382 * Update max_installed_hard_intr to make the emergency intr poll
383 * a bit more efficient.
384 */
385 if (intr < FIRST_SOFTINT) {
ff52cb5b
SZ
386 if (max_installed_hard_intr[cpuid] <= intr)
387 max_installed_hard_intr[cpuid] = intr + 1;
5f456c40 388 }
9d522d14 389
c83c147e
SZ
390 if (intr >= FIRST_SOFTINT)
391 swi_info_ary[intr - FIRST_SOFTINT] = info;
392
9d522d14
MD
393 /*
394 * Setup the machine level interrupt vector
395 */
f416026e
SZ
396 if (intr < FIRST_SOFTINT && info->i_slow + info->i_fast == 1)
397 machintr_intr_setup(intr, intr_flags);
9d522d14 398
7bdce293 399done:
4c846371 400 int_moveto_origcpu(orig_cpuid, cpuid);
477d3c1c 401 return(rec);
ef0fdad1 402}
984263bc 403
9d522d14 404void
1da8d52f 405unregister_swi(void *id, int intr, int cpuid)
ef0fdad1 406{
1da8d52f
SZ
407 if (cpuid < 0)
408 cpuid = intr % ncpus;
409
410 unregister_int(id, cpuid);
984263bc
MD
411}
412
9d522d14 413void
6355d931 414unregister_int(void *id, int cpuid)
984263bc 415{
477d3c1c
MD
416 struct intr_info *info;
417 struct intrec **list;
418 intrec_t rec;
6355d931
SZ
419 int intr, orig_cpuid;
420
421 KKASSERT(cpuid >= 0 && cpuid < ncpus);
477d3c1c
MD
422
423 intr = ((intrec_t)id)->intr;
ef0fdad1 424
5f456c40 425 if (intr < 0 || intr >= MAX_INTS)
ef0fdad1 426 panic("register_int: bad intr %d", intr);
477d3c1c 427
d8f4ebf4 428 info = &intr_block->ary[cpuid][intr];
477d3c1c 429
6355d931 430 int_moveto_destcpu(&orig_cpuid, cpuid);
4c846371 431
477d3c1c 432 /*
9d522d14
MD
433 * Remove the interrupt descriptor, adjust the descriptor count,
434 * and teardown the machine level vector if this was the last interrupt.
477d3c1c 435 */
ef0fdad1 436 crit_enter();
477d3c1c 437 list = &info->i_reclist;
ef0fdad1 438 while ((rec = *list) != NULL) {
9d522d14 439 if (rec == id)
ef0fdad1 440 break;
ef0fdad1
MD
441 list = &rec->next;
442 }
9d522d14 443 if (rec) {
acf7409e
SZ
444 intrec_t rec0;
445
9d522d14 446 *list = rec->next;
f8a09be1 447 if (rec->intr_flags & INTR_CLOCK)
9d522d14
MD
448 --info->i_fast;
449 else
450 --info->i_slow;
e8727dce 451 if (intr < FIRST_SOFTINT && info->i_fast + info->i_slow == 0)
f416026e 452 machintr_intr_teardown(intr);
862f2618 453
acf7409e
SZ
454 /*
455 * Clear i_mplock_required if no handlers in the chain require the
456 * MP lock.
457 */
458 for (rec0 = info->i_reclist; rec0; rec0 = rec0->next) {
459 if ((rec0->intr_flags & INTR_MPSAFE) == 0)
460 break;
461 }
462 if (rec0 == NULL)
862f2618 463 info->i_mplock_required = 0;
acf7409e 464 }
862f2618 465
7bdce293
SZ
466 if (info->i_reclist == NULL) {
467 info->i_flags = 0;
468 if (intr >= FIRST_SOFTINT)
469 swi_info_ary[intr - FIRST_SOFTINT] = NULL;
6ad84740
SZ
470 } else if (info->i_fast + info->i_slow == 1 &&
471 (info->i_reclist->intr_flags & INTR_HIFREQ)) {
472 /* Unshared high frequency interrupt. */
473 info->i_flags |= INTR_HIFREQ;
7bdce293 474 }
c83c147e 475
ef0fdad1 476 crit_exit();
477d3c1c 477
4c846371
SZ
478 int_moveto_origcpu(orig_cpuid, cpuid);
479
477d3c1c 480 /*
9d522d14 481 * Free the record.
477d3c1c 482 */
ef0fdad1 483 if (rec != NULL) {
efda3bd0
MD
484 kfree(rec->name, M_DEVBUF);
485 kfree(rec, M_DEVBUF);
ef0fdad1 486 } else {
6ea70f76 487 kprintf("warning: unregister_int: int %d handler for %s not found\n",
477d3c1c 488 intr, ((intrec_t)id)->name);
ef0fdad1 489 }
477d3c1c
MD
490}
491
477d3c1c 492long
c83c147e 493get_interrupt_counter(int intr, int cpuid)
477d3c1c
MD
494{
495 struct intr_info *info;
496
c83c147e
SZ
497 KKASSERT(cpuid >= 0 && cpuid < ncpus);
498
5f456c40 499 if (intr < 0 || intr >= MAX_INTS)
477d3c1c 500 panic("register_int: bad intr %d", intr);
d8f4ebf4 501 info = &intr_block->ary[cpuid][intr];
477d3c1c
MD
502 return(info->i_count);
503}
504
7e071e7a
MD
505void
506register_randintr(int intr)
507{
477d3c1c 508 struct intr_info *info;
c83c147e 509 int cpuid;
477d3c1c 510
5f456c40 511 if (intr < 0 || intr >= MAX_INTS)
417c990a 512 panic("register_randintr: bad intr %d", intr);
c83c147e
SZ
513
514 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
d8f4ebf4 515 info = &intr_block->ary[cpuid][intr];
c83c147e
SZ
516 info->i_random.sc_intr = intr;
517 info->i_random.sc_enabled = 1;
518 }
7e071e7a
MD
519}
520
521void
522unregister_randintr(int intr)
523{
477d3c1c 524 struct intr_info *info;
c83c147e 525 int cpuid;
477d3c1c 526
5f456c40 527 if (intr < 0 || intr >= MAX_INTS)
477d3c1c 528 panic("register_swi: bad intr %d", intr);
c83c147e
SZ
529
530 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
d8f4ebf4 531 info = &intr_block->ary[cpuid][intr];
c83c147e
SZ
532 info->i_random.sc_enabled = -1;
533 }
7e071e7a
MD
534}
535
5f456c40
MD
536int
537next_registered_randintr(int intr)
538{
539 struct intr_info *info;
540
541 if (intr < 0 || intr >= MAX_INTS)
542 panic("register_swi: bad intr %d", intr);
c83c147e 543
5f456c40 544 while (intr < MAX_INTS) {
c83c147e
SZ
545 int cpuid;
546
547 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
d8f4ebf4 548 info = &intr_block->ary[cpuid][intr];
c83c147e
SZ
549 if (info->i_random.sc_enabled > 0)
550 return intr;
551 }
5f456c40
MD
552 ++intr;
553 }
c83c147e 554 return intr;
5f456c40
MD
555}
556
ef0fdad1 557/*
b68b7282
MD
558 * Dispatch an interrupt. If there's nothing to do we have a stray
559 * interrupt and can just return, leaving the interrupt masked.
96728c05 560 *
477d3c1c 561 * We need to schedule the interrupt and set its i_running bit. If
96728c05
MD
562 * we are not on the interrupt thread's cpu we have to send a message
563 * to the correct cpu that will issue the desired action (interlocking
f33e9c1c
MD
564 * with the interrupt thread's critical section). We do NOT attempt to
565 * reschedule interrupts whos i_running bit is already set because
566 * this would prematurely wakeup a livelock-limited interrupt thread.
567 *
568 * i_running is only tested/set on the same cpu as the interrupt thread.
96728c05
MD
569 *
570 * We are NOT in a critical section, which will allow the scheduled
71ef2f5c 571 * interrupt to preempt us. The MP lock might *NOT* be held here.
ef0fdad1 572 */
96728c05
MD
573static void
574sched_ithd_remote(void *arg)
575{
c83c147e 576 sched_ithd_intern(arg);
96728c05
MD
577}
578
c83c147e
SZ
579static void
580sched_ithd_intern(struct intr_info *info)
ef0fdad1 581{
477d3c1c 582 ++info->i_count;
f33e9c1c 583 if (info->i_state != ISTATE_NOTHREAD) {
477d3c1c 584 if (info->i_reclist == NULL) {
c83c147e 585 report_stray_interrupt(info, "sched_ithd");
b68b7282 586 } else {
877d4511 587 if (info->i_thread->td_gd == mycpu) {
f33e9c1c
MD
588 if (info->i_running == 0) {
589 info->i_running = 1;
590 if (info->i_state != ISTATE_LIVELOCKED)
877d4511 591 lwkt_schedule(info->i_thread); /* MIGHT PREEMPT */
f33e9c1c 592 }
96728c05 593 } else {
877d4511 594 lwkt_send_ipiq(info->i_thread->td_gd, sched_ithd_remote, info);
96728c05 595 }
b68b7282 596 }
ef0fdad1 597 } else {
c83c147e 598 report_stray_interrupt(info, "sched_ithd");
ef0fdad1
MD
599 }
600}
601
c83c147e
SZ
602void
603sched_ithd_soft(int intr)
604{
605 struct intr_info *info;
606
607 KKASSERT(intr >= FIRST_SOFTINT && intr < MAX_INTS);
608
609 info = swi_info_ary[intr - FIRST_SOFTINT];
610 if (info != NULL) {
611 sched_ithd_intern(info);
612 } else {
613 kprintf("unregistered softint %d got scheduled on cpu%d\n",
614 intr, mycpuid);
615 }
616}
617
618void
619sched_ithd_hard(int intr)
620{
621 KKASSERT(intr >= 0 && intr < MAX_HARDINTS);
d8f4ebf4 622 sched_ithd_intern(&intr_block->ary[mycpuid][intr]);
c83c147e
SZ
623}
624
bae88a6f
SZ
625#ifdef _KERNEL_VIRTUAL
626
627void
628sched_ithd_hard_virtual(int intr)
629{
630 KKASSERT(intr >= 0 && intr < MAX_HARDINTS);
d8f4ebf4 631 sched_ithd_intern(&intr_block->ary[0][intr]);
bae88a6f
SZ
632}
633
634void *
635register_int_virtual(int intr, inthand2_t *handler, void *arg, const char *name,
636 struct lwkt_serialize *serializer, int intr_flags)
637{
638 return register_int(intr, handler, arg, name, serializer, intr_flags, 0);
639}
640
641void
642unregister_int_virtual(void *id)
643{
644 unregister_int(id, 0);
645}
646
647#endif /* _KERN_VIRTUAL */
648
b560de96 649static void
c83c147e 650report_stray_interrupt(struct intr_info *info, const char *func)
b560de96
MD
651{
652 ++info->i_straycount;
653 if (info->i_straycount < 10) {
654 if (info->i_errorticks == ticks)
655 return;
656 info->i_errorticks = ticks;
c83c147e
SZ
657 kprintf("%s: stray interrupt %d on cpu%d\n",
658 func, info->i_intr, mycpuid);
7e88c0e6 659 } else if (info->i_straycount == 10) {
c83c147e
SZ
660 kprintf("%s: %ld stray interrupts %d on cpu%d - "
661 "there will be no further reports\n", func,
662 info->i_straycount, info->i_intr, mycpuid);
b560de96
MD
663 }
664}
665
37d44089
MD
666/*
667 * This is run from a periodic SYSTIMER (and thus must be MP safe, the BGL
668 * might not be held).
669 */
670static void
96d52ac8
SZ
671ithread_livelock_wakeup(systimer_t st, int in_ipi __unused,
672 struct intrframe *frame __unused)
37d44089 673{
477d3c1c 674 struct intr_info *info;
37d44089 675
d8f4ebf4 676 info = &intr_block->ary[mycpuid][(int)(intptr_t)st->data];
f33e9c1c 677 if (info->i_state != ISTATE_NOTHREAD)
877d4511 678 lwkt_schedule(info->i_thread);
37d44089
MD
679}
680
729e15a8
SZ
681/*
682 * Schedule ithread within fast intr handler
683 *
203592a0
MD
684 * Temporarily bump the current thread's td_nest_count to prevent deep
685 * preemptions and splz/doreti stacks.
729e15a8
SZ
686 */
687static __inline void
688ithread_fast_sched(int intr, thread_t td)
689{
690 ++td->td_nest_count;
729e15a8 691 crit_exit_quick(td);
c83c147e 692 sched_ithd_hard(intr);
729e15a8 693 crit_enter_quick(td);
729e15a8
SZ
694 --td->td_nest_count;
695}
696
67b9bb39 697/*
7bd34050 698 * This function is called directly from the ICU or APIC vector code assembly
477d3c1c
MD
699 * to process an interrupt. The critical section and interrupt deferral
700 * checks have already been done but the function is entered WITHOUT
701 * a critical section held. The BGL may or may not be held.
702 *
703 * Must return non-zero if we do not want the vector code to re-enable
704 * the interrupt (which we don't if we have to schedule the interrupt)
67b9bb39 705 */
c7eb0589 706int ithread_fast_handler(struct intrframe *frame);
477d3c1c
MD
707
708int
c7eb0589 709ithread_fast_handler(struct intrframe *frame)
477d3c1c
MD
710{
711 int intr;
712 struct intr_info *info;
713 struct intrec **list;
714 int must_schedule;
477d3c1c 715 int got_mplock;
3933a3ab 716 TD_INVARIANTS_DECLARE;
c24c20c0 717 intrec_t rec, nrec;
477d3c1c 718 globaldata_t gd;
729e15a8 719 thread_t td;
477d3c1c 720
c7eb0589 721 intr = frame->if_vec;
477d3c1c 722 gd = mycpu;
729e15a8
SZ
723 td = curthread;
724
725 /* We must be in critical section. */
f9235b6d 726 KKASSERT(td->td_critcount);
477d3c1c 727
94fd1ee9
MD
728 /* Race condition during early boot */
729 if (intr_block == NULL)
730 return 0;
731
d8f4ebf4 732 info = &intr_block->ary[mycpuid][intr];
477d3c1c
MD
733
734 /*
735 * If we are not processing any FAST interrupts, just schedule the thing.
477d3c1c
MD
736 */
737 if (info->i_fast == 0) {
3848f1c7 738 ++gd->gd_cnt.v_intr;
729e15a8 739 ithread_fast_sched(intr, td);
477d3c1c
MD
740 return(1);
741 }
742
743 /*
744 * This should not normally occur since interrupts ought to be
745 * masked if the ithread has been scheduled or is running.
746 */
747 if (info->i_running)
748 return(1);
749
750 /*
751 * Bump the interrupt nesting level to process any FAST interrupts.
752 * Obtain the MP lock as necessary. If the MP lock cannot be obtained,
753 * schedule the interrupt thread to deal with the issue instead.
754 *
755 * To reduce overhead, just leave the MP lock held once it has been
756 * obtained.
757 */
477d3c1c
MD
758 ++gd->gd_intr_nesting_level;
759 ++gd->gd_cnt.v_intr;
760 must_schedule = info->i_slow;
477d3c1c 761 got_mplock = 0;
477d3c1c 762
3933a3ab 763 TD_INVARIANTS_GET(td);
477d3c1c 764 list = &info->i_reclist;
3933a3ab 765
c24c20c0
MD
766 for (rec = *list; rec; rec = nrec) {
767 /* rec may be invalid after call */
768 nrec = rec->next;
477d3c1c 769
f8a09be1 770 if (rec->intr_flags & INTR_CLOCK) {
477d3c1c
MD
771 if ((rec->intr_flags & INTR_MPSAFE) == 0 && got_mplock == 0) {
772 if (try_mplock() == 0) {
f5c2d910
SZ
773 /* Couldn't get the MP lock; just schedule it. */
774 must_schedule = 1;
477d3c1c
MD
775 break;
776 }
777 got_mplock = 1;
778 }
477d3c1c
MD
779 if (rec->serializer) {
780 must_schedule += lwkt_serialize_handler_try(
781 rec->serializer, rec->handler,
c7eb0589 782 rec->argument, frame);
477d3c1c 783 } else {
c7eb0589 784 rec->handler(rec->argument, frame);
477d3c1c 785 }
3933a3ab 786 TD_INVARIANTS_TEST(td, rec->name);
477d3c1c
MD
787 }
788 }
789
790 /*
791 * Cleanup
792 */
793 --gd->gd_intr_nesting_level;
477d3c1c
MD
794 if (got_mplock)
795 rel_mplock();
477d3c1c
MD
796
797 /*
729e15a8
SZ
798 * If we had a problem, or mixed fast and slow interrupt handlers are
799 * registered, schedule the ithread to catch the missed records (it
800 * will just re-run all of them). A return value of 0 indicates that
801 * all handlers have been run and the interrupt can be re-enabled, and
802 * a non-zero return indicates that the interrupt thread controls
803 * re-enablement.
477d3c1c 804 */
afd7b1c0 805 if (must_schedule > 0)
729e15a8 806 ithread_fast_sched(intr, td);
afd7b1c0 807 else if (must_schedule == 0)
477d3c1c
MD
808 ++info->i_count;
809 return(must_schedule);
810}
811
b68b7282 812/*
45d76888
MD
813 * Interrupt threads run this as their main loop.
814 *
68b3ccd4 815 * The handler begins execution outside a critical section and no MP lock.
37d44089 816 *
477d3c1c 817 * The i_running state starts at 0. When an interrupt occurs, the hardware
4b19a4d1
SZ
818 * interrupt is disabled and sched_ithd_hard(). The HW interrupt remains
819 * disabled until all routines have run. We then call machintr_intr_enable()
820 * to reenable the HW interrupt and deschedule us until the next interrupt.
45d76888 821 *
4b19a4d1
SZ
822 * We are responsible for atomically checking i_running. i_running for our
823 * irq is only set in the context of our cpu, so a critical section is a
824 * sufficient interlock.
b68b7282 825 */
93781523
MD
826#define LIVELOCK_TIMEFRAME(freq) ((freq) >> 2) /* 1/4 second */
827
ef0fdad1
MD
828static void
829ithread_handler(void *arg)
830{
477d3c1c 831 struct intr_info *info;
f33e9c1c 832 int use_limit;
e28c8ef4 833 uint32_t lseconds;
c83c147e 834 int intr, cpuid = mycpuid;
9d522d14 835 int mpheld;
477d3c1c
MD
836 struct intrec **list;
837 intrec_t rec, nrec;
f33e9c1c 838 globaldata_t gd;
67b9bb39 839 struct systimer ill_timer; /* enforced freq. timer */
f33e9c1c 840 u_int ill_count; /* interrupt livelock counter */
6ad84740 841 int upper_limit; /* interrupt livelock upper limit */
3933a3ab 842 TD_INVARIANTS_DECLARE;
45d76888 843
f33e9c1c 844 ill_count = 0;
973c11b9 845 intr = (int)(intptr_t)arg;
d8f4ebf4 846 info = &intr_block->ary[cpuid][intr];
477d3c1c 847 list = &info->i_reclist;
477d3c1c 848
45d76888 849 /*
862f2618 850 * The loop must be entered with one critical section held. The thread
fdce8919 851 * does not hold the mplock on startup.
45d76888 852 */
e381e77c
MD
853 gd = mycpu;
854 lseconds = gd->gd_time_seconds;
45d76888 855 crit_enter_gd(gd);
862f2618 856 mpheld = 0;
ef0fdad1 857
ef0fdad1 858 for (;;) {
862f2618
MD
859 /*
860 * The chain is only considered MPSAFE if all its interrupt handlers
861 * are MPSAFE. However, if intr_mpsafe has been turned off we
862 * always operate with the BGL.
863 */
c9e9fb21 864 if (info->i_mplock_required != mpheld) {
862f2618
MD
865 if (info->i_mplock_required) {
866 KKASSERT(mpheld == 0);
c9e9fb21 867 get_mplock();
862f2618
MD
868 mpheld = 1;
869 } else {
870 KKASSERT(mpheld != 0);
871 rel_mplock();
872 mpheld = 0;
873 }
874 }
875
3933a3ab
MD
876 TD_INVARIANTS_GET(gd->gd_curthread);
877
93781523 878 /*
f33e9c1c
MD
879 * If an interrupt is pending, clear i_running and execute the
880 * handlers. Note that certain types of interrupts can re-trigger
881 * and set i_running again.
45d76888 882 *
f33e9c1c 883 * Each handler is run in a critical section. Note that we run both
862f2618 884 * FAST and SLOW designated service routines.
93781523 885 */
f33e9c1c
MD
886 if (info->i_running) {
887 ++ill_count;
888 info->i_running = 0;
9d522d14 889
b560de96 890 if (*list == NULL)
c83c147e 891 report_stray_interrupt(info, "ithread_handler");
b560de96 892
f33e9c1c 893 for (rec = *list; rec; rec = nrec) {
c24c20c0 894 /* rec may be invalid after call */
f33e9c1c 895 nrec = rec->next;
c91894e0
MD
896 if (rec->handler == NULL) {
897 kprintf("NULL HANDLER %s\n", rec->name);
898 } else
f33e9c1c
MD
899 if (rec->serializer) {
900 lwkt_serialize_handler_call(rec->serializer, rec->handler,
901 rec->argument, NULL);
902 } else {
903 rec->handler(rec->argument, NULL);
904 }
3933a3ab 905 TD_INVARIANTS_TEST(gd->gd_curthread, rec->name);
477d3c1c 906 }
ef0fdad1 907 }
37d44089
MD
908
909 /*
910 * This is our interrupt hook to add rate randomness to the random
911 * number generator.
912 */
8b3ec75a 913 if (info->i_random.sc_enabled > 0)
96728c05 914 add_interrupt_randomness(intr);
37d44089
MD
915
916 /*
f33e9c1c
MD
917 * Unmask the interrupt to allow it to trigger again. This only
918 * applies to certain types of interrupts (typ level interrupts).
919 * This can result in the interrupt retriggering, but the retrigger
920 * will not be processed until we cycle our critical section.
363d922a
MD
921 *
922 * Only unmask interrupts while handlers are installed. It is
923 * possible to hit a situation where no handlers are installed
924 * due to a device driver livelocking and then tearing down its
925 * interrupt on close (the parallel bus being a good example).
37d44089 926 */
6d164b20 927 if (intr < FIRST_SOFTINT && *list)
35b2edcb 928 machintr_intr_enable(intr);
f33e9c1c
MD
929
930 /*
931 * Do a quick exit/enter to catch any higher-priority interrupt
932 * sources, such as the statclock, so thread time accounting
933 * will still work. This may also cause an interrupt to re-trigger.
934 */
935 crit_exit_gd(gd);
936 crit_enter_gd(gd);
937
938 /*
939 * LIVELOCK STATE MACHINE
940 */
941 switch(info->i_state) {
942 case ISTATE_NORMAL:
943 /*
b560de96 944 * Reset the count each second.
f33e9c1c 945 */
b560de96
MD
946 if (lseconds != gd->gd_time_seconds) {
947 lseconds = gd->gd_time_seconds;
948 ill_count = 0;
f33e9c1c
MD
949 }
950
951 /*
952 * If we did not exceed the frequency limit, we are done.
953 * If the interrupt has not retriggered we deschedule ourselves.
954 */
6ad84740
SZ
955 if (info->i_flags & INTR_HIFREQ)
956 upper_limit = livelock_limit_hi;
957 else
958 upper_limit = livelock_limit;
959 if (ill_count <= upper_limit) {
f33e9c1c
MD
960 if (info->i_running == 0) {
961 lwkt_deschedule_self(gd->gd_curthread);
962 lwkt_switch();
963 }
37d44089 964 break;
f33e9c1c
MD
965 }
966
967 /*
968 * Otherwise we are livelocked. Set up a periodic systimer
969 * to wake the thread up at the limit frequency.
970 */
c83c147e 971 kprintf("intr %d on cpu%d at %d/%d hz, livelocked limit engaged!\n",
6ad84740 972 intr, cpuid, ill_count, upper_limit);
f33e9c1c 973 info->i_state = ISTATE_LIVELOCKED;
6ad84740 974 if ((use_limit = upper_limit) < 100)
f33e9c1c
MD
975 use_limit = 100;
976 else if (use_limit > 500000)
977 use_limit = 500000;
79b38af2 978 systimer_init_periodic_nq(&ill_timer, ithread_livelock_wakeup,
973c11b9 979 (void *)(intptr_t)intr, use_limit);
37d44089 980 /* fall through */
f33e9c1c 981 case ISTATE_LIVELOCKED:
37d44089 982 /*
f33e9c1c
MD
983 * Wait for our periodic timer to go off. Since the interrupt
984 * has re-armed it can still set i_running, but it will not
985 * reschedule us while we are in a livelocked state.
37d44089 986 */
f33e9c1c 987 lwkt_deschedule_self(gd->gd_curthread);
37d44089 988 lwkt_switch();
93781523 989
37d44089 990 /*
b560de96
MD
991 * Check once a second to see if the livelock condition no
992 * longer applies.
37d44089 993 */
b560de96
MD
994 if (lseconds != gd->gd_time_seconds) {
995 lseconds = gd->gd_time_seconds;
f33e9c1c 996 if (ill_count < livelock_lowater) {
b560de96
MD
997 info->i_state = ISTATE_NORMAL;
998 systimer_del(&ill_timer);
c83c147e
SZ
999 kprintf("intr %d on cpu%d at %d/%d hz, livelock removed\n",
1000 intr, cpuid, ill_count, livelock_lowater);
b560de96
MD
1001 } else if (livelock_debug == intr ||
1002 (bootverbose && cold)) {
c83c147e
SZ
1003 kprintf("intr %d on cpu%d at %d/%d hz, in livelock\n",
1004 intr, cpuid, ill_count, livelock_lowater);
f33e9c1c 1005 }
b560de96 1006 ill_count = 0;
37d44089
MD
1007 }
1008 break;
1009 }
ef0fdad1 1010 }
eccb255f 1011 /* NOT REACHED */
ef0fdad1
MD
1012}
1013
a9d00ec1
MD
1014/*
1015 * Emergency interrupt polling thread. The thread begins execution
1016 * outside a critical section with the BGL held.
1017 *
1018 * If emergency interrupt polling is enabled, this thread will
1019 * execute all system interrupts not marked INTR_NOPOLL at the
1020 * specified polling frequency.
1021 *
1022 * WARNING! This thread runs *ALL* interrupt service routines that
1023 * are not marked INTR_NOPOLL, which basically means everything except
1024 * the 8254 clock interrupt and the ATA interrupt. It has very high
1025 * overhead and should only be used in situations where the machine
1026 * cannot otherwise be made to work. Due to the severe performance
1027 * degredation, it should not be enabled on production machines.
1028 */
1029static void
1030ithread_emergency(void *arg __unused)
1031{
eccb255f 1032 globaldata_t gd = mycpu;
a9d00ec1
MD
1033 struct intr_info *info;
1034 intrec_t rec, nrec;
ff52cb5b 1035 int intr, cpuid = mycpuid;
3933a3ab 1036 TD_INVARIANTS_DECLARE;
a9d00ec1 1037
c9e9fb21 1038 get_mplock();
eccb255f
MD
1039 crit_enter_gd(gd);
1040 TD_INVARIANTS_GET(gd->gd_curthread);
c9e9fb21 1041
a9d00ec1 1042 for (;;) {
ff52cb5b 1043 for (intr = 0; intr < max_installed_hard_intr[cpuid]; ++intr) {
d8f4ebf4 1044 info = &intr_block->ary[cpuid][intr];
a9d00ec1 1045 for (rec = info->i_reclist; rec; rec = nrec) {
c24c20c0
MD
1046 /* rec may be invalid after call */
1047 nrec = rec->next;
a9d00ec1
MD
1048 if ((rec->intr_flags & INTR_NOPOLL) == 0) {
1049 if (rec->serializer) {
c24c20c0 1050 lwkt_serialize_handler_try(rec->serializer,
a9d00ec1
MD
1051 rec->handler, rec->argument, NULL);
1052 } else {
1053 rec->handler(rec->argument, NULL);
1054 }
eccb255f 1055 TD_INVARIANTS_TEST(gd->gd_curthread, rec->name);
a9d00ec1 1056 }
a9d00ec1
MD
1057 }
1058 }
eccb255f 1059 lwkt_deschedule_self(gd->gd_curthread);
a9d00ec1
MD
1060 lwkt_switch();
1061 }
eccb255f 1062 /* NOT REACHED */
a9d00ec1
MD
1063}
1064
1065/*
1066 * Systimer callback - schedule the emergency interrupt poll thread
1067 * if emergency polling is enabled.
1068 */
1069static
1070void
96d52ac8
SZ
1071emergency_intr_timer_callback(systimer_t info, int in_ipi __unused,
1072 struct intrframe *frame __unused)
a9d00ec1
MD
1073{
1074 if (emergency_intr_enable)
1075 lwkt_schedule(info->data);
1076}
1077
984263bc
MD
1078/*
1079 * Sysctls used by systat and others: hw.intrnames and hw.intrcnt.
1080 * The data for this machine dependent, and the declarations are in machine
1081 * dependent code. The layout of intrnames and intrcnt however is machine
1082 * independent.
1083 *
1084 * We do not know the length of intrcnt and intrnames at compile time, so
1085 * calculate things at run time.
1086 */
477d3c1c 1087
984263bc
MD
1088static int
1089sysctl_intrnames(SYSCTL_HANDLER_ARGS)
1090{
477d3c1c
MD
1091 struct intr_info *info;
1092 intrec_t rec;
1093 int error = 0;
1094 int len;
c83c147e 1095 int intr, cpuid;
477d3c1c
MD
1096 char buf[64];
1097
c83c147e
SZ
1098 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1099 for (intr = 0; error == 0 && intr < MAX_INTS; ++intr) {
d8f4ebf4 1100 info = &intr_block->ary[cpuid][intr];
477d3c1c 1101
c83c147e
SZ
1102 len = 0;
1103 buf[0] = 0;
1104 for (rec = info->i_reclist; rec; rec = rec->next) {
1105 ksnprintf(buf + len, sizeof(buf) - len, "%s%s",
1106 (len ? "/" : ""), rec->name);
1107 len += strlen(buf + len);
1108 }
1109 if (len == 0) {
1110 ksnprintf(buf, sizeof(buf), "irq%d", intr);
1111 len = strlen(buf);
1112 }
1113 error = SYSCTL_OUT(req, buf, len + 1);
477d3c1c 1114 }
477d3c1c
MD
1115 }
1116 return (error);
984263bc
MD
1117}
1118
1119SYSCTL_PROC(_hw, OID_AUTO, intrnames, CTLTYPE_OPAQUE | CTLFLAG_RD,
1120 NULL, 0, sysctl_intrnames, "", "Interrupt Names");
1121
3242c748
SZ
1122static int
1123sysctl_intrcnt_all(SYSCTL_HANDLER_ARGS)
1124{
1125 struct intr_info *info;
1126 int error = 0;
c83c147e 1127 int intr, cpuid;
3242c748 1128
c83c147e
SZ
1129 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1130 for (intr = 0; intr < MAX_INTS; ++intr) {
d8f4ebf4 1131 info = &intr_block->ary[cpuid][intr];
3242c748 1132
c83c147e
SZ
1133 error = SYSCTL_OUT(req, &info->i_count, sizeof(info->i_count));
1134 if (error)
3242c748 1135 goto failed;
c83c147e 1136 }
3242c748
SZ
1137 }
1138failed:
1139 return(error);
1140}
1141
1142SYSCTL_PROC(_hw, OID_AUTO, intrcnt_all, CTLTYPE_OPAQUE | CTLFLAG_RD,
1143 NULL, 0, sysctl_intrcnt_all, "", "Interrupt Counts");
1144
c24bcdf9
SZ
1145SYSCTL_PROC(_hw, OID_AUTO, intrcnt, CTLTYPE_OPAQUE | CTLFLAG_RD,
1146 NULL, 0, sysctl_intrcnt_all, "", "Interrupt Counts");
1147
4c846371 1148static void
6355d931 1149int_moveto_destcpu(int *orig_cpuid0, int cpuid)
4c846371 1150{
6355d931 1151 int orig_cpuid = mycpuid;
4c846371
SZ
1152
1153 if (cpuid != orig_cpuid)
1154 lwkt_migratecpu(cpuid);
1155
1156 *orig_cpuid0 = orig_cpuid;
4c846371
SZ
1157}
1158
1159static void
1160int_moveto_origcpu(int orig_cpuid, int cpuid)
1161{
1162 if (cpuid != orig_cpuid)
1163 lwkt_migratecpu(orig_cpuid);
1164}
c83c147e
SZ
1165
1166static void
1167intr_init(void *dummy __unused)
1168{
1169 int cpuid;
1170
94fd1ee9 1171 kprintf("Initialize MI interrupts for %d cpus\n", ncpus);
c83c147e 1172
94fd1ee9
MD
1173 intr_block = kmalloc(offsetof(struct intr_info_block, ary[ncpus][0]),
1174 M_INTRMNG, M_INTWAIT | M_ZERO);
d8f4ebf4 1175
c83c147e
SZ
1176 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1177 int intr;
1178
1179 for (intr = 0; intr < MAX_INTS; ++intr) {
d8f4ebf4 1180 struct intr_info *info = &intr_block->ary[cpuid][intr];
c83c147e
SZ
1181
1182 info->i_cpuid = cpuid;
1183 info->i_intr = intr;
1184 }
1185 }
1186}
1187SYSINIT(intr_init, SI_BOOT2_FINISH_PIC, SI_ORDER_ANY, intr_init, NULL);