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c8fe38ae MD |
1 | /* |
2 | * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved. | |
3 | * | |
4 | * This code is derived from software contributed to The DragonFly Project | |
5 | * by Matthew Dillon <dillon@backplane.com> | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions and the following disclaimer. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in | |
15 | * the documentation and/or other materials provided with the | |
16 | * distribution. | |
17 | * 3. Neither the name of The DragonFly Project nor the names of its | |
18 | * contributors may be used to endorse or promote products derived | |
19 | * from this software without specific, prior written permission. | |
20 | * | |
21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
22 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
23 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | |
24 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | |
25 | * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, | |
27 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
28 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED | |
29 | * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
31 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
32 | * SUCH DAMAGE. | |
33 | * | |
34 | * Copyright (c) 1996, by Peter Wemm and Steve Passe, All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * 1. Redistributions of source code must retain the above copyright | |
40 | * notice, this list of conditions and the following disclaimer. | |
41 | * 2. The name of the developer may NOT be used to endorse or promote products | |
42 | * derived from this software without specific prior written permission. | |
43 | * | |
44 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
45 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
46 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
47 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | |
48 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
49 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
50 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
51 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
53 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
54 | * SUCH DAMAGE. | |
55 | * | |
56 | * $FreeBSD: src/sys/i386/include/apic.h,v 1.14.2.2 2003/03/21 21:46:15 jhb Exp $ | |
57 | * $DragonFly: src/sys/platform/pc64/apic/apicreg.h,v 1.1 2008/08/29 17:07:12 dillon Exp $ | |
58 | */ | |
59 | ||
60 | #ifndef _MACHINE_APICREG_H_ | |
61 | #define _MACHINE_APICREG_H_ | |
62 | ||
63 | /* | |
64 | * Local && I/O APIC definitions for Pentium P54C+ Built-in APIC. | |
65 | * | |
66 | * A per-cpu APIC resides in memory location 0xFEE00000. | |
67 | * | |
68 | * 31 ... 24 23 ... 16 15 ... 8 7 ... 0 | |
69 | * +-----------+-----------+-----------+-----------+ | |
70 | * 0000 | | | | | | |
71 | * 0010 | | | | | | |
72 | * +-----------+-----------+-----------+-----------+ | |
73 | * | |
74 | * +-----------+-----------+-----------+-----------+ | |
75 | * 0020 ID | | ID | | | | RW | |
76 | * +-----------+-----------+-----------+-----------+ | |
77 | * | |
78 | * The physical APIC ID is used with physical interrupt | |
79 | * delivery modes. | |
80 | * | |
81 | * +-----------+-----------+-----------+-----------+ | |
82 | * 0030 VER | | | | | | |
83 | * +-----------+-----------+-----------+-----------+ | |
84 | * 0040 | | | | | | |
85 | * 0050 | | | | | | |
86 | * 0060 | | | | | | |
87 | * 0070 | | | | | | |
88 | * +-----------+-----------+-----------+-----------+ | |
89 | * 0080 TPR | | | | PRIO SUBC | | |
90 | * 0090 APR | | | | | | |
91 | * 00A0 PPR | | | | | | |
92 | * +-----------+-----------+-----------+-----------+ | |
93 | * | |
94 | * The Task Priority Register provides a priority threshold | |
95 | * mechanism for interrupting the processor. Only interrupts | |
96 | * with a higher priority then that specified in the TPR will | |
97 | * be served. Other interrupts are recorded and serviced | |
98 | * as soon as the TPR value decreases enough to allow that | |
99 | * (unless EOId by another APIC). | |
100 | * | |
101 | * PRIO (7:4). Main priority. If 15 the APIC will not | |
102 | * accept any interrupts. | |
103 | * SUBC (3:0) Sub priority. See APR/PPR. | |
104 | * | |
105 | * | |
106 | * The Processor Priority Register determines whether a | |
107 | * pending interrupt can be dispensed to the processor. ISRV | |
108 | * Is the vector of the highest priority ISR bit set or | |
109 | * zero if no ISR bit is set. | |
110 | * | |
111 | * IF TPR[7:4] >= ISRV[7:4] | |
112 | * PPR[7:0] = TPR[7:0] | |
113 | * ELSE | |
114 | * PPR[7:0] = ISRV[7:4].000 | |
115 | * | |
116 | * The Arbitration Priority Register holds the current | |
117 | * lowest priority of the procsesor, a value used during | |
118 | * lowest-priority arbitration. | |
119 | * | |
120 | * IF (TPR[7:4] >= IRRV[7:4] AND TPR[7:4] > ISRV[7:4]) | |
121 | * APR[7:0] = TPR[7:0] | |
122 | * ELSE | |
123 | * APR[7:4] = max((TPR[7:4]&ISRV[7:4]),IRRV[7:4]).000 | |
124 | * | |
125 | * +-----------+-----------+-----------+-----------+ | |
126 | * 00B0 EOI | | | | | | |
127 | * +-----------+-----------+-----------+-----------+ | |
128 | * 00C0 | | | | | | |
129 | * +-----------+-----------+-----------+-----------+ | |
130 | * 00D0 LDR |LOG APICID | | | | | |
131 | * +-----------+-----------+-----------+-----------+ | |
132 | * 00E0 DFR |MODEL| | | | | | |
133 | * +-----------+-----------+-----------+-----------+ | |
134 | * | |
135 | * The logical APIC ID is used with logical interrupt | |
136 | * delivery modes. Interpretation of logical destination | |
137 | * information depends on the MODEL bits in the Destination | |
138 | * Format Regiuster. | |
139 | * | |
140 | * MODEL=1111 FLAT MODEL - The MDA is interpreted as | |
141 | * a decoded address. By setting | |
142 | * one bit in the LDR for each | |
143 | * local apic 8 APICs can coexist. | |
144 | * | |
145 | * MODEL=0000 CLUSTER MODEL - | |
146 | * | |
147 | * 31 ... 24 23 ... 16 15 ... 8 7 ... 0 | |
148 | * +-----------+-----------+-----------+-----------+ | |
149 | * 00F0 SVR | | | FE | vvvvvvvv | | |
150 | * +-----------+-----------+-----------+-----------+ | |
151 | * | |
152 | * Spurious interrupt vector register. The 4 low | |
153 | * vector bits must be programmed to 1111, e.g. | |
154 | * vvvv1111. | |
155 | * | |
bb467734 | 156 | * E - LAPIC enable (0 = disable, 1 = enable) |
c8fe38ae MD |
157 | * |
158 | * F - Focus processor disable (1 = disable, 0 = enable) | |
159 | * | |
160 | * NOTE: The handler for the spurious interrupt vector | |
161 | * should *NOT* issue an EOI because the spurious | |
162 | * interrupt does not effect the ISR. | |
163 | * | |
164 | * +-----------+-----------+-----------+-----------+ | |
165 | * 0100-0170 ISR| | | | | | |
166 | * 0180-01F0 TMR| | | | | | |
167 | * 0200-0270 IRR| | | | | | |
168 | * +-----------+-----------+-----------+-----------+ | |
169 | * | |
170 | * These registers represent 256 bits, one bit for each | |
171 | * possible interrupt. Interrupts 0-15 are reserved so | |
172 | * bits 0-15 are also reserved. | |
173 | * | |
174 | * TMR - Trigger mode register. Upon acceptance of an int | |
175 | * the corresponding bit is cleared for edge-trig and | |
176 | * set for level-trig. If the TMR bit is set (level), | |
177 | * the local APIC sends an EOI to all I/O APICs as | |
178 | * a result of software issuing an EOI command. | |
179 | * | |
180 | * IRR - Interrupt Request Register. Contains active | |
181 | * interrupt requests that have been accepted but not | |
182 | * yet dispensed by the current local APIC. The bit is | |
183 | * cleared and the corresponding ISR bit is set when | |
184 | * the INTA cycle is issued. | |
185 | * | |
186 | * ISR - Interrupt In-Service register. Interrupt has been | |
187 | * delivered but not yet fully serviced. Cleared when | |
188 | * an EOI is issued from the processor. An EOI will | |
189 | * also send an EOI to all I/O APICs if TMR was set. | |
190 | * | |
191 | * +-----------+-----------+-----------+-----------+ | |
192 | * 0280 ESR | | | | | | |
193 | * 0290-02F0 | | | | | | |
194 | * +--FEDCBA98-+--76543210-+--FEDCBA98-+-----------+ | |
195 | * 0300 ICR_LO | | XX | TL SDMMM | vector | | |
196 | * 0310 ICR_HI | DEST FIELD| | | | | |
197 | * +-----------+-----------+-----------+-----------+ | |
198 | * | |
199 | * The interrupt command register. Generally speaking | |
200 | * writing to ICR_LO initiates a command. All fields | |
201 | * are R/W except the 'S' (delivery status) field, which | |
202 | * is read-only. When | |
203 | * | |
204 | * | |
205 | * XX: Destination Shorthand field: | |
206 | * | |
207 | * 00 Use Destination field | |
208 | * 01 Self only. Dest field ignored. | |
209 | * 10 All including self (uses a | |
210 | * destination field of 0x0F) | |
211 | * 11 All excluding self (uses a | |
212 | * destination field of 0x0F) | |
213 | * | |
214 | * T: 1 = Level 0 = Edge Trigger modde, used for | |
215 | * the INIT level de-assert delivery mode only | |
216 | * to de-assert a request. | |
217 | * | |
218 | * L: 0 = De-Assert, 1 = Assert. Always write as | |
219 | * 1 when initiating a new command. Can only | |
220 | * write as 0 for INIT mode de-assertion of | |
221 | * command. | |
222 | * | |
223 | * S: 1 = Send Pending. Interrupt has been injected | |
224 | * but APIC has not yet accepted it. | |
225 | * | |
226 | * D: 0=physical 1=logical. In physical mode | |
227 | * only 24-27 of DEST FIELD is used from ICR_HI. | |
228 | * | |
229 | * MMM: 000 Fixed. Deliver to all processors according | |
230 | * to the ICR. Always treated as edge trig. | |
231 | * | |
232 | * 001 Lowest Priority. Deliver to just the | |
233 | * processor running at the lowest priority. | |
234 | * | |
235 | * 010 SMI. The vector must be 00B. Only edge | |
236 | * triggered is allowed. The vector field | |
237 | * must be programmed to zero (huh?). | |
238 | * | |
239 | * 011 <reserved> | |
240 | * | |
241 | * 100 NMI. Deliver as an NMI to all processors | |
242 | * listed in the destination field. The | |
243 | * vector is ignored. Alawys treated as | |
244 | * edge triggered. | |
245 | * | |
246 | * 101 INIT. Deliver as an INIT signal to all | |
247 | * processors (like FIXED). Vector is ignored | |
248 | * and it is always edge-triggered. | |
249 | * | |
250 | * 110 Start Up. Sends a special message between | |
251 | * cpus. the vector contains a start-up | |
252 | * address for MP boot protocol. | |
253 | * Always edge triggered. Note: a startup | |
254 | * int is not automatically tried in case of | |
255 | * failure. | |
256 | * | |
257 | * 111 <reserved> | |
258 | * | |
259 | * +-----------+--------10-+--FEDCBA98-+-----------+ | |
260 | * 0320 LTIMER | | TM | ---S---- | vector | | |
261 | * 0330 | | | | | | |
262 | * +-----------+--------10-+--FEDCBA98-+-----------+ | |
263 | * 0340 LVPCINT | | -M | ---S-MMM | vector | | |
264 | * 0350 LVINT0 | | -M | LRPS-MMM | vector | | |
265 | * 0360 LVINT1 | | -M | LRPS-MMM | vector | | |
266 | * 0370 LVERROR | | -M | -------- | vector | | |
267 | * +-----------+-----------+-----------+-----------+ | |
268 | * | |
269 | * T: 1 = periodic, 0 = one-shot | |
270 | * | |
271 | * M: 1 = masked | |
272 | * | |
273 | * L: 1 = level, 0 = edge | |
274 | * | |
275 | * R: For level triggered only, set to 1 when a | |
276 | * level int is accepted, cleared by EOI. | |
277 | * | |
278 | * P: Pin Polarity 0 = Active High, 1 = Active Low | |
279 | * | |
280 | * S: 1 = Send Pending. Interrupt has been injected | |
281 | * but APIC has not yet accepted it. | |
282 | * | |
283 | * MMM 000 = Fixed deliver to cpu according to LVT | |
284 | * | |
285 | * MMM 100 = NMI deliver as an NMI. Always edge | |
286 | * | |
287 | * MMM 111 = ExtInt deliver from 8259, routes INTA | |
288 | * bus cycle to external | |
289 | * controller. Controller is | |
290 | * expected to supply vector. | |
291 | * Always level. | |
292 | * | |
293 | * +-----------+-----------+-----------+-----------+ | |
294 | * 0380 TMR_ICR | | | | | | |
295 | * 0390 TMR_CCR | | | | | | |
296 | * +-----------+-----------+-----------+-----------+ | |
297 | * | |
298 | * The timer initial count register and current count | |
299 | * register (32 bits) | |
300 | * | |
301 | * +-----------+-----------+-----------+-----------+ | |
302 | * 03A0 | | | | | | |
303 | * 03B0 | | | | | | |
304 | * 03C0 | | | | | | |
305 | * 03D0 | | | | | | |
306 | * +-----------+-----------+-----------+-----------+ | |
307 | * 03E0 TMR_DCR | | | | d-dd | | |
308 | * +-----------+-----------+-----------+-----------+ | |
309 | * | |
310 | * The timer divide configuration register. d-dd is: | |
311 | * | |
312 | * 0000 - divide by 2 | |
313 | * 0001 - divide by 4 | |
314 | * 0010 - divide by 8 | |
315 | * 0011 - divide by 16 | |
316 | * 1000 - divide by 32 | |
317 | * 1001 - divide by 64 | |
318 | * 1010 - divide by 128 | |
319 | * 1011 - divide by 1 | |
320 | * | |
321 | * NOTE ON EOI: Upon receiving an EOI the APIC clears the highest priority | |
322 | * interrupt in the ISR and selects the next highest priority interrupt | |
323 | * for posting to the CPU. If the interrupt being EOId was level | |
324 | * triggered the APIC will send an EOI to all I/O APICs. For the moment | |
325 | * you can write garbage to the EOI register but for future compatibility | |
326 | * 0 should be written. | |
67534613 MD |
327 | * |
328 | * 03F0 SELF_IPI | |
329 | * 0400 EXT_FEAT | |
330 | * 0410 EXT_CTRL | |
331 | * 0420 EXT_SEOI | |
332 | * 0430 | |
333 | * 0440 | |
334 | * 0450 | |
335 | * 0460 | |
336 | * 0470 | |
337 | * 0480 EXT_IER0 | |
338 | * 0490 EXT_IER1 | |
339 | * 04A0 EXT_IER2 | |
340 | * 04B0 EXT_IER3 | |
341 | * 04C0 EXT_IER4 | |
342 | * 04D0 EXT_IER5 | |
343 | * 04E0 EXT_IER6 | |
344 | * 04F0 EXT_IER7 | |
345 | * 0500 EXT_LVT0 | |
346 | * 0510 EXT_LVT1 | |
347 | * 0520 EXT_LVT2 | |
348 | * 0530 EXT_LVT3 | |
c8fe38ae MD |
349 | */ |
350 | ||
351 | #ifndef LOCORE | |
352 | #include <sys/types.h> | |
353 | ||
354 | #define PAD3 int : 32; int : 32; int : 32 | |
355 | #define PAD4 int : 32; int : 32; int : 32; int : 32 | |
356 | ||
357 | struct LAPIC { | |
358 | /* reserved */ PAD4; | |
359 | /* reserved */ PAD4; | |
360 | u_int32_t id; PAD3; /* 0020 R/W */ | |
361 | u_int32_t version; PAD3; /* 0030 RO */ | |
362 | /* reserved */ PAD4; | |
363 | /* reserved */ PAD4; | |
364 | /* reserved */ PAD4; | |
365 | /* reserved */ PAD4; | |
366 | u_int32_t tpr; PAD3; | |
367 | u_int32_t apr; PAD3; | |
368 | u_int32_t ppr; PAD3; | |
369 | u_int32_t eoi; PAD3; | |
370 | /* reserved */ PAD4; | |
371 | u_int32_t ldr; PAD3; | |
372 | u_int32_t dfr; PAD3; | |
373 | u_int32_t svr; PAD3; | |
374 | u_int32_t isr0; PAD3; | |
375 | u_int32_t isr1; PAD3; | |
376 | u_int32_t isr2; PAD3; | |
377 | u_int32_t isr3; PAD3; | |
378 | u_int32_t isr4; PAD3; | |
379 | u_int32_t isr5; PAD3; | |
380 | u_int32_t isr6; PAD3; | |
381 | u_int32_t isr7; PAD3; | |
382 | u_int32_t tmr0; PAD3; | |
383 | u_int32_t tmr1; PAD3; | |
384 | u_int32_t tmr2; PAD3; | |
385 | u_int32_t tmr3; PAD3; | |
386 | u_int32_t tmr4; PAD3; | |
387 | u_int32_t tmr5; PAD3; | |
388 | u_int32_t tmr6; PAD3; | |
389 | u_int32_t tmr7; PAD3; | |
390 | u_int32_t irr0; PAD3; | |
391 | u_int32_t irr1; PAD3; | |
392 | u_int32_t irr2; PAD3; | |
393 | u_int32_t irr3; PAD3; | |
394 | u_int32_t irr4; PAD3; | |
395 | u_int32_t irr5; PAD3; | |
396 | u_int32_t irr6; PAD3; | |
397 | u_int32_t irr7; PAD3; | |
398 | u_int32_t esr; PAD3; | |
399 | /* reserved */ PAD4; | |
400 | /* reserved */ PAD4; | |
401 | /* reserved */ PAD4; | |
402 | /* reserved */ PAD4; | |
403 | /* reserved */ PAD4; | |
404 | /* reserved */ PAD4; | |
405 | /* reserved */ PAD4; | |
406 | u_int32_t icr_lo; PAD3; | |
407 | u_int32_t icr_hi; PAD3; | |
408 | u_int32_t lvt_timer; PAD3; | |
409 | /* reserved */ PAD4; | |
410 | u_int32_t lvt_pcint; PAD3; | |
411 | u_int32_t lvt_lint0; PAD3; | |
412 | u_int32_t lvt_lint1; PAD3; | |
413 | u_int32_t lvt_error; PAD3; | |
414 | u_int32_t icr_timer; PAD3; | |
67534613 | 415 | u_int32_t ccr_timer; PAD3; /* e9 */ |
c8fe38ae MD |
416 | /* reserved */ PAD4; |
417 | /* reserved */ PAD4; | |
418 | /* reserved */ PAD4; | |
419 | /* reserved */ PAD4; | |
67534613 MD |
420 | u_int32_t dcr_timer; PAD3; /* 3e */ |
421 | u_int32_t self_ipi; PAD3; /* 3f - Only in x2APIC */ | |
422 | u_int32_t ext_feat; PAD3; | |
423 | u_int32_t ext_ctrl; PAD3; | |
424 | u_int32_t ext_seoi; PAD3; | |
c8fe38ae | 425 | /* reserved */ PAD4; |
67534613 MD |
426 | /* reserved */ PAD4; |
427 | /* reserved */ PAD4; | |
428 | /* reserved */ PAD4; | |
429 | /* reserved */ PAD4; | |
430 | u_int32_t ext_ier0; PAD3; | |
431 | u_int32_t ext_ier1; PAD3; | |
432 | u_int32_t ext_ier2; PAD3; | |
433 | u_int32_t ext_ier3; PAD3; | |
434 | u_int32_t ext_ier4; PAD3; | |
435 | u_int32_t ext_ier5; PAD3; | |
436 | u_int32_t ext_ier6; PAD3; | |
437 | u_int32_t ext_ier7; PAD3; | |
438 | struct { /* 50 */ | |
439 | u_int32_t lvt; PAD3; | |
440 | } ext_lvt[16]; | |
441 | } __packed; | |
c8fe38ae MD |
442 | |
443 | typedef struct LAPIC lapic_t; | |
444 | ||
445 | /****************************************************************************** | |
446 | * I/O APIC structure | |
447 | */ | |
448 | ||
449 | struct IOAPIC { | |
450 | u_int32_t ioregsel; PAD3; | |
451 | u_int32_t iowin; PAD3; | |
452 | }; | |
453 | ||
454 | typedef struct IOAPIC ioapic_t; | |
455 | ||
456 | #undef PAD4 | |
457 | #undef PAD3 | |
458 | ||
f89b4a45 SZ |
459 | /* X2APIC */ |
460 | #define MSR_X2APIC_BASE 0x00000800 | |
461 | #define MSR_X2APIC_ID 0x00000802 | |
462 | #define MSR_X2APIC_EOI 0x0000080b | |
463 | #define MSR_X2APIC_DFR_RSVD 0x0000080e | |
464 | #define MSR_X2APIC_ICR 0x00000830 | |
465 | #define MSR_X2APIC_ICR_RSVD 0x00000831 | |
466 | #define MSR_X2APIC_ICR_TIMER 0x00000838 | |
467 | #define MSR_X2APIC_CCR_TIMER 0x00000839 | |
468 | #define MSR_X2APIC_SELFIPI 0x0000083f | |
469 | ||
470 | #define MSR_X2APIC_MIN MSR_X2APIC_ID | |
471 | #define MSR_X2APIC_MAX MSR_X2APIC_SELFIPI | |
472 | ||
473 | #define LAPIC2MSR(field) __extension__ ({ \ | |
474 | uint32_t __msr; \ | |
475 | \ | |
476 | __msr = MSR_X2APIC_BASE + \ | |
477 | (__offsetof(struct LAPIC, field) >> 4); \ | |
478 | KASSERT(__msr >= MSR_X2APIC_MIN && \ | |
479 | __msr <= MSR_X2APIC_MAX && \ | |
480 | __msr != MSR_X2APIC_DFR_RSVD && \ | |
481 | __msr != MSR_X2APIC_ICR && \ | |
482 | __msr != MSR_X2APIC_ICR_RSVD, \ | |
483 | ("invalid MSR 0x%08x", __msr)); \ | |
484 | __msr; \ | |
485 | }) | |
486 | ||
c8fe38ae MD |
487 | #endif /* !LOCORE */ |
488 | ||
489 | ||
490 | /****************************************************************************** | |
491 | * various code 'logical' values | |
492 | */ | |
493 | ||
494 | /* | |
495 | * TPR loads to prioritize which cpu grabs an interrupt | |
496 | * | |
497 | * (note: some fields of the TPR are reserved) | |
498 | */ | |
499 | #define LOPRIO_LEVEL 0x00000010 /* TPR of CPU accepting INTs */ | |
500 | #define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */ | |
501 | ||
502 | /****************************************************************************** | |
503 | * LOCAL APIC defines | |
504 | */ | |
505 | ||
506 | /* | |
507 | * default physical location for the LOCAL (CPU) APIC | |
508 | */ | |
509 | #define DEFAULT_APIC_BASE 0xfee00000 | |
510 | ||
511 | /* | |
512 | * lapic.id (rw) | |
513 | */ | |
514 | #define APIC_ID_MASK 0xff000000 | |
515 | #define APIC_ID_SHIFT 24 | |
516 | #define APIC_ID_CLUSTER 0xf0 | |
517 | #define APIC_ID_CLUSTER_ID 0x0f | |
518 | #define APIC_MAX_CLUSTER 0xe | |
519 | #define APIC_MAX_INTRACLUSTER_ID 3 | |
520 | #define APIC_ID_CLUSTER_SHIFT 4 | |
521 | ||
b38251dc MN |
522 | #define APIC_ID(id) (((id) & APIC_ID_MASK) >> APIC_ID_SHIFT) |
523 | ||
c8fe38ae MD |
524 | /* |
525 | * lapic.ver (ro) | |
526 | */ | |
527 | #define APIC_VER_VERSION 0x000000ff | |
528 | #define APIC_VER_MAXLVT 0x00ff0000 | |
529 | #define MAXLVTSHIFT 16 | |
67534613 MD |
530 | #define APIC_VER_EOI_SUPP 0x01000000 |
531 | #define APIC_VER_AMD_EXT_SPACE 0x80000000 | |
c8fe38ae MD |
532 | |
533 | /* | |
534 | * lapic.ldr (rw) | |
535 | */ | |
536 | #define APIC_LDR_RESERVED 0x00ffffff | |
537 | ||
538 | /* | |
539 | * lapic.dfr (rw) | |
540 | * | |
541 | * The logical APIC ID is used with logical interrupt | |
542 | * delivery modes. Interpretation of logical destination | |
543 | * information depends on the MODEL bits in the Destination | |
544 | * Format Regiuster. | |
545 | * | |
546 | * MODEL=1111 FLAT MODEL - The MDA is interpreted as | |
547 | * a decoded address. By setting | |
548 | * one bit in the LDR for each | |
549 | * local apic 8 APICs can coexist. | |
550 | * | |
551 | * MODEL=0000 CLUSTER MODEL - | |
552 | */ | |
553 | #define APIC_DFR_RESERVED 0x0fffffff | |
554 | #define APIC_DFR_MODEL_MASK 0xf0000000 | |
555 | #define APIC_DFR_MODEL_FLAT 0xf0000000 | |
556 | #define APIC_DFR_MODEL_CLUSTER 0x00000000 | |
557 | ||
558 | /* | |
559 | * lapic.svr | |
560 | * | |
561 | * Contains the spurious interrupt vector and bits to enable/disable | |
562 | * the local apic and focus processor. | |
563 | */ | |
564 | #define APIC_SVR_VECTOR 0x000000ff | |
565 | #define APIC_SVR_ENABLE 0x00000100 | |
566 | #define APIC_SVR_FOCUS_DISABLE 0x00000200 | |
67534613 | 567 | #define APIC_SVR_EOI_SUPP 0x00001000 |
c8fe38ae MD |
568 | |
569 | /* | |
570 | * lapic.tpr | |
571 | * | |
572 | * PRIO (7:4). Main priority. If 15 the APIC will not | |
573 | * accept any interrupts. | |
574 | * SUBC (3:0) Sub priority. See APR/PPR. | |
575 | */ | |
576 | #define APIC_TPR_PRIO 0x000000ff | |
577 | #define APIC_TPR_INT 0x000000f0 | |
578 | #define APIC_TPR_SUB 0x0000000f | |
579 | ||
580 | /* | |
581 | * lapic.icr_lo -------- ----XXRR TL-SDMMM vvvvvvvv | |
582 | * | |
583 | * The interrupt command register. Generally speaking | |
584 | * writing to ICR_LO initiates a command. All fields | |
585 | * are R/W except the 'S' (delivery status) field, which | |
586 | * is read-only. When | |
587 | * | |
588 | * XX: Destination Shorthand field: | |
589 | * | |
590 | * 00 - Use Destination field | |
591 | * 01 - Self only. Dest field ignored. | |
592 | * 10 - All including self (uses a | |
593 | * destination field of 0x0F) | |
594 | * 11 - All excluding self (uses a | |
595 | * destination field of 0x0F) | |
596 | * | |
597 | * RR: RR mode (? needs documentation) | |
598 | * | |
599 | * T: 1 = Level 0 = Edge Trigger modde, used for | |
600 | * the INIT level de-assert delivery mode only | |
601 | * to de-assert a request. | |
602 | * | |
603 | * L: 0 = De-Assert, 1 = Assert. Always write as | |
604 | * 1 when initiating a new command. Can only | |
605 | * write as 0 for INIT mode de-assertion of | |
606 | * command. | |
607 | * | |
608 | * S: 1 = Send Pending. Interrupt has been injected but the APIC | |
609 | * has not yet accepted it. | |
610 | * | |
611 | * D: 0 = physical 1 = logical. In physical mode only bits 24-27 | |
612 | * of the DEST field is used from ICR_HI. | |
613 | * | |
614 | * MMM: Delivery mode | |
615 | * | |
616 | * 000 - Fixed. Deliver to all processors according to the | |
617 | * ICR. Always treated as edge triggered. | |
618 | * | |
619 | * 001 - Lowest Priority. Deliver to just the processor | |
620 | * running at the lowest priority. | |
621 | * | |
622 | * 010 - SMI. The vector must be 00B. Only edge triggered | |
623 | * is allowed. The vector field must be programmed to | |
624 | * 0 (huh?) | |
625 | * | |
626 | * 011 - RR Delivery mode (?? needs documentation). | |
627 | * | |
628 | * 100 - NMI. Deliver as an NMI to all processors listed in | |
629 | * the destination field. The vector is ignored. Always | |
630 | * treated as edge triggered. | |
631 | * | |
632 | * 101 - INIT. Deliver as an INIT signal to all processors | |
633 | * (like FIXED) according to the ICR. The vector is | |
634 | * ignored and delivery is always edge-triggered. | |
635 | * | |
636 | * 110 - Startup. Send a special message between cpus. The | |
637 | * vector contains a startup address for the MP boot | |
638 | * protocol. Always edge triggered. Note: a startup | |
639 | * interrupt is not automatically tried in case of failure. | |
640 | * | |
641 | * 111 - <reserved> | |
642 | */ | |
643 | #define APIC_VECTOR_MASK 0x000000ff | |
644 | ||
645 | #define APIC_DELMODE_MASK 0x00000700 | |
646 | #define APIC_DELMODE_FIXED 0x00000000 | |
647 | #define APIC_DELMODE_LOWPRIO 0x00000100 | |
648 | #define APIC_DELMODE_SMI 0x00000200 | |
649 | #define APIC_DELMODE_RR 0x00000300 | |
650 | #define APIC_DELMODE_NMI 0x00000400 | |
651 | #define APIC_DELMODE_INIT 0x00000500 | |
652 | #define APIC_DELMODE_STARTUP 0x00000600 | |
653 | #define APIC_DELMODE_RESV7 0x00000700 | |
654 | ||
655 | #define APIC_DESTMODE_MASK 0x00000800 | |
656 | #define APIC_DESTMODE_PHY 0x00000000 | |
657 | #define APIC_DESTMODE_LOG 0x00000800 | |
658 | ||
659 | #define APIC_DELSTAT_MASK 0x00001000 | |
660 | #define APIC_DELSTAT_IDLE 0x00000000 | |
661 | #define APIC_DELSTAT_PEND 0x00001000 | |
662 | ||
663 | #define APIC_LEVEL_MASK 0x00004000 | |
664 | #define APIC_LEVEL_DEASSERT 0x00000000 | |
665 | #define APIC_LEVEL_ASSERT 0x00004000 | |
666 | ||
667 | #define APIC_TRIGMOD_MASK 0x00008000 | |
668 | #define APIC_TRIGMOD_EDGE 0x00000000 | |
669 | #define APIC_TRIGMOD_LEVEL 0x00008000 | |
670 | ||
671 | #define APIC_RRSTAT_MASK 0x00030000 | |
672 | #define APIC_RRSTAT_INVALID 0x00000000 | |
673 | #define APIC_RRSTAT_INPROG 0x00010000 | |
674 | #define APIC_RRSTAT_VALID 0x00020000 | |
675 | #define APIC_RRSTAT_RESV 0x00030000 | |
676 | ||
677 | #define APIC_DEST_MASK 0x000c0000 | |
678 | #define APIC_DEST_DESTFLD 0x00000000 | |
679 | #define APIC_DEST_SELF 0x00040000 | |
680 | #define APIC_DEST_ALLISELF 0x00080000 | |
681 | #define APIC_DEST_ALLESELF 0x000c0000 | |
682 | ||
683 | #define APIC_ICRLO_RESV_MASK 0xfff02000 | |
684 | ||
685 | /* | |
686 | * lapic.icr_hi | |
687 | */ | |
688 | #define APIC_ICRH_ID_MASK APIC_ID_MASK | |
689 | ||
690 | /* | |
691 | * lapic.lvt_timer | |
692 | * lapic.lvt_pcint | |
693 | * lapic.lvt_lint0 | |
694 | * lapic.lvt_lint1 | |
695 | * lapic.lvt_error | |
696 | * | |
697 | * +-----------+--------10-+--FEDCBA98-+-----------+ | |
698 | * 0320 LTIMER | | TM | ---S---- | vector | | |
699 | * 0330 | | | | | | |
700 | * +-----------+--------10-+--FEDCBA98-+-----------+ | |
701 | * 0340 LVPCINT | | -M | ---S-MMM | vector | | |
702 | * 0350 LVINT0 | | -M | LRPS-MMM | vector | | |
703 | * 0360 LVINT1 | | -M | LRPS-MMM | vector | | |
704 | * 0370 LVERROR | | -M | -------- | vector | | |
705 | * +-----------+-----------+-----------+-----------+ | |
706 | * | |
707 | * T: 1 = periodic, 0 = one-shot | |
708 | * (LTIMER only) | |
709 | * | |
710 | * M: 1 = masked | |
711 | * | |
712 | * L: 1 = level, 0 = edge | |
713 | * (LVINT0/1 only) | |
714 | * | |
715 | * R: For level triggered only, set to 1 when a | |
716 | * level int is accepted, cleared by EOI. | |
717 | * (LVINT0/1 only) | |
718 | * | |
719 | * P: Pin Polarity 0 = Active High, 1 = Active Low | |
720 | * (LVINT0/1 only) | |
721 | * | |
722 | * S: 1 = Send Pending. Interrupt has been injected | |
723 | * but APIC has not yet accepted it. | |
724 | * | |
725 | * MMM 000 = Fixed deliver to cpu according to LVT | |
726 | * | |
727 | * MMM 100 = NMI deliver as an NMI. Always edge | |
728 | * | |
729 | * MMM 111 = ExtInt deliver from 8259, routes INTA | |
730 | * bus cycle to external | |
731 | * controller. Controller is | |
732 | * expected to supply vector. | |
733 | * Always level. | |
734 | */ | |
735 | #define APIC_LVT_VECTOR 0x000000ff | |
736 | ||
737 | #define APIC_LVT_DM_MASK 0x00000700 | |
738 | #define APIC_LVT_DM_FIXED 0x00000000 | |
739 | #define APIC_LVT_DM_NMI 0x00000400 | |
740 | #define APIC_LVT_DM_EXTINT 0x00000700 | |
741 | ||
742 | #define APIC_LVT_DS 0x00001000 /* (S) Send Pending */ | |
743 | #define APIC_LVT_POLARITY_MASK 0x00002000 | |
744 | #define APIC_LVT_POLARITY_LO 0x00002000 /* (P) Pin Polarity */ | |
745 | #define APIC_LVT_POLARITY_HI 0x00000000 | |
746 | #define APIC_LVT_LEVELSTATUS 0x00004000 /* (R) level trig status */ | |
747 | #define APIC_LVT_TRIG_MASK 0x00008000 | |
748 | #define APIC_LVT_LEVELTRIG 0x00008000 /* (L) 1 = level, 0 = edge */ | |
749 | #define APIC_LVT_MASKED 0x00010000 /* (M) 1 = masked */ | |
750 | ||
751 | /* | |
752 | * lapic.lvt_timer | |
753 | */ | |
754 | #define APIC_LVTT_VECTOR APIC_LVT_VECTOR | |
755 | #define APIC_LVTT_DS APIC_LVT_DS | |
756 | #define APIC_LVTT_MASKED APIC_LVT_MASKED | |
757 | #define APIC_LVTT_PERIODIC 0x00020000 | |
185b27fa | 758 | #define APIC_LVTT_TSCDLT 0x00040000 |
c8fe38ae MD |
759 | |
760 | #define APIC_TIMER_MAX_COUNT 0xffffffff | |
761 | ||
762 | /* | |
763 | * lapic.icr_timer - initial count register (32 bits) | |
764 | * lapic.ccr_timer - current count register (32 bits) | |
765 | */ | |
766 | ||
767 | /* | |
768 | * lapic.dcr_timer - timer divider register | |
769 | * | |
770 | * d0dd | |
771 | * | |
772 | * 0000 - divide by 2 | |
773 | * 0001 - divide by 4 | |
774 | * 0010 - divide by 8 | |
775 | * 0011 - divide by 16 | |
776 | * 1000 - divide by 32 | |
777 | * 1001 - divide by 64 | |
778 | * 1010 - divide by 128 | |
779 | * 1011 - divide by 1 | |
780 | */ | |
781 | #define APIC_TDCR_2 0x00 | |
782 | #define APIC_TDCR_4 0x01 | |
783 | #define APIC_TDCR_8 0x02 | |
784 | #define APIC_TDCR_16 0x03 | |
785 | #define APIC_TDCR_32 0x08 | |
786 | #define APIC_TDCR_64 0x09 | |
787 | #define APIC_TDCR_128 0x0a | |
788 | #define APIC_TDCR_1 0x0b | |
789 | ||
67534613 MD |
790 | /* |
791 | * lapic.self_ipi (x2APIC only) | |
792 | */ | |
793 | /* | |
794 | * lapic.ext_feat (AMD only) | |
795 | */ | |
796 | #define APIC_EXTFEAT_MASK 0x00ff0000 | |
797 | #define APIC_EXTFEAT_SHIFT 16 | |
798 | #define APIC_EXTFEAT_EXTID_CAP 0x00000004 | |
799 | #define APIC_EXTFEAT_SEIO_CAP 0x00000002 | |
800 | #define APIC_EXTFEAT_IER_CAP 0x00000001 | |
801 | ||
802 | /* | |
803 | * lapic.ext_ctrl | |
804 | * lapic.ext_seoi | |
805 | * lapic.ext_ier{0-7} | |
806 | */ | |
807 | /* | |
808 | * lapic.ext_lvt[N].lvt | |
809 | */ | |
810 | #define APIC_EXTLVT_IBS 0 /* Instruction based sampling */ | |
811 | #define APIC_EXTLVT_MCA 1 /* MCE thresholding */ | |
812 | #define APIC_EXTLVT_DEI 2 /* Deferred error interrupt */ | |
813 | #define APIC_EXTLVT_SBI 3 /* Sideband interface */ | |
814 | ||
c8fe38ae MD |
815 | /****************************************************************************** |
816 | * I/O APIC defines | |
817 | */ | |
818 | ||
819 | /* default physical locations of an IO APIC */ | |
820 | #define DEFAULT_IO_APIC_BASE 0xfec00000 | |
821 | ||
822 | /* window register offset */ | |
823 | #define IOAPIC_WINDOW 0x10 | |
824 | ||
825 | /* | |
826 | * indexes into IO APIC (index into array of 32 bit entities) | |
827 | */ | |
828 | #define IOAPIC_ID 0x00 | |
829 | #define IOAPIC_VER 0x01 | |
830 | #define IOAPIC_ARB 0x02 | |
831 | #define IOAPIC_REDTBL 0x10 | |
832 | #define IOAPIC_REDTBL0 IOAPIC_REDTBL | |
833 | #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) | |
834 | #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) | |
835 | #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) | |
836 | #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) | |
837 | #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) | |
838 | #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) | |
839 | #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) | |
840 | #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) | |
841 | #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) | |
842 | #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) | |
843 | #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) | |
844 | #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) | |
845 | #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) | |
846 | #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) | |
847 | #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) | |
848 | #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) | |
849 | #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) | |
850 | #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) | |
851 | #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) | |
852 | #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) | |
853 | #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) | |
854 | #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) | |
855 | #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) | |
856 | ||
857 | /* fields in VER */ | |
858 | #define IOART_VER_VERSION 0x000000ff | |
859 | #define IOART_VER_MAXREDIR 0x00ff0000 | |
860 | #define MAXREDIRSHIFT 16 | |
861 | ||
862 | /* | |
863 | * fields in the IO APIC's redirection table entries | |
864 | */ | |
865 | ||
866 | /* | |
867 | * High 32 bit word. The high 8 bits contain the destination field. | |
868 | * | |
869 | * If this entry is set up for Physical Mode, bits 59:56 (the low 4 bits | |
870 | * of the 8 bit destination field) contain an APIC ID. | |
871 | * | |
872 | * If this entry is set up for Logical Mode, the destination field potentially | |
873 | * defines a set of processors. Bits 63:56 (all 8 bits) specify the logical | |
874 | * destination address. | |
875 | * | |
876 | * Current we use IOART_HI_DEST_BROADCAST to broadcast to all LAPICs | |
877 | */ | |
878 | #define IOART_HI_DEST_MASK APIC_ID_MASK | |
879 | #define IOART_HI_DEST_RESV ~APIC_ID_MASK | |
880 | #define IOART_HI_DEST_BROADCAST IOART_HI_DEST_MASK | |
46d4e165 | 881 | #define IOART_HI_DEST_SHIFT 24 |
c8fe38ae MD |
882 | |
883 | /* | |
884 | * Low 32 bit word | |
885 | */ | |
886 | #define IOART_RESV 0x00fe0000 /* reserved */ | |
887 | ||
888 | /* | |
889 | * Interrupt mask bit. If 1 the interrupt is masked. An edge sensitive | |
890 | * interrupt which is masked will be lost. | |
891 | */ | |
892 | #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ | |
893 | #define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ | |
894 | #define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ | |
895 | ||
896 | /* | |
897 | * Select trigger mode. | |
898 | */ | |
899 | #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ | |
900 | #define IOART_TRGREDG 0x00000000 /* edge */ | |
901 | #define IOART_TRGRLVL 0x00008000 /* level */ | |
902 | ||
903 | /* | |
904 | * Remote IRR. Only applies to level triggered interrupts, this bit | |
905 | * is set to 1 when the IOAPIC has delivered a level triggered interrupt | |
906 | * to a local APIC. It is cleared when the LAPIC EOI's the interrupt. | |
907 | * This field is read-only. | |
908 | */ | |
909 | #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ | |
910 | ||
911 | /* | |
912 | * Select interrupt pin polarity | |
913 | */ | |
914 | #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ | |
915 | #define IOART_INTAHI 0x00000000 /* active high */ | |
916 | #define IOART_INTALO 0x00002000 /* active low */ | |
917 | ||
918 | /* | |
919 | * Delivery Status (read only). 0 = no interrupt pending, 1 = interrupt | |
920 | * pending for tranmission to an LAPIC. Note that this bit does not | |
921 | * indicate whether the interrupt has been processed or is undergoing | |
922 | * processing by a cpu. | |
923 | */ | |
924 | #define IOART_DELIVS 0x00001000 /* RO: delivery status */ | |
925 | ||
926 | /* | |
927 | * Destination mode. | |
928 | * | |
929 | * In physical mode the destination APIC is identified by its ID. | |
b9f7ba13 | 930 | * Bits 56-63 specify the 8 bit APIC ID. |
c8fe38ae MD |
931 | * |
932 | * In logical mode destinations are identified by matching on the logical | |
933 | * destination under the control of the destination format register and | |
934 | * logical destination register in each local APIC. | |
935 | * | |
936 | */ | |
937 | #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ | |
938 | #define IOART_DESTPHY 0x00000000 /* physical */ | |
939 | #define IOART_DESTLOG 0x00000800 /* logical */ | |
940 | ||
941 | /* | |
942 | * Delivery mode. | |
943 | * | |
944 | * 000 Fixed Deliver the signal on the INTR signal for | |
945 | * all processor core's LAPICs listed in the | |
946 | * destination. The trigger mode may be | |
947 | * edge or level. | |
948 | * | |
949 | * 001 Lowest Pri Deliver to the processor core whos LAPIC | |
950 | * is operating at the lowest priority (TPR). | |
951 | * The trigger mode may be edge or level. | |
952 | * | |
953 | * 010 SMI System management interrupt. the vector | |
954 | * information is ignored but must be programmed | |
955 | * to all zero's for future compatibility. | |
956 | * Must be edge triggered. | |
957 | * | |
958 | * 011 Reserved | |
959 | * | |
960 | * 100 NMI Deliver on the NMI signal for all cpu cores | |
961 | * listed in the destination. Vector information | |
962 | * is ignored. NMIs are treated as edge triggered | |
963 | * interrupts even if programmed as level | |
964 | * triggered. For proper operation the pin must | |
965 | * be programmed as an edge trigger. | |
966 | * | |
967 | * 101 INIT Deliver to all processor cores listed in | |
968 | * the destination by asserting their INIT signal. | |
969 | * All addressed LAPICs will assume their INIT | |
970 | * state. Always treated as edge-triggered even | |
971 | * if programmed as level. For proper operation | |
972 | * the pin must be programed as an edge trigger. | |
973 | * | |
974 | * 110 Reserved | |
975 | * | |
976 | * 111 ExINT Deliver as an INTR signal to all processor | |
977 | * cores listed in the destination as an | |
978 | * interrupt originating in an externally | |
979 | * connected interrupt controller. | |
980 | * The INTA cycle corresponding to this ExINT | |
981 | * will be routed to the external controller | |
982 | * that is expected to supply the vector. | |
983 | * Must be edge triggered. | |
984 | * | |
985 | */ | |
986 | #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ | |
987 | #define IOART_DELFIXED 0x00000000 /* fixed */ | |
988 | #define IOART_DELLOPRI 0x00000100 /* lowest priority */ | |
989 | #define IOART_DELSMI 0x00000200 /* System Management INT */ | |
990 | #define IOART_DELRSV1 0x00000300 /* reserved */ | |
991 | #define IOART_DELNMI 0x00000400 /* NMI signal */ | |
992 | #define IOART_DELINIT 0x00000500 /* INIT signal */ | |
993 | #define IOART_DELRSV2 0x00000600 /* reserved */ | |
994 | #define IOART_DELEXINT 0x00000700 /* External INTerrupt */ | |
995 | ||
996 | /* | |
997 | * The interrupt vector. Valid values range from 0x10 to 0xFE. | |
998 | */ | |
999 | #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ | |
1000 | ||
1001 | #endif /* _MACHINE_APIC_H_ */ |