| 1 | /*- |
| 2 | * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer, |
| 10 | * without modification. |
| 11 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 12 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any |
| 13 | * redistribution must be conditioned upon including a substantially |
| 14 | * similar Disclaimer requirement for further binary redistribution. |
| 15 | * |
| 16 | * NO WARRANTY |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 18 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 19 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY |
| 20 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL |
| 21 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, |
| 22 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER |
| 25 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | * THE POSSIBILITY OF SUCH DAMAGES. |
| 28 | * |
| 29 | * $FreeBSD: head/sys/dev/ath/if_athvar.h 203683 2010-02-08 20:23:20Z rpaulo $ |
| 30 | */ |
| 31 | |
| 32 | /* |
| 33 | * Defintions for the Atheros Wireless LAN controller driver. |
| 34 | */ |
| 35 | #ifndef _DEV_ATH_ATHVAR_H |
| 36 | #define _DEV_ATH_ATHVAR_H |
| 37 | |
| 38 | #include <dev/netif/ath/hal/ath_hal/ah.h> |
| 39 | #include <dev/netif/ath/hal/ath_hal/ah_desc.h> |
| 40 | #include <netproto/802_11/ieee80211_radiotap.h> |
| 41 | #include <dev/netif/ath/ath/if_athioctl.h> |
| 42 | #include <dev/netif/ath/ath/if_athrate.h> |
| 43 | |
| 44 | #define ATH_TIMEOUT 1000 |
| 45 | |
| 46 | #ifndef ATH_RXBUF |
| 47 | #define ATH_RXBUF 40 /* number of RX buffers */ |
| 48 | #endif |
| 49 | #ifndef ATH_TXBUF |
| 50 | #define ATH_TXBUF 200 /* number of TX buffers */ |
| 51 | #endif |
| 52 | #define ATH_BCBUF 4 /* number of beacon buffers */ |
| 53 | |
| 54 | #define ATH_TXDESC 10 /* number of descriptors per buffer */ |
| 55 | #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ |
| 56 | #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ |
| 57 | #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ |
| 58 | |
| 59 | #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ |
| 60 | #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ |
| 61 | #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ |
| 62 | |
| 63 | /* |
| 64 | * The key cache is used for h/w cipher state and also for |
| 65 | * tracking station state such as the current tx antenna. |
| 66 | * We also setup a mapping table between key cache slot indices |
| 67 | * and station state to short-circuit node lookups on rx. |
| 68 | * Different parts have different size key caches. We handle |
| 69 | * up to ATH_KEYMAX entries (could dynamically allocate state). |
| 70 | */ |
| 71 | #define ATH_KEYMAX 128 /* max key cache size we handle */ |
| 72 | #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ |
| 73 | |
| 74 | struct taskqueue; |
| 75 | struct kthread; |
| 76 | struct ath_buf; |
| 77 | |
| 78 | /* driver-specific node state */ |
| 79 | struct ath_node { |
| 80 | struct ieee80211_node an_node; /* base class */ |
| 81 | u_int8_t an_mgmtrix; /* min h/w rate index */ |
| 82 | u_int8_t an_mcastrix; /* mcast h/w rate index */ |
| 83 | struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ |
| 84 | /* variable-length rate control state follows */ |
| 85 | }; |
| 86 | #define ATH_NODE(ni) ((struct ath_node *)(ni)) |
| 87 | #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) |
| 88 | |
| 89 | #define ATH_RSSI_LPF_LEN 10 |
| 90 | #define ATH_RSSI_DUMMY_MARKER 0x127 |
| 91 | #define ATH_EP_MUL(x, mul) ((x) * (mul)) |
| 92 | #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) |
| 93 | #define ATH_LPF_RSSI(x, y, len) \ |
| 94 | ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) |
| 95 | #define ATH_RSSI_LPF(x, y) do { \ |
| 96 | if ((y) >= -20) \ |
| 97 | x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ |
| 98 | } while (0) |
| 99 | #define ATH_EP_RND(x,mul) \ |
| 100 | ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) |
| 101 | #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) |
| 102 | |
| 103 | struct ath_buf { |
| 104 | STAILQ_ENTRY(ath_buf) bf_list; |
| 105 | int bf_nseg; |
| 106 | uint16_t bf_txflags; /* tx descriptor flags */ |
| 107 | uint16_t bf_flags; /* status flags (below) */ |
| 108 | struct ath_desc *bf_desc; /* virtual addr of desc */ |
| 109 | struct ath_desc_status bf_status; /* tx/rx status */ |
| 110 | bus_addr_t bf_daddr; /* physical addr of desc */ |
| 111 | bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ |
| 112 | struct mbuf *bf_m; /* mbuf for buf */ |
| 113 | struct ieee80211_node *bf_node; /* pointer to the node */ |
| 114 | bus_size_t bf_mapsize; |
| 115 | #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ |
| 116 | bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; |
| 117 | }; |
| 118 | typedef STAILQ_HEAD(, ath_buf) ath_bufhead; |
| 119 | |
| 120 | #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ |
| 121 | |
| 122 | /* |
| 123 | * DMA state for tx/rx descriptors. |
| 124 | */ |
| 125 | struct ath_descdma { |
| 126 | const char* dd_name; |
| 127 | struct ath_desc *dd_desc; /* descriptors */ |
| 128 | bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ |
| 129 | bus_size_t dd_desc_len; /* size of dd_desc */ |
| 130 | bus_dma_segment_t dd_dseg; |
| 131 | bus_dma_tag_t dd_dmat; /* bus DMA tag */ |
| 132 | bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ |
| 133 | struct ath_buf *dd_bufptr; /* associated buffers */ |
| 134 | }; |
| 135 | |
| 136 | /* |
| 137 | * Data transmit queue state. One of these exists for each |
| 138 | * hardware transmit queue. Packets sent to us from above |
| 139 | * are assigned to queues based on their priority. Not all |
| 140 | * devices support a complete set of hardware transmit queues. |
| 141 | * For those devices the array sc_ac2q will map multiple |
| 142 | * priorities to fewer hardware queues (typically all to one |
| 143 | * hardware queue). |
| 144 | */ |
| 145 | struct ath_txq { |
| 146 | u_int axq_qnum; /* hardware q number */ |
| 147 | #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ |
| 148 | u_int axq_ac; /* WME AC */ |
| 149 | u_int axq_flags; |
| 150 | #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ |
| 151 | u_int axq_depth; /* queue depth (stat only) */ |
| 152 | u_int axq_intrcnt; /* interrupt count */ |
| 153 | u_int32_t *axq_link; /* link ptr in last TX desc */ |
| 154 | STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ |
| 155 | struct lock axq_lock; /* lock on q and link */ |
| 156 | char axq_name[12]; /* e.g. "ath0_txq4" */ |
| 157 | }; |
| 158 | |
| 159 | #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ |
| 160 | ksnprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ |
| 161 | device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ |
| 162 | lockinit(&(_tq)->axq_lock, (_tq)->axq_name, 0, 0); \ |
| 163 | } while (0) |
| 164 | #define ATH_TXQ_LOCK_DESTROY(_tq) lockuninit(&(_tq)->axq_lock) |
| 165 | #define ATH_TXQ_LOCK(_tq) lockmgr(&(_tq)->axq_lock, LK_EXCLUSIVE) |
| 166 | #define ATH_TXQ_UNLOCK(_tq) lockmgr(&(_tq)->axq_lock, LK_RELEASE) |
| 167 | #define ATH_TXQ_LOCK_ASSERT(_tq) \ |
| 168 | KKASSERT(lockstatus(&(_tq)->axq_lock, curthread) == LK_EXCLUSIVE) |
| 169 | |
| 170 | #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ |
| 171 | STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ |
| 172 | (_tq)->axq_depth++; \ |
| 173 | } while (0) |
| 174 | #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ |
| 175 | STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ |
| 176 | (_tq)->axq_depth--; \ |
| 177 | } while (0) |
| 178 | /* NB: this does not do the "head empty check" that STAILQ_LAST does */ |
| 179 | #define ATH_TXQ_LAST(_tq) \ |
| 180 | ((struct ath_buf *)(void *) \ |
| 181 | ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) |
| 182 | |
| 183 | struct ath_vap { |
| 184 | struct ieee80211vap av_vap; /* base class */ |
| 185 | int av_bslot; /* beacon slot index */ |
| 186 | struct ath_buf *av_bcbuf; /* beacon buffer */ |
| 187 | struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ |
| 188 | struct ath_txq av_mcastq; /* buffered mcast s/w queue */ |
| 189 | |
| 190 | void (*av_recv_mgmt)(struct ieee80211_node *, |
| 191 | struct mbuf *, int, int, int); |
| 192 | int (*av_newstate)(struct ieee80211vap *, |
| 193 | enum ieee80211_state, int); |
| 194 | void (*av_bmiss)(struct ieee80211vap *); |
| 195 | }; |
| 196 | #define ATH_VAP(vap) ((struct ath_vap *)(vap)) |
| 197 | |
| 198 | struct taskqueue; |
| 199 | struct ath_tx99; |
| 200 | |
| 201 | struct ath_softc { |
| 202 | struct arpcom arpcom; |
| 203 | struct ifnet *sc_ifp; /* interface common */ |
| 204 | struct ath_stats sc_stats; /* interface statistics */ |
| 205 | int sc_debug; |
| 206 | int sc_nvaps; /* # vaps */ |
| 207 | int sc_nstavaps; /* # station vaps */ |
| 208 | int sc_nmeshvaps; /* # mbss vaps */ |
| 209 | u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; |
| 210 | u_int8_t sc_nbssid0; /* # vap's using base mac */ |
| 211 | uint32_t sc_bssidmask; /* bssid mask */ |
| 212 | |
| 213 | void (*sc_node_free)(struct ieee80211_node *); |
| 214 | device_t sc_dev; |
| 215 | HAL_BUS_TAG sc_st; /* bus space tag */ |
| 216 | HAL_BUS_HANDLE sc_sh; /* bus space handle */ |
| 217 | bus_dma_tag_t sc_dmat; /* bus DMA tag */ |
| 218 | struct lock sc_lock; /* master lock (recursive) */ |
| 219 | struct taskqueue *sc_tq; /* private task queue */ |
| 220 | struct ath_hal *sc_ah; /* Atheros HAL */ |
| 221 | struct ath_ratectrl *sc_rc; /* tx rate control support */ |
| 222 | struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ |
| 223 | void (*sc_setdefantenna)(struct ath_softc *, u_int); |
| 224 | unsigned int sc_invalid : 1,/* disable hardware accesses */ |
| 225 | sc_mrretry : 1,/* multi-rate retry support */ |
| 226 | sc_softled : 1,/* enable LED gpio status */ |
| 227 | sc_splitmic : 1,/* split TKIP MIC keys */ |
| 228 | sc_needmib : 1,/* enable MIB stats intr */ |
| 229 | sc_diversity: 1,/* enable rx diversity */ |
| 230 | sc_hasveol : 1,/* tx VEOL support */ |
| 231 | sc_ledstate : 1,/* LED on/off state */ |
| 232 | sc_blinking : 1,/* LED blink operation active */ |
| 233 | sc_mcastkey : 1,/* mcast key cache search */ |
| 234 | sc_scanning : 1,/* scanning active */ |
| 235 | sc_syncbeacon:1,/* sync/resync beacon timers */ |
| 236 | sc_hasclrkey: 1,/* CLR key supported */ |
| 237 | sc_xchanmode: 1,/* extended channel mode */ |
| 238 | sc_outdoor : 1,/* outdoor operation */ |
| 239 | sc_dturbo : 1,/* dynamic turbo in use */ |
| 240 | sc_hasbmask : 1,/* bssid mask support */ |
| 241 | sc_hasbmatch: 1,/* bssid match disable support*/ |
| 242 | sc_hastsfadd: 1,/* tsf adjust support */ |
| 243 | sc_beacons : 1,/* beacons running */ |
| 244 | sc_swbmiss : 1,/* sta mode using sw bmiss */ |
| 245 | sc_stagbeacons:1,/* use staggered beacons */ |
| 246 | sc_wmetkipmic:1,/* can do WME+TKIP MIC */ |
| 247 | sc_resume_up: 1,/* on resume, start all vaps */ |
| 248 | sc_tdma : 1,/* TDMA in use */ |
| 249 | sc_setcca : 1,/* set/clr CCA with TDMA */ |
| 250 | sc_resetcal : 1;/* reset cal state next trip */ |
| 251 | uint32_t sc_eerd; /* regdomain from EEPROM */ |
| 252 | uint32_t sc_eecc; /* country code from EEPROM */ |
| 253 | /* rate tables */ |
| 254 | const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; |
| 255 | const HAL_RATE_TABLE *sc_currates; /* current rate table */ |
| 256 | enum ieee80211_phymode sc_curmode; /* current phy mode */ |
| 257 | HAL_OPMODE sc_opmode; /* current operating mode */ |
| 258 | u_int16_t sc_curtxpow; /* current tx power limit */ |
| 259 | u_int16_t sc_curaid; /* current association id */ |
| 260 | struct ieee80211_channel *sc_curchan; /* current installed channel */ |
| 261 | u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; |
| 262 | u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ |
| 263 | struct { |
| 264 | u_int8_t ieeerate; /* IEEE rate */ |
| 265 | u_int8_t rxflags; /* radiotap rx flags */ |
| 266 | u_int8_t txflags; /* radiotap tx flags */ |
| 267 | u_int16_t ledon; /* softled on time */ |
| 268 | u_int16_t ledoff; /* softled off time */ |
| 269 | } sc_hwmap[32]; /* h/w rate ix mappings */ |
| 270 | u_int8_t sc_protrix; /* protection rate index */ |
| 271 | u_int8_t sc_lastdatarix; /* last data frame rate index */ |
| 272 | u_int sc_mcastrate; /* ieee rate for mcastrateix */ |
| 273 | u_int sc_fftxqmin; /* min frames before staging */ |
| 274 | u_int sc_fftxqmax; /* max frames before drop */ |
| 275 | u_int sc_txantenna; /* tx antenna (fixed or auto) */ |
| 276 | HAL_INT sc_imask; /* interrupt mask copy */ |
| 277 | u_int sc_keymax; /* size of key cache */ |
| 278 | u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ |
| 279 | |
| 280 | u_int sc_ledpin; /* GPIO pin for driving LED */ |
| 281 | u_int sc_ledon; /* pin setting for LED on */ |
| 282 | u_int sc_ledidle; /* idle polling interval */ |
| 283 | int sc_ledevent; /* time of last LED event */ |
| 284 | u_int8_t sc_txrix; /* current tx rate for LED */ |
| 285 | u_int16_t sc_ledoff; /* off time for current blink */ |
| 286 | struct callout sc_ledtimer; /* led off timer */ |
| 287 | |
| 288 | u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ |
| 289 | u_int sc_rfsilentpol; /* pin setting for rfkill on */ |
| 290 | |
| 291 | struct ath_descdma sc_rxdma; /* RX descriptors */ |
| 292 | ath_bufhead sc_rxbuf; /* receive buffer */ |
| 293 | struct mbuf *sc_rxpending; /* pending receive data */ |
| 294 | u_int32_t *sc_rxlink; /* link ptr in last RX desc */ |
| 295 | struct task sc_rxtask; /* rx int processing */ |
| 296 | u_int8_t sc_defant; /* current default antenna */ |
| 297 | u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ |
| 298 | u_int64_t sc_lastrx; /* tsf at last rx'd frame */ |
| 299 | struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ |
| 300 | struct ath_rx_radiotap_header sc_rx_th; |
| 301 | int sc_rx_th_len; |
| 302 | u_int sc_monpass; /* frames to pass in mon.mode */ |
| 303 | |
| 304 | struct ath_descdma sc_txdma; /* TX descriptors */ |
| 305 | ath_bufhead sc_txbuf; /* transmit buffer */ |
| 306 | struct lock sc_txbuflock; /* txbuf lock */ |
| 307 | char sc_txname[12]; /* e.g. "ath0_buf" */ |
| 308 | u_int sc_txqsetup; /* h/w queues setup */ |
| 309 | u_int sc_txintrperiod;/* tx interrupt batching */ |
| 310 | struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; |
| 311 | struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ |
| 312 | struct task sc_txtask; /* tx int processing */ |
| 313 | int sc_wd_timer; /* count down for wd timer */ |
| 314 | struct callout sc_wd_ch; /* tx watchdog timer */ |
| 315 | struct ath_tx_radiotap_header sc_tx_th; |
| 316 | int sc_tx_th_len; |
| 317 | |
| 318 | struct ath_descdma sc_bdma; /* beacon descriptors */ |
| 319 | ath_bufhead sc_bbuf; /* beacon buffers */ |
| 320 | u_int sc_bhalq; /* HAL q for outgoing beacons */ |
| 321 | u_int sc_bmisscount; /* missed beacon transmits */ |
| 322 | u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ |
| 323 | struct ath_txq *sc_cabq; /* tx q for cab frames */ |
| 324 | struct task sc_bmisstask; /* bmiss int processing */ |
| 325 | struct task sc_bstucktask; /* stuck beacon processing */ |
| 326 | enum { |
| 327 | OK, /* no change needed */ |
| 328 | UPDATE, /* update pending */ |
| 329 | COMMIT /* beacon sent, commit change */ |
| 330 | } sc_updateslot; /* slot time update fsm */ |
| 331 | int sc_slotupdate; /* slot to advance fsm */ |
| 332 | struct ieee80211vap *sc_bslot[ATH_BCBUF]; |
| 333 | int sc_nbcnvaps; /* # vaps with beacons */ |
| 334 | |
| 335 | struct callout sc_cal_ch; /* callout handle for cals */ |
| 336 | int sc_lastlongcal; /* last long cal completed */ |
| 337 | int sc_lastcalreset;/* last cal reset done */ |
| 338 | HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ |
| 339 | u_int sc_tdmadbaprep; /* TDMA DBA prep time */ |
| 340 | u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ |
| 341 | u_int sc_tdmaswba; /* TDMA SWBA counter */ |
| 342 | u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ |
| 343 | u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ |
| 344 | u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ |
| 345 | u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ |
| 346 | u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ |
| 347 | struct sysctl_ctx_list sc_sysctl_ctx; |
| 348 | struct sysctl_oid *sc_sysctl_tree; |
| 349 | }; |
| 350 | |
| 351 | #define ATH_LOCK_INIT(_sc) \ |
| 352 | lockinit(&(_sc)->sc_lock, \ |
| 353 | __DECONST(char *, device_get_nameunit((_sc)->sc_dev)), \ |
| 354 | 0, LK_CANRECURSE) |
| 355 | #define ATH_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_lock) |
| 356 | #define ATH_LOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_EXCLUSIVE) |
| 357 | #define ATH_UNLOCK(_sc) lockmgr(&(_sc)->sc_lock, LK_RELEASE) |
| 358 | #define ATH_LOCK_ASSERT(_sc) \ |
| 359 | KKASSERT(lockstatus(&(_sc)->sc_lock, curthread) == LK_EXCLUSIVE) |
| 360 | |
| 361 | #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) |
| 362 | |
| 363 | #define ATH_TXBUF_LOCK_INIT(_sc) do { \ |
| 364 | ksnprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ |
| 365 | device_get_nameunit((_sc)->sc_dev)); \ |
| 366 | lockinit(&(_sc)->sc_txbuflock, (_sc)->sc_txname, 0, 0); \ |
| 367 | } while (0) |
| 368 | #define ATH_TXBUF_LOCK_DESTROY(_sc) lockuninit(&(_sc)->sc_txbuflock) |
| 369 | #define ATH_TXBUF_LOCK(_sc) \ |
| 370 | lockmgr(&(_sc)->sc_txbuflock, LK_EXCLUSIVE) |
| 371 | #define ATH_TXBUF_UNLOCK(_sc) \ |
| 372 | lockmgr(&(_sc)->sc_txbuflock, LK_RELEASE) |
| 373 | #define ATH_TXBUF_LOCK_ASSERT(_sc) \ |
| 374 | KKASSERT(lockstatus(&(_sc)->sc_txbuflock, curthread) == LK_EXCLUSIVE) |
| 375 | |
| 376 | int ath_attach(u_int16_t, struct ath_softc *); |
| 377 | int ath_detach(struct ath_softc *); |
| 378 | void ath_resume(struct ath_softc *); |
| 379 | void ath_suspend(struct ath_softc *); |
| 380 | void ath_shutdown(struct ath_softc *); |
| 381 | void ath_intr(void *); |
| 382 | |
| 383 | /* |
| 384 | * HAL definitions to comply with local coding convention. |
| 385 | */ |
| 386 | #define ath_hal_detach(_ah) \ |
| 387 | ((*(_ah)->ah_detach)((_ah))) |
| 388 | #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ |
| 389 | ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) |
| 390 | #define ath_hal_macversion(_ah) \ |
| 391 | (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) |
| 392 | #define ath_hal_getratetable(_ah, _mode) \ |
| 393 | ((*(_ah)->ah_getRateTable)((_ah), (_mode))) |
| 394 | #define ath_hal_getmac(_ah, _mac) \ |
| 395 | ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) |
| 396 | #define ath_hal_setmac(_ah, _mac) \ |
| 397 | ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) |
| 398 | #define ath_hal_getbssidmask(_ah, _mask) \ |
| 399 | ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) |
| 400 | #define ath_hal_setbssidmask(_ah, _mask) \ |
| 401 | ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) |
| 402 | #define ath_hal_intrset(_ah, _mask) \ |
| 403 | ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) |
| 404 | #define ath_hal_intrget(_ah) \ |
| 405 | ((*(_ah)->ah_getInterrupts)((_ah))) |
| 406 | #define ath_hal_intrpend(_ah) \ |
| 407 | ((*(_ah)->ah_isInterruptPending)((_ah))) |
| 408 | #define ath_hal_getisr(_ah, _pmask) \ |
| 409 | ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) |
| 410 | #define ath_hal_updatetxtriglevel(_ah, _inc) \ |
| 411 | ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) |
| 412 | #define ath_hal_setpower(_ah, _mode) \ |
| 413 | ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) |
| 414 | #define ath_hal_keycachesize(_ah) \ |
| 415 | ((*(_ah)->ah_getKeyCacheSize)((_ah))) |
| 416 | #define ath_hal_keyreset(_ah, _ix) \ |
| 417 | ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) |
| 418 | #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ |
| 419 | ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) |
| 420 | #define ath_hal_keyisvalid(_ah, _ix) \ |
| 421 | (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) |
| 422 | #define ath_hal_keysetmac(_ah, _ix, _mac) \ |
| 423 | ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) |
| 424 | #define ath_hal_getrxfilter(_ah) \ |
| 425 | ((*(_ah)->ah_getRxFilter)((_ah))) |
| 426 | #define ath_hal_setrxfilter(_ah, _filter) \ |
| 427 | ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) |
| 428 | #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ |
| 429 | ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) |
| 430 | #define ath_hal_waitforbeacon(_ah, _bf) \ |
| 431 | ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) |
| 432 | #define ath_hal_putrxbuf(_ah, _bufaddr) \ |
| 433 | ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) |
| 434 | /* NB: common across all chips */ |
| 435 | #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ |
| 436 | #define ath_hal_gettsf32(_ah) \ |
| 437 | OS_REG_READ(_ah, AR_TSF_L32) |
| 438 | #define ath_hal_gettsf64(_ah) \ |
| 439 | ((*(_ah)->ah_getTsf64)((_ah))) |
| 440 | #define ath_hal_resettsf(_ah) \ |
| 441 | ((*(_ah)->ah_resetTsf)((_ah))) |
| 442 | #define ath_hal_rxena(_ah) \ |
| 443 | ((*(_ah)->ah_enableReceive)((_ah))) |
| 444 | #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ |
| 445 | ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) |
| 446 | #define ath_hal_gettxbuf(_ah, _q) \ |
| 447 | ((*(_ah)->ah_getTxDP)((_ah), (_q))) |
| 448 | #define ath_hal_numtxpending(_ah, _q) \ |
| 449 | ((*(_ah)->ah_numTxPending)((_ah), (_q))) |
| 450 | #define ath_hal_getrxbuf(_ah) \ |
| 451 | ((*(_ah)->ah_getRxDP)((_ah))) |
| 452 | #define ath_hal_txstart(_ah, _q) \ |
| 453 | ((*(_ah)->ah_startTxDma)((_ah), (_q))) |
| 454 | #define ath_hal_setchannel(_ah, _chan) \ |
| 455 | ((*(_ah)->ah_setChannel)((_ah), (_chan))) |
| 456 | #define ath_hal_calibrate(_ah, _chan, _iqcal) \ |
| 457 | ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) |
| 458 | #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ |
| 459 | ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) |
| 460 | #define ath_hal_calreset(_ah, _chan) \ |
| 461 | ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) |
| 462 | #define ath_hal_setledstate(_ah, _state) \ |
| 463 | ((*(_ah)->ah_setLedState)((_ah), (_state))) |
| 464 | #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ |
| 465 | ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) |
| 466 | #define ath_hal_beaconreset(_ah) \ |
| 467 | ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) |
| 468 | #define ath_hal_beaconsettimers(_ah, _bt) \ |
| 469 | ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) |
| 470 | #define ath_hal_beacontimers(_ah, _bs) \ |
| 471 | ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) |
| 472 | #define ath_hal_setassocid(_ah, _bss, _associd) \ |
| 473 | ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) |
| 474 | #define ath_hal_phydisable(_ah) \ |
| 475 | ((*(_ah)->ah_phyDisable)((_ah))) |
| 476 | #define ath_hal_setopmode(_ah) \ |
| 477 | ((*(_ah)->ah_setPCUConfig)((_ah))) |
| 478 | #define ath_hal_stoptxdma(_ah, _qnum) \ |
| 479 | ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) |
| 480 | #define ath_hal_stoppcurecv(_ah) \ |
| 481 | ((*(_ah)->ah_stopPcuReceive)((_ah))) |
| 482 | #define ath_hal_startpcurecv(_ah) \ |
| 483 | ((*(_ah)->ah_startPcuReceive)((_ah))) |
| 484 | #define ath_hal_stopdmarecv(_ah) \ |
| 485 | ((*(_ah)->ah_stopDmaReceive)((_ah))) |
| 486 | #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ |
| 487 | ((*(_ah)->ah_getDiagState)((_ah), (_id), \ |
| 488 | (_indata), (_insize), (_outdata), (_outsize))) |
| 489 | #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ |
| 490 | ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) |
| 491 | #define ath_hal_setuptxqueue(_ah, _type, _irq) \ |
| 492 | ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) |
| 493 | #define ath_hal_resettxqueue(_ah, _q) \ |
| 494 | ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) |
| 495 | #define ath_hal_releasetxqueue(_ah, _q) \ |
| 496 | ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) |
| 497 | #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ |
| 498 | ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) |
| 499 | #define ath_hal_settxqueueprops(_ah, _q, _qi) \ |
| 500 | ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) |
| 501 | /* NB: common across all chips */ |
| 502 | #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ |
| 503 | #define ath_hal_txqenabled(_ah, _qnum) \ |
| 504 | (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) |
| 505 | #define ath_hal_getrfgain(_ah) \ |
| 506 | ((*(_ah)->ah_getRfGain)((_ah))) |
| 507 | #define ath_hal_getdefantenna(_ah) \ |
| 508 | ((*(_ah)->ah_getDefAntenna)((_ah))) |
| 509 | #define ath_hal_setdefantenna(_ah, _ant) \ |
| 510 | ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) |
| 511 | #define ath_hal_rxmonitor(_ah, _arg, _chan) \ |
| 512 | ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) |
| 513 | #define ath_hal_mibevent(_ah, _stats) \ |
| 514 | ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) |
| 515 | #define ath_hal_setslottime(_ah, _us) \ |
| 516 | ((*(_ah)->ah_setSlotTime)((_ah), (_us))) |
| 517 | #define ath_hal_getslottime(_ah) \ |
| 518 | ((*(_ah)->ah_getSlotTime)((_ah))) |
| 519 | #define ath_hal_setacktimeout(_ah, _us) \ |
| 520 | ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) |
| 521 | #define ath_hal_getacktimeout(_ah) \ |
| 522 | ((*(_ah)->ah_getAckTimeout)((_ah))) |
| 523 | #define ath_hal_setctstimeout(_ah, _us) \ |
| 524 | ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) |
| 525 | #define ath_hal_getctstimeout(_ah) \ |
| 526 | ((*(_ah)->ah_getCTSTimeout)((_ah))) |
| 527 | #define ath_hal_getcapability(_ah, _cap, _param, _result) \ |
| 528 | ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) |
| 529 | #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ |
| 530 | ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) |
| 531 | #define ath_hal_ciphersupported(_ah, _cipher) \ |
| 532 | (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) |
| 533 | #define ath_hal_getregdomain(_ah, _prd) \ |
| 534 | (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) |
| 535 | #define ath_hal_setregdomain(_ah, _rd) \ |
| 536 | ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) |
| 537 | #define ath_hal_getcountrycode(_ah, _pcc) \ |
| 538 | (*(_pcc) = (_ah)->ah_countryCode) |
| 539 | #define ath_hal_gettkipmic(_ah) \ |
| 540 | (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) |
| 541 | #define ath_hal_settkipmic(_ah, _v) \ |
| 542 | ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) |
| 543 | #define ath_hal_hastkipsplit(_ah) \ |
| 544 | (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) |
| 545 | #define ath_hal_gettkipsplit(_ah) \ |
| 546 | (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) |
| 547 | #define ath_hal_settkipsplit(_ah, _v) \ |
| 548 | ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) |
| 549 | #define ath_hal_haswmetkipmic(_ah) \ |
| 550 | (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) |
| 551 | #define ath_hal_hwphycounters(_ah) \ |
| 552 | (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) |
| 553 | #define ath_hal_hasdiversity(_ah) \ |
| 554 | (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) |
| 555 | #define ath_hal_getdiversity(_ah) \ |
| 556 | (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) |
| 557 | #define ath_hal_setdiversity(_ah, _v) \ |
| 558 | ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) |
| 559 | #define ath_hal_getantennaswitch(_ah) \ |
| 560 | ((*(_ah)->ah_getAntennaSwitch)((_ah))) |
| 561 | #define ath_hal_setantennaswitch(_ah, _v) \ |
| 562 | ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) |
| 563 | #define ath_hal_getdiag(_ah, _pv) \ |
| 564 | (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) |
| 565 | #define ath_hal_setdiag(_ah, _v) \ |
| 566 | ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) |
| 567 | #define ath_hal_getnumtxqueues(_ah, _pv) \ |
| 568 | (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) |
| 569 | #define ath_hal_hasveol(_ah) \ |
| 570 | (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) |
| 571 | #define ath_hal_hastxpowlimit(_ah) \ |
| 572 | (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) |
| 573 | #define ath_hal_settxpowlimit(_ah, _pow) \ |
| 574 | ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) |
| 575 | #define ath_hal_gettxpowlimit(_ah, _ppow) \ |
| 576 | (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) |
| 577 | #define ath_hal_getmaxtxpow(_ah, _ppow) \ |
| 578 | (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) |
| 579 | #define ath_hal_gettpscale(_ah, _scale) \ |
| 580 | (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) |
| 581 | #define ath_hal_settpscale(_ah, _v) \ |
| 582 | ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) |
| 583 | #define ath_hal_hastpc(_ah) \ |
| 584 | (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) |
| 585 | #define ath_hal_gettpc(_ah) \ |
| 586 | (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) |
| 587 | #define ath_hal_settpc(_ah, _v) \ |
| 588 | ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) |
| 589 | #define ath_hal_hasbursting(_ah) \ |
| 590 | (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) |
| 591 | #define ath_hal_setmcastkeysearch(_ah, _v) \ |
| 592 | ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) |
| 593 | #define ath_hal_hasmcastkeysearch(_ah) \ |
| 594 | (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) |
| 595 | #define ath_hal_getmcastkeysearch(_ah) \ |
| 596 | (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) |
| 597 | #define ath_hal_hasfastframes(_ah) \ |
| 598 | (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) |
| 599 | #define ath_hal_hasbssidmask(_ah) \ |
| 600 | (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) |
| 601 | #define ath_hal_hasbssidmatch(_ah) \ |
| 602 | (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) |
| 603 | #define ath_hal_hastsfadjust(_ah) \ |
| 604 | (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) |
| 605 | #define ath_hal_gettsfadjust(_ah) \ |
| 606 | (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) |
| 607 | #define ath_hal_settsfadjust(_ah, _onoff) \ |
| 608 | ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) |
| 609 | #define ath_hal_hasrfsilent(_ah) \ |
| 610 | (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) |
| 611 | #define ath_hal_getrfkill(_ah) \ |
| 612 | (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) |
| 613 | #define ath_hal_setrfkill(_ah, _onoff) \ |
| 614 | ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) |
| 615 | #define ath_hal_getrfsilent(_ah, _prfsilent) \ |
| 616 | (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) |
| 617 | #define ath_hal_setrfsilent(_ah, _rfsilent) \ |
| 618 | ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) |
| 619 | #define ath_hal_gettpack(_ah, _ptpack) \ |
| 620 | (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) |
| 621 | #define ath_hal_settpack(_ah, _tpack) \ |
| 622 | ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) |
| 623 | #define ath_hal_gettpcts(_ah, _ptpcts) \ |
| 624 | (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) |
| 625 | #define ath_hal_settpcts(_ah, _tpcts) \ |
| 626 | ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) |
| 627 | #define ath_hal_hasintmit(_ah) \ |
| 628 | (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK) |
| 629 | #define ath_hal_getintmit(_ah) \ |
| 630 | (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK) |
| 631 | #define ath_hal_setintmit(_ah, _v) \ |
| 632 | ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL) |
| 633 | #define ath_hal_getchannoise(_ah, _c) \ |
| 634 | ((*(_ah)->ah_getChanNoise)((_ah), (_c))) |
| 635 | |
| 636 | #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ |
| 637 | ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) |
| 638 | #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ |
| 639 | ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) |
| 640 | #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ |
| 641 | _txr0, _txtr0, _keyix, _ant, _flags, \ |
| 642 | _rtsrate, _rtsdura) \ |
| 643 | ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ |
| 644 | (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ |
| 645 | (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) |
| 646 | #define ath_hal_setupxtxdesc(_ah, _ds, \ |
| 647 | _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ |
| 648 | ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ |
| 649 | (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) |
| 650 | #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ |
| 651 | ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) |
| 652 | #define ath_hal_txprocdesc(_ah, _ds, _ts) \ |
| 653 | ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) |
| 654 | #define ath_hal_gettxintrtxqs(_ah, _txqs) \ |
| 655 | ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) |
| 656 | |
| 657 | #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ |
| 658 | ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) |
| 659 | #define ath_hal_gpioset(_ah, _gpio, _b) \ |
| 660 | ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) |
| 661 | #define ath_hal_gpioget(_ah, _gpio) \ |
| 662 | ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) |
| 663 | #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ |
| 664 | ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) |
| 665 | |
| 666 | #define ath_hal_radar_wait(_ah, _chan) \ |
| 667 | ((*(_ah)->ah_radarWait)((_ah), (_chan))) |
| 668 | |
| 669 | #endif /* _DEV_ATH_ATHVAR_H */ |