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Remove ipw(4) from LINT building and module building
[dragonfly.git] / sys / dev / netif / ipw / if_ipwreg.h
... / ...
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1/*-
2 * Copyright (c) 2004, 2005
3 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: if_ipwreg.h,v 1.2.2.1 2005/01/13 20:01:04 damien Exp $
28 * $DragonFly: src/sys/dev/netif/ipw/Attic/if_ipwreg.h,v 1.1 2005/03/06 18:25:12 dillon Exp $
29 */
30
31#define IPW_NTBD 128
32#define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd))
33#define IPW_NDATA (IPW_NTBD / 2)
34#define IPW_NRBD 128
35#define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd))
36#define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status))
37
38#define IPW_CSR_INTR 0x0008
39#define IPW_CSR_INTR_MASK 0x000c
40#define IPW_CSR_INDIRECT_ADDR 0x0010
41#define IPW_CSR_INDIRECT_DATA 0x0014
42#define IPW_CSR_AUTOINC_ADDR 0x0018
43#define IPW_CSR_AUTOINC_DATA 0x001c
44#define IPW_CSR_RST 0x0020
45#define IPW_CSR_CTL 0x0024
46#define IPW_CSR_IO 0x0030
47#define IPW_CSR_TX_BD_BASE 0x0200
48#define IPW_CSR_TX_BD_SIZE 0x0204
49#define IPW_CSR_RX_BD_BASE 0x0240
50#define IPW_CSR_RX_STATUS_BASE 0x0244
51#define IPW_CSR_RX_BD_SIZE 0x0248
52#define IPW_CSR_TX_READ_INDEX 0x0280
53#define IPW_CSR_RX_READ_INDEX 0x02a0
54#define IPW_CSR_TABLE1_BASE 0x0380
55#define IPW_CSR_TABLE2_BASE 0x0384
56#define IPW_CSR_TX_WRITE_INDEX 0x0f80
57#define IPW_CSR_RX_WRITE_INDEX 0x0fa0
58
59/* possible flags for register IPW_CSR_INTR */
60#define IPW_INTR_TX_TRANSFER 0x00000001
61#define IPW_INTR_RX_TRANSFER 0x00000002
62#define IPW_INTR_STATUS_CHANGE 0x00000010
63#define IPW_INTR_COMMAND_DONE 0x00010000
64#define IPW_INTR_FW_INIT_DONE 0x01000000
65#define IPW_INTR_FATAL_ERROR 0x40000000
66#define IPW_INTR_PARITY_ERROR 0x80000000
67
68#define IPW_INTR_MASK \
69 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \
70 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \
71 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \
72 IPW_INTR_PARITY_ERROR)
73
74/* possible flags for register IPW_CSR_RST */
75#define IPW_RST_PRINCETON_RESET 0x00000001
76#define IPW_RST_SW_RESET 0x00000080
77#define IPW_RST_MASTER_DISABLED 0x00000100
78#define IPW_RST_STOP_MASTER 0x00000200
79
80/* possible flags for register IPW_CSR_CTL */
81#define IPW_CTL_CLOCK_READY 0x00000001
82#define IPW_CTL_ALLOW_STANDBY 0x00000002
83#define IPW_CTL_INIT 0x00000004
84
85/* possible flags for register IPW_CSR_IO */
86#define IPW_IO_GPIO1_ENABLE 0x00000008
87#define IPW_IO_GPIO1_MASK 0x0000000c
88#define IPW_IO_GPIO3_MASK 0x000000c0
89#define IPW_IO_LED_OFF 0x00002000
90#define IPW_IO_RADIO_DISABLED 0x00010000
91
92#define IPW_STATE_ASSOCIATED 0x0004
93#define IPW_STATE_ASSOCIATION_LOST 0x0008
94#define IPW_STATE_SCAN_COMPLETE 0x0020
95#define IPW_STATE_RADIO_DISABLED 0x0100
96#define IPW_STATE_DISABLED 0x0200
97#define IPW_STATE_SCANNING 0x0800
98
99/* table1 offsets */
100#define IPW_INFO_LOCK 480
101#define IPW_INFO_APS_CNT 604
102#define IPW_INFO_APS_BASE 608
103#define IPW_INFO_CARD_DISABLED 628
104#define IPW_INFO_CURRENT_CHANNEL 756
105#define IPW_INFO_CURRENT_TX_RATE 768
106
107/* table2 offsets */
108#define IPW_INFO_CURRENT_SSID 48
109#define IPW_INFO_CURRENT_BSSID 112
110
111/* supported rates */
112#define IPW_RATE_DS1 1
113#define IPW_RATE_DS2 2
114#define IPW_RATE_DS5 4
115#define IPW_RATE_DS11 8
116
117/* firmware binary image header */
118struct ipw_firmware_hdr {
119 u_int32_t version;
120 u_int32_t main_size; /* firmware size */
121 u_int32_t ucode_size; /* microcode size */
122} __packed;
123
124/* buffer descriptor */
125struct ipw_bd {
126 u_int32_t physaddr;
127 u_int32_t len;
128 u_int8_t flags;
129#define IPW_BD_FLAG_TX_FRAME_802_3 0x00
130#define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01
131#define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02
132#define IPW_BD_FLAG_TX_FRAME_802_11 0x04
133#define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08
134 u_int8_t nfrag; /* number of fragments */
135 u_int8_t reserved[6];
136} __packed;
137
138/* status */
139struct ipw_status {
140 u_int32_t len;
141 u_int16_t code;
142#define IPW_STATUS_CODE_COMMAND 0
143#define IPW_STATUS_CODE_NEWSTATE 1
144#define IPW_STATUS_CODE_DATA_802_11 2
145#define IPW_STATUS_CODE_DATA_802_3 3
146#define IPW_STATUS_CODE_NOTIFICATION 4
147 u_int8_t flags;
148#define IPW_STATUS_FLAG_DECRYPTED 0x01
149#define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02
150 u_int8_t rssi; /* received signal strength indicator */
151} __packed;
152
153/* data header */
154struct ipw_hdr {
155 u_int32_t type;
156#define IPW_HDR_TYPE_SEND 33
157 u_int32_t subtype;
158 u_int8_t encrypted;
159 u_int8_t encrypt;
160 u_int8_t keyidx;
161 u_int8_t keysz;
162 u_int8_t key[IEEE80211_KEYBUF_SIZE];
163 u_int8_t reserved[10];
164 u_int8_t src_addr[IEEE80211_ADDR_LEN];
165 u_int8_t dst_addr[IEEE80211_ADDR_LEN];
166 u_int16_t fragmentsz;
167} __packed;
168
169/* command */
170struct ipw_cmd {
171 u_int32_t type;
172#define IPW_CMD_ENABLE 2
173#define IPW_CMD_SET_CONFIGURATION 6
174#define IPW_CMD_SET_ESSID 8
175#define IPW_CMD_SET_MANDATORY_BSSID 9
176#define IPW_CMD_SET_MAC_ADDRESS 11
177#define IPW_CMD_SET_MODE 12
178#define IPW_CMD_SET_CHANNEL 14
179#define IPW_CMD_SET_RTS_THRESHOLD 15
180#define IPW_CMD_SET_FRAG_THRESHOLD 16
181#define IPW_CMD_SET_POWER_MODE 17
182#define IPW_CMD_SET_TX_RATES 18
183#define IPW_CMD_SET_BASIC_TX_RATES 19
184#define IPW_CMD_SET_WEP_KEY 20
185#define IPW_CMD_SET_WEP_KEY_INDEX 25
186#define IPW_CMD_SET_WEP_FLAGS 26
187#define IPW_CMD_ADD_MULTICAST 27
188#define IPW_CMD_SET_BEACON_INTERVAL 29
189#define IPW_CMD_SET_TX_POWER_INDEX 36
190#define IPW_CMD_BROADCAST_SCAN 43
191#define IPW_CMD_DISABLE 44
192#define IPW_CMD_SET_DESIRED_BSSID 45
193#define IPW_CMD_SET_SCAN_OPTIONS 46
194#define IPW_CMD_PREPARE_POWER_DOWN 58
195#define IPW_CMD_DISABLE_PHY 61
196#define IPW_CMD_SET_SECURITY_INFORMATION 67
197 u_int32_t subtype;
198 u_int32_t seq;
199 u_int32_t len;
200 u_int8_t data[400];
201 u_int32_t status;
202 u_int8_t reserved[68];
203} __packed;
204
205/* possible values for command IPW_CMD_SET_POWER_MODE */
206#define IPW_POWER_MODE_CAM 0
207#define IPW_POWER_AUTOMATIC 6
208
209/* possible values for command IPW_CMD_SET_MODE */
210#define IPW_MODE_BSS 0
211#define IPW_MODE_IBSS 1
212#define IPW_MODE_MONITOR 2
213
214/* possible flags for command IPW_CMD_SET_WEP_FLAGS */
215#define IPW_WEPON 0x8
216
217/* structure for command IPW_CMD_SET_WEP_KEY */
218struct ipw_wep_key {
219 u_int8_t idx;
220 u_int8_t len;
221 u_int8_t key[13];
222} __packed;
223
224/* structure for command IPW_CMD_SET_SECURITY_INFORMATION */
225struct ipw_security {
226 u_int32_t ciphers;
227#define IPW_CIPHER_NONE 0x00000001
228#define IPW_CIPHER_WEP40 0x00000002
229#define IPW_CIPHER_WEP104 0x00000020
230 u_int16_t reserved1;
231 u_int8_t authmode;
232#define IPW_AUTH_OPEN 0
233#define IPW_AUTH_SHARED 1
234 u_int16_t reserved2;
235} __packed;
236
237/* structure for command IPW_CMD_SET_SCAN_OPTIONS */
238struct ipw_scan_options {
239 u_int32_t flags;
240#define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001
241#define IPW_SCAN_PASSIVE 0x00000008
242 u_int32_t channels;
243} __packed;
244
245/* structure for command IPW_CMD_SET_CONFIGURATION */
246struct ipw_configuration {
247 u_int32_t flags;
248#define IPW_CFG_PROMISCUOUS 0x00000004
249#define IPW_CFG_PREAMBLE_AUTO 0x00000010
250#define IPW_CFG_IBSS_AUTO_START 0x00000020
251#define IPW_CFG_802_1x_ENABLE 0x00004000
252#define IPW_CFG_BSS_MASK 0x00008000
253#define IPW_CFG_IBSS_MASK 0x00010000
254 u_int32_t bss_chan;
255 u_int32_t ibss_chan;
256} __packed;
257
258/* element in AP table */
259struct ipw_node {
260 u_int32_t reserved1[2];
261 u_int8_t bssid[IEEE80211_ADDR_LEN];
262 u_int8_t chan;
263 u_int8_t rates;
264 u_int16_t reserved2;
265 u_int16_t capinfo;
266 u_int16_t reserved3;
267 u_int16_t intval;
268 u_int8_t reserved4[28];
269 u_int8_t essid[IEEE80211_NWID_LEN];
270 u_int16_t reserved5;
271 u_int8_t esslen;
272 u_int8_t reserved6[7];
273 u_int8_t rssi;
274} __packed;
275
276/* EEPROM = Electrically Erasable Programmable Read-Only Memory */
277
278#define IPW_MEM_EEPROM_CTL 0x00300040
279
280#define IPW_EEPROM_RADIO 0x11
281#define IPW_EEPROM_MAC 0x21
282#define IPW_EEPROM_CHANNEL_LIST 0x37
283
284#define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
285
286#define IPW_EEPROM_C (1 << 0) /* Serial Clock */
287#define IPW_EEPROM_S (1 << 1) /* Chip Select */
288#define IPW_EEPROM_D (1 << 2) /* Serial data input */
289#define IPW_EEPROM_Q (1 << 4) /* Serial data output */
290
291#define IPW_EEPROM_SHIFT_D 2
292#define IPW_EEPROM_SHIFT_Q 4
293
294/*
295 * control and status registers access macros
296 */
297#define CSR_READ_1(sc, reg) \
298 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
299
300#define CSR_READ_2(sc, reg) \
301 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
302
303#define CSR_READ_4(sc, reg) \
304 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
305
306#define CSR_WRITE_1(sc, reg, val) \
307 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
308
309#define CSR_WRITE_2(sc, reg, val) \
310 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
311
312#define CSR_WRITE_4(sc, reg, val) \
313 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
314
315#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
316 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
317 (buf), (len))
318
319/*
320 * indirect memory space access macros
321 */
322#define MEM_WRITE_1(sc, addr, val) do { \
323 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
324 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
325} while (/* CONSTCOND */0)
326
327#define MEM_WRITE_2(sc, addr, val) do { \
328 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
329 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
330} while (/* CONSTCOND */0)
331
332#define MEM_WRITE_4(sc, addr, val) do { \
333 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
334 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
335} while (/* CONSTCOND */0)
336
337#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
338 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
339 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \
340} while (/* CONSTCOND */0)
341
342/*
343 * EEPROM access macro
344 */
345#define IPW_EEPROM_CTL(sc, val) do { \
346 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \
347 DELAY(IPW_EEPROM_DELAY); \
348} while (0)
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