| 1 | /* |
| 2 | * Copyright (c) 1996, by Steve Passe |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * 2. The name of the developer may NOT be used to endorse or promote products |
| 11 | * derived from this software without specific prior written permission. |
| 12 | * |
| 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 23 | * SUCH DAMAGE. |
| 24 | * |
| 25 | * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $ |
| 26 | */ |
| 27 | |
| 28 | #include <sys/param.h> |
| 29 | #include <sys/systm.h> |
| 30 | #include <sys/kernel.h> |
| 31 | #include <sys/bus.h> |
| 32 | #include <sys/machintr.h> |
| 33 | #include <machine/globaldata.h> |
| 34 | #include <machine/smp.h> |
| 35 | #include <machine/cputypes.h> |
| 36 | #include <machine/md_var.h> |
| 37 | #include <machine/pmap.h> |
| 38 | #include <machine_base/apic/lapic.h> |
| 39 | #include <machine_base/apic/ioapic_abi.h> |
| 40 | #include <machine/segments.h> |
| 41 | #include <sys/thread2.h> |
| 42 | |
| 43 | #include <machine/intr_machdep.h> |
| 44 | |
| 45 | volatile lapic_t *lapic; |
| 46 | |
| 47 | static void lapic_timer_calibrate(void); |
| 48 | static void lapic_timer_set_divisor(int); |
| 49 | static void lapic_timer_fixup_handler(void *); |
| 50 | static void lapic_timer_restart_handler(void *); |
| 51 | |
| 52 | void lapic_timer_process(void); |
| 53 | void lapic_timer_process_frame(struct intrframe *); |
| 54 | |
| 55 | static int lapic_timer_enable = 1; |
| 56 | TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable); |
| 57 | |
| 58 | static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t); |
| 59 | static void lapic_timer_intr_enable(struct cputimer_intr *); |
| 60 | static void lapic_timer_intr_restart(struct cputimer_intr *); |
| 61 | static void lapic_timer_intr_pmfixup(struct cputimer_intr *); |
| 62 | |
| 63 | static struct cputimer_intr lapic_cputimer_intr = { |
| 64 | .freq = 0, |
| 65 | .reload = lapic_timer_intr_reload, |
| 66 | .enable = lapic_timer_intr_enable, |
| 67 | .config = cputimer_intr_default_config, |
| 68 | .restart = lapic_timer_intr_restart, |
| 69 | .pmfixup = lapic_timer_intr_pmfixup, |
| 70 | .initclock = cputimer_intr_default_initclock, |
| 71 | .next = SLIST_ENTRY_INITIALIZER, |
| 72 | .name = "lapic", |
| 73 | .type = CPUTIMER_INTR_LAPIC, |
| 74 | .prio = CPUTIMER_INTR_PRIO_LAPIC, |
| 75 | .caps = CPUTIMER_INTR_CAP_NONE |
| 76 | }; |
| 77 | |
| 78 | static int lapic_timer_divisor_idx = -1; |
| 79 | static const uint32_t lapic_timer_divisors[] = { |
| 80 | APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, |
| 81 | APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1 |
| 82 | }; |
| 83 | #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors)) |
| 84 | |
| 85 | /* |
| 86 | * APIC ID logical/physical mapping structures. |
| 87 | * We oversize these to simplify boot-time config. |
| 88 | */ |
| 89 | int cpu_num_to_apic_id[NAPICID]; |
| 90 | int apic_id_to_logical[NAPICID]; |
| 91 | |
| 92 | /* |
| 93 | * Enable LAPIC, configure interrupts. |
| 94 | */ |
| 95 | void |
| 96 | lapic_init(boolean_t bsp) |
| 97 | { |
| 98 | uint32_t timer; |
| 99 | u_int temp; |
| 100 | |
| 101 | /* |
| 102 | * Install vectors |
| 103 | * |
| 104 | * Since IDT is shared between BSP and APs, these vectors |
| 105 | * only need to be installed once; we do it on BSP. |
| 106 | */ |
| 107 | if (bsp) { |
| 108 | /* Install a 'Spurious INTerrupt' vector */ |
| 109 | setidt(XSPURIOUSINT_OFFSET, Xspuriousint, |
| 110 | SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 111 | |
| 112 | /* Install an inter-CPU IPI for TLB invalidation */ |
| 113 | setidt(XINVLTLB_OFFSET, Xinvltlb, |
| 114 | SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 115 | |
| 116 | /* Install an inter-CPU IPI for IPIQ messaging */ |
| 117 | setidt(XIPIQ_OFFSET, Xipiq, |
| 118 | SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 119 | |
| 120 | /* Install a timer vector */ |
| 121 | setidt(XTIMER_OFFSET, Xtimer, |
| 122 | SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 123 | |
| 124 | /* Install an inter-CPU IPI for CPU stop/restart */ |
| 125 | setidt(XCPUSTOP_OFFSET, Xcpustop, |
| 126 | SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); |
| 127 | } |
| 128 | |
| 129 | /* |
| 130 | * Setup LINT0 as ExtINT on the BSP. This is theoretically an |
| 131 | * aggregate interrupt input from the 8259. The INTA cycle |
| 132 | * will be routed to the external controller (the 8259) which |
| 133 | * is expected to supply the vector. |
| 134 | * |
| 135 | * Must be setup edge triggered, active high. |
| 136 | * |
| 137 | * Disable LINT0 on BSP, if I/O APIC is enabled. |
| 138 | * |
| 139 | * Disable LINT0 on the APs. It doesn't matter what delivery |
| 140 | * mode we use because we leave it masked. |
| 141 | */ |
| 142 | temp = lapic->lvt_lint0; |
| 143 | temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | |
| 144 | APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); |
| 145 | if (bsp) { |
| 146 | temp |= APIC_LVT_DM_EXTINT; |
| 147 | if (apic_io_enable) |
| 148 | temp |= APIC_LVT_MASKED; |
| 149 | } else { |
| 150 | temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED; |
| 151 | } |
| 152 | lapic->lvt_lint0 = temp; |
| 153 | |
| 154 | /* |
| 155 | * Setup LINT1 as NMI. |
| 156 | * |
| 157 | * Must be setup edge trigger, active high. |
| 158 | * |
| 159 | * Enable LINT1 on BSP, if I/O APIC is enabled. |
| 160 | * |
| 161 | * Disable LINT1 on the APs. |
| 162 | */ |
| 163 | temp = lapic->lvt_lint1; |
| 164 | temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | |
| 165 | APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); |
| 166 | temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI; |
| 167 | if (bsp && apic_io_enable) |
| 168 | temp &= ~APIC_LVT_MASKED; |
| 169 | lapic->lvt_lint1 = temp; |
| 170 | |
| 171 | /* |
| 172 | * Mask the LAPIC error interrupt, LAPIC performance counter |
| 173 | * interrupt. |
| 174 | */ |
| 175 | lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED; |
| 176 | lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED; |
| 177 | |
| 178 | /* |
| 179 | * Set LAPIC timer vector and mask the LAPIC timer interrupt. |
| 180 | */ |
| 181 | timer = lapic->lvt_timer; |
| 182 | timer &= ~APIC_LVTT_VECTOR; |
| 183 | timer |= XTIMER_OFFSET; |
| 184 | timer |= APIC_LVTT_MASKED; |
| 185 | lapic->lvt_timer = timer; |
| 186 | |
| 187 | /* |
| 188 | * Set the Task Priority Register as needed. At the moment allow |
| 189 | * interrupts on all cpus (the APs will remain CLId until they are |
| 190 | * ready to deal). We could disable all but IPIs by setting |
| 191 | * temp |= TPR_IPI for cpu != 0. |
| 192 | */ |
| 193 | temp = lapic->tpr; |
| 194 | temp &= ~APIC_TPR_PRIO; /* clear priority field */ |
| 195 | #ifdef SMP /* APIC-IO */ |
| 196 | if (!apic_io_enable) { |
| 197 | #endif |
| 198 | /* |
| 199 | * If we are NOT running the IO APICs, the LAPIC will only be used |
| 200 | * for IPIs. Set the TPR to prevent any unintentional interrupts. |
| 201 | */ |
| 202 | temp |= TPR_IPI; |
| 203 | #ifdef SMP /* APIC-IO */ |
| 204 | } |
| 205 | #endif |
| 206 | |
| 207 | lapic->tpr = temp; |
| 208 | |
| 209 | /* |
| 210 | * Enable the LAPIC |
| 211 | */ |
| 212 | temp = lapic->svr; |
| 213 | temp |= APIC_SVR_ENABLE; /* enable the LAPIC */ |
| 214 | temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */ |
| 215 | |
| 216 | /* |
| 217 | * Set the spurious interrupt vector. The low 4 bits of the vector |
| 218 | * must be 1111. |
| 219 | */ |
| 220 | if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F) |
| 221 | panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET); |
| 222 | temp &= ~APIC_SVR_VECTOR; |
| 223 | temp |= XSPURIOUSINT_OFFSET; |
| 224 | |
| 225 | lapic->svr = temp; |
| 226 | |
| 227 | /* |
| 228 | * Pump out a few EOIs to clean out interrupts that got through |
| 229 | * before we were able to set the TPR. |
| 230 | */ |
| 231 | lapic->eoi = 0; |
| 232 | lapic->eoi = 0; |
| 233 | lapic->eoi = 0; |
| 234 | |
| 235 | if (bsp) { |
| 236 | lapic_timer_calibrate(); |
| 237 | if (lapic_timer_enable) { |
| 238 | cputimer_intr_register(&lapic_cputimer_intr); |
| 239 | cputimer_intr_select(&lapic_cputimer_intr, 0); |
| 240 | } |
| 241 | } else { |
| 242 | lapic_timer_set_divisor(lapic_timer_divisor_idx); |
| 243 | } |
| 244 | |
| 245 | if (bootverbose) |
| 246 | apic_dump("apic_initialize()"); |
| 247 | } |
| 248 | |
| 249 | static void |
| 250 | lapic_timer_set_divisor(int divisor_idx) |
| 251 | { |
| 252 | KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS); |
| 253 | lapic->dcr_timer = lapic_timer_divisors[divisor_idx]; |
| 254 | } |
| 255 | |
| 256 | static void |
| 257 | lapic_timer_oneshot(u_int count) |
| 258 | { |
| 259 | uint32_t value; |
| 260 | |
| 261 | value = lapic->lvt_timer; |
| 262 | value &= ~APIC_LVTT_PERIODIC; |
| 263 | lapic->lvt_timer = value; |
| 264 | lapic->icr_timer = count; |
| 265 | } |
| 266 | |
| 267 | static void |
| 268 | lapic_timer_oneshot_quick(u_int count) |
| 269 | { |
| 270 | lapic->icr_timer = count; |
| 271 | } |
| 272 | |
| 273 | static void |
| 274 | lapic_timer_calibrate(void) |
| 275 | { |
| 276 | sysclock_t value; |
| 277 | |
| 278 | /* Try to calibrate the local APIC timer. */ |
| 279 | for (lapic_timer_divisor_idx = 0; |
| 280 | lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS; |
| 281 | lapic_timer_divisor_idx++) { |
| 282 | lapic_timer_set_divisor(lapic_timer_divisor_idx); |
| 283 | lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); |
| 284 | DELAY(2000000); |
| 285 | value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; |
| 286 | if (value != APIC_TIMER_MAX_COUNT) |
| 287 | break; |
| 288 | } |
| 289 | if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS) |
| 290 | panic("lapic: no proper timer divisor?!\n"); |
| 291 | lapic_cputimer_intr.freq = value / 2; |
| 292 | |
| 293 | kprintf("lapic: divisor index %d, frequency %u Hz\n", |
| 294 | lapic_timer_divisor_idx, lapic_cputimer_intr.freq); |
| 295 | } |
| 296 | |
| 297 | static void |
| 298 | lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame) |
| 299 | { |
| 300 | sysclock_t count; |
| 301 | |
| 302 | gd->gd_timer_running = 0; |
| 303 | |
| 304 | count = sys_cputimer->count(); |
| 305 | if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) |
| 306 | systimer_intr(&count, 0, frame); |
| 307 | } |
| 308 | |
| 309 | void |
| 310 | lapic_timer_process(void) |
| 311 | { |
| 312 | lapic_timer_process_oncpu(mycpu, NULL); |
| 313 | } |
| 314 | |
| 315 | void |
| 316 | lapic_timer_process_frame(struct intrframe *frame) |
| 317 | { |
| 318 | lapic_timer_process_oncpu(mycpu, frame); |
| 319 | } |
| 320 | |
| 321 | static void |
| 322 | lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload) |
| 323 | { |
| 324 | struct globaldata *gd = mycpu; |
| 325 | |
| 326 | reload = (int64_t)reload * cti->freq / sys_cputimer->freq; |
| 327 | if (reload < 2) |
| 328 | reload = 2; |
| 329 | |
| 330 | if (gd->gd_timer_running) { |
| 331 | if (reload < lapic->ccr_timer) |
| 332 | lapic_timer_oneshot_quick(reload); |
| 333 | } else { |
| 334 | gd->gd_timer_running = 1; |
| 335 | lapic_timer_oneshot_quick(reload); |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | static void |
| 340 | lapic_timer_intr_enable(struct cputimer_intr *cti __unused) |
| 341 | { |
| 342 | uint32_t timer; |
| 343 | |
| 344 | timer = lapic->lvt_timer; |
| 345 | timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC); |
| 346 | lapic->lvt_timer = timer; |
| 347 | |
| 348 | lapic_timer_fixup_handler(NULL); |
| 349 | } |
| 350 | |
| 351 | static void |
| 352 | lapic_timer_fixup_handler(void *arg) |
| 353 | { |
| 354 | int *started = arg; |
| 355 | |
| 356 | if (started != NULL) |
| 357 | *started = 0; |
| 358 | |
| 359 | if (cpu_vendor_id == CPU_VENDOR_AMD) { |
| 360 | /* |
| 361 | * Detect the presence of C1E capability mostly on latest |
| 362 | * dual-cores (or future) k8 family. This feature renders |
| 363 | * the local APIC timer dead, so we disable it by reading |
| 364 | * the Interrupt Pending Message register and clearing both |
| 365 | * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). |
| 366 | * |
| 367 | * Reference: |
| 368 | * "BIOS and Kernel Developer's Guide for AMD NPT |
| 369 | * Family 0Fh Processors" |
| 370 | * #32559 revision 3.00 |
| 371 | */ |
| 372 | if ((cpu_id & 0x00000f00) == 0x00000f00 && |
| 373 | (cpu_id & 0x0fff0000) >= 0x00040000) { |
| 374 | uint64_t msr; |
| 375 | |
| 376 | msr = rdmsr(0xc0010055); |
| 377 | if (msr & 0x18000000) { |
| 378 | struct globaldata *gd = mycpu; |
| 379 | |
| 380 | kprintf("cpu%d: AMD C1E detected\n", |
| 381 | gd->gd_cpuid); |
| 382 | wrmsr(0xc0010055, msr & ~0x18000000ULL); |
| 383 | |
| 384 | /* |
| 385 | * We are kinda stalled; |
| 386 | * kick start again. |
| 387 | */ |
| 388 | gd->gd_timer_running = 1; |
| 389 | lapic_timer_oneshot_quick(2); |
| 390 | |
| 391 | if (started != NULL) |
| 392 | *started = 1; |
| 393 | } |
| 394 | } |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | static void |
| 399 | lapic_timer_restart_handler(void *dummy __unused) |
| 400 | { |
| 401 | int started; |
| 402 | |
| 403 | lapic_timer_fixup_handler(&started); |
| 404 | if (!started) { |
| 405 | struct globaldata *gd = mycpu; |
| 406 | |
| 407 | gd->gd_timer_running = 1; |
| 408 | lapic_timer_oneshot_quick(2); |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | /* |
| 413 | * This function is called only by ACPI-CA code currently: |
| 414 | * - AMD C1E fixup. AMD C1E only seems to happen after ACPI |
| 415 | * module controls PM. So once ACPI-CA is attached, we try |
| 416 | * to apply the fixup to prevent LAPIC timer from hanging. |
| 417 | */ |
| 418 | static void |
| 419 | lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused) |
| 420 | { |
| 421 | lwkt_send_ipiq_mask(smp_active_mask, |
| 422 | lapic_timer_fixup_handler, NULL); |
| 423 | } |
| 424 | |
| 425 | static void |
| 426 | lapic_timer_intr_restart(struct cputimer_intr *cti __unused) |
| 427 | { |
| 428 | lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL); |
| 429 | } |
| 430 | |
| 431 | |
| 432 | /* |
| 433 | * dump contents of local APIC registers |
| 434 | */ |
| 435 | void |
| 436 | apic_dump(char* str) |
| 437 | { |
| 438 | kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str); |
| 439 | kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", |
| 440 | lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); |
| 441 | } |
| 442 | |
| 443 | /* |
| 444 | * Inter Processor Interrupt functions. |
| 445 | */ |
| 446 | |
| 447 | /* |
| 448 | * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'. |
| 449 | * |
| 450 | * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF |
| 451 | * vector is any valid SYSTEM INT vector |
| 452 | * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO |
| 453 | * |
| 454 | * A backlog of requests can create a deadlock between cpus. To avoid this |
| 455 | * we have to be able to accept IPIs at the same time we are trying to send |
| 456 | * them. The critical section prevents us from attempting to send additional |
| 457 | * IPIs reentrantly, but also prevents IPIQ processing so we have to call |
| 458 | * lwkt_process_ipiq() manually. It's rather messy and expensive for this |
| 459 | * to occur but fortunately it does not happen too often. |
| 460 | */ |
| 461 | int |
| 462 | apic_ipi(int dest_type, int vector, int delivery_mode) |
| 463 | { |
| 464 | u_long icr_lo; |
| 465 | |
| 466 | crit_enter(); |
| 467 | if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 468 | unsigned int eflags = read_eflags(); |
| 469 | cpu_enable_intr(); |
| 470 | DEBUG_PUSH_INFO("apic_ipi"); |
| 471 | while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 472 | lwkt_process_ipiq(); |
| 473 | } |
| 474 | DEBUG_POP_INFO(); |
| 475 | write_eflags(eflags); |
| 476 | } |
| 477 | |
| 478 | icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type | |
| 479 | delivery_mode | vector; |
| 480 | lapic->icr_lo = icr_lo; |
| 481 | crit_exit(); |
| 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | void |
| 486 | single_apic_ipi(int cpu, int vector, int delivery_mode) |
| 487 | { |
| 488 | u_long icr_lo; |
| 489 | u_long icr_hi; |
| 490 | |
| 491 | crit_enter(); |
| 492 | if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 493 | unsigned int eflags = read_eflags(); |
| 494 | cpu_enable_intr(); |
| 495 | DEBUG_PUSH_INFO("single_apic_ipi"); |
| 496 | while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 497 | lwkt_process_ipiq(); |
| 498 | } |
| 499 | DEBUG_POP_INFO(); |
| 500 | write_eflags(eflags); |
| 501 | } |
| 502 | icr_hi = lapic->icr_hi & ~APIC_ID_MASK; |
| 503 | icr_hi |= (CPU_TO_ID(cpu) << 24); |
| 504 | lapic->icr_hi = icr_hi; |
| 505 | |
| 506 | /* build ICR_LOW */ |
| 507 | icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) |
| 508 | | APIC_DEST_DESTFLD | delivery_mode | vector; |
| 509 | |
| 510 | /* write APIC ICR */ |
| 511 | lapic->icr_lo = icr_lo; |
| 512 | crit_exit(); |
| 513 | } |
| 514 | |
| 515 | #if 0 |
| 516 | |
| 517 | /* |
| 518 | * Returns 0 if the apic is busy, 1 if we were able to queue the request. |
| 519 | * |
| 520 | * NOT WORKING YET! The code as-is may end up not queueing an IPI at all |
| 521 | * to the target, and the scheduler does not 'poll' for IPI messages. |
| 522 | */ |
| 523 | int |
| 524 | single_apic_ipi_passive(int cpu, int vector, int delivery_mode) |
| 525 | { |
| 526 | u_long icr_lo; |
| 527 | u_long icr_hi; |
| 528 | |
| 529 | crit_enter(); |
| 530 | if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 531 | crit_exit(); |
| 532 | return(0); |
| 533 | } |
| 534 | icr_hi = lapic->icr_hi & ~APIC_ID_MASK; |
| 535 | icr_hi |= (CPU_TO_ID(cpu) << 24); |
| 536 | lapic->icr_hi = icr_hi; |
| 537 | |
| 538 | /* build IRC_LOW */ |
| 539 | icr_lo = (lapic->icr_lo & APIC_RESV2_MASK) |
| 540 | | APIC_DEST_DESTFLD | delivery_mode | vector; |
| 541 | |
| 542 | /* write APIC ICR */ |
| 543 | lapic->icr_lo = icr_lo; |
| 544 | crit_exit(); |
| 545 | return(1); |
| 546 | } |
| 547 | |
| 548 | #endif |
| 549 | |
| 550 | /* |
| 551 | * Send APIC IPI 'vector' to 'target's via 'delivery_mode'. |
| 552 | * |
| 553 | * target is a bitmask of destination cpus. Vector is any |
| 554 | * valid system INT vector. Delivery mode may be either |
| 555 | * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO. |
| 556 | */ |
| 557 | void |
| 558 | selected_apic_ipi(cpumask_t target, int vector, int delivery_mode) |
| 559 | { |
| 560 | crit_enter(); |
| 561 | while (target) { |
| 562 | int n = BSFCPUMASK(target); |
| 563 | target &= ~CPUMASK(n); |
| 564 | single_apic_ipi(n, vector, delivery_mode); |
| 565 | } |
| 566 | crit_exit(); |
| 567 | } |
| 568 | |
| 569 | /* |
| 570 | * Timer code, in development... |
| 571 | * - suggested by rgrimes@gndrsh.aac.dev.com |
| 572 | */ |
| 573 | int |
| 574 | get_apic_timer_frequency(void) |
| 575 | { |
| 576 | return(lapic_cputimer_intr.freq); |
| 577 | } |
| 578 | |
| 579 | /* |
| 580 | * Load a 'downcount time' in uSeconds. |
| 581 | */ |
| 582 | void |
| 583 | set_apic_timer(int us) |
| 584 | { |
| 585 | u_int count; |
| 586 | |
| 587 | /* |
| 588 | * When we reach here, lapic timer's frequency |
| 589 | * must have been calculated as well as the |
| 590 | * divisor (lapic.dcr_timer is setup during the |
| 591 | * divisor calculation). |
| 592 | */ |
| 593 | KKASSERT(lapic_cputimer_intr.freq != 0 && |
| 594 | lapic_timer_divisor_idx >= 0); |
| 595 | |
| 596 | count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000; |
| 597 | lapic_timer_oneshot(count); |
| 598 | } |
| 599 | |
| 600 | |
| 601 | /* |
| 602 | * Read remaining time in timer. |
| 603 | */ |
| 604 | int |
| 605 | read_apic_timer(void) |
| 606 | { |
| 607 | #if 0 |
| 608 | /** XXX FIXME: we need to return the actual remaining time, |
| 609 | * for now we just return the remaining count. |
| 610 | */ |
| 611 | #else |
| 612 | return lapic->ccr_timer; |
| 613 | #endif |
| 614 | } |
| 615 | |
| 616 | |
| 617 | /* |
| 618 | * Spin-style delay, set delay time in uS, spin till it drains. |
| 619 | */ |
| 620 | void |
| 621 | u_sleep(int count) |
| 622 | { |
| 623 | set_apic_timer(count); |
| 624 | while (read_apic_timer()) |
| 625 | /* spin */ ; |
| 626 | } |
| 627 | |
| 628 | int |
| 629 | lapic_unused_apic_id(int start) |
| 630 | { |
| 631 | int i; |
| 632 | |
| 633 | for (i = start; i < NAPICID; ++i) { |
| 634 | if (ID_TO_CPU(i) == -1) |
| 635 | return i; |
| 636 | } |
| 637 | return NAPICID; |
| 638 | } |
| 639 | |
| 640 | void |
| 641 | lapic_map(vm_offset_t lapic_addr) |
| 642 | { |
| 643 | lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC)); |
| 644 | |
| 645 | kprintf("lapic: at %p\n", (void *)lapic_addr); |
| 646 | } |
| 647 | |
| 648 | static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators = |
| 649 | TAILQ_HEAD_INITIALIZER(lapic_enumerators); |
| 650 | |
| 651 | void |
| 652 | lapic_config(void) |
| 653 | { |
| 654 | struct lapic_enumerator *e; |
| 655 | int error, i; |
| 656 | |
| 657 | for (i = 0; i < NAPICID; ++i) |
| 658 | ID_TO_CPU(i) = -1; |
| 659 | |
| 660 | TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { |
| 661 | error = e->lapic_probe(e); |
| 662 | if (!error) |
| 663 | break; |
| 664 | } |
| 665 | if (e == NULL) |
| 666 | panic("can't config lapic\n"); |
| 667 | |
| 668 | e->lapic_enumerate(e); |
| 669 | } |
| 670 | |
| 671 | void |
| 672 | lapic_enumerator_register(struct lapic_enumerator *ne) |
| 673 | { |
| 674 | struct lapic_enumerator *e; |
| 675 | |
| 676 | TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { |
| 677 | if (e->lapic_prio < ne->lapic_prio) { |
| 678 | TAILQ_INSERT_BEFORE(e, ne, lapic_link); |
| 679 | return; |
| 680 | } |
| 681 | } |
| 682 | TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link); |
| 683 | } |
| 684 | |
| 685 | void |
| 686 | lapic_set_cpuid(int cpu_id, int apic_id) |
| 687 | { |
| 688 | CPU_TO_ID(cpu_id) = apic_id; |
| 689 | ID_TO_CPU(apic_id) = cpu_id; |
| 690 | } |