| 1 | /* |
| 2 | * Copyright (c) 2001 Wind River Systems |
| 3 | * Copyright (c) 1997, 1998, 1999, 2000, 2001 |
| 4 | * Bill Paul <wpaul@bsdi.com>. All rights reserved. |
| 5 | * |
| 6 | * Redistribution and use in source and binary forms, with or without |
| 7 | * modification, are permitted provided that the following conditions |
| 8 | * are met: |
| 9 | * 1. Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
| 14 | * 3. All advertising materials mentioning features or use of this software |
| 15 | * must display the following acknowledgement: |
| 16 | * This product includes software developed by Bill Paul. |
| 17 | * 4. Neither the name of the author nor the names of any co-contributors |
| 18 | * may be used to endorse or promote products derived from this software |
| 19 | * without specific prior written permission. |
| 20 | * |
| 21 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 22 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 23 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 24 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 25 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 26 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 27 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 28 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 29 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 31 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | * |
| 33 | * $FreeBSD: src/sys/dev/nge/if_ngereg.h,v 1.4.2.5 2002/11/13 12:54:06 simokawa Exp $ |
| 34 | * $DragonFly: src/sys/dev/netif/nge/if_ngereg.h,v 1.9 2006/08/01 18:05:43 swildner Exp $ |
| 35 | */ |
| 36 | |
| 37 | #define NGE_CSR 0x00 |
| 38 | #define NGE_CFG 0x04 |
| 39 | #define NGE_MEAR 0x08 |
| 40 | #define NGE_PCITST 0x0C |
| 41 | #define NGE_ISR 0x10 |
| 42 | #define NGE_IMR 0x14 |
| 43 | #define NGE_IER 0x18 |
| 44 | #define NGE_IHR 0x1C |
| 45 | #define NGE_TX_LISTPTR_LO 0x20 |
| 46 | #define NGE_TX_LISTPTR_HI 0x24 |
| 47 | #define NGE_TX_LISTPTR NGE_TX_LISTPTR_LO |
| 48 | #define NGE_TX_CFG 0x28 |
| 49 | #define NGE_GPIO 0x2C |
| 50 | #define NGE_RX_LISTPTR_LO 0x30 |
| 51 | #define NGE_RX_LISTPTR_HI 0x34 |
| 52 | #define NGE_RX_LISTPTR NGE_RX_LISTPTR_LO |
| 53 | #define NGE_RX_CFG 0x38 |
| 54 | #define NGE_PRIOQCTL 0x3C |
| 55 | #define NGE_WOLCSR 0x40 |
| 56 | #define NGE_PAUSECSR 0x44 |
| 57 | #define NGE_RXFILT_CTL 0x48 |
| 58 | #define NGE_RXFILT_DATA 0x4C |
| 59 | #define NGE_BOOTROM_ADDR 0x50 |
| 60 | #define NGE_BOOTROM_DATA 0x54 |
| 61 | #define NGE_SILICONREV 0x58 |
| 62 | #define NGE_MIBCTL 0x5C |
| 63 | #define NGE_MIB_RXERRPKT 0x60 |
| 64 | #define NGE_MIB_RXERRFCS 0x64 |
| 65 | #define NGE_MIB_RXERRMISSEDPKT 0x68 |
| 66 | #define NGE_MIB_RXERRALIGN 0x6C |
| 67 | #define NGE_MIB_RXERRSYM 0x70 |
| 68 | #define NGE_MIB_RXERRGIANT 0x74 |
| 69 | #define NGE_MIB_RXERRRANGLEN 0x78 |
| 70 | #define NGE_MIB_RXBADOPCODE 0x7C |
| 71 | #define NGE_MIB_RXPAUSEPKTS 0x80 |
| 72 | #define NGE_MIB_TXPAUSEPKTS 0x84 |
| 73 | #define NGE_MIB_TXERRSQE 0x88 |
| 74 | #define NGE_TXPRIOQ_PTR1 0xA0 |
| 75 | #define NGE_TXPRIOQ_PTR2 0xA4 |
| 76 | #define NGE_TXPRIOQ_PTR3 0xA8 |
| 77 | #define NGE_RXPRIOQ_PTR1 0xB0 |
| 78 | #define NGE_RXPRIOQ_PTR2 0xB4 |
| 79 | #define NGE_RXPRIOQ_PTR3 0xB8 |
| 80 | #define NGE_VLAN_IP_RXCTL 0xBC |
| 81 | #define NGE_VLAN_IP_TXCTL 0xC0 |
| 82 | #define NGE_VLAN_DATA 0xC4 |
| 83 | #define NGE_CLKRUN 0xCC |
| 84 | #define NGE_TBI_BMCR 0xE0 |
| 85 | #define NGE_TBI_BMSR 0xE4 |
| 86 | #define NGE_TBI_ANAR 0xE8 |
| 87 | #define NGE_TBI_ANLPAR 0xEC |
| 88 | #define NGE_TBI_ANER 0xF0 |
| 89 | #define NGE_TBI_ESR 0xF4 |
| 90 | |
| 91 | /* Control/status register */ |
| 92 | #define NGE_CSR_TX_ENABLE 0x00000001 |
| 93 | #define NGE_CSR_TX_DISABLE 0x00000002 |
| 94 | #define NGE_CSR_RX_ENABLE 0x00000004 |
| 95 | #define NGE_CSR_RX_DISABLE 0x00000008 |
| 96 | #define NGE_CSR_TX_RESET 0x00000010 |
| 97 | #define NGE_CSR_RX_RESET 0x00000020 |
| 98 | #define NGE_CSR_SOFTINTR 0x00000080 |
| 99 | #define NGE_CSR_RESET 0x00000100 |
| 100 | #define NGE_CSR_TX_PRIOQ_ENB0 0x00000200 |
| 101 | #define NGE_CSR_TX_PRIOQ_ENB1 0x00000400 |
| 102 | #define NGE_CSR_TX_PRIOQ_ENB2 0x00000800 |
| 103 | #define NGE_CSR_TX_PRIOQ_ENB3 0x00001000 |
| 104 | #define NGE_CSR_RX_PRIOQ_ENB0 0x00002000 |
| 105 | #define NGE_CSR_RX_PRIOQ_ENB1 0x00004000 |
| 106 | #define NGE_CSR_RX_PRIOQ_ENB2 0x00008000 |
| 107 | #define NGE_CSR_RX_PRIOQ_ENB3 0x00010000 |
| 108 | |
| 109 | /* Configuration register */ |
| 110 | #define NGE_CFG_BIGENDIAN 0x00000001 |
| 111 | #define NGE_CFG_EXT_125MHZ 0x00000002 |
| 112 | #define NGE_CFG_BOOTROM_DIS 0x00000004 |
| 113 | #define NGE_CFG_PERR_DETECT 0x00000008 |
| 114 | #define NGE_CFG_DEFER_DISABLE 0x00000010 |
| 115 | #define NGE_CFG_OUTOFWIN_TIMER 0x00000020 |
| 116 | #define NGE_CFG_SINGLE_BACKOFF 0x00000040 |
| 117 | #define NGE_CFG_PCIREQ_ALG 0x00000080 |
| 118 | #define NGE_CFG_EXTSTS_ENB 0x00000100 |
| 119 | #define NGE_CFG_PHY_DIS 0x00000200 |
| 120 | #define NGE_CFG_PHY_RST 0x00000400 |
| 121 | #define NGE_CFG_64BIT_ADDR_ENB 0x00000800 |
| 122 | #define NGE_CFG_64BIT_DATA_ENB 0x00001000 |
| 123 | #define NGE_CFG_64BIT_PCI_DET 0x00002000 |
| 124 | #define NGE_CFG_64BIT_TARG 0x00004000 |
| 125 | #define NGE_CFG_MWI_DIS 0x00008000 |
| 126 | #define NGE_CFG_MRM_DIS 0x00010000 |
| 127 | #define NGE_CFG_TMRTST 0x00020000 |
| 128 | #define NGE_CFG_PHYINTR_SPD 0x00040000 |
| 129 | #define NGE_CFG_PHYINTR_LNK 0x00080000 |
| 130 | #define NGE_CFG_PHYINTR_DUP 0x00100000 |
| 131 | #define NGE_CFG_MODE_1000 0x00400000 |
| 132 | #define NGE_CFG_TBI_EN 0x01000000 |
| 133 | #define NGE_CFG_DUPLEX_STS 0x10000000 |
| 134 | #define NGE_CFG_SPEED_STS 0x60000000 |
| 135 | #define NGE_CFG_LINK_STS 0x80000000 |
| 136 | |
| 137 | /* MII/EEPROM control register */ |
| 138 | #define NGE_MEAR_EE_DIN 0x00000001 |
| 139 | #define NGE_MEAR_EE_DOUT 0x00000002 |
| 140 | #define NGE_MEAR_EE_CLK 0x00000004 |
| 141 | #define NGE_MEAR_EE_CSEL 0x00000008 |
| 142 | #define NGE_MEAR_MII_DATA 0x00000010 |
| 143 | #define NGE_MEAR_MII_DIR 0x00000020 |
| 144 | #define NGE_MEAR_MII_CLK 0x00000040 |
| 145 | |
| 146 | #define NGE_EECMD_WRITE 0x140 |
| 147 | #define NGE_EECMD_READ 0x180 |
| 148 | #define NGE_EECMD_ERASE 0x1c0 |
| 149 | |
| 150 | #define NGE_EE_NODEADDR 0xA |
| 151 | |
| 152 | /* PCI control register */ |
| 153 | #define NGE_PCICTL_SRAMADDR 0x0000001F |
| 154 | #define NGE_PCICTL_RAMTSTENB 0x00000020 |
| 155 | #define NGE_PCICTL_TXTSTENB 0x00000040 |
| 156 | #define NGE_PCICTL_RXTSTENB 0x00000080 |
| 157 | #define NGE_PCICTL_BMTSTENB 0x00000200 |
| 158 | #define NGE_PCICTL_RAMADDR 0x001F0000 |
| 159 | #define NGE_PCICTL_ROMTIME 0x0F000000 |
| 160 | #define NGE_PCICTL_DISCTEST 0x40000000 |
| 161 | |
| 162 | /* Interrupt/status register */ |
| 163 | #define NGE_ISR_RX_OK 0x00000001 |
| 164 | #define NGE_ISR_RX_DESC_OK 0x00000002 |
| 165 | #define NGE_ISR_RX_ERR 0x00000004 |
| 166 | #define NGE_ISR_RX_EARLY 0x00000008 |
| 167 | #define NGE_ISR_RX_IDLE 0x00000010 |
| 168 | #define NGE_ISR_RX_OFLOW 0x00000020 |
| 169 | #define NGE_ISR_TX_OK 0x00000040 |
| 170 | #define NGE_ISR_TX_DESC_OK 0x00000080 |
| 171 | #define NGE_ISR_TX_ERR 0x00000100 |
| 172 | #define NGE_ISR_TX_IDLE 0x00000200 |
| 173 | #define NGE_ISR_TX_UFLOW 0x00000400 |
| 174 | #define NGE_ISR_MIB_SERVICE 0x00000800 |
| 175 | #define NGE_ISR_SOFTINTR 0x00001000 |
| 176 | #define NGE_ISR_PME_EVENT 0x00002000 |
| 177 | #define NGE_ISR_PHY_INTR 0x00004000 |
| 178 | #define NGE_ISR_HIBITS 0x00008000 |
| 179 | #define NGE_ISR_RX_FIFO_OFLOW 0x00010000 |
| 180 | #define NGE_ISR_TGT_ABRT 0x00020000 |
| 181 | #define NGE_ISR_BM_ABRT 0x00040000 |
| 182 | #define NGE_ISR_SYSERR 0x00080000 |
| 183 | #define NGE_ISR_PARITY_ERR 0x00100000 |
| 184 | #define NGE_ISR_RX_RESET_DONE 0x00200000 |
| 185 | #define NGE_ISR_TX_RESET_DONE 0x00400000 |
| 186 | #define NGE_ISR_RX_PRIOQ_DESC0 0x00800000 |
| 187 | #define NGE_ISR_RX_PRIOQ_DESC1 0x01000000 |
| 188 | #define NGE_ISR_RX_PRIOQ_DESC2 0x02000000 |
| 189 | #define NGE_ISR_RX_PRIOQ_DESC3 0x04000000 |
| 190 | #define NGE_ISR_TX_PRIOQ_DESC0 0x08000000 |
| 191 | #define NGE_ISR_TX_PRIOQ_DESC1 0x10000000 |
| 192 | #define NGE_ISR_TX_PRIOQ_DESC2 0x20000000 |
| 193 | #define NGE_ISR_TX_PRIOQ_DESC3 0x40000000 |
| 194 | |
| 195 | /* Interrupt mask register */ |
| 196 | #define NGE_IMR_RX_OK 0x00000001 |
| 197 | #define NGE_IMR_RX_DESC_OK 0x00000002 |
| 198 | #define NGE_IMR_RX_ERR 0x00000004 |
| 199 | #define NGE_IMR_RX_EARLY 0x00000008 |
| 200 | #define NGE_IMR_RX_IDLE 0x00000010 |
| 201 | #define NGE_IMR_RX_OFLOW 0x00000020 |
| 202 | #define NGE_IMR_TX_OK 0x00000040 |
| 203 | #define NGE_IMR_TX_DESC_OK 0x00000080 |
| 204 | #define NGE_IMR_TX_ERR 0x00000100 |
| 205 | #define NGE_IMR_TX_IDLE 0x00000200 |
| 206 | #define NGE_IMR_TX_UFLOW 0x00000400 |
| 207 | #define NGE_IMR_MIB_SERVICE 0x00000800 |
| 208 | #define NGE_IMR_SOFTINTR 0x00001000 |
| 209 | #define NGE_IMR_PME_EVENT 0x00002000 |
| 210 | #define NGE_IMR_PHY_INTR 0x00004000 |
| 211 | #define NGE_IMR_HIBITS 0x00008000 |
| 212 | #define NGE_IMR_RX_FIFO_OFLOW 0x00010000 |
| 213 | #define NGE_IMR_TGT_ABRT 0x00020000 |
| 214 | #define NGE_IMR_BM_ABRT 0x00040000 |
| 215 | #define NGE_IMR_SYSERR 0x00080000 |
| 216 | #define NGE_IMR_PARITY_ERR 0x00100000 |
| 217 | #define NGE_IMR_RX_RESET_DONE 0x00200000 |
| 218 | #define NGE_IMR_TX_RESET_DONE 0x00400000 |
| 219 | #define NGE_IMR_RX_PRIOQ_DESC0 0x00800000 |
| 220 | #define NGE_IMR_RX_PRIOQ_DESC1 0x01000000 |
| 221 | #define NGE_IMR_RX_PRIOQ_DESC2 0x02000000 |
| 222 | #define NGE_IMR_RX_PRIOQ_DESC3 0x04000000 |
| 223 | #define NGE_IMR_TX_PRIOQ_DESC0 0x08000000 |
| 224 | #define NGE_IMR_TX_PRIOQ_DESC1 0x10000000 |
| 225 | #define NGE_IMR_TX_PRIOQ_DESC2 0x20000000 |
| 226 | #define NGE_IMR_TX_PRIOQ_DESC3 0x40000000 |
| 227 | |
| 228 | #define NGE_INTRS \ |
| 229 | (NGE_IMR_RX_OFLOW|NGE_IMR_TX_UFLOW|NGE_IMR_TX_OK|\ |
| 230 | NGE_IMR_TX_IDLE|NGE_IMR_RX_OK|NGE_IMR_RX_ERR|\ |
| 231 | NGE_IMR_SYSERR|NGE_IMR_PHY_INTR|\ |
| 232 | NGE_IMR_RX_IDLE|NGE_IMR_RX_FIFO_OFLOW) |
| 233 | |
| 234 | /* Interrupt enable register */ |
| 235 | #define NGE_IER_INTRENB 0x00000001 |
| 236 | |
| 237 | /* Interrupt moderation timer register */ |
| 238 | #define NGE_IHR_HOLDOFF 0x000000FF |
| 239 | #define NGE_IHR_HOLDCTL 0x00000100 |
| 240 | |
| 241 | /* Transmit configuration register */ |
| 242 | #define NGE_TXCFG_DRAIN_THRESH 0x000000FF /* 32-byte units */ |
| 243 | #define NGE_TXCFG_FILL_THRESH 0x0000FF00 /* 32-byte units */ |
| 244 | #define NGE_1000MB_BURST_DIS 0x00080000 |
| 245 | #define NGE_TXCFG_DMABURST 0x00700000 |
| 246 | #define NGE_TXCFG_ECRETRY 0x00800000 |
| 247 | #define NGE_TXCFG_AUTOPAD 0x10000000 |
| 248 | #define NGE_TXCFG_LOOPBK 0x20000000 |
| 249 | #define NGE_TXCFG_IGN_HBEAT 0x40000000 |
| 250 | #define NGE_TXCFG_IGN_CARR 0x80000000 |
| 251 | |
| 252 | #define NGE_TXCFG_DRAIN(x) (((x) >> 5) & NGE_TXCFG_DRAIN_THRESH) |
| 253 | #define NGE_TXCFG_FILL(x) ((((x) >> 5) << 8) & NGE_TXCFG_FILL_THRESH) |
| 254 | |
| 255 | #define NGE_TXDMA_1024BYTES 0x00000000 |
| 256 | #define NGE_TXDMA_8BYTES 0x00100000 |
| 257 | #define NGE_TXDMA_16BYTES 0x00200000 |
| 258 | #define NGE_TXDMA_32BYTES 0x00300000 |
| 259 | #define NGE_TXDMA_64BYTES 0x00400000 |
| 260 | #define NGE_TXDMA_128BYTES 0x00500000 |
| 261 | #define NGE_TXDMA_256BYTES 0x00600000 |
| 262 | #define NGE_TXDMA_512BYTES 0x00700000 |
| 263 | |
| 264 | #define NGE_TXCFG \ |
| 265 | (NGE_TXDMA_512BYTES|NGE_TXCFG_AUTOPAD|\ |
| 266 | NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(6400)) |
| 267 | |
| 268 | /* GPIO register */ |
| 269 | #define NGE_GPIO_GP1_OUT 0x00000001 |
| 270 | #define NGE_GPIO_GP2_OUT 0x00000002 |
| 271 | #define NGE_GPIO_GP3_OUT 0x00000004 |
| 272 | #define NGE_GPIO_GP4_OUT 0x00000008 |
| 273 | #define NGE_GPIO_GP5_OUT 0x00000010 |
| 274 | #define NGE_GPIO_GP1_OUTENB 0x00000020 |
| 275 | #define NGE_GPIO_GP2_OUTENB 0x00000040 |
| 276 | #define NGE_GPIO_GP3_OUTENB 0x00000080 |
| 277 | #define NGE_GPIO_GP4_OUTENB 0x00000100 |
| 278 | #define NGE_GPIO_GP5_OUTENB 0x00000200 |
| 279 | #define NGE_GPIO_GP1_IN 0x00000400 |
| 280 | #define NGE_GPIO_GP2_IN 0x00000800 |
| 281 | #define NGE_GPIO_GP3_IN 0x00001000 |
| 282 | #define NGE_GPIO_GP4_IN 0x00002000 |
| 283 | #define NGE_GPIO_GP5_IN 0x00004000 |
| 284 | |
| 285 | /* Receive configuration register */ |
| 286 | #define NGE_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ |
| 287 | #define NGE_RXCFG_DMABURST 0x00700000 |
| 288 | #define NGE_RXCFG_RX_RANGEERR 0x04000000 /* accept in-range err frames */ |
| 289 | #define NGE_RXCFG_RX_GIANTS 0x08000000 /* accept packets > 1518 bytes */ |
| 290 | #define NGE_RXCFG_RX_FDX 0x10000000 /* full duplex receive */ |
| 291 | #define NGE_RXCFG_RX_NOCRC 0x20000000 /* strip CRC */ |
| 292 | #define NGE_RXCFG_RX_RUNT 0x40000000 /* accept short frames */ |
| 293 | #define NGE_RXCFG_RX_BADPKTS 0x80000000 /* accept error frames */ |
| 294 | |
| 295 | #define NGE_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & NGE_RXCFG_DRAIN_THRESH) |
| 296 | |
| 297 | #define NGE_RXDMA_1024BYTES 0x00000000 |
| 298 | #define NGE_RXDMA_8BYTES 0x00100000 |
| 299 | #define NGE_RXDMA_16BYTES 0x00200000 |
| 300 | #define NGE_RXDMA_32YTES 0x00300000 |
| 301 | #define NGE_RXDMA_64BYTES 0x00400000 |
| 302 | #define NGE_RXDMA_128BYTES 0x00500000 |
| 303 | #define NGE_RXDMA_256BYTES 0x00600000 |
| 304 | #define NGE_RXDMA_512BYTES 0x00700000 |
| 305 | |
| 306 | #define NGE_RXCFG \ |
| 307 | (NGE_RXCFG_DRAIN(64)|NGE_RXDMA_256BYTES|\ |
| 308 | NGE_RXCFG_RX_GIANTS|NGE_RXCFG_RX_NOCRC) |
| 309 | |
| 310 | /* Priority queue control */ |
| 311 | #define NGE_PRIOQCTL_TXPRIO_ENB 0x00000001 |
| 312 | #define NGE_PRIOQCTL_TXFAIR_ENB 0x00000002 |
| 313 | #define NGE_PRIOQCTL_RXPRIO 0x0000000C |
| 314 | |
| 315 | #define NGE_RXPRIOQ_DISABLED 0x00000000 |
| 316 | #define NGE_RXPRIOQ_TWOQS 0x00000004 |
| 317 | #define NGE_RXPRIOQ_THREEQS 0x00000008 |
| 318 | #define NGE_RXPRIOQ_FOURQS 0x0000000C |
| 319 | |
| 320 | /* Wake On LAN command/status register */ |
| 321 | #define NGE_WOLCSR_WAKE_ON_PHYINTR 0x00000001 |
| 322 | #define NGE_WOLCSR_WAKE_ON_UNICAST 0x00000002 |
| 323 | #define NGE_WOLCSR_WAKE_ON_MULTICAST 0x00000004 |
| 324 | #define NGR_WOLCSR_WAKE_ON_BROADCAST 0x00000008 |
| 325 | #define NGE_WOLCSR_WAKE_ON_ARP 0x00000010 |
| 326 | #define NGE_WOLCSR_WAKE_ON_PAT0_MATCH 0x00000020 |
| 327 | #define NGE_WOLCSR_WAKE_ON_PAT1_MATCH 0x00000040 |
| 328 | #define NGE_WOLCSR_WAKE_ON_PAT2_MATCH 0x00000080 |
| 329 | #define NGE_WOLCSR_WAKE_ON_PAT3_MATCH 0x00000100 |
| 330 | #define NGE_WOLCSR_SECUREON_ENB 0x00000200 |
| 331 | #define NGE_WOLCSR_SECUREON_HACK 0x00200000 |
| 332 | #define NGE_WOLCSR_PHYINTR 0x00400000 |
| 333 | #define NGE_WOLCSR_UNICAST 0x00800000 |
| 334 | #define NGE_WOLCSR_MULTICAST 0x01000000 |
| 335 | #define NGE_WOLCSR_BROADCAST 0x02000000 |
| 336 | #define NGE_WOLCSR_ARP_RCVD 0x04000000 |
| 337 | #define NGE_WOLCSR_PAT0_MATCH 0x08000000 |
| 338 | #define NGE_WOLCSR_PAT1_MATCH 0x10000000 |
| 339 | #define NGE_WOLCSR_PAT2_MATCH 0x20000000 |
| 340 | #define NGE_WOLCSR_PAT3_MATCH 0x40000000 |
| 341 | #define NGE_WOLCSR_MAGICPKT 0x80000000 |
| 342 | |
| 343 | /* Pause control/status register */ |
| 344 | #define NGE_PAUSECSR_CNT 0x0000FFFF |
| 345 | #define NGE_PAUSECSR_PFRAME_SENT 0x00020000 |
| 346 | #define NGE_PAUSECSR_RX_DATAFIFO_THR_LO 0x000C0000 |
| 347 | #define NGE_PAUSECSR_RX_DATAFIFO_THR_HI 0x00300000 |
| 348 | #define NGE_PAUSECSR_RX_STATFIFO_THR_LO 0x00C00000 |
| 349 | #define NGE_PAUSECSR_RX_STATFIFO_THR_HI 0x03000000 |
| 350 | #define NGE_PAUSECSR_PFRAME_RCVD 0x08000000 |
| 351 | #define NGE_PAUSECSR_PAUSE_ACTIVE 0x10000000 |
| 352 | #define NGE_PAUSECSR_PAUSE_ON_DA 0x20000000 /* pause on direct addr */ |
| 353 | #define NGE_PAUSECSR_PAUSE_ON_MCAST 0x40000000 /* pause on mcast */ |
| 354 | #define NGE_PAUSECSR_PAUSE_ENB 0x80000000 |
| 355 | |
| 356 | /* Receive filter/match control message */ |
| 357 | #define MGE_RXFILTCTL_ADDR 0x000003FF |
| 358 | #define NGE_RXFILTCTL_ULMASK 0x00080000 |
| 359 | #define NGE_RXFILTCTL_UCHASH 0x00100000 |
| 360 | #define NGE_RXFILTCTL_MCHASH 0x00200000 |
| 361 | #define NGE_RXFILTCTL_ARP 0x00400000 |
| 362 | #define NGE_RXFILTCTL_PMATCH0 0x00800000 |
| 363 | #define NGE_RXFILTCTL_PMATCH1 0x01000000 |
| 364 | #define NGE_RXFILTCTL_PMATCH2 0x02000000 |
| 365 | #define NGE_RXFILTCTL_PMATCH3 0x04000000 |
| 366 | #define NGE_RXFILTCTL_PERFECT 0x08000000 |
| 367 | #define NGE_RXFILTCTL_ALLPHYS 0x10000000 |
| 368 | #define NGE_RXFILTCTL_ALLMULTI 0x20000000 |
| 369 | #define NGE_RXFILTCTL_BROAD 0x40000000 |
| 370 | #define NGE_RXFILTCTL_ENABLE 0x80000000 |
| 371 | |
| 372 | |
| 373 | #define NGE_FILTADDR_PAR0 0x00000000 |
| 374 | #define NGE_FILTADDR_PAR1 0x00000002 |
| 375 | #define NGE_FILTADDR_PAR2 0x00000004 |
| 376 | #define NGE_FILTADDR_PMATCH0 0x00000006 |
| 377 | #define NGE_FILTADDR_PMATCH1 0x00000008 |
| 378 | #define NGE_FILTADDR_SOPASS0 0x0000000A |
| 379 | #define NGE_FILTADDR_SOPASS1 0x0000000C |
| 380 | #define NGE_FILTADDR_SOPASS2 0x0000000E |
| 381 | #define NGE_FILTADDR_FMEM_LO 0x00000100 |
| 382 | #define NGE_FILTADDR_FMEM_HI 0x000003FE |
| 383 | #define NGE_FILTADDR_MCAST_LO 0x00000100 /* start of multicast filter */ |
| 384 | #define NGE_FILTADDR_MCAST_HI 0x000001FE /* end of multicast filter */ |
| 385 | #define NGE_MCAST_FILTER_LEN 256 /* bytes */ |
| 386 | #define NGE_FILTADDR_PBUF0 0x00000200 /* pattern buffer 0 */ |
| 387 | #define NGE_FILTADDR_PBUF1 0x00000280 /* pattern buffer 1 */ |
| 388 | #define NGE_FILTADDR_PBUF2 0x00000300 /* pattern buffer 2 */ |
| 389 | #define NGE_FILTADDR_PBUF3 0x00000380 /* pattern buffer 3 */ |
| 390 | |
| 391 | /* MIB control register */ |
| 392 | #define NGE_MIBCTL_WARNTEST 0x00000001 |
| 393 | #define NGE_MIBCTL_FREEZE_CNT 0x00000002 |
| 394 | #define NGE_MIBCTL_CLEAR_CNT 0x00000004 |
| 395 | #define NGE_MIBCTL_STROBE_CNT 0x00000008 |
| 396 | |
| 397 | /* VLAN/IP RX control register */ |
| 398 | #define NGE_VIPRXCTL_TAG_DETECT_ENB 0x00000001 |
| 399 | #define NGE_VIPRXCTL_TAG_STRIP_ENB 0x00000002 |
| 400 | #define NGE_VIPRXCTL_DROP_TAGGEDPKTS 0x00000004 |
| 401 | #define NGE_VIPRXCTL_DROP_UNTAGGEDPKTS 0x00000008 |
| 402 | #define NGE_VIPRXCTL_IPCSUM_ENB 0x00000010 |
| 403 | #define NGE_VIPRXCTL_REJECT_BADIPCSUM 0x00000020 |
| 404 | #define NGE_VIPRXCTL_REJECT_BADTCPCSUM 0x00000040 |
| 405 | #define NGE_VIPRXCTL_REJECT_BADUDPCSUM 0x00000080 |
| 406 | |
| 407 | /* VLAN/IP TX control register */ |
| 408 | #define NGE_VIPTXCTL_TAG_ALL 0x00000001 |
| 409 | #define NGE_VIPTXCTL_TAG_PER_PKT 0x00000002 |
| 410 | #define NGE_VIPTXCTL_CSUM_ALL 0x00000004 |
| 411 | #define NGE_VIPTXCTL_CSUM_PER_PKT 0x00000008 |
| 412 | |
| 413 | /* VLAN data register */ |
| 414 | #define NGE_VLANDATA_VTYPE 0x0000FFFF |
| 415 | #define NGE_VLANDATA_VTCI 0xFFFF0000 |
| 416 | |
| 417 | /* Clockrun register */ |
| 418 | #define NGE_CLKRUN_PMESTS 0x00008000 |
| 419 | #define NGE_CLKRUN_PMEENB 0x00000100 |
| 420 | #define NGE_CLNRUN_CLKRUN_ENB 0x00000001 |
| 421 | |
| 422 | |
| 423 | /* TBI BMCR */ |
| 424 | #define NGE_TBIBMCR_RESTART_ANEG 0x00000200 |
| 425 | #define NGE_TBIBMCR_ENABLE_ANEG 0x00001000 |
| 426 | #define NGE_TBIBMCR_LOOPBACK 0x00004000 |
| 427 | |
| 428 | /* TBI BMSR */ |
| 429 | #define NGE_TBIBMSR_ANEG_DONE 0x00000004 |
| 430 | #define NGE_TBIBMSR_LINKSTAT 0x00000020 |
| 431 | |
| 432 | /* TBI ANAR */ |
| 433 | #define NGE_TBIANAR_HDX 0x00000020 |
| 434 | #define NGE_TBIANAR_FDX 0x00000040 |
| 435 | #define NGE_TBIANAR_PS1 0x00000080 |
| 436 | #define NGE_TBIANAR_PS2 0x00000100 |
| 437 | #define NGE_TBIANAR_PCAP 0x00000180 |
| 438 | #define NGE_TBIANAR_REMFAULT 0x00003000 |
| 439 | #define NGE_TBIANAR_NEXTPAGE 0x00008000 |
| 440 | |
| 441 | /* TBI ANLPAR */ |
| 442 | #define NGE_TBIANLPAR_HDX 0x00000020 |
| 443 | #define NGE_TBIANLPAR_FDX 0x00000040 |
| 444 | #define NGE_TBIANAR_PS1 0x00000080 |
| 445 | #define NGE_TBIANAR_PS2 0x00000100 |
| 446 | #define NGE_TBIANLPAR_PCAP 0x00000180 |
| 447 | #define NGE_TBIANLPAR_REMFAULT 0x00003000 |
| 448 | #define NGE_TBIANLPAR_NEXTPAGE 0x00008000 |
| 449 | |
| 450 | /* TBI ANER */ |
| 451 | #define NGE_TBIANER_PAGERCVD 0x00000002 |
| 452 | #define NGE_TBIANER_NEXTPGABLE 0x00000004 |
| 453 | |
| 454 | /* TBI EXTSTS */ |
| 455 | #define NGE_TBIEXTSTS_HXD 0x00004000 |
| 456 | #define NGE_TBIEXTSTS_FXD 0x00008000 |
| 457 | |
| 458 | /* |
| 459 | * DMA descriptor structures. The RX and TX descriptor formats are |
| 460 | * deliberately designed to be similar to facilitate passing them between |
| 461 | * RX and TX queues on multiple controllers, in the case where you have |
| 462 | * multiple MACs in a switching configuration. With the 83820, the pointer |
| 463 | * values can be either 64 bits or 32 bits depending on how the chip is |
| 464 | * configured. For the 83821, the fields are always 32-bits. There is |
| 465 | * also an optional extended status field for VLAN and TCP/IP checksum |
| 466 | * functions. We use the checksum feature so we enable the use of this |
| 467 | * field. Descriptors must be 64-bit aligned. |
| 468 | * After this, we include some additional structure members for |
| 469 | * use by the driver. |
| 470 | */ |
| 471 | struct nge_desc_64 { |
| 472 | /* Hardware descriptor section */ |
| 473 | uint32_t nge_next_lo; |
| 474 | uint32_t nge_next_hi; |
| 475 | uint32_t nge_ptr_lo; |
| 476 | uint32_t nge_ptr_hi; |
| 477 | uint32_t nge_cmdsts; |
| 478 | #define nge_rxstat nge_cmdsts |
| 479 | #define nge_txstat nge_cmdsts |
| 480 | #define nge_ctl nge_cmdsts |
| 481 | uint32_t nge_extsts; |
| 482 | /* Driver software section */ |
| 483 | union { |
| 484 | struct mbuf *nge_mbuf; |
| 485 | uint64_t nge_dummy; |
| 486 | } nge_mb_u; |
| 487 | union { |
| 488 | struct nge_desc_64 *nge_nextdesc; |
| 489 | uint64_t nge_dummy; |
| 490 | } nge_nd_u; |
| 491 | }; |
| 492 | |
| 493 | struct nge_desc_32 { |
| 494 | /* Hardware descriptor section */ |
| 495 | uint32_t nge_next; |
| 496 | uint32_t nge_ptr; |
| 497 | uint32_t nge_cmdsts; |
| 498 | #define nge_rxstat nge_cmdsts |
| 499 | #define nge_txstat nge_cmdsts |
| 500 | #define nge_ctl nge_cmdsts |
| 501 | uint32_t nge_extsts; |
| 502 | /* Driver software section */ |
| 503 | union { |
| 504 | struct mbuf *nge_mbuf; |
| 505 | uint64_t nge_dummy; |
| 506 | } nge_mb_u; |
| 507 | union { |
| 508 | struct nge_desc_32 *nge_nextdesc; |
| 509 | uint64_t nge_dummy; |
| 510 | } nge_nd_u; |
| 511 | }; |
| 512 | |
| 513 | #define nge_desc nge_desc_32 |
| 514 | #define nge_mbuf nge_mb_u.nge_mbuf |
| 515 | #define nge_nextdesc nge_nd_u.nge_nextdesc |
| 516 | |
| 517 | #define NGE_CMDSTS_BUFLEN 0x0000FFFF |
| 518 | #define NGE_CMDSTS_PKT_OK 0x08000000 |
| 519 | #define NGE_CMDSTS_CRC 0x10000000 |
| 520 | #define NGE_CMDSTS_INTR 0x20000000 |
| 521 | #define NGE_CMDSTS_MORE 0x40000000 |
| 522 | #define NGE_CMDSTS_OWN 0x80000000 |
| 523 | |
| 524 | #define NGE_LASTDESC(x) (!((x)->nge_ctl & NGE_CMDSTS_MORE))) |
| 525 | #define NGE_OWNDESC(x) ((x)->nge_ctl & NGE_CMDSTS_OWN) |
| 526 | #define NGE_INC(x, y) (x) = (x + 1) % y |
| 527 | #define NGE_RXBYTES(x) ((x)->nge_ctl & NGE_CMDSTS_BUFLEN) |
| 528 | |
| 529 | #define NGE_RXSTAT_RANGELENERR 0x00010000 |
| 530 | #define NGE_RXSTAT_LOOPBK 0x00020000 |
| 531 | #define NGE_RXSTAT_ALIGNERR 0x00040000 |
| 532 | #define NGE_RXSTAT_CRCERR 0x00080000 |
| 533 | #define NGE_RXSTAT_SYMBOLERR 0x00100000 |
| 534 | #define NGE_RXSTAT_RUNT 0x00200000 |
| 535 | #define NGE_RXSTAT_GIANT 0x00400000 |
| 536 | #define NGE_RXSTAT_DSTCLASS 0x01800000 |
| 537 | #define NGE_RXSTAT_OVERRUN 0x02000000 |
| 538 | #define NGE_RXSTAT_RX_ABORT 0x04000000 |
| 539 | |
| 540 | #define NGE_DSTCLASS_REJECT 0x00000000 |
| 541 | #define NGE_DSTCLASS_UNICAST 0x00800000 |
| 542 | #define NGE_DSTCLASS_MULTICAST 0x01000000 |
| 543 | #define NGE_DSTCLASS_BROADCAST 0x02000000 |
| 544 | |
| 545 | #define NGE_TXSTAT_COLLCNT 0x000F0000 |
| 546 | #define NGE_TXSTAT_EXCESSCOLLS 0x00100000 |
| 547 | #define NGE_TXSTAT_OUTOFWINCOLL 0x00200000 |
| 548 | #define NGE_TXSTAT_EXCESS_DEFER 0x00400000 |
| 549 | #define NGE_TXSTAT_DEFERED 0x00800000 |
| 550 | #define NGE_TXSTAT_CARR_LOST 0x01000000 |
| 551 | #define NGE_TXSTAT_UNDERRUN 0x02000000 |
| 552 | #define NGE_TXSTAT_TX_ABORT 0x04000000 |
| 553 | |
| 554 | #define NGE_TXEXTSTS_VLAN_TCI 0x0000FFFF |
| 555 | #define NGE_TXEXTSTS_VLANPKT 0x00010000 |
| 556 | #define NGE_TXEXTSTS_IPCSUM 0x00020000 |
| 557 | #define NGE_TXEXTSTS_TCPCSUM 0x00080000 |
| 558 | #define NGE_TXEXTSTS_UDPCSUM 0x00200000 |
| 559 | |
| 560 | #define NGE_RXEXTSTS_VTCI 0x0000FFFF |
| 561 | #define NGE_RXEXTSTS_VLANPKT 0x00010000 |
| 562 | #define NGE_RXEXTSTS_IPPKT 0x00020000 |
| 563 | #define NGE_RXEXTSTS_IPCSUMERR 0x00040000 |
| 564 | #define NGE_RXEXTSTS_TCPPKT 0x00080000 |
| 565 | #define NGE_RXEXTSTS_TCPCSUMERR 0x00100000 |
| 566 | #define NGE_RXEXTSTS_UDPPKT 0x00200000 |
| 567 | #define NGE_RXEXTSTS_UDPCSUMERR 0x00400000 |
| 568 | |
| 569 | #define NGE_RX_LIST_CNT 128 |
| 570 | #define NGE_TX_LIST_CNT 128 |
| 571 | |
| 572 | struct nge_list_data { |
| 573 | struct nge_desc nge_rx_list[NGE_RX_LIST_CNT]; |
| 574 | struct nge_desc nge_tx_list[NGE_TX_LIST_CNT]; |
| 575 | }; |
| 576 | |
| 577 | struct nge_type { |
| 578 | uint16_t nge_vid; |
| 579 | uint16_t nge_did; |
| 580 | char *nge_name; |
| 581 | }; |
| 582 | |
| 583 | struct nge_mii_frame { |
| 584 | uint8_t mii_stdelim; |
| 585 | uint8_t mii_opcode; |
| 586 | uint8_t mii_phyaddr; |
| 587 | uint8_t mii_regaddr; |
| 588 | uint8_t mii_turnaround; |
| 589 | uint16_t mii_data; |
| 590 | }; |
| 591 | |
| 592 | /* |
| 593 | * MII constants |
| 594 | */ |
| 595 | #define NGE_MII_STARTDELIM 0x01 |
| 596 | #define NGE_MII_READOP 0x02 |
| 597 | #define NGE_MII_WRITEOP 0x01 |
| 598 | #define NGE_MII_TURNAROUND 0x02 |
| 599 | |
| 600 | #define NGE_JUMBO_FRAMELEN 9018 |
| 601 | #define NGE_JUMBO_MTU (NGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) |
| 602 | #define NGE_JSLOTS 384 |
| 603 | |
| 604 | #define NGE_JRAWLEN (NGE_JUMBO_FRAMELEN + ETHER_ALIGN) |
| 605 | #define NGE_JLEN (NGE_JRAWLEN + \ |
| 606 | (sizeof(uint64_t) - NGE_JRAWLEN % sizeof(uint64_t))) |
| 607 | #define NGE_JPAGESZ PAGE_SIZE |
| 608 | #define NGE_RESID (NGE_JPAGESZ - (NGE_JLEN * NGE_JSLOTS) % NGE_JPAGESZ) |
| 609 | #define NGE_JMEM ((NGE_JLEN * NGE_JSLOTS) + NGE_RESID) |
| 610 | |
| 611 | struct nge_softc; |
| 612 | |
| 613 | struct nge_jslot { |
| 614 | struct nge_softc *nge_sc; |
| 615 | void *nge_buf; |
| 616 | int nge_inuse; |
| 617 | int nge_slot; |
| 618 | SLIST_ENTRY(nge_jslot) jslot_link; |
| 619 | }; |
| 620 | |
| 621 | struct nge_ring_data { |
| 622 | int nge_rx_prod; |
| 623 | int nge_tx_prod; |
| 624 | int nge_tx_cons; |
| 625 | int nge_tx_cnt; |
| 626 | /* Stick the jumbo mem management stuff here too. */ |
| 627 | struct nge_jslot nge_jslots[NGE_JSLOTS]; |
| 628 | void *nge_jumbo_buf; |
| 629 | }; |
| 630 | |
| 631 | struct nge_softc { |
| 632 | struct arpcom arpcom; /* interface info */ |
| 633 | bus_space_handle_t nge_bhandle; |
| 634 | bus_space_tag_t nge_btag; |
| 635 | struct resource *nge_res; |
| 636 | struct resource *nge_irq; |
| 637 | void *nge_intrhand; |
| 638 | device_t nge_miibus; |
| 639 | int nge_if_flags; |
| 640 | uint8_t nge_unit; |
| 641 | uint8_t nge_type; |
| 642 | uint8_t nge_link; |
| 643 | uint8_t nge_width; |
| 644 | #define NGE_WIDTH_32BITS 0 |
| 645 | #define NGE_WIDTH_64BITS 1 |
| 646 | struct ifpoll_compat nge_npoll; |
| 647 | struct nge_list_data *nge_ldata; |
| 648 | struct nge_ring_data nge_cdata; |
| 649 | struct callout nge_stat_timer; |
| 650 | SLIST_HEAD(__nge_jfreehead, nge_jslot) nge_jfree_listhead; |
| 651 | struct lwkt_serialize nge_jslot_serializer; |
| 652 | uint8_t nge_tbi; |
| 653 | struct ifmedia nge_ifmedia; |
| 654 | int rxcycles; |
| 655 | }; |
| 656 | |
| 657 | /* |
| 658 | * register space access macros |
| 659 | */ |
| 660 | #define CSR_WRITE_4(sc, reg, val) \ |
| 661 | bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val) |
| 662 | |
| 663 | #define CSR_READ_4(sc, reg) \ |
| 664 | bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg) |
| 665 | |
| 666 | #define NGE_TIMEOUT 1000 |
| 667 | #define ETHER_ALIGN 2 |
| 668 | #define NGE_RXLEN 1536 |
| 669 | #define NGE_MIN_FRAMELEN 60 |
| 670 | |
| 671 | /* |
| 672 | * PCI low memory base and low I/O base register, and |
| 673 | * other PCI registers. |
| 674 | */ |
| 675 | |
| 676 | #define NGE_PCI_VENDOR_ID 0x00 |
| 677 | #define NGE_PCI_DEVICE_ID 0x02 |
| 678 | #define NGE_PCI_COMMAND 0x04 |
| 679 | #define NGE_PCI_STATUS 0x06 |
| 680 | #define NGE_PCI_REVID 0x08 |
| 681 | #define NGE_PCI_CLASSCODE 0x09 |
| 682 | #define NGE_PCI_CACHELEN 0x0C |
| 683 | #define NGE_PCI_LATENCY_TIMER 0x0D |
| 684 | #define NGE_PCI_HEADER_TYPE 0x0E |
| 685 | #define NGE_PCI_LOIO 0x10 |
| 686 | #define NGE_PCI_LOMEM 0x14 |
| 687 | #define NGE_PCI_BIOSROM 0x30 |
| 688 | #define NGE_PCI_INTLINE 0x3C |
| 689 | #define NGE_PCI_INTPIN 0x3D |
| 690 | #define NGE_PCI_MINGNT 0x3E |
| 691 | #define NGE_PCI_MINLAT 0x0F |
| 692 | #define NGE_PCI_RESETOPT 0x48 |
| 693 | #define NGE_PCI_EEPROM_DATA 0x4C |
| 694 | |
| 695 | /* power management registers */ |
| 696 | #define NGE_PCI_CAPID 0x50 /* 8 bits */ |
| 697 | #define NGE_PCI_NEXTPTR 0x51 /* 8 bits */ |
| 698 | #define NGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ |
| 699 | #define NGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ |
| 700 | |
| 701 | #define NGE_PSTATE_MASK 0x0003 |
| 702 | #define NGE_PSTATE_D0 0x0000 |
| 703 | #define NGE_PSTATE_D1 0x0001 |
| 704 | #define NGE_PSTATE_D2 0x0002 |
| 705 | #define NGE_PSTATE_D3 0x0003 |
| 706 | #define NGE_PME_EN 0x0010 |
| 707 | #define NGE_PME_STATUS 0x8000 |