| 1 | /* |
| 2 | * Copyright (c) 1996, by Steve Passe |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer. |
| 10 | * 2. The name of the developer may NOT be used to endorse or promote products |
| 11 | * derived from this software without specific prior written permission. |
| 12 | * |
| 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 23 | * SUCH DAMAGE. |
| 24 | * |
| 25 | * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $ |
| 26 | * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $ |
| 27 | */ |
| 28 | |
| 29 | #include <sys/param.h> |
| 30 | #include <sys/systm.h> |
| 31 | #include <sys/kernel.h> |
| 32 | #include <machine/globaldata.h> |
| 33 | #include <machine/smp.h> |
| 34 | #include <machine/md_var.h> |
| 35 | #include <machine/pmap.h> |
| 36 | #include <machine_base/apic/mpapic.h> |
| 37 | #include <machine/segments.h> |
| 38 | #include <sys/thread2.h> |
| 39 | |
| 40 | #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */ |
| 41 | |
| 42 | /* XXX */ |
| 43 | extern pt_entry_t *SMPpt; |
| 44 | |
| 45 | /* EISA Edge/Level trigger control registers */ |
| 46 | #define ELCR0 0x4d0 /* eisa irq 0-7 */ |
| 47 | #define ELCR1 0x4d1 /* eisa irq 8-15 */ |
| 48 | |
| 49 | static void lapic_timer_calibrate(void); |
| 50 | static void lapic_timer_set_divisor(int); |
| 51 | static void lapic_timer_fixup_handler(void *); |
| 52 | static void lapic_timer_restart_handler(void *); |
| 53 | |
| 54 | void lapic_timer_process(void); |
| 55 | void lapic_timer_process_frame(struct intrframe *); |
| 56 | |
| 57 | static int lapic_timer_enable = 1; |
| 58 | TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable); |
| 59 | |
| 60 | static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t); |
| 61 | static void lapic_timer_intr_enable(struct cputimer_intr *); |
| 62 | static void lapic_timer_intr_restart(struct cputimer_intr *); |
| 63 | static void lapic_timer_intr_pmfixup(struct cputimer_intr *); |
| 64 | |
| 65 | static struct cputimer_intr lapic_cputimer_intr = { |
| 66 | .freq = 0, |
| 67 | .reload = lapic_timer_intr_reload, |
| 68 | .enable = lapic_timer_intr_enable, |
| 69 | .config = cputimer_intr_default_config, |
| 70 | .restart = lapic_timer_intr_restart, |
| 71 | .pmfixup = lapic_timer_intr_pmfixup, |
| 72 | .initclock = cputimer_intr_default_initclock, |
| 73 | .next = SLIST_ENTRY_INITIALIZER, |
| 74 | .name = "lapic", |
| 75 | .type = CPUTIMER_INTR_LAPIC, |
| 76 | .prio = CPUTIMER_INTR_PRIO_LAPIC, |
| 77 | .caps = CPUTIMER_INTR_CAP_NONE |
| 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * pointers to pmapped apic hardware. |
| 82 | */ |
| 83 | |
| 84 | volatile ioapic_t **ioapic; |
| 85 | |
| 86 | static int lapic_timer_divisor_idx = -1; |
| 87 | static const uint32_t lapic_timer_divisors[] = { |
| 88 | APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, |
| 89 | APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1 |
| 90 | }; |
| 91 | #define APIC_TIMER_NDIVISORS \ |
| 92 | (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0])) |
| 93 | |
| 94 | |
| 95 | /* |
| 96 | * Enable APIC, configure interrupts. |
| 97 | */ |
| 98 | void |
| 99 | apic_initialize(boolean_t bsp) |
| 100 | { |
| 101 | uint32_t timer; |
| 102 | u_int temp; |
| 103 | |
| 104 | /* |
| 105 | * setup LVT1 as ExtINT on the BSP. This is theoretically an |
| 106 | * aggregate interrupt input from the 8259. The INTA cycle |
| 107 | * will be routed to the external controller (the 8259) which |
| 108 | * is expected to supply the vector. |
| 109 | * |
| 110 | * Must be setup edge triggered, active high. |
| 111 | * |
| 112 | * Disable LVT1 on the APs. It doesn't matter what delivery |
| 113 | * mode we use because we leave it masked. |
| 114 | */ |
| 115 | temp = lapic.lvt_lint0; |
| 116 | temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | |
| 117 | APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); |
| 118 | if (mycpu->gd_cpuid == 0) |
| 119 | temp |= APIC_LVT_DM_EXTINT; |
| 120 | else |
| 121 | temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED; |
| 122 | lapic.lvt_lint0 = temp; |
| 123 | |
| 124 | /* |
| 125 | * setup LVT2 as NMI, masked till later. Edge trigger, active high. |
| 126 | */ |
| 127 | temp = lapic.lvt_lint1; |
| 128 | temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK | |
| 129 | APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK); |
| 130 | temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI; |
| 131 | lapic.lvt_lint1 = temp; |
| 132 | |
| 133 | /* |
| 134 | * Mask the apic error interrupt, apic performance counter |
| 135 | * interrupt. |
| 136 | */ |
| 137 | lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED; |
| 138 | lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED; |
| 139 | |
| 140 | /* Set apic timer vector and mask the apic timer interrupt. */ |
| 141 | timer = lapic.lvt_timer; |
| 142 | timer &= ~APIC_LVTT_VECTOR; |
| 143 | timer |= XTIMER_OFFSET; |
| 144 | timer |= APIC_LVTT_MASKED; |
| 145 | lapic.lvt_timer = timer; |
| 146 | |
| 147 | /* |
| 148 | * Set the Task Priority Register as needed. At the moment allow |
| 149 | * interrupts on all cpus (the APs will remain CLId until they are |
| 150 | * ready to deal). We could disable all but IPIs by setting |
| 151 | * temp |= TPR_IPI_ONLY for cpu != 0. |
| 152 | */ |
| 153 | temp = lapic.tpr; |
| 154 | temp &= ~APIC_TPR_PRIO; /* clear priority field */ |
| 155 | #ifndef APIC_IO |
| 156 | /* |
| 157 | * If we are NOT running the IO APICs, the LAPIC will only be used |
| 158 | * for IPIs. Set the TPR to prevent any unintentional interrupts. |
| 159 | */ |
| 160 | temp |= TPR_IPI_ONLY; |
| 161 | #endif |
| 162 | |
| 163 | lapic.tpr = temp; |
| 164 | |
| 165 | /* |
| 166 | * enable the local APIC |
| 167 | */ |
| 168 | temp = lapic.svr; |
| 169 | temp |= APIC_SVR_ENABLE; /* enable the APIC */ |
| 170 | temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */ |
| 171 | |
| 172 | /* |
| 173 | * Set the spurious interrupt vector. The low 4 bits of the vector |
| 174 | * must be 1111. |
| 175 | */ |
| 176 | if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F) |
| 177 | panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET); |
| 178 | temp &= ~APIC_SVR_VECTOR; |
| 179 | temp |= XSPURIOUSINT_OFFSET; |
| 180 | |
| 181 | lapic.svr = temp; |
| 182 | |
| 183 | /* |
| 184 | * Pump out a few EOIs to clean out interrupts that got through |
| 185 | * before we were able to set the TPR. |
| 186 | */ |
| 187 | lapic.eoi = 0; |
| 188 | lapic.eoi = 0; |
| 189 | lapic.eoi = 0; |
| 190 | |
| 191 | if (bsp) { |
| 192 | lapic_timer_calibrate(); |
| 193 | if (lapic_timer_enable) { |
| 194 | cputimer_intr_register(&lapic_cputimer_intr); |
| 195 | cputimer_intr_select(&lapic_cputimer_intr, 0); |
| 196 | } |
| 197 | } else { |
| 198 | lapic_timer_set_divisor(lapic_timer_divisor_idx); |
| 199 | } |
| 200 | |
| 201 | if (bootverbose) |
| 202 | apic_dump("apic_initialize()"); |
| 203 | } |
| 204 | |
| 205 | |
| 206 | static void |
| 207 | lapic_timer_set_divisor(int divisor_idx) |
| 208 | { |
| 209 | KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS); |
| 210 | lapic.dcr_timer = lapic_timer_divisors[divisor_idx]; |
| 211 | } |
| 212 | |
| 213 | static void |
| 214 | lapic_timer_oneshot(u_int count) |
| 215 | { |
| 216 | uint32_t value; |
| 217 | |
| 218 | value = lapic.lvt_timer; |
| 219 | value &= ~APIC_LVTT_PERIODIC; |
| 220 | lapic.lvt_timer = value; |
| 221 | lapic.icr_timer = count; |
| 222 | } |
| 223 | |
| 224 | static void |
| 225 | lapic_timer_oneshot_quick(u_int count) |
| 226 | { |
| 227 | lapic.icr_timer = count; |
| 228 | } |
| 229 | |
| 230 | static void |
| 231 | lapic_timer_calibrate(void) |
| 232 | { |
| 233 | sysclock_t value; |
| 234 | |
| 235 | /* Try to calibrate the local APIC timer. */ |
| 236 | for (lapic_timer_divisor_idx = 0; |
| 237 | lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS; |
| 238 | lapic_timer_divisor_idx++) { |
| 239 | lapic_timer_set_divisor(lapic_timer_divisor_idx); |
| 240 | lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); |
| 241 | DELAY(2000000); |
| 242 | value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer; |
| 243 | if (value != APIC_TIMER_MAX_COUNT) |
| 244 | break; |
| 245 | } |
| 246 | if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS) |
| 247 | panic("lapic: no proper timer divisor?!\n"); |
| 248 | lapic_cputimer_intr.freq = value / 2; |
| 249 | |
| 250 | kprintf("lapic: divisor index %d, frequency %u Hz\n", |
| 251 | lapic_timer_divisor_idx, lapic_cputimer_intr.freq); |
| 252 | } |
| 253 | |
| 254 | static void |
| 255 | lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame) |
| 256 | { |
| 257 | sysclock_t count; |
| 258 | |
| 259 | gd->gd_timer_running = 0; |
| 260 | |
| 261 | count = sys_cputimer->count(); |
| 262 | if (TAILQ_FIRST(&gd->gd_systimerq) != NULL) |
| 263 | systimer_intr(&count, 0, frame); |
| 264 | } |
| 265 | |
| 266 | void |
| 267 | lapic_timer_process(void) |
| 268 | { |
| 269 | lapic_timer_process_oncpu(mycpu, NULL); |
| 270 | } |
| 271 | |
| 272 | void |
| 273 | lapic_timer_process_frame(struct intrframe *frame) |
| 274 | { |
| 275 | lapic_timer_process_oncpu(mycpu, frame); |
| 276 | } |
| 277 | |
| 278 | static void |
| 279 | lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload) |
| 280 | { |
| 281 | struct globaldata *gd = mycpu; |
| 282 | |
| 283 | reload = (int64_t)reload * cti->freq / sys_cputimer->freq; |
| 284 | if (reload < 2) |
| 285 | reload = 2; |
| 286 | |
| 287 | if (gd->gd_timer_running) { |
| 288 | if (reload < lapic.ccr_timer) |
| 289 | lapic_timer_oneshot_quick(reload); |
| 290 | } else { |
| 291 | gd->gd_timer_running = 1; |
| 292 | lapic_timer_oneshot_quick(reload); |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | static void |
| 297 | lapic_timer_intr_enable(struct cputimer_intr *cti __unused) |
| 298 | { |
| 299 | uint32_t timer; |
| 300 | |
| 301 | timer = lapic.lvt_timer; |
| 302 | timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC); |
| 303 | lapic.lvt_timer = timer; |
| 304 | |
| 305 | lapic_timer_fixup_handler(NULL); |
| 306 | } |
| 307 | |
| 308 | static void |
| 309 | lapic_timer_fixup_handler(void *arg) |
| 310 | { |
| 311 | int *started = arg; |
| 312 | |
| 313 | if (started != NULL) |
| 314 | *started = 0; |
| 315 | |
| 316 | if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { |
| 317 | /* |
| 318 | * Detect the presence of C1E capability mostly on latest |
| 319 | * dual-cores (or future) k8 family. This feature renders |
| 320 | * the local APIC timer dead, so we disable it by reading |
| 321 | * the Interrupt Pending Message register and clearing both |
| 322 | * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). |
| 323 | * |
| 324 | * Reference: |
| 325 | * "BIOS and Kernel Developer's Guide for AMD NPT |
| 326 | * Family 0Fh Processors" |
| 327 | * #32559 revision 3.00 |
| 328 | */ |
| 329 | if ((cpu_id & 0x00000f00) == 0x00000f00 && |
| 330 | (cpu_id & 0x0fff0000) >= 0x00040000) { |
| 331 | uint64_t msr; |
| 332 | |
| 333 | msr = rdmsr(0xc0010055); |
| 334 | if (msr & 0x18000000) { |
| 335 | struct globaldata *gd = mycpu; |
| 336 | |
| 337 | kprintf("cpu%d: AMD C1E detected\n", |
| 338 | gd->gd_cpuid); |
| 339 | wrmsr(0xc0010055, msr & ~0x18000000ULL); |
| 340 | |
| 341 | /* |
| 342 | * We are kinda stalled; |
| 343 | * kick start again. |
| 344 | */ |
| 345 | gd->gd_timer_running = 1; |
| 346 | lapic_timer_oneshot_quick(2); |
| 347 | |
| 348 | if (started != NULL) |
| 349 | *started = 1; |
| 350 | } |
| 351 | } |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | static void |
| 356 | lapic_timer_restart_handler(void *dummy __unused) |
| 357 | { |
| 358 | int started; |
| 359 | |
| 360 | lapic_timer_fixup_handler(&started); |
| 361 | if (!started) { |
| 362 | struct globaldata *gd = mycpu; |
| 363 | |
| 364 | gd->gd_timer_running = 1; |
| 365 | lapic_timer_oneshot_quick(2); |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * This function is called only by ACPI-CA code currently: |
| 371 | * - AMD C1E fixup. AMD C1E only seems to happen after ACPI |
| 372 | * module controls PM. So once ACPI-CA is attached, we try |
| 373 | * to apply the fixup to prevent LAPIC timer from hanging. |
| 374 | */ |
| 375 | static void |
| 376 | lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused) |
| 377 | { |
| 378 | lwkt_send_ipiq_mask(smp_active_mask, |
| 379 | lapic_timer_fixup_handler, NULL); |
| 380 | } |
| 381 | |
| 382 | static void |
| 383 | lapic_timer_intr_restart(struct cputimer_intr *cti __unused) |
| 384 | { |
| 385 | lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL); |
| 386 | } |
| 387 | |
| 388 | |
| 389 | /* |
| 390 | * dump contents of local APIC registers |
| 391 | */ |
| 392 | void |
| 393 | apic_dump(char* str) |
| 394 | { |
| 395 | kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str); |
| 396 | kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", |
| 397 | lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr); |
| 398 | } |
| 399 | |
| 400 | |
| 401 | #if defined(APIC_IO) |
| 402 | |
| 403 | /* |
| 404 | * IO APIC code, |
| 405 | */ |
| 406 | |
| 407 | #define IOAPIC_ISA_INTS 16 |
| 408 | #define REDIRCNT_IOAPIC(A) \ |
| 409 | ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1) |
| 410 | |
| 411 | static int trigger (int apic, int pin, u_int32_t * flags); |
| 412 | static void polarity (int apic, int pin, u_int32_t * flags, int level); |
| 413 | |
| 414 | #define DEFAULT_FLAGS \ |
| 415 | ((u_int32_t) \ |
| 416 | (IOART_INTMSET | \ |
| 417 | IOART_DESTPHY | \ |
| 418 | IOART_DELLOPRI)) |
| 419 | |
| 420 | #define DEFAULT_ISA_FLAGS \ |
| 421 | ((u_int32_t) \ |
| 422 | (IOART_INTMSET | \ |
| 423 | IOART_TRGREDG | \ |
| 424 | IOART_INTAHI | \ |
| 425 | IOART_DESTPHY | \ |
| 426 | IOART_DELLOPRI)) |
| 427 | |
| 428 | void |
| 429 | io_apic_set_id(int apic, int id) |
| 430 | { |
| 431 | u_int32_t ux; |
| 432 | |
| 433 | ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */ |
| 434 | if (((ux & APIC_ID_MASK) >> 24) != id) { |
| 435 | kprintf("Changing APIC ID for IO APIC #%d" |
| 436 | " from %d to %d on chip\n", |
| 437 | apic, ((ux & APIC_ID_MASK) >> 24), id); |
| 438 | ux &= ~APIC_ID_MASK; /* clear the ID field */ |
| 439 | ux |= (id << 24); |
| 440 | io_apic_write(apic, IOAPIC_ID, ux); /* write new value */ |
| 441 | ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */ |
| 442 | if (((ux & APIC_ID_MASK) >> 24) != id) |
| 443 | panic("can't control IO APIC #%d ID, reg: 0x%08x", |
| 444 | apic, ux); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | |
| 449 | int |
| 450 | io_apic_get_id(int apic) |
| 451 | { |
| 452 | return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24; |
| 453 | } |
| 454 | |
| 455 | |
| 456 | |
| 457 | /* |
| 458 | * Setup the IO APIC. |
| 459 | */ |
| 460 | void |
| 461 | io_apic_setup_intpin(int apic, int pin) |
| 462 | { |
| 463 | int bus, bustype, irq; |
| 464 | u_char select; /* the select register is 8 bits */ |
| 465 | u_int32_t flags; /* the window register is 32 bits */ |
| 466 | u_int32_t target; /* the window register is 32 bits */ |
| 467 | u_int32_t vector; /* the window register is 32 bits */ |
| 468 | int level; |
| 469 | int cpuid; |
| 470 | char envpath[32]; |
| 471 | |
| 472 | select = pin * 2 + IOAPIC_REDTBL0; /* register */ |
| 473 | |
| 474 | /* |
| 475 | * Always clear an IO APIC pin before [re]programming it. This is |
| 476 | * particularly important if the pin is set up for a level interrupt |
| 477 | * as the IOART_REM_IRR bit might be set. When we reprogram the |
| 478 | * vector any EOI from pending ints on this pin could be lost and |
| 479 | * IRR might never get reset. |
| 480 | * |
| 481 | * To fix this problem, clear the vector and make sure it is |
| 482 | * programmed as an edge interrupt. This should theoretically |
| 483 | * clear IRR so we can later, safely program it as a level |
| 484 | * interrupt. |
| 485 | */ |
| 486 | imen_lock(); |
| 487 | |
| 488 | flags = io_apic_read(apic, select) & IOART_RESV; |
| 489 | flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI; |
| 490 | flags |= IOART_DESTPHY | IOART_DELFIXED; |
| 491 | |
| 492 | target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV; |
| 493 | target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */ |
| 494 | |
| 495 | vector = 0; |
| 496 | |
| 497 | io_apic_write(apic, select, flags | vector); |
| 498 | io_apic_write(apic, select + 1, target); |
| 499 | |
| 500 | imen_unlock(); |
| 501 | |
| 502 | /* |
| 503 | * We only deal with vectored interrupts here. ? documentation is |
| 504 | * lacking, I'm guessing an interrupt type of 0 is the 'INT' type, |
| 505 | * vs ExTINT, etc. |
| 506 | * |
| 507 | * This test also catches unconfigured pins. |
| 508 | */ |
| 509 | if (apic_int_type(apic, pin) != 0) |
| 510 | return; |
| 511 | |
| 512 | /* |
| 513 | * Leave the pin unprogrammed if it does not correspond to |
| 514 | * an IRQ. |
| 515 | */ |
| 516 | irq = apic_irq(apic, pin); |
| 517 | if (irq < 0) |
| 518 | return; |
| 519 | |
| 520 | /* determine the bus type for this pin */ |
| 521 | bus = apic_src_bus_id(apic, pin); |
| 522 | if (bus < 0) |
| 523 | return; |
| 524 | bustype = apic_bus_type(bus); |
| 525 | |
| 526 | if ((bustype == ISA) && |
| 527 | (pin < IOAPIC_ISA_INTS) && |
| 528 | (irq == pin) && |
| 529 | (apic_polarity(apic, pin) == 0x1) && |
| 530 | (apic_trigger(apic, pin) == 0x3)) { |
| 531 | /* |
| 532 | * A broken BIOS might describe some ISA |
| 533 | * interrupts as active-high level-triggered. |
| 534 | * Use default ISA flags for those interrupts. |
| 535 | */ |
| 536 | flags = DEFAULT_ISA_FLAGS; |
| 537 | } else { |
| 538 | /* |
| 539 | * Program polarity and trigger mode according to |
| 540 | * interrupt entry. |
| 541 | */ |
| 542 | flags = DEFAULT_FLAGS; |
| 543 | level = trigger(apic, pin, &flags); |
| 544 | if (level == 1) |
| 545 | int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL; |
| 546 | polarity(apic, pin, &flags, level); |
| 547 | } |
| 548 | |
| 549 | cpuid = 0; |
| 550 | ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq); |
| 551 | kgetenv_int(envpath, &cpuid); |
| 552 | |
| 553 | /* ncpus may not be available yet */ |
| 554 | if (cpuid > mp_naps) |
| 555 | cpuid = 0; |
| 556 | |
| 557 | if (bootverbose) { |
| 558 | kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n", |
| 559 | apic, pin, irq, cpuid); |
| 560 | } |
| 561 | |
| 562 | /* |
| 563 | * Program the appropriate registers. This routing may be |
| 564 | * overridden when an interrupt handler for a device is |
| 565 | * actually added (see register_int(), which calls through |
| 566 | * the MACHINTR ABI to set up an interrupt handler/vector). |
| 567 | * |
| 568 | * The order in which we must program the two registers for |
| 569 | * safety is unclear! XXX |
| 570 | */ |
| 571 | imen_lock(); |
| 572 | |
| 573 | vector = IDT_OFFSET + irq; /* IDT vec */ |
| 574 | target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV; |
| 575 | /* Deliver all interrupts to CPU0 (BSP) */ |
| 576 | target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) & |
| 577 | IOART_HI_DEST_MASK; |
| 578 | flags |= io_apic_read(apic, select) & IOART_RESV; |
| 579 | io_apic_write(apic, select, flags | vector); |
| 580 | io_apic_write(apic, select + 1, target); |
| 581 | |
| 582 | imen_unlock(); |
| 583 | } |
| 584 | |
| 585 | int |
| 586 | io_apic_setup(int apic) |
| 587 | { |
| 588 | int maxpin; |
| 589 | int pin; |
| 590 | |
| 591 | maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */ |
| 592 | kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic); |
| 593 | |
| 594 | for (pin = 0; pin < maxpin; ++pin) { |
| 595 | io_apic_setup_intpin(apic, pin); |
| 596 | } |
| 597 | while (pin < 32) { |
| 598 | if (apic_int_type(apic, pin) >= 0) { |
| 599 | kprintf("Warning: IOAPIC #%d pin %d does not exist," |
| 600 | " cannot program!\n", apic, pin); |
| 601 | } |
| 602 | ++pin; |
| 603 | } |
| 604 | |
| 605 | /* return GOOD status */ |
| 606 | return 0; |
| 607 | } |
| 608 | #undef DEFAULT_ISA_FLAGS |
| 609 | #undef DEFAULT_FLAGS |
| 610 | |
| 611 | |
| 612 | #define DEFAULT_EXTINT_FLAGS \ |
| 613 | ((u_int32_t) \ |
| 614 | (IOART_INTMSET | \ |
| 615 | IOART_TRGREDG | \ |
| 616 | IOART_INTAHI | \ |
| 617 | IOART_DESTPHY | \ |
| 618 | IOART_DELLOPRI)) |
| 619 | |
| 620 | /* |
| 621 | * XXX this function is only used by 8254 setup |
| 622 | * Setup the source of External INTerrupts. |
| 623 | */ |
| 624 | int |
| 625 | ext_int_setup(int apic, int intr) |
| 626 | { |
| 627 | u_char select; /* the select register is 8 bits */ |
| 628 | u_int32_t flags; /* the window register is 32 bits */ |
| 629 | u_int32_t target; /* the window register is 32 bits */ |
| 630 | u_int32_t vector; /* the window register is 32 bits */ |
| 631 | int cpuid; |
| 632 | char envpath[32]; |
| 633 | |
| 634 | if (apic_int_type(apic, intr) != 3) |
| 635 | return -1; |
| 636 | |
| 637 | cpuid = 0; |
| 638 | ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr); |
| 639 | kgetenv_int(envpath, &cpuid); |
| 640 | |
| 641 | /* ncpus may not be available yet */ |
| 642 | if (cpuid > mp_naps) |
| 643 | cpuid = 0; |
| 644 | |
| 645 | /* Deliver interrupts to CPU0 (BSP) */ |
| 646 | target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) & |
| 647 | IOART_HI_DEST_MASK; |
| 648 | select = IOAPIC_REDTBL0 + (2 * intr); |
| 649 | vector = IDT_OFFSET + intr; |
| 650 | flags = DEFAULT_EXTINT_FLAGS; |
| 651 | |
| 652 | io_apic_write(apic, select, flags | vector); |
| 653 | io_apic_write(apic, select + 1, target); |
| 654 | |
| 655 | return 0; |
| 656 | } |
| 657 | #undef DEFAULT_EXTINT_FLAGS |
| 658 | |
| 659 | |
| 660 | /* |
| 661 | * Set the trigger level for an IO APIC pin. |
| 662 | */ |
| 663 | static int |
| 664 | trigger(int apic, int pin, u_int32_t * flags) |
| 665 | { |
| 666 | int id; |
| 667 | int eirq; |
| 668 | int level; |
| 669 | static int intcontrol = -1; |
| 670 | |
| 671 | switch (apic_trigger(apic, pin)) { |
| 672 | |
| 673 | case 0x00: |
| 674 | break; |
| 675 | |
| 676 | case 0x01: |
| 677 | *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */ |
| 678 | return 0; |
| 679 | |
| 680 | case 0x03: |
| 681 | *flags |= IOART_TRGRLVL; |
| 682 | return 1; |
| 683 | |
| 684 | case -1: |
| 685 | default: |
| 686 | goto bad; |
| 687 | } |
| 688 | |
| 689 | if ((id = apic_src_bus_id(apic, pin)) == -1) |
| 690 | goto bad; |
| 691 | |
| 692 | switch (apic_bus_type(id)) { |
| 693 | case ISA: |
| 694 | *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */ |
| 695 | return 0; |
| 696 | |
| 697 | case EISA: |
| 698 | eirq = apic_src_bus_irq(apic, pin); |
| 699 | |
| 700 | if (eirq < 0 || eirq > 15) { |
| 701 | kprintf("EISA IRQ %d?!?!\n", eirq); |
| 702 | goto bad; |
| 703 | } |
| 704 | |
| 705 | if (intcontrol == -1) { |
| 706 | intcontrol = inb(ELCR1) << 8; |
| 707 | intcontrol |= inb(ELCR0); |
| 708 | kprintf("EISA INTCONTROL = %08x\n", intcontrol); |
| 709 | } |
| 710 | |
| 711 | /* Use ELCR settings to determine level or edge mode */ |
| 712 | level = (intcontrol >> eirq) & 1; |
| 713 | |
| 714 | /* |
| 715 | * Note that on older Neptune chipset based systems, any |
| 716 | * pci interrupts often show up here and in the ELCR as well |
| 717 | * as level sensitive interrupts attributed to the EISA bus. |
| 718 | */ |
| 719 | |
| 720 | if (level) |
| 721 | *flags |= IOART_TRGRLVL; |
| 722 | else |
| 723 | *flags &= ~IOART_TRGRLVL; |
| 724 | |
| 725 | return level; |
| 726 | |
| 727 | case PCI: |
| 728 | *flags |= IOART_TRGRLVL; |
| 729 | return 1; |
| 730 | |
| 731 | case -1: |
| 732 | default: |
| 733 | goto bad; |
| 734 | } |
| 735 | |
| 736 | bad: |
| 737 | panic("bad APIC IO INT flags"); |
| 738 | } |
| 739 | |
| 740 | |
| 741 | /* |
| 742 | * Set the polarity value for an IO APIC pin. |
| 743 | */ |
| 744 | static void |
| 745 | polarity(int apic, int pin, u_int32_t * flags, int level) |
| 746 | { |
| 747 | int id; |
| 748 | |
| 749 | switch (apic_polarity(apic, pin)) { |
| 750 | |
| 751 | case 0x00: |
| 752 | break; |
| 753 | |
| 754 | case 0x01: |
| 755 | *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */ |
| 756 | return; |
| 757 | |
| 758 | case 0x03: |
| 759 | *flags |= IOART_INTALO; |
| 760 | return; |
| 761 | |
| 762 | case -1: |
| 763 | default: |
| 764 | goto bad; |
| 765 | } |
| 766 | |
| 767 | if ((id = apic_src_bus_id(apic, pin)) == -1) |
| 768 | goto bad; |
| 769 | |
| 770 | switch (apic_bus_type(id)) { |
| 771 | case ISA: |
| 772 | *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */ |
| 773 | return; |
| 774 | |
| 775 | case EISA: |
| 776 | /* polarity converter always gives active high */ |
| 777 | *flags &= ~IOART_INTALO; |
| 778 | return; |
| 779 | |
| 780 | case PCI: |
| 781 | *flags |= IOART_INTALO; |
| 782 | return; |
| 783 | |
| 784 | case -1: |
| 785 | default: |
| 786 | goto bad; |
| 787 | } |
| 788 | |
| 789 | bad: |
| 790 | panic("bad APIC IO INT flags"); |
| 791 | } |
| 792 | |
| 793 | |
| 794 | /* |
| 795 | * Print contents of unmasked IRQs. |
| 796 | */ |
| 797 | void |
| 798 | imen_dump(void) |
| 799 | { |
| 800 | int x; |
| 801 | |
| 802 | kprintf("SMP: enabled INTs: "); |
| 803 | for (x = 0; x < APIC_INTMAPSIZE; ++x) { |
| 804 | if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0) |
| 805 | kprintf("%d ", x); |
| 806 | } |
| 807 | kprintf("\n"); |
| 808 | } |
| 809 | |
| 810 | |
| 811 | /* |
| 812 | * Inter Processor Interrupt functions. |
| 813 | */ |
| 814 | |
| 815 | #endif /* APIC_IO */ |
| 816 | |
| 817 | /* |
| 818 | * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'. |
| 819 | * |
| 820 | * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF |
| 821 | * vector is any valid SYSTEM INT vector |
| 822 | * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO |
| 823 | * |
| 824 | * A backlog of requests can create a deadlock between cpus. To avoid this |
| 825 | * we have to be able to accept IPIs at the same time we are trying to send |
| 826 | * them. The critical section prevents us from attempting to send additional |
| 827 | * IPIs reentrantly, but also prevents IPIQ processing so we have to call |
| 828 | * lwkt_process_ipiq() manually. It's rather messy and expensive for this |
| 829 | * to occur but fortunately it does not happen too often. |
| 830 | */ |
| 831 | int |
| 832 | apic_ipi(int dest_type, int vector, int delivery_mode) |
| 833 | { |
| 834 | u_long icr_lo; |
| 835 | |
| 836 | crit_enter(); |
| 837 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 838 | unsigned int eflags = read_eflags(); |
| 839 | cpu_enable_intr(); |
| 840 | while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 841 | lwkt_process_ipiq(); |
| 842 | } |
| 843 | write_eflags(eflags); |
| 844 | } |
| 845 | |
| 846 | icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type | |
| 847 | delivery_mode | vector; |
| 848 | lapic.icr_lo = icr_lo; |
| 849 | crit_exit(); |
| 850 | return 0; |
| 851 | } |
| 852 | |
| 853 | void |
| 854 | single_apic_ipi(int cpu, int vector, int delivery_mode) |
| 855 | { |
| 856 | u_long icr_lo; |
| 857 | u_long icr_hi; |
| 858 | |
| 859 | crit_enter(); |
| 860 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 861 | unsigned int eflags = read_eflags(); |
| 862 | cpu_enable_intr(); |
| 863 | while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 864 | lwkt_process_ipiq(); |
| 865 | } |
| 866 | write_eflags(eflags); |
| 867 | } |
| 868 | icr_hi = lapic.icr_hi & ~APIC_ID_MASK; |
| 869 | icr_hi |= (CPU_TO_ID(cpu) << 24); |
| 870 | lapic.icr_hi = icr_hi; |
| 871 | |
| 872 | /* build ICR_LOW */ |
| 873 | icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) |
| 874 | | APIC_DEST_DESTFLD | delivery_mode | vector; |
| 875 | |
| 876 | /* write APIC ICR */ |
| 877 | lapic.icr_lo = icr_lo; |
| 878 | crit_exit(); |
| 879 | } |
| 880 | |
| 881 | #if 0 |
| 882 | |
| 883 | /* |
| 884 | * Returns 0 if the apic is busy, 1 if we were able to queue the request. |
| 885 | * |
| 886 | * NOT WORKING YET! The code as-is may end up not queueing an IPI at all |
| 887 | * to the target, and the scheduler does not 'poll' for IPI messages. |
| 888 | */ |
| 889 | int |
| 890 | single_apic_ipi_passive(int cpu, int vector, int delivery_mode) |
| 891 | { |
| 892 | u_long icr_lo; |
| 893 | u_long icr_hi; |
| 894 | |
| 895 | crit_enter(); |
| 896 | if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) { |
| 897 | crit_exit(); |
| 898 | return(0); |
| 899 | } |
| 900 | icr_hi = lapic.icr_hi & ~APIC_ID_MASK; |
| 901 | icr_hi |= (CPU_TO_ID(cpu) << 24); |
| 902 | lapic.icr_hi = icr_hi; |
| 903 | |
| 904 | /* build IRC_LOW */ |
| 905 | icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) |
| 906 | | APIC_DEST_DESTFLD | delivery_mode | vector; |
| 907 | |
| 908 | /* write APIC ICR */ |
| 909 | lapic.icr_lo = icr_lo; |
| 910 | crit_exit(); |
| 911 | return(1); |
| 912 | } |
| 913 | |
| 914 | #endif |
| 915 | |
| 916 | /* |
| 917 | * Send APIC IPI 'vector' to 'target's via 'delivery_mode'. |
| 918 | * |
| 919 | * target is a bitmask of destination cpus. Vector is any |
| 920 | * valid system INT vector. Delivery mode may be either |
| 921 | * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO. |
| 922 | */ |
| 923 | void |
| 924 | selected_apic_ipi(u_int target, int vector, int delivery_mode) |
| 925 | { |
| 926 | crit_enter(); |
| 927 | while (target) { |
| 928 | int n = bsfl(target); |
| 929 | target &= ~(1 << n); |
| 930 | single_apic_ipi(n, vector, delivery_mode); |
| 931 | } |
| 932 | crit_exit(); |
| 933 | } |
| 934 | |
| 935 | /* |
| 936 | * Timer code, in development... |
| 937 | * - suggested by rgrimes@gndrsh.aac.dev.com |
| 938 | */ |
| 939 | |
| 940 | /* |
| 941 | * Load a 'downcount time' in uSeconds. |
| 942 | */ |
| 943 | void |
| 944 | set_apic_timer(int us) |
| 945 | { |
| 946 | u_int count; |
| 947 | |
| 948 | /* |
| 949 | * When we reach here, lapic timer's frequency |
| 950 | * must have been calculated as well as the |
| 951 | * divisor (lapic.dcr_timer is setup during the |
| 952 | * divisor calculation). |
| 953 | */ |
| 954 | KKASSERT(lapic_cputimer_intr.freq != 0 && |
| 955 | lapic_timer_divisor_idx >= 0); |
| 956 | |
| 957 | count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000; |
| 958 | lapic_timer_oneshot(count); |
| 959 | } |
| 960 | |
| 961 | |
| 962 | /* |
| 963 | * Read remaining time in timer. |
| 964 | */ |
| 965 | int |
| 966 | read_apic_timer(void) |
| 967 | { |
| 968 | #if 0 |
| 969 | /** XXX FIXME: we need to return the actual remaining time, |
| 970 | * for now we just return the remaining count. |
| 971 | */ |
| 972 | #else |
| 973 | return lapic.ccr_timer; |
| 974 | #endif |
| 975 | } |
| 976 | |
| 977 | |
| 978 | /* |
| 979 | * Spin-style delay, set delay time in uS, spin till it drains. |
| 980 | */ |
| 981 | void |
| 982 | u_sleep(int count) |
| 983 | { |
| 984 | set_apic_timer(count); |
| 985 | while (read_apic_timer()) |
| 986 | /* spin */ ; |
| 987 | } |
| 988 | |
| 989 | void |
| 990 | lapic_init(vm_offset_t lapic_addr) |
| 991 | { |
| 992 | /* Local apic is mapped on last page */ |
| 993 | SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N | |
| 994 | pmap_get_pgeflag() | (lapic_addr & PG_FRAME)); |
| 995 | |
| 996 | kprintf("lapic: at 0x%08x\n", lapic_addr); |
| 997 | } |
| 998 | |
| 999 | static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators = |
| 1000 | TAILQ_HEAD_INITIALIZER(lapic_enumerators); |
| 1001 | |
| 1002 | void |
| 1003 | lapic_config(void) |
| 1004 | { |
| 1005 | struct lapic_enumerator *e; |
| 1006 | int error; |
| 1007 | |
| 1008 | TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { |
| 1009 | error = e->lapic_probe(e); |
| 1010 | if (!error) |
| 1011 | break; |
| 1012 | } |
| 1013 | if (e == NULL) |
| 1014 | panic("can't config lapic\n"); |
| 1015 | |
| 1016 | e->lapic_enumerate(e); |
| 1017 | } |
| 1018 | |
| 1019 | void |
| 1020 | lapic_enumerator_register(struct lapic_enumerator *ne) |
| 1021 | { |
| 1022 | struct lapic_enumerator *e; |
| 1023 | |
| 1024 | TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) { |
| 1025 | if (e->lapic_prio < ne->lapic_prio) { |
| 1026 | TAILQ_INSERT_BEFORE(e, ne, lapic_link); |
| 1027 | return; |
| 1028 | } |
| 1029 | } |
| 1030 | TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link); |
| 1031 | } |