2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Based on FreeBSD v1.2.
27 * $DragonFly: src/sys/dev/agp/agp_nvidia.c,v 1.4 2006/10/25 20:55:52 dillon Exp $
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
52 #include <vm/vm_object.h>
55 #define NVIDIA_VENDORID 0x10de
56 #define NVIDIA_DEVICEID_NFORCE 0x01a4
57 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
59 struct agp_nvidia_softc {
61 u_int32_t initial_aperture; /* aperture size at startup */
62 struct agp_gatt * gatt;
64 device_t dev; /* AGP Controller */
65 device_t mc1_dev; /* Memory Controller */
66 device_t mc2_dev; /* Memory Controller */
67 device_t bdev; /* Bridge */
71 int num_active_entries;
75 static const char * agp_nvidia_match (device_t dev);
76 static int agp_nvidia_probe (device_t);
77 static int agp_nvidia_attach (device_t);
78 static int agp_nvidia_detach (device_t);
79 static u_int32_t agp_nvidia_get_aperture (device_t);
80 static int agp_nvidia_set_aperture (device_t, u_int32_t);
81 static int agp_nvidia_bind_page (device_t, int, vm_offset_t);
82 static int agp_nvidia_unbind_page (device_t, int);
84 static int nvidia_init_iorr (u_int32_t, u_int32_t);
87 agp_nvidia_match (device_t dev)
89 if (pci_get_class(dev) != PCIC_BRIDGE ||
90 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
91 pci_get_vendor(dev) != NVIDIA_VENDORID)
94 switch (pci_get_device(dev)) {
95 case NVIDIA_DEVICEID_NFORCE:
96 return ("NVIDIA nForce AGP Controller");
97 case NVIDIA_DEVICEID_NFORCE2:
98 return ("NVIDIA nForce2 AGP Controller");
100 return ("NVIDIA Generic AGP Controller");
104 agp_nvidia_probe (device_t dev)
108 desc = agp_nvidia_match(dev);
111 device_set_desc(dev, desc);
118 agp_nvidia_attach (device_t dev)
120 struct agp_nvidia_softc *sc = device_get_softc(dev);
121 struct agp_gatt *gatt;
129 switch (pci_get_device(dev)) {
130 case NVIDIA_DEVICEID_NFORCE:
131 sc->wbc_mask = 0x00010000;
133 case NVIDIA_DEVICEID_NFORCE2:
134 sc->wbc_mask = 0x80000000;
144 /* Memory Controller 1 */
145 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
146 if (sc->mc1_dev == NULL) {
148 "Unable to find NVIDIA Memory Controller 1.\n");
152 /* Memory Controller 2 */
153 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
154 if (sc->mc2_dev == NULL) {
156 "Unable to find NVIDIA Memory Controller 2.\n");
160 /* AGP Host to PCI Bridge */
161 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
162 if (sc->bdev == NULL) {
164 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
168 error = agp_generic_attach(dev);
172 sc->initial_aperture = AGP_GET_APERTURE(dev);
175 gatt = agp_alloc_gatt(dev);
179 * Probably contigmalloc failure. Try reducing the
180 * aperture so that the gatt size reduces.
182 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
187 apbase = rman_get_start(sc->agp.as_aperture);
188 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
189 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
190 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
191 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
192 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
194 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
196 device_printf(dev, "Failed to setup IORRs\n");
200 /* directory size is 64k */
201 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
202 sc->num_dirs = size / 64;
203 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
205 if (sc->num_dirs == 0) {
207 sc->num_active_entries /= (64 / size);
208 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
209 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
212 /* (G)ATT Base Address */
213 for (i = 0; i < 8; i++) {
214 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
215 (sc->gatt->ag_physical +
216 (i % sc->num_dirs) * 64 * 1024),
221 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
222 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
225 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
226 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
230 agp_generic_detach(dev);
235 agp_nvidia_detach (device_t dev)
237 struct agp_nvidia_softc *sc = device_get_softc(dev);
241 error = agp_generic_detach(dev);
246 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
247 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
250 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
251 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
253 /* Put the aperture back the way it started. */
254 AGP_SET_APERTURE(dev, sc->initial_aperture);
256 /* restore iorr for previous aperture size */
257 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
258 sc->initial_aperture);
260 agp_free_gatt(sc->gatt);
266 agp_nvidia_get_aperture(device_t dev)
270 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
271 return (1 << (24 + (key ? key : 5)));
275 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
281 case (512 * 1024 * 1024): key = 0; break;
282 case (256 * 1024 * 1024): key = 8; break;
283 case (128 * 1024 * 1024): key = 12; break;
284 case (64 * 1024 * 1024): key = 14; break;
285 case (32 * 1024 * 1024): key = 15; break;
287 device_printf(dev, "Invalid aperture size (%dMb)\n",
288 aperture / 1024 / 1024);
291 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
292 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
298 agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
300 struct agp_nvidia_softc *sc = device_get_softc(dev);
303 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
306 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
307 sc->gatt->ag_virtual[index] = physical;
313 agp_nvidia_unbind_page(device_t dev, int offset)
315 struct agp_nvidia_softc *sc = device_get_softc(dev);
318 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
321 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
322 sc->gatt->ag_virtual[index] = 0;
328 agp_nvidia_flush_tlb (device_t dev, int offset)
330 struct agp_nvidia_softc *sc;
331 u_int32_t wbc_reg, temp;
334 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
337 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
338 wbc_reg |= sc->wbc_mask;
339 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
341 /* Wait no more than 3 seconds. */
342 for (i = 0; i < 3000; i++) {
343 wbc_reg = pci_read_config(sc->mc1_dev,
344 AGP_NVIDIA_1_WBC, 4);
345 if ((sc->wbc_mask & wbc_reg) == 0)
352 "TLB flush took more than 3 seconds.\n");
355 /* Flush TLB entries. */
356 for(i = 0; i < 32 + 1; i++)
357 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
358 for(i = 0; i < 32 + 1; i++)
359 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
364 #define SYSCFG 0xC0010010
365 #define IORR_BASE0 0xC0010016
366 #define IORR_MASK0 0xC0010017
367 #define AMD_K7_NUM_IORR 2
370 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
372 quad_t base, mask, sys;
373 u_int32_t iorr_addr, free_iorr_addr;
375 /* Find the iorr that is already used for the addr */
376 /* If not found, determine the uppermost available iorr */
377 free_iorr_addr = AMD_K7_NUM_IORR;
378 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
379 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
380 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
382 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
385 if ((mask & 0x00000800ULL) == 0)
386 free_iorr_addr = iorr_addr;
389 if (iorr_addr >= AMD_K7_NUM_IORR) {
390 iorr_addr = free_iorr_addr;
391 if (iorr_addr >= AMD_K7_NUM_IORR)
395 base = (addr & ~0xfff) | 0x18;
396 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
397 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
398 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
401 sys |= 0x00100000ULL;
407 static device_method_t agp_nvidia_methods[] = {
408 /* Device interface */
409 DEVMETHOD(device_probe, agp_nvidia_probe),
410 DEVMETHOD(device_attach, agp_nvidia_attach),
411 DEVMETHOD(device_detach, agp_nvidia_detach),
412 DEVMETHOD(device_shutdown, bus_generic_shutdown),
413 DEVMETHOD(device_suspend, bus_generic_suspend),
414 DEVMETHOD(device_resume, bus_generic_resume),
417 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
418 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
419 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
420 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
421 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
423 DEVMETHOD(agp_enable, agp_generic_enable),
424 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
425 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
426 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
427 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
432 static driver_t agp_nvidia_driver = {
435 sizeof(struct agp_nvidia_softc),
438 static devclass_t agp_devclass;
440 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
441 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
442 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);