2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/interrupt.h>
37 #include <sys/kernel.h>
38 #include <sys/memrange.h>
40 #include <sys/types.h>
43 #include <vm/vm_extern.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_object.h>
46 #include <vm/vm_page.h>
48 #include <sys/mplock2.h>
50 #include <machine/cpu.h>
51 #include <machine/cpufunc.h>
52 #include <machine/globaldata.h>
53 #include <machine/md_var.h>
54 #include <machine/pmap.h>
55 #include <machine/smp.h>
56 #include <machine/tls.h>
57 #include <machine/param.h>
64 extern pt_entry_t *KPTphys;
66 extern int vmm_enabled;
68 volatile cpumask_t stopped_cpus;
69 /* which cpus are ready for IPIs etc? */
70 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE;
71 static int boot_address;
72 /* which cpus have been started */
73 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE;
74 int mp_naps; /* # of Applications processors */
77 /* Local data for detecting CPU TOPOLOGY */
78 static int core_bits = 0;
79 static int logical_CPU_bits = 0;
81 /* function prototypes XXX these should go elsewhere */
82 void bootstrap_idle(void);
83 void single_cpu_ipi(int, int, int);
84 void selected_cpu_ipi(cpumask_t, int, int);
86 void ipi_handler(int);
91 /* AP uses this during bootstrap. Do not staticize. */
96 /* XXX these need to go into the appropriate header file */
97 static int start_all_aps(u_int);
98 void init_secondary(void);
99 void *start_ap(void *);
102 * Get SMP fully working before we start initializing devices.
110 kprintf("Finish MP startup\n");
112 /* build our map of 'other' CPUs */
113 mycpu->gd_other_cpus = smp_startup_mask;
114 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
117 * Let the other cpu's finish initializing and build their map
121 while (CPUMASK_CMPMASKNEQ(smp_active_mask,smp_startup_mask)) {
126 while (try_mplock() == 0)
129 kprintf("Active CPU Mask: %08lx\n",
130 (long)CPUMASK_LOWMASK(smp_active_mask));
133 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL);
136 start_ap(void *arg __unused)
142 return(NULL); /* NOTREACHED */
145 /* storage for AP thread IDs */
146 pthread_t ap_tids[MAXCPU];
158 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
159 for (shift = 0; (1 << shift) <= ncpus; ++shift)
162 ncpus2_shift = shift;
164 ncpus2_mask = ncpus2 - 1;
166 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
167 if ((1 << shift) < ncpus)
169 ncpus_fit = 1 << shift;
170 ncpus_fit_mask = ncpus_fit - 1;
173 * cpu0 initialization
175 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
176 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
177 bzero(mycpu->gd_ipiq, ipiq_size);
182 start_all_aps(boot_address);
191 kprintf("DragonFly/MP: Multiprocessor\n");
192 kprintf(" cpu0 (BSP)\n");
194 for (x = 1; x <= mp_naps; ++x)
195 kprintf(" cpu%d (AP)\n", x);
199 cpu_send_ipiq(int dcpu)
201 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) {
202 if (pthread_kill(ap_tids[dcpu], SIGUSR1) != 0)
203 panic("pthread_kill failed in cpu_send_ipiq");
206 panic("XXX cpu_send_ipiq()");
211 single_cpu_ipi(int cpu, int vector, int delivery_mode)
213 kprintf("XXX single_cpu_ipi\n");
217 selected_cpu_ipi(cpumask_t target, int vector, int delivery_mode)
220 while (CPUMASK_TESTNZERO(target)) {
221 int n = BSFCPUMASK(target);
222 CPUMASK_NANDBIT(target, n);
223 single_cpu_ipi(n, vector, delivery_mode);
229 stop_cpus(cpumask_t map)
231 CPUMASK_ANDMASK(map, smp_active_mask);
234 while (CPUMASK_TESTNZERO(map)) {
235 int n = BSFCPUMASK(map);
236 CPUMASK_NANDBIT(map, n);
237 ATOMIC_CPUMASK_ORBIT(stopped_cpus, n);
238 if (pthread_kill(ap_tids[n], SIGXCPU) != 0)
239 panic("stop_cpus: pthread_kill failed");
243 panic("XXX stop_cpus()");
250 restart_cpus(cpumask_t map)
252 CPUMASK_ANDMASK(map, smp_active_mask);
255 while (CPUMASK_TESTNZERO(map)) {
256 int n = BSFCPUMASK(map);
257 CPUMASK_NANDBIT(map, n);
258 ATOMIC_CPUMASK_NANDBIT(stopped_cpus, n);
259 if (pthread_kill(ap_tids[n], SIGXCPU) != 0)
260 panic("restart_cpus: pthread_kill failed");
264 panic("XXX restart_cpus()");
273 * Adjust smp_startup_mask to signal the BSP that we have started
274 * up successfully. Note that we do not yet hold the BGL. The BSP
275 * is waiting for our signal.
277 * We can't set our bit in smp_active_mask yet because we are holding
278 * interrupts physically disabled and remote cpus could deadlock
279 * trying to send us an IPI.
281 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid);
285 * Interlock for finalization. Wait until mp_finish is non-zero,
286 * then get the MP lock.
288 * Note: We are in a critical section.
290 * Note: we are the idle thread, we can only spin.
292 * Note: The load fence is memory volatile and prevents the compiler
293 * from improperly caching mp_finish, and the cpu from improperly
297 while (mp_finish == 0) {
301 while (try_mplock() == 0)
304 /* BSP may have changed PTD while we're waiting for the lock */
307 /* Build our map of 'other' CPUs. */
308 mycpu->gd_other_cpus = smp_startup_mask;
309 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
311 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
314 /* Set memory range attributes for this CPU to match the BSP */
317 * Once we go active we must process any IPIQ messages that may
318 * have been queued, because no actual IPI will occur until we
319 * set our bit in the smp_active_mask. If we don't the IPI
320 * message interlock could be left set which would also prevent
323 * The idle loop doesn't expect the BGL to be held and while
324 * lwkt_switch() normally cleans things up this is a special case
325 * because we returning almost directly into the idle loop.
327 * The idle thread is never placed on the runq, make sure
328 * nothing we've done put it there.
330 KKASSERT(get_mplock_count(curthread) == 1);
331 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid);
333 mdcpu->gd_fpending = 0;
334 mdcpu->gd_ipending = 0;
335 initclocks_pcpu(); /* clock interrupts (via IPIs) */
339 * Releasing the mp lock lets the BSP finish up the SMP init
342 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
349 struct mdglobaldata *md;
350 struct privatespace *ps;
352 ps = &CPU_prvspace[myid];
354 KKASSERT(ps->mdglobaldata.mi.gd_prvspace == ps);
357 * Setup the %gs for cpu #n. The mycpu macro works after this
358 * point. Note that %fs is used by pthreads.
360 tls_set_gs(&CPU_prvspace[myid], sizeof(struct privatespace));
362 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
365 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
366 //md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
367 //md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
370 * Set to a known state:
371 * Set by mpboot.s: CR0_PG, CR0_PE
372 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
377 start_all_aps(u_int boot_addr)
380 struct mdglobaldata *gd;
381 struct privatespace *ps;
388 struct lwp_params params;
392 * needed for ipis to initial thread
393 * FIXME: rename ap_tids?
395 ap_tids[0] = pthread_self();
396 pthread_attr_init(&attr);
398 vm_object_hold(&kernel_object);
399 for (x = 1; x <= mp_naps; x++)
401 /* Allocate space for the CPU's private space. */
402 for (i = 0; i < sizeof(struct mdglobaldata); i += PAGE_SIZE) {
403 va =(vm_offset_t)&CPU_prvspace[x].mdglobaldata + i;
404 m = vm_page_alloc(&kernel_object, va, VM_ALLOC_SYSTEM);
405 pmap_kenter_quick(va, m->phys_addr);
408 for (i = 0; i < sizeof(CPU_prvspace[x].idlestack); i += PAGE_SIZE) {
409 va =(vm_offset_t)&CPU_prvspace[x].idlestack + i;
410 m = vm_page_alloc(&kernel_object, va, VM_ALLOC_SYSTEM);
411 pmap_kenter_quick(va, m->phys_addr);
414 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
415 bzero(gd, sizeof(*gd));
416 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
418 /* prime data page for it to use */
419 mi_gdinit(&gd->mi, x);
423 gd->gd_CMAP1 = pmap_kpte((vm_offset_t)CPU_prvspace[x].CPAGE1);
424 gd->gd_CMAP2 = pmap_kpte((vm_offset_t)CPU_prvspace[x].CPAGE2);
425 gd->gd_CMAP3 = pmap_kpte((vm_offset_t)CPU_prvspace[x].CPAGE3);
426 gd->gd_PMAP1 = pmap_kpte((vm_offset_t)CPU_prvspace[x].PPAGE1);
427 gd->gd_CADDR1 = ps->CPAGE1;
428 gd->gd_CADDR2 = ps->CPAGE2;
429 gd->gd_CADDR3 = ps->CPAGE3;
430 gd->gd_PADDR1 = (vpte_t *)ps->PPAGE1;
433 ipiq_size = sizeof(struct lwkt_ipiq) * (mp_naps + 1);
434 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
435 bzero(gd->mi.gd_ipiq, ipiq_size);
438 * Setup the AP boot stack
440 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
444 * Setup the AP's lwp, this is the 'cpu'
446 * We have to make sure our signals are masked or the new LWP
447 * may pick up a signal that it isn't ready for yet. SMP
448 * startup occurs after SI_BOOT2_LEAVE_CRIT so interrupts
449 * have already been enabled.
454 stack = mmap(NULL, KERNEL_STACK_SIZE,
455 PROT_READ|PROT_WRITE|PROT_EXEC,
457 if (stack == MAP_FAILED) {
458 panic("Unable to allocate stack for thread %d\n", x);
460 pthread_attr_setstack(&attr, stack, KERNEL_STACK_SIZE);
463 pthread_create(&ap_tids[x], &attr, start_ap, NULL);
466 while (CPUMASK_TESTBIT(smp_startup_mask, x) == 0) {
467 cpu_lfence(); /* XXX spin until the AP has started */
471 vm_object_drop(&kernel_object);
472 pthread_attr_destroy(&attr);
478 * CPU TOPOLOGY DETECTION FUNCTIONS.
482 detect_cpu_topology(void)
484 logical_CPU_bits = vkernel_b_arg;
485 core_bits = vkernel_B_arg;
489 get_chip_ID(int cpuid)
491 return get_apicid_from_cpuid(cpuid) >>
492 (logical_CPU_bits + core_bits);
496 get_core_number_within_chip(int cpuid)
498 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) &
499 ( (1 << core_bits) -1);
503 get_logical_CPU_number_within_core(int cpuid)
505 return get_apicid_from_cpuid(cpuid) &
506 ( (1 << logical_CPU_bits) -1);