2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pcivar.h,v 1.48 2000/09/28 00:37:32 peter Exp $
27 * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.17 2008/10/19 09:13:58 sephe Exp $
34 #include <sys/queue.h>
36 /* some PCI bus constants */
38 #define PCI_BUSMAX 255 /* highest supported bus number */
39 #define PCI_SLOTMAX 31 /* highest supported slot number */
40 #define PCI_FUNCMAX 7 /* highest supported function number */
41 #define PCI_REGMAX 255 /* highest supported config register addr. */
43 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
44 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
45 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
47 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */
50 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
52 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */
55 /* config values for PCI power management capability */
57 u_int16_t pp_cap; /* PCI power management capabilities */
58 u_int8_t pp_status; /* config space address of PCI power status reg */
59 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */
60 u_int8_t pp_data; /* config space address of PCI power data reg */
63 /* config values for PCI Express capability */
65 uint8_t expr_ptr; /* capability ptr */
66 uint16_t expr_cap; /* capabilities */
67 uint32_t expr_slotcap; /* slot capabilities */
70 /* config header information common to all header types */
72 typedef struct pcicfg {
73 struct device *dev; /* device which owns this */
74 void *hdrspec; /* pointer to header type specific data */
76 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
77 uint32_t bios; /* BIOS mapping */
79 u_int16_t subvendor; /* card vendor ID */
80 u_int16_t subdevice; /* card device ID, assigned by card vendor */
81 u_int16_t vendor; /* chip vendor ID */
82 u_int16_t device; /* chip device ID, assigned by chip vendor */
84 u_int16_t cmdreg; /* disable/enable chip and PCI options */
85 u_int16_t statreg; /* supported PCI features and error state */
87 u_int8_t baseclass; /* chip PCI class */
88 u_int8_t subclass; /* chip PCI subclass */
89 u_int8_t progif; /* chip PCI programming interface */
90 u_int8_t revid; /* chip revision ID */
92 u_int8_t hdrtype; /* chip config header type */
93 u_int8_t cachelnsz; /* cache line size in 4byte units */
94 u_int8_t intpin; /* PCI interrupt pin */
95 u_int8_t intline; /* interrupt line (IRQ for PC arch) */
97 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */
98 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */
99 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */
101 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */
102 u_int8_t nummaps; /* actual number of PCI maps used */
104 u_int8_t bus; /* config space bus address */
105 u_int8_t slot; /* config space slot address */
106 u_int8_t func; /* config space function number */
108 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */
109 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */
111 struct pcicfg_pmgt pmgt; /* power management capability */
112 struct pcicfg_expr expr; /* PCI Express capability */
113 u_int8_t pcixcap_ptr; /* PCI-X capability PTR */
116 /* additional type 1 device config header information (PCI to PCI bridge) */
119 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
120 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
122 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff)
123 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff)
126 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
127 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff)
130 pci_addr_t pmembase; /* base address of prefetchable memory */
131 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
132 u_int32_t membase; /* base address of memory window */
133 u_int32_t memlimit; /* topmost address of memory window */
134 u_int32_t iobase; /* base address of port window */
135 u_int32_t iolimit; /* topmost address of port window */
136 u_int16_t secstat; /* secondary bus status register */
137 u_int16_t bridgectl; /* bridge control register */
138 u_int8_t seclat; /* CardBus latency timer */
141 /* additional type 2 device config header information (CardBus bridge) */
144 u_int32_t membase0; /* base address of memory window */
145 u_int32_t memlimit0; /* topmost address of memory window */
146 u_int32_t membase1; /* base address of memory window */
147 u_int32_t memlimit1; /* topmost address of memory window */
148 u_int32_t iobase0; /* base address of port window */
149 u_int32_t iolimit0; /* topmost address of port window */
150 u_int32_t iobase1; /* base address of port window */
151 u_int32_t iolimit1; /* topmost address of port window */
152 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
153 u_int16_t secstat; /* secondary bus status register */
154 u_int16_t bridgectl; /* bridge control register */
155 u_int8_t seclat; /* CardBus latency timer */
158 extern u_int32_t pci_numdevs;
159 extern const char *pcib_owner; /* arbitrate who owns the pci device arch */
161 /* Only if the prerequisites are present */
162 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
164 STAILQ_ENTRY(pci_devinfo) pci_links;
165 struct resource_list resources;
167 struct pci_conf conf;
171 /* externally visible functions */
173 const char *pci_ata_match(struct device *dev);
174 const char *pci_usb_match(struct device *dev);
175 const char *pci_vga_match(struct device *dev);
176 const char *pci_chip_match(struct device *dev);
178 /* low level PCI config register functions provided by pcibus.c */
180 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes);
181 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
183 /* low level devlist operations for the 2.2 compatibility code in pci.c */
184 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg);
191 * Define pci-specific resource flags for accessing memory via dense
192 * or bwx memory spaces. These flags are ignored on i386.
194 #define PCI_RF_DENSE 0x10000
195 #define PCI_RF_BWX 0x20000
197 enum pci_device_ivars {
212 PCI_IVAR_SECONDARYBUS,
213 PCI_IVAR_SUBORDINATEBUS,
215 PCI_IVAR_PCIXCAP_PTR,
220 * Simplified accessors for pci devices
222 * The PCI device passed in actually represents a PCI function number
223 * for the current slot. The parent of dev is the "pci" slot device.
224 * Each function number has its own set of ivars.
226 #define PCI_ACCESSOR(A, B, T) \
228 static __inline T pci_get_ ## A(device_t dev) \
231 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \
235 static __inline void pci_set_ ## A(device_t dev, T t) \
237 uintptr_t v = (uintptr_t) t; \
238 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \
241 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t)
242 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t)
243 PCI_ACCESSOR(vendor, VENDOR, u_int16_t)
244 PCI_ACCESSOR(device, DEVICE, u_int16_t)
245 PCI_ACCESSOR(devid, DEVID, u_int32_t)
246 PCI_ACCESSOR(class, CLASS, u_int8_t)
247 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t)
248 PCI_ACCESSOR(progif, PROGIF, u_int8_t)
249 PCI_ACCESSOR(revid, REVID, u_int8_t)
250 PCI_ACCESSOR(intpin, INTPIN, u_int8_t)
251 PCI_ACCESSOR(irq, IRQ, u_int8_t)
252 PCI_ACCESSOR(bus, BUS, u_int8_t)
253 PCI_ACCESSOR(slot, SLOT, u_int8_t)
254 PCI_ACCESSOR(function, FUNCTION, u_int8_t)
255 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t)
256 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t)
257 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
258 PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t)
259 PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t)
263 static __inline u_int32_t
264 pci_read_config(device_t dev, int reg, int width)
266 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
270 pci_write_config(device_t dev, int reg, u_int32_t val, int width)
272 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
276 * Convenience functions.
278 * These should be used in preference to manually manipulating
279 * configuration space.
282 pci_enable_busmaster(device_t dev)
284 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev);
288 pci_disable_busmaster(device_t dev)
290 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev);
294 pci_enable_io(device_t dev, int space)
296 PCI_ENABLE_IO(device_get_parent(dev), dev, space);
300 pci_disable_io(device_t dev, int space)
302 PCI_DISABLE_IO(device_get_parent(dev), dev, space);
306 pci_is_pcie(device_t dev)
308 return (pci_get_pciecap_ptr(dev) != 0);
312 pci_is_pcix(device_t dev)
314 return (pci_get_pcixcap_ptr(dev) != 0);
318 * PCI power states are as defined by ACPI:
320 * D0 State in which device is on and running. It is receiving full
321 * power from the system and delivering full functionality to the user.
322 * D1 Class-specific low-power state in which device context may or may not
323 * be lost. Buses in D1 cannot do anything to the bus that would force
324 * devices on that bus to loose context.
325 * D2 Class-specific low-power state in which device context may or may
326 * not be lost. Attains greater power savings than D1. Buses in D2
327 * can cause devices on that bus to loose some context. Devices in D2
328 * must be prepared for the bus to be in D2 or higher.
329 * D3 State in which the device is off and not running. Device context is
330 * lost. Power can be removed from the device.
332 #define PCI_POWERSTATE_D0 0
333 #define PCI_POWERSTATE_D1 1
334 #define PCI_POWERSTATE_D2 2
335 #define PCI_POWERSTATE_D3 3
336 #define PCI_POWERSTATE_UNKNOWN -1
339 pci_set_powerstate(device_t dev, int state)
341 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
345 pci_get_powerstate(device_t dev)
347 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
351 * Ivars for pci bridges.
353 * Whereas PCI devices are arranged [pciX]->[pciX.Y] with the pci driver
354 * functions in [pciX] but the individual ivars in [pciX.Y], PCI bridges
355 * are installed in [pciX.Y] and store their ivars in a softc. This
356 * is why the accessor functions for a bridge do not call device_get_parent().
358 /*typedef enum pci_device_ivars pcib_device_ivars;*/
359 enum pcib_device_ivars {
363 #define PCIB_ACCESSOR(A, B, T) \
365 static __inline T pcib_get_ ## A(device_t dev) \
368 BUS_READ_IVAR(dev, dev, PCIB_IVAR_ ## B, &v); \
372 static __inline void pcib_set_ ## A(device_t dev, T t) \
374 uintptr_t v = (uintptr_t) t; \
375 BUS_WRITE_IVAR(dev, dev, PCIB_IVAR_ ## B, v); \
378 PCIB_ACCESSOR(bus, BUS, u_int32_t)
382 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t);
383 device_t pci_find_device(u_int16_t, u_int16_t);
384 int pcie_slot_implemented(device_t);
385 void pcie_set_max_readrq(device_t, uint16_t);
388 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
390 #if defined(_KERNEL) && !defined(KLD_MODULE)
391 #include "opt_compat_oldpci.h"
395 /* all this is going some day */
397 typedef pcicfgregs *pcici_t;
398 typedef unsigned pcidi_t;
399 typedef void pci_inthand_t(void *arg);
401 #define pci_max_burst_len (3)
403 /* just copied from old PCI code for now ... */
407 const char* (*pd_probe ) (pcici_t tag, pcidi_t type);
408 void (*pd_attach) (pcici_t tag, int unit);
410 int (*pd_shutdown) (int, int);
414 typedef u_short pci_port_t;
416 typedef u_int pci_port_t;
419 u_long pci_conf_read (pcici_t tag, u_long reg);
420 void pci_conf_write (pcici_t tag, u_long reg, u_long data);
421 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
422 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
423 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg);
424 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg,
426 int pci_unmap_int (pcici_t tag);
428 pcici_t pci_get_parent_from_tag(pcici_t tag);
429 int pci_get_bus_from_tag(pcici_t tag);
432 int compat_pci_handler (struct module *, int, void *);
433 #define COMPAT_PCI_DRIVER(name, pcidata) \
434 static moduledata_t name##_mod = { \
436 compat_pci_handler, \
439 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)
442 #endif /* COMPAT_OLDPCI */
443 #endif /* _PCIVAR_H_ */