1 /******************************************************************************
4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5 * Version: $Revision: 1.23 $
6 * Date : $Date: 2005/12/22 09:04:11 $
7 * Purpose: Main driver source file
9 *****************************************************************************/
11 /******************************************************************************
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
46 *****************************************************************************/
49 * Copyright (c) 1997, 1998, 1999, 2000
50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 * 3. All advertising materials mentioning features or use of this software
61 * must display the following acknowledgement:
62 * This product includes software developed by Bill Paul.
63 * 4. Neither the name of the author nor the names of any co-contributors
64 * may be used to endorse or promote products derived from this software
65 * without specific prior written permission.
67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77 * THE POSSIBILITY OF SUCH DAMAGE.
80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
82 * Permission to use, copy, modify, and distribute this software for any
83 * purpose with or without fee is hereby granted, provided that the above
84 * copyright notice and this permission notice appear in all copies.
86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
95 /* $FreeBSD: src/sys/dev/msk/if_msk.c,v 1.26 2007/12/05 09:41:58 remko Exp $ */
98 * Device driver for the Marvell Yukon II Ethernet controller.
99 * Due to lack of documentation, this driver is based on the code from
100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
103 #include <sys/param.h>
104 #include <sys/endian.h>
105 #include <sys/kernel.h>
107 #include <sys/in_cksum.h>
108 #include <sys/interrupt.h>
109 #include <sys/malloc.h>
110 #include <sys/proc.h>
111 #include <sys/rman.h>
112 #include <sys/serialize.h>
113 #include <sys/socket.h>
114 #include <sys/sockio.h>
115 #include <sys/sysctl.h>
117 #include <net/ethernet.h>
120 #include <net/if_arp.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/ifq_var.h>
124 #include <net/vlan/if_vlan_var.h>
126 #include <netinet/ip.h>
127 #include <netinet/ip_var.h>
129 #include <dev/netif/mii_layer/miivar.h>
131 #include <bus/pci/pcireg.h>
132 #include <bus/pci/pcivar.h>
134 #include "if_mskreg.h"
136 /* "device miibus" required. See GENERIC if you get errors here. */
137 #include "miibus_if.h"
139 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
142 * Devices supported by this driver.
144 static const struct msk_product {
145 uint16_t msk_vendorid;
146 uint16_t msk_deviceid;
147 const char *msk_name;
149 { VENDORID_SK, DEVICEID_SK_YUKON2,
150 "SK-9Sxx Gigabit Ethernet" },
151 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
152 "SK-9Exx Gigabit Ethernet"},
153 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
154 "Marvell Yukon 88E8021CU Gigabit Ethernet" },
155 { VENDORID_MARVELL, DEVICEID_MRVL_8021X,
156 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
157 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
158 "Marvell Yukon 88E8022CU Gigabit Ethernet" },
159 { VENDORID_MARVELL, DEVICEID_MRVL_8022X,
160 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
161 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
162 "Marvell Yukon 88E8061CU Gigabit Ethernet" },
163 { VENDORID_MARVELL, DEVICEID_MRVL_8061X,
164 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
165 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
166 "Marvell Yukon 88E8062CU Gigabit Ethernet" },
167 { VENDORID_MARVELL, DEVICEID_MRVL_8062X,
168 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
169 { VENDORID_MARVELL, DEVICEID_MRVL_8035,
170 "Marvell Yukon 88E8035 Fast Ethernet" },
171 { VENDORID_MARVELL, DEVICEID_MRVL_8036,
172 "Marvell Yukon 88E8036 Fast Ethernet" },
173 { VENDORID_MARVELL, DEVICEID_MRVL_8038,
174 "Marvell Yukon 88E8038 Fast Ethernet" },
175 { VENDORID_MARVELL, DEVICEID_MRVL_8039,
176 "Marvell Yukon 88E8039 Fast Ethernet" },
177 { VENDORID_MARVELL, DEVICEID_MRVL_8040,
178 "Marvell Yukon 88E8040 Fast Ethernet" },
179 { VENDORID_MARVELL, DEVICEID_MRVL_8040T,
180 "Marvell Yukon 88E8040T Fast Ethernet" },
181 { VENDORID_MARVELL, DEVICEID_MRVL_8042,
182 "Marvell Yukon 88E8042 Fast Ethernet" },
183 { VENDORID_MARVELL, DEVICEID_MRVL_8048,
184 "Marvell Yukon 88E8048 Fast Ethernet" },
185 { VENDORID_MARVELL, DEVICEID_MRVL_4361,
186 "Marvell Yukon 88E8050 Gigabit Ethernet" },
187 { VENDORID_MARVELL, DEVICEID_MRVL_4360,
188 "Marvell Yukon 88E8052 Gigabit Ethernet" },
189 { VENDORID_MARVELL, DEVICEID_MRVL_4362,
190 "Marvell Yukon 88E8053 Gigabit Ethernet" },
191 { VENDORID_MARVELL, DEVICEID_MRVL_4363,
192 "Marvell Yukon 88E8055 Gigabit Ethernet" },
193 { VENDORID_MARVELL, DEVICEID_MRVL_4364,
194 "Marvell Yukon 88E8056 Gigabit Ethernet" },
195 { VENDORID_MARVELL, DEVICEID_MRVL_4365,
196 "Marvell Yukon 88E8070 Gigabit Ethernet" },
197 { VENDORID_MARVELL, DEVICEID_MRVL_436A,
198 "Marvell Yukon 88E8058 Gigabit Ethernet" },
199 { VENDORID_MARVELL, DEVICEID_MRVL_436B,
200 "Marvell Yukon 88E8071 Gigabit Ethernet" },
201 { VENDORID_MARVELL, DEVICEID_MRVL_436C,
202 "Marvell Yukon 88E8072 Gigabit Ethernet" },
203 { VENDORID_MARVELL, DEVICEID_MRVL_4380,
204 "Marvell Yukon 88E8057 Gigabit Ethernet" },
205 { VENDORID_MARVELL, DEVICEID_MRVL_4381,
206 "Marvell Yukon 88E8059 Gigabit Ethernet" },
207 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
208 "D-Link 550SX Gigabit Ethernet" },
209 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
210 "D-Link 560T Gigabit Ethernet" },
214 static const char *model_name[] = {
227 static int mskc_probe(device_t);
228 static int mskc_attach(device_t);
229 static int mskc_detach(device_t);
230 static int mskc_shutdown(device_t);
231 static int mskc_suspend(device_t);
232 static int mskc_resume(device_t);
233 static void mskc_intr(void *);
235 static void mskc_reset(struct msk_softc *);
236 static void mskc_set_imtimer(struct msk_softc *);
237 static void mskc_intr_hwerr(struct msk_softc *);
238 static int mskc_handle_events(struct msk_softc *);
239 static void mskc_phy_power(struct msk_softc *, int);
240 static int mskc_setup_rambuffer(struct msk_softc *);
241 static int mskc_status_dma_alloc(struct msk_softc *);
242 static void mskc_status_dma_free(struct msk_softc *);
243 static int mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS);
244 static int mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
246 static int msk_probe(device_t);
247 static int msk_attach(device_t);
248 static int msk_detach(device_t);
249 static int msk_miibus_readreg(device_t, int, int);
250 static int msk_miibus_writereg(device_t, int, int, int);
251 static void msk_miibus_statchg(device_t);
253 static void msk_init(void *);
254 static int msk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
255 static void msk_start(struct ifnet *);
256 static void msk_watchdog(struct ifnet *);
257 static int msk_mediachange(struct ifnet *);
258 static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
260 static void msk_tick(void *);
261 static void msk_intr_phy(struct msk_if_softc *);
262 static void msk_intr_gmac(struct msk_if_softc *);
264 msk_rxput(struct msk_if_softc *);
265 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
266 static void msk_rxeof(struct msk_if_softc *, uint32_t, int,
267 struct mbuf_chain *);
268 static void msk_txeof(struct msk_if_softc *, int);
269 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
270 static void msk_set_rambuffer(struct msk_if_softc *);
271 static void msk_stop(struct msk_if_softc *);
273 static int msk_txrx_dma_alloc(struct msk_if_softc *);
274 static void msk_txrx_dma_free(struct msk_if_softc *);
275 static int msk_init_rx_ring(struct msk_if_softc *);
276 static void msk_init_tx_ring(struct msk_if_softc *);
278 msk_discard_rxbuf(struct msk_if_softc *, int);
279 static int msk_newbuf(struct msk_if_softc *, int, int);
280 static int msk_encap(struct msk_if_softc *, struct mbuf **);
283 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
284 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
285 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
286 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int);
287 static void *msk_jalloc(struct msk_if_softc *);
288 static void msk_jfree(void *, void *);
291 static int msk_phy_readreg(struct msk_if_softc *, int, int);
292 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
294 static void msk_rxfilter(struct msk_if_softc *);
295 static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
296 static void msk_set_tx_stfwd(struct msk_if_softc *);
298 static int msk_dmamem_create(device_t, bus_size_t, bus_dma_tag_t *,
299 void **, bus_addr_t *, bus_dmamap_t *);
300 static void msk_dmamem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
302 static device_method_t mskc_methods[] = {
303 /* Device interface */
304 DEVMETHOD(device_probe, mskc_probe),
305 DEVMETHOD(device_attach, mskc_attach),
306 DEVMETHOD(device_detach, mskc_detach),
307 DEVMETHOD(device_suspend, mskc_suspend),
308 DEVMETHOD(device_resume, mskc_resume),
309 DEVMETHOD(device_shutdown, mskc_shutdown),
312 DEVMETHOD(bus_print_child, bus_generic_print_child),
313 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
318 static DEFINE_CLASS_0(mskc, mskc_driver, mskc_methods, sizeof(struct msk_softc));
319 static devclass_t mskc_devclass;
321 static device_method_t msk_methods[] = {
322 /* Device interface */
323 DEVMETHOD(device_probe, msk_probe),
324 DEVMETHOD(device_attach, msk_attach),
325 DEVMETHOD(device_detach, msk_detach),
326 DEVMETHOD(device_shutdown, bus_generic_shutdown),
329 DEVMETHOD(bus_print_child, bus_generic_print_child),
330 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
333 DEVMETHOD(miibus_readreg, msk_miibus_readreg),
334 DEVMETHOD(miibus_writereg, msk_miibus_writereg),
335 DEVMETHOD(miibus_statchg, msk_miibus_statchg),
340 static DEFINE_CLASS_0(msk, msk_driver, msk_methods, sizeof(struct msk_if_softc));
341 static devclass_t msk_devclass;
343 DECLARE_DUMMY_MODULE(if_msk);
344 DRIVER_MODULE(if_msk, pci, mskc_driver, mskc_devclass, NULL, NULL);
345 DRIVER_MODULE(if_msk, mskc, msk_driver, msk_devclass, NULL, NULL);
346 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, NULL, NULL);
348 static int mskc_intr_rate = 0;
349 static int mskc_process_limit = MSK_PROC_DEFAULT;
351 TUNABLE_INT("hw.mskc.intr_rate", &mskc_intr_rate);
352 TUNABLE_INT("hw.mskc.process_limit", &mskc_process_limit);
355 msk_miibus_readreg(device_t dev, int phy, int reg)
357 struct msk_if_softc *sc_if;
359 if (phy != PHY_ADDR_MARV)
362 sc_if = device_get_softc(dev);
364 return (msk_phy_readreg(sc_if, phy, reg));
368 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
370 struct msk_softc *sc;
373 sc = sc_if->msk_softc;
375 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
376 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
378 for (i = 0; i < MSK_TIMEOUT; i++) {
380 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
381 if ((val & GM_SMI_CT_RD_VAL) != 0) {
382 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
387 if (i == MSK_TIMEOUT) {
388 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
396 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
398 struct msk_if_softc *sc_if;
400 if (phy != PHY_ADDR_MARV)
403 sc_if = device_get_softc(dev);
405 return (msk_phy_writereg(sc_if, phy, reg, val));
409 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
411 struct msk_softc *sc;
414 sc = sc_if->msk_softc;
416 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
417 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
418 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
419 for (i = 0; i < MSK_TIMEOUT; i++) {
421 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
422 GM_SMI_CT_BUSY) == 0)
425 if (i == MSK_TIMEOUT)
426 if_printf(sc_if->msk_ifp, "phy write timeout\n");
432 msk_miibus_statchg(device_t dev)
434 struct msk_if_softc *sc_if;
435 struct msk_softc *sc;
436 struct mii_data *mii;
440 sc_if = device_get_softc(dev);
441 sc = sc_if->msk_softc;
443 mii = device_get_softc(sc_if->msk_miibus);
444 ifp = sc_if->msk_ifp;
447 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
448 (IFM_AVALID | IFM_ACTIVE)) {
449 switch (IFM_SUBTYPE(mii->mii_media_active)) {
458 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
464 if (sc_if->msk_link != 0) {
465 /* Enable Tx FIFO Underrun. */
466 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
467 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
469 * Because mii(4) notify msk(4) that it detected link status
470 * change, there is no need to enable automatic
471 * speed/flow-control/duplex updates.
473 gmac = GM_GPCR_AU_ALL_DIS;
474 switch (IFM_SUBTYPE(mii->mii_media_active)) {
477 gmac |= GM_GPCR_SPEED_1000;
480 gmac |= GM_GPCR_SPEED_100;
486 if ((mii->mii_media_active & IFM_GMASK) & IFM_FDX)
487 gmac |= GM_GPCR_DUP_FULL;
489 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
490 /* Disable Rx flow control. */
491 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0)
492 gmac |= GM_GPCR_FC_RX_DIS;
493 /* Disable Tx flow control. */
494 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0)
495 gmac |= GM_GPCR_FC_TX_DIS;
496 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
497 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
498 /* Read again to ensure writing. */
499 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
501 gmac = GMC_PAUSE_OFF;
502 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) &&
503 ((mii->mii_media_active & IFM_GMASK) & IFM_FDX))
505 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
507 /* Enable PHY interrupt for FIFO underrun/overflow. */
508 msk_phy_writereg(sc_if, PHY_ADDR_MARV,
509 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
512 * Link state changed to down.
513 * Disable PHY interrupts.
515 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
516 /* Disable Rx/Tx MAC. */
517 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
518 if (gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) {
519 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
520 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
521 /* Read again to ensure writing. */
522 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
528 msk_rxfilter(struct msk_if_softc *sc_if)
530 struct msk_softc *sc;
532 struct ifmultiaddr *ifma;
537 sc = sc_if->msk_softc;
538 ifp = sc_if->msk_ifp;
540 bzero(mchash, sizeof(mchash));
541 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
542 if ((ifp->if_flags & IFF_PROMISC) != 0) {
543 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
544 } else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
545 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
549 mode |= GM_RXCR_UCF_ENA;
550 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
551 if (ifma->ifma_addr->sa_family != AF_LINK)
553 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
554 ifma->ifma_addr), ETHER_ADDR_LEN);
555 /* Just want the 6 least significant bits. */
557 /* Set the corresponding bit in the hash table. */
558 mchash[crc >> 5] |= 1 << (crc & 0x1f);
560 if (mchash[0] != 0 || mchash[1] != 0)
561 mode |= GM_RXCR_MCF_ENA;
564 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
566 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
567 (mchash[0] >> 16) & 0xffff);
568 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
570 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
571 (mchash[1] >> 16) & 0xffff);
572 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
576 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
578 struct msk_softc *sc;
580 sc = sc_if->msk_softc;
581 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
582 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
584 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
587 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
589 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
595 msk_init_rx_ring(struct msk_if_softc *sc_if)
597 struct msk_ring_data *rd;
598 struct msk_rxdesc *rxd;
601 sc_if->msk_cdata.msk_rx_cons = 0;
602 sc_if->msk_cdata.msk_rx_prod = 0;
603 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
605 rd = &sc_if->msk_rdata;
606 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
607 prod = sc_if->msk_cdata.msk_rx_prod;
608 for (i = 0; i < MSK_RX_RING_CNT; i++) {
609 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
611 rxd->rx_le = &rd->msk_rx_ring[prod];
612 if (msk_newbuf(sc_if, prod, 1) != 0)
614 MSK_INC(prod, MSK_RX_RING_CNT);
617 /* Update prefetch unit. */
618 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
619 CSR_WRITE_2(sc_if->msk_softc,
620 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
621 sc_if->msk_cdata.msk_rx_prod);
628 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
630 struct msk_ring_data *rd;
631 struct msk_rxdesc *rxd;
634 MSK_IF_LOCK_ASSERT(sc_if);
636 sc_if->msk_cdata.msk_rx_cons = 0;
637 sc_if->msk_cdata.msk_rx_prod = 0;
638 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
640 rd = &sc_if->msk_rdata;
641 bzero(rd->msk_jumbo_rx_ring,
642 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
643 prod = sc_if->msk_cdata.msk_rx_prod;
644 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
645 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
647 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
648 if (msk_jumbo_newbuf(sc_if, prod) != 0)
650 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
653 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
654 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
655 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
657 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1;
658 CSR_WRITE_2(sc_if->msk_softc,
659 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
660 sc_if->msk_cdata.msk_rx_prod);
667 msk_init_tx_ring(struct msk_if_softc *sc_if)
669 struct msk_ring_data *rd;
670 struct msk_txdesc *txd;
673 sc_if->msk_cdata.msk_tx_prod = 0;
674 sc_if->msk_cdata.msk_tx_cons = 0;
675 sc_if->msk_cdata.msk_tx_cnt = 0;
677 rd = &sc_if->msk_rdata;
678 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
679 for (i = 0; i < MSK_TX_RING_CNT; i++) {
680 txd = &sc_if->msk_cdata.msk_txdesc[i];
682 txd->tx_le = &rd->msk_tx_ring[i];
687 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
689 struct msk_rx_desc *rx_le;
690 struct msk_rxdesc *rxd;
693 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
696 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
701 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx)
703 struct msk_rx_desc *rx_le;
704 struct msk_rxdesc *rxd;
707 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
710 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
715 msk_newbuf(struct msk_if_softc *sc_if, int idx, int init)
717 struct msk_rx_desc *rx_le;
718 struct msk_rxdesc *rxd;
720 bus_dma_segment_t seg;
724 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
728 m->m_len = m->m_pkthdr.len = MCLBYTES;
729 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
730 m_adj(m, ETHER_ALIGN);
732 error = bus_dmamap_load_mbuf_segment(sc_if->msk_cdata.msk_rx_tag,
733 sc_if->msk_cdata.msk_rx_sparemap,
734 m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
738 if_printf(&sc_if->arpcom.ac_if, "can't load RX mbuf\n");
742 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
743 if (rxd->rx_m != NULL) {
744 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
745 BUS_DMASYNC_POSTREAD);
746 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
749 map = rxd->rx_dmamap;
750 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
751 sc_if->msk_cdata.msk_rx_sparemap = map;
755 rx_le->msk_addr = htole32(MSK_ADDR_LO(seg.ds_addr));
756 rx_le->msk_control = htole32(seg.ds_len | OP_PACKET | HW_OWNER);
763 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
765 struct msk_rx_desc *rx_le;
766 struct msk_rxdesc *rxd;
768 bus_dma_segment_t segs[1];
773 MGETHDR(m, M_DONTWAIT, MT_DATA);
776 buf = msk_jalloc(sc_if);
781 /* Attach the buffer to the mbuf. */
782 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0,
784 if ((m->m_flags & M_EXT) == 0) {
788 m->m_pkthdr.len = m->m_len = MSK_JLEN;
789 m_adj(m, ETHER_ALIGN);
791 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
792 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
793 BUS_DMA_NOWAIT) != 0) {
797 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
799 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
800 if (rxd->rx_m != NULL) {
801 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
802 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
803 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
806 map = rxd->rx_dmamap;
807 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
808 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
809 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
810 BUS_DMASYNC_PREREAD);
813 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
815 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
825 msk_mediachange(struct ifnet *ifp)
827 struct msk_if_softc *sc_if = ifp->if_softc;
828 struct mii_data *mii;
831 mii = device_get_softc(sc_if->msk_miibus);
832 error = mii_mediachg(mii);
838 * Report current media status.
841 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
843 struct msk_if_softc *sc_if = ifp->if_softc;
844 struct mii_data *mii;
846 mii = device_get_softc(sc_if->msk_miibus);
849 ifmr->ifm_active = mii->mii_media_active;
850 ifmr->ifm_status = mii->mii_media_status;
854 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
856 struct msk_if_softc *sc_if;
858 struct mii_data *mii;
861 sc_if = ifp->if_softc;
862 ifr = (struct ifreq *)data;
868 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) {
872 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
873 ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
877 ifp->if_mtu = ifr->ifr_mtu;
878 if ((ifp->if_flags & IFF_RUNNING) != 0)
886 if (ifp->if_flags & IFF_UP) {
887 if (ifp->if_flags & IFF_RUNNING) {
888 if (((ifp->if_flags ^ sc_if->msk_if_flags)
889 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
892 if (sc_if->msk_detach == 0)
896 if (ifp->if_flags & IFF_RUNNING)
899 sc_if->msk_if_flags = ifp->if_flags;
904 if (ifp->if_flags & IFF_RUNNING)
910 mii = device_get_softc(sc_if->msk_miibus);
911 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
915 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
916 if ((mask & IFCAP_TXCSUM) != 0) {
917 ifp->if_capenable ^= IFCAP_TXCSUM;
918 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 &&
919 (IFCAP_TXCSUM & ifp->if_capabilities) != 0)
920 ifp->if_hwassist |= MSK_CSUM_FEATURES;
922 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
925 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
926 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
927 msk_setvlan(sc_if, ifp);
931 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
932 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
934 * In Yukon EC Ultra, TSO & checksum offload is not
935 * supported for jumbo frame.
937 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
938 ifp->if_capenable &= ~IFCAP_TXCSUM;
943 error = ether_ioctl(ifp, command, data);
951 mskc_probe(device_t dev)
953 const struct msk_product *mp;
954 uint16_t vendor, devid;
956 vendor = pci_get_vendor(dev);
957 devid = pci_get_device(dev);
958 for (mp = msk_products; mp->msk_name != NULL; ++mp) {
959 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
960 device_set_desc(dev, mp->msk_name);
968 mskc_setup_rambuffer(struct msk_softc *sc)
973 /* Get adapter SRAM size. */
974 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
976 device_printf(sc->msk_dev,
977 "RAM buffer size : %dKB\n", sc->msk_ramsize);
979 if (sc->msk_ramsize == 0)
981 sc->msk_pflags |= MSK_FLAG_RAMBUF;
984 * Give receiver 2/3 of memory and round down to the multiple
985 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
988 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
989 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
990 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
991 sc->msk_rxqstart[i] = next;
992 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
993 next = sc->msk_rxqend[i] + 1;
994 sc->msk_txqstart[i] = next;
995 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
996 next = sc->msk_txqend[i] + 1;
998 device_printf(sc->msk_dev,
999 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1000 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1002 device_printf(sc->msk_dev,
1003 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1004 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1013 mskc_phy_power(struct msk_softc *sc, int mode)
1019 case MSK_PHY_POWERUP:
1020 /* Switch power to VCC (WA for VAUX problem). */
1021 CSR_WRITE_1(sc, B0_POWER_CTRL,
1022 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1023 /* Disable Core Clock Division, set Clock Select to 0. */
1024 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1027 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1028 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1029 /* Enable bits are inverted. */
1030 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1031 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1032 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1035 * Enable PCI & Core Clock, enable clock gating for both Links.
1037 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1039 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1040 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1041 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1042 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1043 /* Deassert Low Power for 1st PHY. */
1044 val |= PCI_Y2_PHY1_COMA;
1045 if (sc->msk_num_port > 1)
1046 val |= PCI_Y2_PHY2_COMA;
1049 /* Release PHY from PowerDown/COMA mode. */
1050 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1051 switch (sc->msk_hw_id) {
1052 case CHIP_ID_YUKON_EC_U:
1053 case CHIP_ID_YUKON_EX:
1054 case CHIP_ID_YUKON_FE_P:
1055 case CHIP_ID_YUKON_UL_2:
1056 case CHIP_ID_YUKON_OPT:
1057 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
1059 /* Enable all clocks. */
1060 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1061 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1062 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
1063 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
1064 /* Set all bits to 0 except bits 15..12. */
1065 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
1066 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1067 our &= PCI_CTL_TIM_VMAIN_AV_MSK;
1068 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
1069 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1071 * Disable status race, workaround for
1072 * Yukon EC Ultra & Yukon EX.
1074 val = CSR_READ_4(sc, B2_GP_IO);
1075 val |= GLB_GPIO_STAT_RACE_DIS;
1076 CSR_WRITE_4(sc, B2_GP_IO, val);
1077 CSR_READ_4(sc, B2_GP_IO);
1080 for (i = 0; i < sc->msk_num_port; i++) {
1081 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1083 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1087 case MSK_PHY_POWERDOWN:
1088 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1089 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1090 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1091 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1092 val &= ~PCI_Y2_PHY1_COMA;
1093 if (sc->msk_num_port > 1)
1094 val &= ~PCI_Y2_PHY2_COMA;
1096 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1098 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1099 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1100 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1101 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1102 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1103 /* Enable bits are inverted. */
1107 * Disable PCI & Core Clock, disable clock gating for
1110 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1111 CSR_WRITE_1(sc, B0_POWER_CTRL,
1112 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1120 mskc_reset(struct msk_softc *sc)
1127 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1130 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
1131 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1132 /* Clear AHB bridge & microcontroller reset. */
1133 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1134 Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1135 /* Clear ASF microcontroller state. */
1136 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1137 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1139 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1141 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1144 * Since we disabled ASF, S/W reset is required for Power Management.
1146 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1147 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1149 /* Clear all error bits in the PCI status register. */
1150 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1151 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1153 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1154 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1155 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
1156 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1158 switch (sc->msk_bustype) {
1160 /* Clear all PEX errors. */
1161 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1162 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1163 if ((val & PEX_RX_OV) != 0) {
1164 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1165 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1170 /* Set Cache Line Size to 2(8bytes) if configured to 0. */
1171 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1173 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1174 if (sc->msk_bustype == MSK_PCIX_BUS) {
1175 /* Set Cache Line Size opt. */
1176 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1178 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1182 /* Set PHY power state. */
1183 mskc_phy_power(sc, MSK_PHY_POWERUP);
1185 /* Reset GPHY/GMAC Control */
1186 for (i = 0; i < sc->msk_num_port; i++) {
1187 /* GPHY Control reset. */
1188 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1189 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1190 /* GMAC Control reset. */
1191 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1192 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1193 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1194 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
1195 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1196 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1200 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1201 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1202 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1204 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1207 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1209 /* Clear TWSI IRQ. */
1210 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1212 /* Turn off hardware timer. */
1213 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1214 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1216 /* Turn off descriptor polling. */
1217 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1219 /* Turn off time stamps. */
1220 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1221 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1223 if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1224 sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1225 sc->msk_hw_id == CHIP_ID_YUKON_FE) {
1226 /* Configure timeout values. */
1227 for (i = 0; i < sc->msk_num_port; i++) {
1228 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL),
1230 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL),
1232 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1234 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1236 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1238 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1240 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1242 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1244 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1246 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1248 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1250 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1252 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1254 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1259 /* Disable all interrupts. */
1260 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1261 CSR_READ_4(sc, B0_HWE_IMSK);
1262 CSR_WRITE_4(sc, B0_IMSK, 0);
1263 CSR_READ_4(sc, B0_IMSK);
1266 * On dual port PCI-X card, there is an problem where status
1267 * can be received out of order due to split transactions.
1269 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1272 pcix_cmd = pci_read_config(sc->msk_dev,
1273 sc->msk_pcixcap + PCIXR_COMMAND, 2);
1274 /* Clear Max Outstanding Split Transactions. */
1275 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
1276 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1277 pci_write_config(sc->msk_dev,
1278 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1279 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1281 if (sc->msk_pciecap != 0) {
1282 /* Change Max. Read Request Size to 2048 bytes. */
1283 if (pcie_get_max_readrq(sc->msk_dev) ==
1284 PCIEM_DEVCTL_MAX_READRQ_512) {
1285 pcie_set_max_readrq(sc->msk_dev,
1286 PCIEM_DEVCTL_MAX_READRQ_2048);
1290 /* Clear status list. */
1291 bzero(sc->msk_stat_ring,
1292 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT);
1293 sc->msk_stat_cons = 0;
1294 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1295 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1296 /* Set the status list base address. */
1297 addr = sc->msk_stat_ring_paddr;
1298 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1299 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1300 /* Set the status list last index. */
1301 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
1302 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1303 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1304 /* WA for dev. #4.3 */
1305 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1306 /* WA for dev. #4.18 */
1307 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1308 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1310 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1311 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1312 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1313 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1314 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1316 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1317 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1320 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1322 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1324 /* Enable status unit. */
1325 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1327 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1328 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1329 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1333 msk_probe(device_t dev)
1335 struct msk_softc *sc = device_get_softc(device_get_parent(dev));
1339 * Not much to do here. We always know there will be
1340 * at least one GMAC present, and if there are two,
1341 * mskc_attach() will create a second device instance
1344 ksnprintf(desc, sizeof(desc),
1345 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1346 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1348 device_set_desc_copy(dev, desc);
1354 msk_attach(device_t dev)
1356 struct msk_softc *sc = device_get_softc(device_get_parent(dev));
1357 struct msk_if_softc *sc_if = device_get_softc(dev);
1358 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1360 uint8_t eaddr[ETHER_ADDR_LEN];
1362 port = *(int *)device_get_ivars(dev);
1363 KKASSERT(port == MSK_PORT_A || port == MSK_PORT_B);
1365 kfree(device_get_ivars(dev), M_DEVBUF);
1366 device_set_ivars(dev, NULL);
1368 callout_init(&sc_if->msk_tick_ch);
1369 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1371 sc_if->msk_if_dev = dev;
1372 sc_if->msk_port = port;
1373 sc_if->msk_softc = sc;
1374 sc_if->msk_ifp = ifp;
1375 sc_if->msk_flags = sc->msk_pflags;
1376 sc->msk_if[port] = sc_if;
1378 /* Setup Tx/Rx queue register offsets. */
1379 if (port == MSK_PORT_A) {
1380 sc_if->msk_txq = Q_XA1;
1381 sc_if->msk_txsq = Q_XS1;
1382 sc_if->msk_rxq = Q_R1;
1384 sc_if->msk_txq = Q_XA2;
1385 sc_if->msk_txsq = Q_XS2;
1386 sc_if->msk_rxq = Q_R2;
1389 error = msk_txrx_dma_alloc(sc_if);
1393 ifp->if_softc = sc_if;
1394 ifp->if_mtu = ETHERMTU;
1395 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1396 ifp->if_init = msk_init;
1397 ifp->if_ioctl = msk_ioctl;
1398 ifp->if_start = msk_start;
1399 ifp->if_watchdog = msk_watchdog;
1400 ifq_set_maxlen(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1401 ifq_set_ready(&ifp->if_snd);
1405 * IFCAP_RXCSUM capability is intentionally disabled as the hardware
1406 * has serious bug in Rx checksum offload for all Yukon II family
1407 * hardware. It seems there is a workaround to make it work somtimes.
1408 * However, the workaround also have to check OP code sequences to
1409 * verify whether the OP code is correct. Sometimes it should compute
1410 * IP/TCP/UDP checksum in driver in order to verify correctness of
1411 * checksum computed by hardware. If you have to compute checksum
1412 * with software to verify the hardware's checksum why have hardware
1413 * compute the checksum? I think there is no reason to spend time to
1414 * make Rx checksum offload work on Yukon II hardware.
1416 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU |
1417 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM;
1418 ifp->if_hwassist = MSK_CSUM_FEATURES;
1419 ifp->if_capenable = ifp->if_capabilities;
1423 * Get station address for this interface. Note that
1424 * dual port cards actually come with three station
1425 * addresses: one for each port, plus an extra. The
1426 * extra one is used by the SysKonnect driver software
1427 * as a 'virtual' station address for when both ports
1428 * are operating in failover mode. Currently we don't
1429 * use this extra address.
1431 for (i = 0; i < ETHER_ADDR_LEN; i++)
1432 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1434 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
1439 error = mii_phy_probe(dev, &sc_if->msk_miibus,
1440 msk_mediachange, msk_mediastatus);
1442 device_printf(sc_if->msk_if_dev, "no PHY found!\n");
1447 * Call MI attach routine. Can't hold locks when calling into ether_*.
1449 ether_ifattach(ifp, eaddr, &sc->msk_serializer);
1452 * Tell the upper layer(s) we support long frames.
1453 * Must appear after the call to ether_ifattach() because
1454 * ether_ifattach() sets ifi_hdrlen to the default value.
1456 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1462 sc->msk_if[port] = NULL;
1467 * Attach the interface. Allocate softc structures, do ifmedia
1468 * setup and ethernet/BPF attach.
1471 mskc_attach(device_t dev)
1473 struct msk_softc *sc;
1474 int error, *port, cpuid;
1476 sc = device_get_softc(dev);
1478 lwkt_serialize_init(&sc->msk_serializer);
1481 * Initailize sysctl variables
1483 sc->msk_process_limit = mskc_process_limit;
1484 sc->msk_intr_rate = mskc_intr_rate;
1486 #ifndef BURN_BRIDGES
1488 * Handle power management nonsense.
1490 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1491 uint32_t irq, bar0, bar1;
1493 /* Save important PCI config data. */
1494 bar0 = pci_read_config(dev, PCIR_BAR(0), 4);
1495 bar1 = pci_read_config(dev, PCIR_BAR(1), 4);
1496 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1498 /* Reset the power state. */
1499 device_printf(dev, "chip is in D%d power mode "
1500 "-- setting to D0\n", pci_get_powerstate(dev));
1502 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1504 /* Restore PCI config data. */
1505 pci_write_config(dev, PCIR_BAR(0), bar0, 4);
1506 pci_write_config(dev, PCIR_BAR(1), bar1, 4);
1507 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1509 #endif /* BURN_BRIDGES */
1512 * Map control/status registers.
1514 pci_enable_busmaster(dev);
1517 * Allocate I/O resource
1519 #ifdef MSK_USEIOSPACE
1520 sc->msk_res_type = SYS_RES_IOPORT;
1521 sc->msk_res_rid = PCIR_BAR(1);
1523 sc->msk_res_type = SYS_RES_MEMORY;
1524 sc->msk_res_rid = PCIR_BAR(0);
1526 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type,
1527 &sc->msk_res_rid, RF_ACTIVE);
1528 if (sc->msk_res == NULL) {
1529 if (sc->msk_res_type == SYS_RES_MEMORY) {
1530 sc->msk_res_type = SYS_RES_IOPORT;
1531 sc->msk_res_rid = PCIR_BAR(1);
1533 sc->msk_res_type = SYS_RES_MEMORY;
1534 sc->msk_res_rid = PCIR_BAR(0);
1536 sc->msk_res = bus_alloc_resource_any(dev, sc->msk_res_type,
1539 if (sc->msk_res == NULL) {
1540 device_printf(dev, "couldn't allocate %s resources\n",
1541 sc->msk_res_type == SYS_RES_MEMORY ? "memory" : "I/O");
1545 sc->msk_res_bt = rman_get_bustag(sc->msk_res);
1546 sc->msk_res_bh = rman_get_bushandle(sc->msk_res);
1551 sc->msk_irq_rid = 0;
1552 sc->msk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1554 RF_SHAREABLE | RF_ACTIVE);
1555 if (sc->msk_irq == NULL) {
1556 device_printf(dev, "couldn't allocate IRQ resources\n");
1561 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1562 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1563 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1564 /* Bail out if chip is not recognized. */
1565 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1566 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1567 sc->msk_hw_id == CHIP_ID_YUKON_SUPR ||
1568 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1569 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1570 sc->msk_hw_id, sc->msk_hw_rev);
1576 * Create sysctl tree
1578 sysctl_ctx_init(&sc->msk_sysctl_ctx);
1579 sc->msk_sysctl_tree = SYSCTL_ADD_NODE(&sc->msk_sysctl_ctx,
1580 SYSCTL_STATIC_CHILDREN(_hw),
1582 device_get_nameunit(dev),
1584 if (sc->msk_sysctl_tree == NULL) {
1585 device_printf(dev, "can't add sysctl node\n");
1590 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx,
1591 SYSCTL_CHILDREN(sc->msk_sysctl_tree),
1592 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
1593 &sc->msk_process_limit, 0, mskc_sysctl_proc_limit,
1594 "I", "max number of Rx events to process");
1595 SYSCTL_ADD_PROC(&sc->msk_sysctl_ctx,
1596 SYSCTL_CHILDREN(sc->msk_sysctl_tree),
1597 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1598 sc, 0, mskc_sysctl_intr_rate,
1599 "I", "max number of interrupt per second");
1600 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx,
1601 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO,
1602 "defrag_avoided", CTLFLAG_RW, &sc->msk_defrag_avoided,
1603 0, "# of avoided m_defrag on TX path");
1604 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx,
1605 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO,
1606 "leading_copied", CTLFLAG_RW, &sc->msk_leading_copied,
1607 0, "# of leading copies on TX path");
1608 SYSCTL_ADD_INT(&sc->msk_sysctl_ctx,
1609 SYSCTL_CHILDREN(sc->msk_sysctl_tree), OID_AUTO,
1610 "trailing_copied", CTLFLAG_RW, &sc->msk_trailing_copied,
1611 0, "# of trailing copies on TX path");
1614 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1615 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1616 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1617 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1618 sc->msk_coppertype = 0;
1620 sc->msk_coppertype = 1;
1621 /* Check number of MACs. */
1622 sc->msk_num_port = 1;
1623 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1625 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1629 /* Check bus type. */
1630 if (pci_is_pcie(sc->msk_dev) == 0) {
1631 sc->msk_bustype = MSK_PEX_BUS;
1632 sc->msk_pciecap = pci_get_pciecap_ptr(sc->msk_dev);
1633 } else if (pci_is_pcix(sc->msk_dev) == 0) {
1634 sc->msk_bustype = MSK_PCIX_BUS;
1635 sc->msk_pcixcap = pci_get_pcixcap_ptr(sc->msk_dev);
1637 sc->msk_bustype = MSK_PCI_BUS;
1640 switch (sc->msk_hw_id) {
1641 case CHIP_ID_YUKON_EC:
1642 case CHIP_ID_YUKON_EC_U:
1643 sc->msk_clock = 125; /* 125 Mhz */
1645 case CHIP_ID_YUKON_EX:
1646 sc->msk_clock = 125; /* 125 Mhz */
1648 case CHIP_ID_YUKON_FE:
1649 sc->msk_clock = 100; /* 100 Mhz */
1650 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1652 case CHIP_ID_YUKON_FE_P:
1653 sc->msk_clock = 50; /* 50 Mhz */
1655 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1656 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1659 * FE+ A0 has status LE writeback bug so msk(4)
1660 * does not rely on status word of received frame
1661 * in msk_rxeof() which in turn disables all
1662 * hardware assistance bits reported by the status
1663 * word as well as validity of the recevied frame.
1664 * Just pass received frames to upper stack with
1665 * minimal test and let upper stack handle them.
1667 sc->msk_pflags |= MSK_FLAG_NORXCHK;
1670 case CHIP_ID_YUKON_XL:
1671 sc->msk_clock = 156; /* 156 Mhz */
1673 case CHIP_ID_YUKON_UL_2:
1674 sc->msk_clock = 125; /* 125 Mhz */
1676 case CHIP_ID_YUKON_OPT:
1677 sc->msk_clock = 125; /* 125 MHz */
1680 sc->msk_clock = 156; /* 156 Mhz */
1684 error = mskc_status_dma_alloc(sc);
1688 /* Set base interrupt mask. */
1689 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1690 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1691 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1693 /* Reset the adapter. */
1696 error = mskc_setup_rambuffer(sc);
1700 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1701 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1702 device_printf(dev, "failed to add child for PORT_A\n");
1706 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1708 device_set_ivars(sc->msk_devs[MSK_PORT_A], port);
1710 if (sc->msk_num_port > 1) {
1711 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1712 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1713 device_printf(dev, "failed to add child for PORT_B\n");
1717 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1719 device_set_ivars(sc->msk_devs[MSK_PORT_B], port);
1722 bus_generic_attach(dev);
1724 error = bus_setup_intr(dev, sc->msk_irq, INTR_MPSAFE,
1725 mskc_intr, sc, &sc->msk_intrhand,
1726 &sc->msk_serializer);
1728 device_printf(dev, "couldn't set up interrupt handler\n");
1732 cpuid = ithread_cpuid(rman_get_start(sc->msk_irq));
1733 KKASSERT(cpuid >= 0 && cpuid < ncpus);
1735 if (sc->msk_if[0] != NULL)
1736 sc->msk_if[0]->msk_ifp->if_cpuid = cpuid;
1737 if (sc->msk_if[1] != NULL)
1738 sc->msk_if[1]->msk_ifp->if_cpuid = cpuid;
1746 * Shutdown hardware and free up resources. This can be called any
1747 * time after the mutex has been initialized. It is called in both
1748 * the error case in attach and the normal detach case so it needs
1749 * to be careful about only freeing resources that have actually been
1753 msk_detach(device_t dev)
1755 struct msk_if_softc *sc_if = device_get_softc(dev);
1757 if (device_is_attached(dev)) {
1758 struct msk_softc *sc = sc_if->msk_softc;
1759 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1761 lwkt_serialize_enter(ifp->if_serializer);
1763 if (sc->msk_intrhand != NULL) {
1764 if (sc->msk_if[MSK_PORT_A] != NULL)
1765 msk_stop(sc->msk_if[MSK_PORT_A]);
1766 if (sc->msk_if[MSK_PORT_B] != NULL)
1767 msk_stop(sc->msk_if[MSK_PORT_B]);
1769 bus_teardown_intr(sc->msk_dev, sc->msk_irq,
1771 sc->msk_intrhand = NULL;
1774 lwkt_serialize_exit(ifp->if_serializer);
1776 ether_ifdetach(ifp);
1779 if (sc_if->msk_miibus != NULL)
1780 device_delete_child(dev, sc_if->msk_miibus);
1782 msk_txrx_dma_free(sc_if);
1787 mskc_detach(device_t dev)
1789 struct msk_softc *sc = device_get_softc(dev);
1793 if (device_is_attached(dev)) {
1794 KASSERT(sc->msk_intrhand == NULL,
1795 ("intr is not torn down yet\n"));
1799 for (i = 0; i < sc->msk_num_port; ++i) {
1800 if (sc->msk_devs[i] != NULL) {
1801 port = device_get_ivars(sc->msk_devs[i]);
1803 kfree(port, M_DEVBUF);
1804 device_set_ivars(sc->msk_devs[i], NULL);
1806 device_delete_child(dev, sc->msk_devs[i]);
1810 /* Disable all interrupts. */
1811 CSR_WRITE_4(sc, B0_IMSK, 0);
1812 CSR_READ_4(sc, B0_IMSK);
1813 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1814 CSR_READ_4(sc, B0_HWE_IMSK);
1817 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
1819 /* Put hardware reset. */
1820 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1822 mskc_status_dma_free(sc);
1824 if (sc->msk_irq != NULL) {
1825 bus_release_resource(dev, SYS_RES_IRQ, sc->msk_irq_rid,
1828 if (sc->msk_res != NULL) {
1829 bus_release_resource(dev, sc->msk_res_type, sc->msk_res_rid,
1833 if (sc->msk_sysctl_tree != NULL)
1834 sysctl_ctx_free(&sc->msk_sysctl_ctx);
1839 /* Create status DMA region. */
1841 mskc_status_dma_alloc(struct msk_softc *sc)
1846 error = bus_dmamem_coherent(NULL/* XXX parent */, MSK_STAT_ALIGN, 0,
1847 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1848 MSK_STAT_RING_SZ, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1850 device_printf(sc->msk_dev,
1851 "failed to create status coherent DMA memory\n");
1854 sc->msk_stat_tag = dmem.dmem_tag;
1855 sc->msk_stat_map = dmem.dmem_map;
1856 sc->msk_stat_ring = dmem.dmem_addr;
1857 sc->msk_stat_ring_paddr = dmem.dmem_busaddr;
1863 mskc_status_dma_free(struct msk_softc *sc)
1865 /* Destroy status block. */
1866 if (sc->msk_stat_tag) {
1867 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
1868 bus_dmamem_free(sc->msk_stat_tag, sc->msk_stat_ring,
1870 bus_dma_tag_destroy(sc->msk_stat_tag);
1871 sc->msk_stat_tag = NULL;
1876 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
1880 struct msk_rxdesc *jrxd;
1881 struct msk_jpool_entry *entry;
1886 /* Create parent DMA tag. */
1889 * It seems that Yukon II supports full 64bits DMA operations. But
1890 * it needs two descriptors(list elements) for 64bits DMA operations.
1891 * Since we don't know what DMA address mappings(32bits or 64bits)
1892 * would be used in advance for each mbufs, we limits its DMA space
1893 * to be in range of 32bits address space. Otherwise, we should check
1894 * what DMA address is used and chain another descriptor for the
1895 * 64bits DMA operation. This also means descriptor ring size is
1896 * variable. Limiting DMA address to be in 32bit address space greatly
1897 * simplyfies descriptor handling and possibly would increase
1898 * performance a bit due to efficient handling of descriptors.
1899 * Apart from harassing checksum offloading mechanisms, it seems
1900 * it's really bad idea to use a seperate descriptor for 64bit
1901 * DMA operation to save small descriptor memory. Anyway, I've
1902 * never seen these exotic scheme on ethernet interface hardware.
1904 error = bus_dma_tag_create(
1906 1, 0, /* alignment, boundary */
1907 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1908 BUS_SPACE_MAXADDR, /* highaddr */
1909 NULL, NULL, /* filter, filterarg */
1910 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1912 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1914 &sc_if->msk_cdata.msk_parent_tag);
1916 device_printf(sc_if->msk_if_dev,
1917 "failed to create parent DMA tag\n");
1921 /* Create DMA stuffs for Tx ring. */
1922 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_TX_RING_SZ,
1923 &sc_if->msk_cdata.msk_tx_ring_tag,
1924 (void *)&sc_if->msk_rdata.msk_tx_ring,
1925 &sc_if->msk_rdata.msk_tx_ring_paddr,
1926 &sc_if->msk_cdata.msk_tx_ring_map);
1928 device_printf(sc_if->msk_if_dev,
1929 "failed to create TX ring DMA stuffs\n");
1933 /* Create DMA stuffs for Rx ring. */
1934 error = msk_dmamem_create(sc_if->msk_if_dev, MSK_RX_RING_SZ,
1935 &sc_if->msk_cdata.msk_rx_ring_tag,
1936 (void *)&sc_if->msk_rdata.msk_rx_ring,
1937 &sc_if->msk_rdata.msk_rx_ring_paddr,
1938 &sc_if->msk_cdata.msk_rx_ring_map);
1940 device_printf(sc_if->msk_if_dev,
1941 "failed to create RX ring DMA stuffs\n");
1945 /* Create tag for Tx buffers. */
1946 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
1947 1, 0, /* alignment, boundary */
1948 BUS_SPACE_MAXADDR, /* lowaddr */
1949 BUS_SPACE_MAXADDR, /* highaddr */
1950 NULL, NULL, /* filter, filterarg */
1951 MSK_JUMBO_FRAMELEN, /* maxsize */
1952 MSK_MAXTXSEGS, /* nsegments */
1953 MSK_MAXSGSIZE, /* maxsegsize */
1954 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
1955 BUS_DMA_ONEBPAGE, /* flags */
1956 &sc_if->msk_cdata.msk_tx_tag);
1958 device_printf(sc_if->msk_if_dev,
1959 "failed to create Tx DMA tag\n");
1963 /* Create DMA maps for Tx buffers. */
1964 for (i = 0; i < MSK_TX_RING_CNT; i++) {
1965 struct msk_txdesc *txd = &sc_if->msk_cdata.msk_txdesc[i];
1967 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag,
1968 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1971 device_printf(sc_if->msk_if_dev,
1972 "failed to create %dth Tx dmamap\n", i);
1974 for (j = 0; j < i; ++j) {
1975 txd = &sc_if->msk_cdata.msk_txdesc[j];
1976 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
1979 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
1980 sc_if->msk_cdata.msk_tx_tag = NULL;
1987 * Workaround hardware hang which seems to happen when Rx buffer
1988 * is not aligned on multiple of FIFO word(8 bytes).
1990 if (sc_if->msk_flags & MSK_FLAG_RAMBUF)
1991 rxalign = MSK_RX_BUF_ALIGN;
1995 /* Create tag for Rx buffers. */
1996 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
1997 rxalign, 0, /* alignment, boundary */
1998 BUS_SPACE_MAXADDR, /* lowaddr */
1999 BUS_SPACE_MAXADDR, /* highaddr */
2000 NULL, NULL, /* filter, filterarg */
2001 MCLBYTES, /* maxsize */
2003 MCLBYTES, /* maxsegsize */
2004 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2005 BUS_DMA_WAITOK, /* flags */
2006 &sc_if->msk_cdata.msk_rx_tag);
2008 device_printf(sc_if->msk_if_dev,
2009 "failed to create Rx DMA tag\n");
2013 /* Create DMA maps for Rx buffers. */
2014 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, BUS_DMA_WAITOK,
2015 &sc_if->msk_cdata.msk_rx_sparemap);
2017 device_printf(sc_if->msk_if_dev,
2018 "failed to create spare Rx dmamap\n");
2019 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2020 sc_if->msk_cdata.msk_rx_tag = NULL;
2023 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2024 struct msk_rxdesc *rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2026 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag,
2027 BUS_DMA_WAITOK, &rxd->rx_dmamap);
2029 device_printf(sc_if->msk_if_dev,
2030 "failed to create %dth Rx dmamap\n", i);
2032 for (j = 0; j < i; ++j) {
2033 rxd = &sc_if->msk_cdata.msk_rxdesc[j];
2034 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2037 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2038 sc_if->msk_cdata.msk_rx_sparemap);
2039 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2040 sc_if->msk_cdata.msk_rx_tag = NULL;
2047 SLIST_INIT(&sc_if->msk_jfree_listhead);
2048 SLIST_INIT(&sc_if->msk_jinuse_listhead);
2050 /* Create tag for jumbo Rx ring. */
2051 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2052 MSK_RING_ALIGN, 0, /* alignment, boundary */
2053 BUS_SPACE_MAXADDR, /* lowaddr */
2054 BUS_SPACE_MAXADDR, /* highaddr */
2055 NULL, NULL, /* filter, filterarg */
2056 MSK_JUMBO_RX_RING_SZ, /* maxsize */
2058 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */
2060 NULL, NULL, /* lockfunc, lockarg */
2061 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2063 device_printf(sc_if->msk_if_dev,
2064 "failed to create jumbo Rx ring DMA tag\n");
2068 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2069 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2070 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2071 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2072 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2074 device_printf(sc_if->msk_if_dev,
2075 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2079 ctx.msk_busaddr = 0;
2080 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2081 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2082 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2083 msk_dmamap_cb, &ctx, 0);
2085 device_printf(sc_if->msk_if_dev,
2086 "failed to load DMA'able memory for jumbo Rx ring\n");
2089 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2091 /* Create tag for jumbo buffer blocks. */
2092 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2093 PAGE_SIZE, 0, /* alignment, boundary */
2094 BUS_SPACE_MAXADDR, /* lowaddr */
2095 BUS_SPACE_MAXADDR, /* highaddr */
2096 NULL, NULL, /* filter, filterarg */
2097 MSK_JMEM, /* maxsize */
2099 MSK_JMEM, /* maxsegsize */
2101 NULL, NULL, /* lockfunc, lockarg */
2102 &sc_if->msk_cdata.msk_jumbo_tag);
2104 device_printf(sc_if->msk_if_dev,
2105 "failed to create jumbo Rx buffer block DMA tag\n");
2109 /* Create tag for jumbo Rx buffers. */
2110 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2111 PAGE_SIZE, 0, /* alignment, boundary */
2112 BUS_SPACE_MAXADDR, /* lowaddr */
2113 BUS_SPACE_MAXADDR, /* highaddr */
2114 NULL, NULL, /* filter, filterarg */
2115 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */
2116 MSK_MAXRXSEGS, /* nsegments */
2117 MSK_JLEN, /* maxsegsize */
2119 NULL, NULL, /* lockfunc, lockarg */
2120 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2122 device_printf(sc_if->msk_if_dev,
2123 "failed to create jumbo Rx DMA tag\n");
2127 /* Create DMA maps for jumbo Rx buffers. */
2128 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2129 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2130 device_printf(sc_if->msk_if_dev,
2131 "failed to create spare jumbo Rx dmamap\n");
2134 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2135 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2137 jrxd->rx_dmamap = NULL;
2138 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2141 device_printf(sc_if->msk_if_dev,
2142 "failed to create jumbo Rx dmamap\n");
2147 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */
2148 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag,
2149 (void **)&sc_if->msk_rdata.msk_jumbo_buf,
2150 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2151 &sc_if->msk_cdata.msk_jumbo_map);
2153 device_printf(sc_if->msk_if_dev,
2154 "failed to allocate DMA'able memory for jumbo buf\n");
2158 ctx.msk_busaddr = 0;
2159 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag,
2160 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf,
2161 MSK_JMEM, msk_dmamap_cb, &ctx, 0);
2163 device_printf(sc_if->msk_if_dev,
2164 "failed to load DMA'able memory for jumbobuf\n");
2167 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr;
2170 * Now divide it up into 9K pieces and save the addresses
2173 ptr = sc_if->msk_rdata.msk_jumbo_buf;
2174 for (i = 0; i < MSK_JSLOTS; i++) {
2175 sc_if->msk_cdata.msk_jslots[i] = ptr;
2177 entry = malloc(sizeof(struct msk_jpool_entry),
2178 M_DEVBUF, M_WAITOK);
2179 if (entry == NULL) {
2180 device_printf(sc_if->msk_if_dev,
2181 "no memory for jumbo buffers!\n");
2186 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2194 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2196 struct msk_txdesc *txd;
2197 struct msk_rxdesc *rxd;
2199 struct msk_rxdesc *jrxd;
2200 struct msk_jpool_entry *entry;
2205 MSK_JLIST_LOCK(sc_if);
2206 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) {
2207 device_printf(sc_if->msk_if_dev,
2208 "asked to free buffer that is in use!\n");
2209 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2210 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry,
2214 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) {
2215 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2216 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2217 free(entry, M_DEVBUF);
2219 MSK_JLIST_UNLOCK(sc_if);
2221 /* Destroy jumbo buffer block. */
2222 if (sc_if->msk_cdata.msk_jumbo_map)
2223 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag,
2224 sc_if->msk_cdata.msk_jumbo_map);
2226 if (sc_if->msk_rdata.msk_jumbo_buf) {
2227 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag,
2228 sc_if->msk_rdata.msk_jumbo_buf,
2229 sc_if->msk_cdata.msk_jumbo_map);
2230 sc_if->msk_rdata.msk_jumbo_buf = NULL;
2231 sc_if->msk_cdata.msk_jumbo_map = NULL;
2234 /* Jumbo Rx ring. */
2235 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2236 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map)
2237 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2238 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2239 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map &&
2240 sc_if->msk_rdata.msk_jumbo_rx_ring)
2241 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2242 sc_if->msk_rdata.msk_jumbo_rx_ring,
2243 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2244 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2245 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL;
2246 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2247 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2250 /* Jumbo Rx buffers. */
2251 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2252 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2253 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2254 if (jrxd->rx_dmamap) {
2256 sc_if->msk_cdata.msk_jumbo_rx_tag,
2258 jrxd->rx_dmamap = NULL;
2261 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2262 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2263 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2264 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2266 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2267 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2272 msk_dmamem_destroy(sc_if->msk_cdata.msk_tx_ring_tag,
2273 sc_if->msk_rdata.msk_tx_ring,
2274 sc_if->msk_cdata.msk_tx_ring_map);
2277 msk_dmamem_destroy(sc_if->msk_cdata.msk_rx_ring_tag,
2278 sc_if->msk_rdata.msk_rx_ring,
2279 sc_if->msk_cdata.msk_rx_ring_map);
2282 if (sc_if->msk_cdata.msk_tx_tag) {
2283 for (i = 0; i < MSK_TX_RING_CNT; i++) {
2284 txd = &sc_if->msk_cdata.msk_txdesc[i];
2285 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2288 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2289 sc_if->msk_cdata.msk_tx_tag = NULL;
2293 if (sc_if->msk_cdata.msk_rx_tag) {
2294 for (i = 0; i < MSK_RX_RING_CNT; i++) {
2295 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2296 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2299 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2300 sc_if->msk_cdata.msk_rx_sparemap);
2301 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2302 sc_if->msk_cdata.msk_rx_tag = NULL;
2305 if (sc_if->msk_cdata.msk_parent_tag) {
2306 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2307 sc_if->msk_cdata.msk_parent_tag = NULL;
2313 * Allocate a jumbo buffer.
2316 msk_jalloc(struct msk_if_softc *sc_if)
2318 struct msk_jpool_entry *entry;
2320 MSK_JLIST_LOCK(sc_if);
2322 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead);
2324 if (entry == NULL) {
2325 MSK_JLIST_UNLOCK(sc_if);
2329 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries);
2330 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries);
2332 MSK_JLIST_UNLOCK(sc_if);
2334 return (sc_if->msk_cdata.msk_jslots[entry->slot]);
2338 * Release a jumbo buffer.
2341 msk_jfree(void *buf, void *args)
2343 struct msk_if_softc *sc_if;
2344 struct msk_jpool_entry *entry;
2347 /* Extract the softc struct pointer. */
2348 sc_if = (struct msk_if_softc *)args;
2349 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__));
2351 MSK_JLIST_LOCK(sc_if);
2352 /* Calculate the slot this buffer belongs to. */
2353 i = ((vm_offset_t)buf
2354 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN;
2355 KASSERT(i >= 0 && i < MSK_JSLOTS,
2356 ("%s: asked to free buffer that we don't manage!", __func__));
2358 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead);
2359 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__));
2361 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries);
2362 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries);
2363 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead))
2366 MSK_JLIST_UNLOCK(sc_if);
2371 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2373 struct msk_txdesc *txd, *txd_last;
2374 struct msk_tx_desc *tx_le;
2377 bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2378 uint32_t control, prod, si;
2379 uint16_t offset, tcp_offset;
2380 int error, i, nsegs, maxsegs, defrag;
2382 maxsegs = MSK_TX_RING_CNT - sc_if->msk_cdata.msk_tx_cnt -
2383 MSK_RESERVED_TX_DESC_CNT;
2384 KASSERT(maxsegs >= MSK_SPARE_TX_DESC_CNT,
2385 ("not enough spare TX desc\n"));
2386 if (maxsegs > MSK_MAXTXSEGS)
2387 maxsegs = MSK_MAXTXSEGS;
2390 * Align TX buffer to 64bytes boundary. This greately improves
2391 * bulk data TX performance on my 88E8053 (+100Mbps) at least.
2392 * Try avoiding m_defrag(), if the mbufs are not chained together
2393 * by m_next (i.e. m->m_len == m->m_pkthdr.len).
2396 #define MSK_TXBUF_ALIGN 64
2397 #define MSK_TXBUF_MASK (MSK_TXBUF_ALIGN - 1)
2401 if (m->m_len == m->m_pkthdr.len) {
2404 space = ((uintptr_t)m->m_data & MSK_TXBUF_MASK);
2406 if (M_WRITABLE(m)) {
2407 if (M_TRAILINGSPACE(m) >= space) {
2409 bcopy(m->m_data, m->m_data + space,
2413 sc_if->msk_softc->msk_trailing_copied++;
2415 space = MSK_TXBUF_ALIGN - space;
2416 if (M_LEADINGSPACE(m) >= space) {
2417 /* e.g. Small UDP datagrams */
2424 msk_leading_copied++;
2429 /* e.g. on forwarding path */
2434 m = m_defrag(*m_head, MB_DONTWAIT);
2442 sc_if->msk_softc->msk_defrag_avoided++;
2445 #undef MSK_TXBUF_MASK
2446 #undef MSK_TXBUF_ALIGN
2448 tcp_offset = offset = 0;
2449 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) {
2451 * Since mbuf has no protocol specific structure information
2452 * in it we have to inspect protocol information here to
2453 * setup TSO and checksum offload. I don't know why Marvell
2454 * made a such decision in chip design because other GigE
2455 * hardwares normally takes care of all these chores in
2456 * hardware. However, TSO performance of Yukon II is very
2457 * good such that it's worth to implement it.
2459 struct ether_header *eh;
2462 /* TODO check for M_WRITABLE(m) */
2464 offset = sizeof(struct ether_header);
2465 m = m_pullup(m, offset);
2470 eh = mtod(m, struct ether_header *);
2471 /* Check if hardware VLAN insertion is off. */
2472 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2473 offset = sizeof(struct ether_vlan_header);
2474 m = m_pullup(m, offset);
2480 m = m_pullup(m, offset + sizeof(struct ip));
2485 ip = (struct ip *)(mtod(m, char *) + offset);
2486 offset += (ip->ip_hl << 2);
2487 tcp_offset = offset;
2489 * It seems that Yukon II has Tx checksum offload bug for
2490 * small TCP packets that's less than 60 bytes in size
2491 * (e.g. TCP window probe packet, pure ACK packet).
2492 * Common work around like padding with zeros to make the
2493 * frame minimum ethernet frame size didn't work at all.
2494 * Instead of disabling checksum offload completely we
2495 * resort to S/W checksum routine when we encounter short
2497 * Short UDP packets appear to be handled correctly by
2500 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN &&
2501 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2504 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset -
2505 (ip->ip_hl << 2), offset);
2506 *(uint16_t *)(m->m_data + offset +
2507 m->m_pkthdr.csum_data) = csum;
2508 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2513 prod = sc_if->msk_cdata.msk_tx_prod;
2514 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2516 map = txd->tx_dmamap;
2518 error = bus_dmamap_load_mbuf_defrag(sc_if->msk_cdata.msk_tx_tag, map,
2519 m_head, txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2525 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2532 /* Check if we have a VLAN tag to insert. */
2533 if ((m->m_flags & M_VLANTAG) != 0) {
2534 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2535 tx_le->msk_addr = htole32(0);
2536 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2537 htons(m->m_pkthdr.ether_vtag));
2538 sc_if->msk_cdata.msk_tx_cnt++;
2539 MSK_INC(prod, MSK_TX_RING_CNT);
2540 control |= INS_VLAN;
2543 /* Check if we have to handle checksum offload. */
2544 if (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) {
2545 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2546 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data)
2547 & 0xffff) | ((uint32_t)tcp_offset << 16));
2548 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER));
2549 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2550 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2552 sc_if->msk_cdata.msk_tx_cnt++;
2553 MSK_INC(prod, MSK_TX_RING_CNT);
2557 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2558 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2559 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2561 sc_if->msk_cdata.msk_tx_cnt++;
2562 MSK_INC(prod, MSK_TX_RING_CNT);
2564 for (i = 1; i < nsegs; i++) {
2565 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2566 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2567 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2568 OP_BUFFER | HW_OWNER);
2569 sc_if->msk_cdata.msk_tx_cnt++;
2570 MSK_INC(prod, MSK_TX_RING_CNT);
2572 /* Update producer index. */
2573 sc_if->msk_cdata.msk_tx_prod = prod;
2575 /* Set EOP on the last desciptor. */
2576 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2577 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2578 tx_le->msk_control |= htole32(EOP);
2580 /* Turn the first descriptor ownership to hardware. */
2581 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2582 tx_le->msk_control |= htole32(HW_OWNER);
2584 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2585 map = txd_last->tx_dmamap;
2586 txd_last->tx_dmamap = txd->tx_dmamap;
2587 txd->tx_dmamap = map;
2594 msk_start(struct ifnet *ifp)
2596 struct msk_if_softc *sc_if;
2597 struct mbuf *m_head;
2600 sc_if = ifp->if_softc;
2602 ASSERT_SERIALIZED(ifp->if_serializer);
2604 if (!sc_if->msk_link) {
2605 ifq_purge(&ifp->if_snd);
2609 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2613 while (!ifq_is_empty(&ifp->if_snd)) {
2614 if (MSK_IS_OACTIVE(sc_if)) {
2615 ifp->if_flags |= IFF_OACTIVE;
2619 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2624 * Pack the data into the transmit ring. If we
2625 * don't have room, set the OACTIVE flag and wait
2626 * for the NIC to drain the ring.
2628 if (msk_encap(sc_if, &m_head) != 0) {
2630 if (sc_if->msk_cdata.msk_tx_cnt == 0) {
2633 ifp->if_flags |= IFF_OACTIVE;
2640 * If there's a BPF listener, bounce a copy of this frame
2643 BPF_MTAP(ifp, m_head);
2648 CSR_WRITE_2(sc_if->msk_softc,
2649 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2650 sc_if->msk_cdata.msk_tx_prod);
2652 /* Set a timeout in case the chip goes out to lunch. */
2653 ifp->if_timer = MSK_TX_TIMEOUT;
2658 msk_watchdog(struct ifnet *ifp)
2660 struct msk_if_softc *sc_if = ifp->if_softc;
2664 ASSERT_SERIALIZED(ifp->if_serializer);
2666 if (sc_if->msk_link == 0) {
2668 if_printf(sc_if->msk_ifp, "watchdog timeout "
2676 * Reclaim first as there is a possibility of losing Tx completion
2679 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX;
2680 idx = CSR_READ_2(sc_if->msk_softc, ridx);
2681 if (sc_if->msk_cdata.msk_tx_cons != idx) {
2682 msk_txeof(sc_if, idx);
2683 if (sc_if->msk_cdata.msk_tx_cnt == 0) {
2684 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2686 if (!ifq_is_empty(&ifp->if_snd))
2692 if_printf(ifp, "watchdog timeout\n");
2695 if (!ifq_is_empty(&ifp->if_snd))
2700 mskc_shutdown(device_t dev)
2702 struct msk_softc *sc = device_get_softc(dev);
2705 lwkt_serialize_enter(&sc->msk_serializer);
2707 for (i = 0; i < sc->msk_num_port; i++) {
2708 if (sc->msk_if[i] != NULL)
2709 msk_stop(sc->msk_if[i]);
2712 /* Put hardware reset. */
2713 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2715 lwkt_serialize_exit(&sc->msk_serializer);
2720 mskc_suspend(device_t dev)
2722 struct msk_softc *sc = device_get_softc(dev);
2725 lwkt_serialize_enter(&sc->msk_serializer);
2727 for (i = 0; i < sc->msk_num_port; i++) {
2728 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2729 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_RUNNING) != 0))
2730 msk_stop(sc->msk_if[i]);
2733 /* Disable all interrupts. */
2734 CSR_WRITE_4(sc, B0_IMSK, 0);
2735 CSR_READ_4(sc, B0_IMSK);
2736 CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2737 CSR_READ_4(sc, B0_HWE_IMSK);
2739 mskc_phy_power(sc, MSK_PHY_POWERDOWN);
2741 /* Put hardware reset. */
2742 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2743 sc->msk_suspended = 1;
2745 lwkt_serialize_exit(&sc->msk_serializer);
2751 mskc_resume(device_t dev)
2753 struct msk_softc *sc = device_get_softc(dev);
2756 lwkt_serialize_enter(&sc->msk_serializer);
2759 for (i = 0; i < sc->msk_num_port; i++) {
2760 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2761 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0))
2762 msk_init(sc->msk_if[i]);
2764 sc->msk_suspended = 0;
2766 lwkt_serialize_exit(&sc->msk_serializer);
2772 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len,
2773 struct mbuf_chain *chain)
2777 struct msk_rxdesc *rxd;
2780 ifp = sc_if->msk_ifp;
2782 cons = sc_if->msk_cdata.msk_rx_cons;
2784 rxlen = status >> 16;
2785 if ((status & GMR_FS_VLAN) != 0 &&
2786 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2787 rxlen -= EVL_ENCAPLEN;
2788 if (sc_if->msk_flags & MSK_FLAG_NORXCHK) {
2790 * For controllers that returns bogus status code
2791 * just do minimal check and let upper stack
2792 * handle this frame.
2794 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
2796 msk_discard_rxbuf(sc_if, cons);
2799 } else if (len > sc_if->msk_framesize ||
2800 ((status & GMR_FS_ANY_ERR) != 0) ||
2801 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
2802 /* Don't count flow-control packet as errors. */
2803 if ((status & GMR_FS_GOOD_FC) == 0)
2805 msk_discard_rxbuf(sc_if, cons);
2808 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
2810 if (msk_newbuf(sc_if, cons, 0) != 0) {
2812 /* Reuse old buffer. */
2813 msk_discard_rxbuf(sc_if, cons);
2816 m->m_pkthdr.rcvif = ifp;
2817 m->m_pkthdr.len = m->m_len = len;
2820 /* Check for VLAN tagged packets. */
2821 if ((status & GMR_FS_VLAN) != 0 &&
2822 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
2823 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
2824 m->m_flags |= M_VLANTAG;
2828 ether_input_chain(ifp, m, NULL, chain);
2831 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
2832 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
2837 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len)
2841 struct msk_rxdesc *jrxd;
2844 ifp = sc_if->msk_ifp;
2846 MSK_IF_LOCK_ASSERT(sc_if);
2848 cons = sc_if->msk_cdata.msk_rx_cons;
2850 rxlen = status >> 16;
2851 if ((status & GMR_FS_VLAN) != 0 &&
2852 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2853 rxlen -= ETHER_VLAN_ENCAP_LEN;
2854 if (len > sc_if->msk_framesize ||
2855 ((status & GMR_FS_ANY_ERR) != 0) ||
2856 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
2857 /* Don't count flow-control packet as errors. */
2858 if ((status & GMR_FS_GOOD_FC) == 0)
2860 msk_discard_jumbo_rxbuf(sc_if, cons);
2863 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
2865 if (msk_jumbo_newbuf(sc_if, cons) != 0) {
2867 /* Reuse old buffer. */
2868 msk_discard_jumbo_rxbuf(sc_if, cons);
2871 m->m_pkthdr.rcvif = ifp;
2872 m->m_pkthdr.len = m->m_len = len;
2874 /* Check for VLAN tagged packets. */
2875 if ((status & GMR_FS_VLAN) != 0 &&
2876 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
2877 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
2878 m->m_flags |= M_VLANTAG;
2880 MSK_IF_UNLOCK(sc_if);
2881 (*ifp->if_input)(ifp, m);
2885 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
2886 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
2891 msk_txeof(struct msk_if_softc *sc_if, int idx)
2893 struct msk_txdesc *txd;
2894 struct msk_tx_desc *cur_tx;
2899 ifp = sc_if->msk_ifp;
2902 * Go through our tx ring and free mbufs for those
2903 * frames that have been sent.
2905 cons = sc_if->msk_cdata.msk_tx_cons;
2907 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
2908 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
2911 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
2912 control = le32toh(cur_tx->msk_control);
2913 sc_if->msk_cdata.msk_tx_cnt--;
2914 if ((control & EOP) == 0)
2916 txd = &sc_if->msk_cdata.msk_txdesc[cons];
2917 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
2920 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
2927 sc_if->msk_cdata.msk_tx_cons = cons;
2928 if (!MSK_IS_OACTIVE(sc_if))
2929 ifp->if_flags &= ~IFF_OACTIVE;
2930 if (sc_if->msk_cdata.msk_tx_cnt == 0)
2932 /* No need to sync LEs as we didn't update LEs. */
2937 msk_tick(void *xsc_if)
2939 struct msk_if_softc *sc_if = xsc_if;
2940 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2941 struct mii_data *mii;
2943 lwkt_serialize_enter(ifp->if_serializer);
2945 mii = device_get_softc(sc_if->msk_miibus);
2948 if (!sc_if->msk_link)
2949 msk_miibus_statchg(sc_if->msk_if_dev);
2950 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
2952 lwkt_serialize_exit(ifp->if_serializer);
2956 msk_intr_phy(struct msk_if_softc *sc_if)
2960 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
2961 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
2962 /* Handle FIFO Underrun/Overflow? */
2963 if (status & PHY_M_IS_FIFO_ERROR) {
2964 device_printf(sc_if->msk_if_dev,
2965 "PHY FIFO underrun/overflow.\n");
2970 msk_intr_gmac(struct msk_if_softc *sc_if)
2972 struct msk_softc *sc;
2975 sc = sc_if->msk_softc;
2976 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
2978 /* GMAC Rx FIFO overrun. */
2979 if ((status & GM_IS_RX_FF_OR) != 0) {
2980 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
2983 /* GMAC Tx FIFO underrun. */
2984 if ((status & GM_IS_TX_FF_UR) != 0) {
2985 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
2987 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
2990 * In case of Tx underrun, we may need to flush/reset
2991 * Tx MAC but that would also require resynchronization
2992 * with status LEs. Reintializing status LEs would
2993 * affect other port in dual MAC configuration so it
2994 * should be avoided as possible as we can.
2995 * Due to lack of documentation it's all vague guess but
2996 * it needs more investigation.
3002 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3004 struct msk_softc *sc;
3006 sc = sc_if->msk_softc;
3007 if ((status & Y2_IS_PAR_RD1) != 0) {
3008 device_printf(sc_if->msk_if_dev,
3009 "RAM buffer read parity error\n");
3011 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3014 if ((status & Y2_IS_PAR_WR1) != 0) {
3015 device_printf(sc_if->msk_if_dev,
3016 "RAM buffer write parity error\n");
3018 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3021 if ((status & Y2_IS_PAR_MAC1) != 0) {
3022 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3024 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3027 if ((status & Y2_IS_PAR_RX1) != 0) {
3028 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3030 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3032 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3033 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3035 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3040 mskc_intr_hwerr(struct msk_softc *sc)
3043 uint32_t tlphead[4];
3045 status = CSR_READ_4(sc, B0_HWE_ISRC);
3046 /* Time Stamp timer overflow. */
3047 if ((status & Y2_IS_TIST_OV) != 0)
3048 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3049 if ((status & Y2_IS_PCI_NEXP) != 0) {
3051 * PCI Express Error occured which is not described in PEX
3053 * This error is also mapped either to Master Abort(
3054 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3055 * can only be cleared there.
3057 device_printf(sc->msk_dev,
3058 "PCI Express protocol violation error\n");
3061 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3064 if ((status & Y2_IS_MST_ERR) != 0)
3065 device_printf(sc->msk_dev,
3066 "unexpected IRQ Status error\n");
3068 device_printf(sc->msk_dev,
3069 "unexpected IRQ Master error\n");
3070 /* Reset all bits in the PCI status register. */
3071 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3072 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3073 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3074 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3075 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2);
3076 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3079 /* Check for PCI Express Uncorrectable Error. */
3080 if ((status & Y2_IS_PCI_EXP) != 0) {
3084 * On PCI Express bus bridges are called root complexes (RC).
3085 * PCI Express errors are recognized by the root complex too,
3086 * which requests the system to handle the problem. After
3087 * error occurence it may be that no access to the adapter
3088 * may be performed any longer.
3091 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3092 if ((v32 & PEX_UNSUP_REQ) != 0) {
3093 /* Ignore unsupported request error. */
3095 device_printf(sc->msk_dev,
3096 "Uncorrectable PCI Express error\n");
3099 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3102 /* Get TLP header form Log Registers. */
3103 for (i = 0; i < 4; i++)
3104 tlphead[i] = CSR_PCI_READ_4(sc,
3105 PEX_HEADER_LOG + i * 4);
3106 /* Check for vendor defined broadcast message. */
3107 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3108 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3109 CSR_WRITE_4(sc, B0_HWE_IMSK,
3110 sc->msk_intrhwemask);
3111 CSR_READ_4(sc, B0_HWE_IMSK);
3114 /* Clear the interrupt. */
3115 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3116 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3117 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3120 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3121 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3122 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3123 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3126 static __inline void
3127 msk_rxput(struct msk_if_softc *sc_if)
3129 struct msk_softc *sc;
3131 sc = sc_if->msk_softc;
3133 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) {
3135 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3136 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3137 BUS_DMASYNC_PREWRITE);
3140 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3141 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3145 mskc_handle_events(struct msk_softc *sc)
3147 struct msk_if_softc *sc_if;
3149 struct msk_stat_desc *sd;
3150 uint32_t control, status;
3151 int cons, idx, len, port, rxprog;
3152 struct mbuf_chain chain[MAXCPU];
3154 idx = CSR_READ_2(sc, STAT_PUT_IDX);
3155 if (idx == sc->msk_stat_cons)
3158 ether_input_chain_init(chain);
3160 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3163 for (cons = sc->msk_stat_cons; cons != idx;) {
3164 sd = &sc->msk_stat_ring[cons];
3165 control = le32toh(sd->msk_control);
3166 if ((control & HW_OWNER) == 0)
3169 * Marvell's FreeBSD driver updates status LE after clearing
3170 * HW_OWNER. However we don't have a way to sync single LE
3171 * with bus_dma(9) API. bus_dma(9) provides a way to sync
3172 * an entire DMA map. So don't sync LE until we have a better
3175 control &= ~HW_OWNER;
3176 sd->msk_control = htole32(control);
3177 status = le32toh(sd->msk_status);
3178 len = control & STLE_LEN_MASK;
3179 port = (control >> 16) & 0x01;
3180 sc_if = sc->msk_if[port];
3181 if (sc_if == NULL) {
3182 device_printf(sc->msk_dev, "invalid port opcode "
3183 "0x%08x\n", control & STLE_OP_MASK);
3187 switch (control & STLE_OP_MASK) {
3189 sc_if->msk_vtag = ntohs(len);
3192 sc_if->msk_vtag = ntohs(len);
3195 if ((sc_if->msk_ifp->if_flags & IFF_RUNNING) == 0)
3198 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN))
3199 msk_jumbo_rxeof(sc_if, status, len);
3202 msk_rxeof(sc_if, status, len, chain);
3205 * Because there is no way to sync single Rx LE
3206 * put the DMA sync operation off until the end of
3210 /* Update prefetch unit if we've passed water mark. */
3211 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3217 if (sc->msk_if[MSK_PORT_A] != NULL) {
3218 msk_txeof(sc->msk_if[MSK_PORT_A],
3219 status & STLE_TXA1_MSKL);
3221 if (sc->msk_if[MSK_PORT_B] != NULL) {
3222 msk_txeof(sc->msk_if[MSK_PORT_B],
3223 ((status & STLE_TXA2_MSKL) >>
3225 ((len & STLE_TXA2_MSKH) <<
3230 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3231 control & STLE_OP_MASK);
3234 MSK_INC(cons, MSK_STAT_RING_CNT);
3235 if (rxprog > sc->msk_process_limit)
3240 ether_input_dispatch(chain);
3242 sc->msk_stat_cons = cons;
3243 /* XXX We should sync status LEs here. See above notes. */
3245 if (rxput[MSK_PORT_A] > 0)
3246 msk_rxput(sc->msk_if[MSK_PORT_A]);
3247 if (rxput[MSK_PORT_B] > 0)
3248 msk_rxput(sc->msk_if[MSK_PORT_B]);
3250 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3253 /* Legacy interrupt handler for shared interrupt. */
3255 mskc_intr(void *xsc)
3257 struct msk_softc *sc;
3258 struct msk_if_softc *sc_if0, *sc_if1;
3259 struct ifnet *ifp0, *ifp1;
3263 ASSERT_SERIALIZED(&sc->msk_serializer);
3265 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3266 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3267 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 ||
3268 (status & sc->msk_intrmask) == 0) {
3269 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3273 sc_if0 = sc->msk_if[MSK_PORT_A];
3274 sc_if1 = sc->msk_if[MSK_PORT_B];
3277 ifp0 = sc_if0->msk_ifp;
3279 ifp1 = sc_if1->msk_ifp;
3281 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3282 msk_intr_phy(sc_if0);
3283 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3284 msk_intr_phy(sc_if1);
3285 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3286 msk_intr_gmac(sc_if0);
3287 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3288 msk_intr_gmac(sc_if1);
3289 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3290 device_printf(sc->msk_dev, "Rx descriptor error\n");
3291 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3292 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3293 CSR_READ_4(sc, B0_IMSK);
3295 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3296 device_printf(sc->msk_dev, "Tx descriptor error\n");
3297 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3298 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3299 CSR_READ_4(sc, B0_IMSK);
3301 if ((status & Y2_IS_HW_ERR) != 0)
3302 mskc_intr_hwerr(sc);
3304 while (mskc_handle_events(sc) != 0)
3306 if ((status & Y2_IS_STAT_BMU) != 0)
3307 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3309 /* Reenable interrupts. */
3310 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3312 if (ifp0 != NULL && (ifp0->if_flags & IFF_RUNNING) != 0 &&
3313 !ifq_is_empty(&ifp0->if_snd))
3315 if (ifp1 != NULL && (ifp1->if_flags & IFF_RUNNING) != 0 &&
3316 !ifq_is_empty(&ifp1->if_snd))
3321 msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3323 struct msk_softc *sc = sc_if->msk_softc;
3324 struct ifnet *ifp = sc_if->msk_ifp;
3326 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3327 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3328 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3329 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3332 if (ifp->if_mtu > ETHERMTU) {
3333 /* Set Tx GMAC FIFO Almost Empty Threshold. */
3335 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3336 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3337 /* Disable Store & Forward mode for Tx. */
3338 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3341 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3350 struct msk_if_softc *sc_if = xsc;
3351 struct msk_softc *sc = sc_if->msk_softc;
3352 struct ifnet *ifp = sc_if->msk_ifp;
3353 struct mii_data *mii;
3354 uint16_t eaddr[ETHER_ADDR_LEN / 2];
3359 ASSERT_SERIALIZED(ifp->if_serializer);
3361 mii = device_get_softc(sc_if->msk_miibus);
3364 /* Cancel pending I/O and free all Rx/Tx buffers. */
3367 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
3368 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
3369 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
3371 * In Yukon EC Ultra, TSO & checksum offload is not
3372 * supported for jumbo frame.
3374 ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
3375 ifp->if_capenable &= ~IFCAP_TXCSUM;
3378 /* GMAC Control reset. */
3379 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3380 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3381 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3382 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
3383 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3384 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3389 * Initialize GMAC first such that speed/duplex/flow-control
3390 * parameters are renegotiated when interface is brought up.
3392 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3394 /* Dummy read the Interrupt Source Register. */
3395 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3397 /* Set MIB Clear Counter Mode. */
3398 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
3399 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
3400 /* Read all MIB Counters with Clear Mode set. */
3401 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
3402 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
3403 /* Clear MIB Clear Counter Mode. */
3404 gmac &= ~GM_PAR_MIB_CLR;
3405 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
3408 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3410 /* Setup Transmit Control Register. */
3411 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3413 /* Setup Transmit Flow Control Register. */
3414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3416 /* Setup Transmit Parameter Register. */
3417 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3418 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3419 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3421 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3422 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3424 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN)
3425 gmac |= GM_SMOD_JUMBO_ENA;
3426 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3428 /* Set station address. */
3429 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
3430 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3431 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4,
3433 for (i = 0; i < ETHER_ADDR_LEN /2; i++)
3434 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4,
3437 /* Disable interrupts for counter overflows. */
3438 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3439 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3440 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3442 /* Configure Rx MAC FIFO. */
3443 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3444 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3445 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3446 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3447 sc->msk_hw_id == CHIP_ID_YUKON_EX)
3448 reg |= GMF_RX_OVER_ON;
3449 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3451 /* Set receive filter. */
3452 msk_rxfilter(sc_if);
3454 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3455 /* Clear flush mask - HW bug. */
3456 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3458 /* Flush Rx MAC FIFO on any flow control or error. */
3459 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3464 * Set Rx FIFO flush threshold to 64 bytes 1 FIFO word
3465 * due to hardware hang on receipt of pause frames.
3467 reg = RX_GMF_FL_THR_DEF + 1;
3468 /* Another magic for Yukon FE+ - From Linux. */
3469 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3470 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3472 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3475 /* Configure Tx MAC FIFO. */
3476 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3477 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3478 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3480 /* Configure hardware VLAN tag insertion/stripping. */
3481 msk_setvlan(sc_if, ifp);
3483 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3484 /* Set Rx Pause threshould. */
3485 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3487 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3489 /* Configure store-and-forward for Tx. */
3490 msk_set_tx_stfwd(sc_if);
3493 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3494 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3495 /* Disable dynamic watermark - from Linux. */
3496 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3498 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3502 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3503 * arbiter as we don't use Sync Tx queue.
3505 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3506 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3507 /* Enable the RAM Interface Arbiter. */
3508 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3510 /* Setup RAM buffer. */
3511 msk_set_rambuffer(sc_if);
3513 /* Disable Tx sync Queue. */
3514 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3516 /* Setup Tx Queue Bus Memory Interface. */
3517 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3518 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3519 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3520 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3521 switch (sc->msk_hw_id) {
3522 case CHIP_ID_YUKON_EC_U:
3523 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3524 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3525 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3529 case CHIP_ID_YUKON_EX:
3531 * Yukon Extreme seems to have silicon bug for
3532 * automatic Tx checksum calculation capability.
3534 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) {
3535 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3541 /* Setup Rx Queue Bus Memory Interface. */
3542 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3543 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3544 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3545 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3546 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3547 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3548 /* MAC Rx RAM Read is controlled by hardware. */
3549 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3552 msk_set_prefetch(sc, sc_if->msk_txq,
3553 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3554 msk_init_tx_ring(sc_if);
3556 /* Disable Rx checksum offload and RSS hash. */
3557 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
3558 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
3560 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) {
3561 msk_set_prefetch(sc, sc_if->msk_rxq,
3562 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
3563 MSK_JUMBO_RX_RING_CNT - 1);
3564 error = msk_init_jumbo_rx_ring(sc_if);
3568 msk_set_prefetch(sc, sc_if->msk_rxq,
3569 sc_if->msk_rdata.msk_rx_ring_paddr,
3570 MSK_RX_RING_CNT - 1);
3571 error = msk_init_rx_ring(sc_if);
3574 device_printf(sc_if->msk_if_dev,
3575 "initialization failed: no memory for Rx buffers\n");
3579 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
3580 /* Disable flushing of non-ASF packets. */
3581 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3582 GMF_RX_MACSEC_FLUSH_OFF);
3585 /* Configure interrupt handling. */
3586 if (sc_if->msk_port == MSK_PORT_A) {
3587 sc->msk_intrmask |= Y2_IS_PORT_A;
3588 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
3590 sc->msk_intrmask |= Y2_IS_PORT_B;
3591 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
3593 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
3594 CSR_READ_4(sc, B0_HWE_IMSK);
3595 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3596 CSR_READ_4(sc, B0_IMSK);
3598 sc_if->msk_link = 0;
3601 mskc_set_imtimer(sc);
3603 ifp->if_flags |= IFF_RUNNING;
3604 ifp->if_flags &= ~IFF_OACTIVE;
3606 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3610 msk_set_rambuffer(struct msk_if_softc *sc_if)
3612 struct msk_softc *sc;
3615 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
3618 sc = sc_if->msk_softc;
3620 /* Setup Rx Queue. */
3621 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
3622 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
3623 sc->msk_rxqstart[sc_if->msk_port] / 8);
3624 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
3625 sc->msk_rxqend[sc_if->msk_port] / 8);
3626 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
3627 sc->msk_rxqstart[sc_if->msk_port] / 8);
3628 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
3629 sc->msk_rxqstart[sc_if->msk_port] / 8);
3631 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3632 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
3633 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
3634 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
3635 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
3636 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
3637 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
3638 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
3639 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
3641 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
3642 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
3644 /* Setup Tx Queue. */
3645 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
3646 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
3647 sc->msk_txqstart[sc_if->msk_port] / 8);
3648 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
3649 sc->msk_txqend[sc_if->msk_port] / 8);
3650 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
3651 sc->msk_txqstart[sc_if->msk_port] / 8);
3652 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
3653 sc->msk_txqstart[sc_if->msk_port] / 8);
3654 /* Enable Store & Forward for Tx side. */
3655 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
3656 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
3657 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
3661 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
3665 /* Reset the prefetch unit. */
3666 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3668 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3670 /* Set LE base address. */
3671 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
3673 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
3675 /* Set the list last index. */
3676 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
3678 /* Turn on prefetch unit. */
3679 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
3681 /* Dummy read to ensure write. */
3682 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
3686 msk_stop(struct msk_if_softc *sc_if)
3688 struct msk_softc *sc = sc_if->msk_softc;
3689 struct ifnet *ifp = sc_if->msk_ifp;
3690 struct msk_txdesc *txd;
3691 struct msk_rxdesc *rxd;
3693 struct msk_rxdesc *jrxd;
3698 ASSERT_SERIALIZED(ifp->if_serializer);
3700 callout_stop(&sc_if->msk_tick_ch);
3703 /* Disable interrupts. */
3704 if (sc_if->msk_port == MSK_PORT_A) {
3705 sc->msk_intrmask &= ~Y2_IS_PORT_A;
3706 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
3708 sc->msk_intrmask &= ~Y2_IS_PORT_B;
3709 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
3711 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
3712 CSR_READ_4(sc, B0_HWE_IMSK);
3713 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3714 CSR_READ_4(sc, B0_IMSK);
3716 /* Disable Tx/Rx MAC. */
3717 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3718 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
3719 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
3720 /* Read again to ensure writing. */
3721 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
3724 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
3725 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3726 for (i = 0; i < MSK_TIMEOUT; i++) {
3727 if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
3728 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3730 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
3735 if (i == MSK_TIMEOUT)
3736 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
3737 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
3738 RB_RST_SET | RB_DIS_OP_MD);
3740 /* Disable all GMAC interrupt. */
3741 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
3742 /* Disable PHY interrupt. */
3743 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
3745 /* Disable the RAM Interface Arbiter. */
3746 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
3748 /* Reset the PCI FIFO of the async Tx queue */
3749 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
3750 BMU_RST_SET | BMU_FIFO_RST);
3752 /* Reset the Tx prefetch units. */
3753 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
3756 /* Reset the RAM Buffer async Tx queue. */
3757 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
3759 /* Reset Tx MAC FIFO. */
3760 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3761 /* Set Pause Off. */
3762 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
3765 * The Rx Stop command will not work for Yukon-2 if the BMU does not
3766 * reach the end of packet and since we can't make sure that we have
3767 * incoming data, we must reset the BMU while it is not during a DMA
3768 * transfer. Since it is possible that the Rx path is still active,
3769 * the Rx RAM buffer will be stopped first, so any possible incoming
3770 * data will not trigger a DMA. After the RAM buffer is stopped, the
3771 * BMU is polled until any DMA in progress is ended and only then it
3775 /* Disable the RAM Buffer receive queue. */
3776 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
3777 for (i = 0; i < MSK_TIMEOUT; i++) {
3778 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
3779 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
3783 if (i == MSK_TIMEOUT)
3784 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
3785 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
3786 BMU_RST_SET | BMU_FIFO_RST);
3787 /* Reset the Rx prefetch unit. */
3788 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
3790 /* Reset the RAM Buffer receive queue. */
3791 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
3792 /* Reset Rx MAC FIFO. */
3793 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3795 /* Free Rx and Tx mbufs still in the queues. */
3796 for (i = 0; i < MSK_RX_RING_CNT; i++) {
3797 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
3798 if (rxd->rx_m != NULL) {
3799 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
3806 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
3807 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
3808 if (jrxd->rx_m != NULL) {
3809 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
3810 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3811 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
3813 m_freem(jrxd->rx_m);
3818 for (i = 0; i < MSK_TX_RING_CNT; i++) {
3819 txd = &sc_if->msk_cdata.msk_txdesc[i];
3820 if (txd->tx_m != NULL) {
3821 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
3829 * Mark the interface down.
3831 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3832 sc_if->msk_link = 0;
3836 mskc_sysctl_proc_limit(SYSCTL_HANDLER_ARGS)
3838 return sysctl_int_range(oidp, arg1, arg2, req,
3839 MSK_PROC_MIN, MSK_PROC_MAX);
3843 mskc_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3845 struct msk_softc *sc = arg1;
3846 struct lwkt_serialize *serializer = &sc->msk_serializer;
3849 lwkt_serialize_enter(serializer);
3851 v = sc->msk_intr_rate;
3852 error = sysctl_handle_int(oidp, &v, 0, req);
3853 if (error || req->newptr == NULL)
3860 if (sc->msk_intr_rate != v) {
3863 sc->msk_intr_rate = v;
3864 for (i = 0; i < 2; ++i) {
3865 if (sc->msk_if[i] != NULL) {
3866 flag |= sc->msk_if[i]->
3867 arpcom.ac_if.if_flags & IFF_RUNNING;
3871 mskc_set_imtimer(sc);
3874 lwkt_serialize_exit(serializer);
3879 msk_dmamem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag,
3880 void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap)
3882 struct msk_if_softc *sc_if = device_get_softc(dev);
3886 error = bus_dmamem_coherent(sc_if->msk_cdata.msk_parent_tag,
3888 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3889 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3891 device_printf(dev, "can't create coherent DMA memory\n");
3895 *dtag = dmem.dmem_tag;
3896 *dmap = dmem.dmem_map;
3897 *addr = dmem.dmem_addr;
3898 *paddr = dmem.dmem_busaddr;
3904 msk_dmamem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
3907 bus_dmamap_unload(dtag, dmap);
3908 bus_dmamem_free(dtag, addr, dmap);
3909 bus_dma_tag_destroy(dtag);
3914 mskc_set_imtimer(struct msk_softc *sc)
3916 if (sc->msk_intr_rate > 0) {
3918 * XXX myk(4) seems to use 125MHz for EC/FE/XL
3919 * and 78.125MHz for rest of chip types
3921 CSR_WRITE_4(sc, B2_IRQM_INI,
3922 MSK_USECS(sc, 1000000 / sc->msk_intr_rate));
3923 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
3924 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_START);
3926 CSR_WRITE_4(sc, B2_IRQM_CTRL, TIM_STOP);