sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.41 2005/06/21 15:27:55 joerg Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include <sys/param.h>
  76 #include <sys/systm.h>
  77 #include <sys/sockio.h>
  78 #include <sys/mbuf.h>
  79 #include <sys/malloc.h>
  80 #include <sys/kernel.h>
  81 #include <sys/socket.h>
  82 #include <sys/queue.h>
  83 #include <sys/thread2.h>
  84
  85 #include <net/if.h>
  86 #include <net/ifq_var.h>
  87 #include <net/if_arp.h>
  88 #include <net/ethernet.h>
  89 #include <net/if_dl.h>
  90 #include <net/if_media.h>
  91
  92 #include <net/bpf.h>
  93
  94 #include <net/if_types.h>
  95 #include <net/vlan/if_vlan_var.h>
  96
  97 #include <netinet/in_systm.h>
  98 #include <netinet/in.h>
  99 #include <netinet/ip.h>
 100
 101 #include <vm/vm.h>              /* for vtophys */
 102 #include <vm/pmap.h>            /* for vtophys */
 103 #include <machine/resource.h>
 104 #include <sys/bus.h>
 105 #include <sys/rman.h>
 106
 107 #include <dev/netif/mii_layer/mii.h>
 108 #include <dev/netif/mii_layer/miivar.h>
 109 #include <dev/netif/mii_layer/miidevs.h>
 110 #include <dev/netif/mii_layer/brgphyreg.h>
 111
 112 #include <bus/pci/pcidevs.h>
 113 #include <bus/pci/pcireg.h>
 114 #include <bus/pci/pcivar.h>
 115
 116 #include "if_bgereg.h"
 117
 118 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 119
 120 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 121 #include "miibus_if.h"
 122
 123 /*
 124  * Various supported device vendors/types and their names. Note: the
 125  * spec seems to indicate that the hardware still has Alteon's vendor
 126  * ID burned into it, though it will always be overriden by the vendor
 127  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 128  */
 129 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 130
 131 static struct bge_type bge_devs[] = {
 132         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 133                 "Broadcom BCM5700 Gigabit Ethernet" },
 134         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 135                 "Broadcom BCM5701 Gigabit Ethernet" },
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 141                 "Broadcom BCM5702X Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 145                 "Broadcom BCM5703X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5703X,
 147                 "Broadcom BCM5703X Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 149                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 151                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 153                 "Broadcom BCM5705 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 155                 "Broadcom BCM5705M Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705_ALT,
 157                 "Broadcom BCM5705M Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 159                 "Broadcom BCM5751 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 161                 "Broadcom BCM5782 Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5788,
 163                 "Broadcom BCM5788 Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 165                 "Broadcom BCM5901 Fast Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 167                 "Broadcom BCM5901A2 Fast Ethernet" },
 168         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 169                 "SysKonnect Gigabit Ethernet" },
 170         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 171                 "Altima AC1000 Gigabit Ethernet" },
 172         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 173                 "Altima AC1002 Gigabit Ethernet" },
 174         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 175                 "Altima AC9100 Gigabit Ethernet" },
 176         { 0, 0, NULL }
 177 };
 178
 179 static int      bge_probe(device_t);
 180 static int      bge_attach(device_t);
 181 static int      bge_detach(device_t);
 182 static void     bge_release_resources(struct bge_softc *);
 183 static void     bge_txeof(struct bge_softc *);
 184 static void     bge_rxeof(struct bge_softc *);
 185
 186 static void     bge_tick(void *);
 187 static void     bge_stats_update(struct bge_softc *);
 188 static void     bge_stats_update_regs(struct bge_softc *);
 189 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 190
 191 static void     bge_intr(void *);
 192 static void     bge_start(struct ifnet *);
 193 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 194 static void     bge_init(void *);
 195 static void     bge_stop(struct bge_softc *);
 196 static void     bge_watchdog(struct ifnet *);
 197 static void     bge_shutdown(device_t);
 198 static int      bge_ifmedia_upd(struct ifnet *);
 199 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 200
 201 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 202 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 203
 204 static void     bge_setmulti(struct bge_softc *);
 205
 206 static void     bge_handle_events(struct bge_softc *);
 207 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 208 static void     bge_free_jumbo_mem(struct bge_softc *);
 209 static struct bge_jslot
 210                 *bge_jalloc(struct bge_softc *);
 211 static void     bge_jfree(void *);
 212 static void     bge_jref(void *);
 213 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 214 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 215 static int      bge_init_rx_ring_std(struct bge_softc *);
 216 static void     bge_free_rx_ring_std(struct bge_softc *);
 217 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 218 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 219 static void     bge_free_tx_ring(struct bge_softc *);
 220 static int      bge_init_tx_ring(struct bge_softc *);
 221
 222 static int      bge_chipinit(struct bge_softc *);
 223 static int      bge_blockinit(struct bge_softc *);
 224
 225 #ifdef notdef
 226 static uint8_t  bge_vpd_readbyte(struct bge_softc *, uint32_t);
 227 static void     bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
 228 static void     bge_vpd_read(struct bge_softc *);
 229 #endif
 230
 231 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 232 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 233 #ifdef notdef
 234 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 235 #endif
 236 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 237
 238 static int      bge_miibus_readreg(device_t, int, int);
 239 static int      bge_miibus_writereg(device_t, int, int, int);
 240 static void     bge_miibus_statchg(device_t);
 241
 242 static void     bge_reset(struct bge_softc *);
 243
 244 static device_method_t bge_methods[] = {
 245         /* Device interface */
 246         DEVMETHOD(device_probe,         bge_probe),
 247         DEVMETHOD(device_attach,        bge_attach),
 248         DEVMETHOD(device_detach,        bge_detach),
 249         DEVMETHOD(device_shutdown,      bge_shutdown),
 250
 251         /* bus interface */
 252         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 253         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 254
 255         /* MII interface */
 256         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 257         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 258         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 259
 260         { 0, 0 }
 261 };
 262
 263 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 264 static devclass_t bge_devclass;
 265
 266 DECLARE_DUMMY_MODULE(if_bge);
 267 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 268 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 269
 270 static uint32_t
 271 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 272 {
 273         device_t dev = sc->bge_dev;
 274
 275         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 276         return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 277 }
 278
 279 static void
 280 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 281 {
 282         device_t dev = sc->bge_dev;
 283
 284         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 285         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 286 }
 287
 288 #ifdef notdef
 289 static uint32_t
 290 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 291 {
 292         device_t dev = sc->bge_dev;
 293
 294         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 295         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 296 }
 297 #endif
 298
 299 static void
 300 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 301 {
 302         device_t dev = sc->bge_dev;
 303
 304         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 305         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 306 }
 307
 308 #ifdef notdef
 309 static uint8_t
 310 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
 311 {
 312         device_t dev = sc->bge_dev;
 313         uint32_t val;
 314         int i;
 315
 316         pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 317         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 318                 DELAY(10);
 319                 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 320                         break;
 321         }
 322
 323         if (i == BGE_TIMEOUT) {
 324                 device_printf(sc->bge_dev, "VPD read timed out\n");
 325                 return(0);
 326         }
 327
 328         val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 329
 330         return((val >> ((addr % 4) * 8)) & 0xFF);
 331 }
 332
 333 static void
 334 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
 335 {
 336         size_t i;
 337         uint8_t *ptr;
 338
 339         ptr = (uint8_t *)res;
 340         for (i = 0; i < sizeof(struct vpd_res); i++)
 341                 ptr[i] = bge_vpd_readbyte(sc, i + addr);
 342
 343         return;
 344 }
 345
 346 static void
 347 bge_vpd_read(struct bge_softc *sc)
 348 {
 349         int pos = 0, i;
 350         struct vpd_res res;
 351
 352         if (sc->bge_vpd_prodname != NULL)
 353                 free(sc->bge_vpd_prodname, M_DEVBUF);
 354         if (sc->bge_vpd_readonly != NULL)
 355                 free(sc->bge_vpd_readonly, M_DEVBUF);
 356         sc->bge_vpd_prodname = NULL;
 357         sc->bge_vpd_readonly = NULL;
 358
 359         bge_vpd_read_res(sc, &res, pos);
 360
 361         if (res.vr_id != VPD_RES_ID) {
 362                 device_printf(sc->bge_dev,
 363                               "bad VPD resource id: expected %x got %x\n",
 364                               VPD_RES_ID, res.vr_id);
 365                 return;
 366         }
 367
 368         pos += sizeof(res);
 369         sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 370         for (i = 0; i < res.vr_len; i++)
 371                 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 372         sc->bge_vpd_prodname[i] = '\0';
 373         pos += i;
 374
 375         bge_vpd_read_res(sc, &res, pos);
 376
 377         if (res.vr_id != VPD_RES_READ) {
 378                 device_printf(sc->bge_dev,
 379                               "bad VPD resource id: expected %x got %x\n",
 380                               VPD_RES_READ, res.vr_id);
 381                 return;
 382         }
 383
 384         pos += sizeof(res);
 385         sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 386         for (i = 0; i < res.vr_len + 1; i++)
 387                 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 388 }
 389 #endif
 390
 391 /*
 392  * Read a byte of data stored in the EEPROM at address 'addr.' The
 393  * BCM570x supports both the traditional bitbang interface and an
 394  * auto access interface for reading the EEPROM. We use the auto
 395  * access method.
 396  */
 397 static uint8_t
 398 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 399 {
 400         int i;
 401         uint32_t byte = 0;
 402
 403         /*
 404          * Enable use of auto EEPROM access so we can avoid
 405          * having to use the bitbang method.
 406          */
 407         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 408
 409         /* Reset the EEPROM, load the clock period. */
 410         CSR_WRITE_4(sc, BGE_EE_ADDR,
 411             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 412         DELAY(20);
 413
 414         /* Issue the read EEPROM command. */
 415         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 416
 417         /* Wait for completion */
 418         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 419                 DELAY(10);
 420                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 421                         break;
 422         }
 423
 424         if (i == BGE_TIMEOUT) {
 425                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 426                 return(0);
 427         }
 428
 429         /* Get result. */
 430         byte = CSR_READ_4(sc, BGE_EE_DATA);
 431
 432         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 433
 434         return(0);
 435 }
 436
 437 /*
 438  * Read a sequence of bytes from the EEPROM.
 439  */
 440 static int
 441 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 442 {
 443         size_t i;
 444         int err;
 445         uint8_t byte;
 446
 447         for (byte = 0, err = 0, i = 0; i < len; i++) {
 448                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 449                 if (err)
 450                         break;
 451                 *(dest + i) = byte;
 452         }
 453
 454         return(err ? 1 : 0);
 455 }
 456
 457 static int
 458 bge_miibus_readreg(device_t dev, int phy, int reg)
 459 {
 460         struct bge_softc *sc;
 461         struct ifnet *ifp;
 462         uint32_t val, autopoll;
 463         int i;
 464
 465         sc = device_get_softc(dev);
 466         ifp = &sc->arpcom.ac_if;
 467
 468         /*
 469          * Broadcom's own driver always assumes the internal
 470          * PHY is at GMII address 1. On some chips, the PHY responds
 471          * to accesses at all addresses, which could cause us to
 472          * bogusly attach the PHY 32 times at probe type. Always
 473          * restricting the lookup to address 1 is simpler than
 474          * trying to figure out which chips revisions should be
 475          * special-cased.
 476          */
 477         if (phy != 1)
 478                 return(0);
 479
 480         /* Reading with autopolling on may trigger PCI errors */
 481         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 482         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 483                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 484                 DELAY(40);
 485         }
 486
 487         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 488             BGE_MIPHY(phy)|BGE_MIREG(reg));
 489
 490         for (i = 0; i < BGE_TIMEOUT; i++) {
 491                 val = CSR_READ_4(sc, BGE_MI_COMM);
 492                 if (!(val & BGE_MICOMM_BUSY))
 493                         break;
 494         }
 495
 496         if (i == BGE_TIMEOUT) {
 497                 if_printf(ifp, "PHY read timed out\n");
 498                 val = 0;
 499                 goto done;
 500         }
 501
 502         val = CSR_READ_4(sc, BGE_MI_COMM);
 503
 504 done:
 505         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 506                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 507                 DELAY(40);
 508         }
 509
 510         if (val & BGE_MICOMM_READFAIL)
 511                 return(0);
 512
 513         return(val & 0xFFFF);
 514 }
 515
 516 static int
 517 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 518 {
 519         struct bge_softc *sc;
 520         uint32_t autopoll;
 521         int i;
 522
 523         sc = device_get_softc(dev);
 524
 525         /* Reading with autopolling on may trigger PCI errors */
 526         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 527         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 528                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 529                 DELAY(40);
 530         }
 531
 532         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 533             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 534
 535         for (i = 0; i < BGE_TIMEOUT; i++) {
 536                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 537                         break;
 538         }
 539
 540         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 541                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 542                 DELAY(40);
 543         }
 544
 545         if (i == BGE_TIMEOUT) {
 546                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 547                 return(0);
 548         }
 549
 550         return(0);
 551 }
 552
 553 static void
 554 bge_miibus_statchg(device_t dev)
 555 {
 556         struct bge_softc *sc;
 557         struct mii_data *mii;
 558
 559         sc = device_get_softc(dev);
 560         mii = device_get_softc(sc->bge_miibus);
 561
 562         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 563         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 564                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 565         } else {
 566                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 567         }
 568
 569         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 570                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 571         } else {
 572                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 573         }
 574 }
 575
 576 /*
 577  * Handle events that have triggered interrupts.
 578  */
 579 static void
 580 bge_handle_events(struct bge_softc *sc)
 581 {
 582 }
 583
 584 /*
 585  * Memory management for jumbo frames.
 586  */
 587 static int
 588 bge_alloc_jumbo_mem(struct bge_softc *sc)
 589 {
 590         struct bge_jslot *entry;
 591         caddr_t ptr;
 592         int i;
 593
 594         /* Grab a big chunk o' storage. */
 595         sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 596                 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
 597
 598         if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 599                 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
 600                 return(ENOBUFS);
 601         }
 602
 603         SLIST_INIT(&sc->bge_jfree_listhead);
 604
 605         /*
 606          * Now divide it up into 9K pieces and save the addresses
 607          * in an array. Note that we play an evil trick here by using
 608          * the first few bytes in the buffer to hold the the address
 609          * of the softc structure for this interface. This is because
 610          * bge_jfree() needs it, but it is called by the mbuf management
 611          * code which will not pass it to us explicitly.
 612          */
 613         ptr = sc->bge_cdata.bge_jumbo_buf;
 614         for (i = 0; i < BGE_JSLOTS; i++) {
 615                 entry = &sc->bge_cdata.bge_jslots[i];
 616                 entry->bge_sc = sc;
 617                 entry->bge_buf = ptr;
 618                 entry->bge_inuse = 0;
 619                 entry->bge_slot = i;
 620                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 621                 ptr += BGE_JLEN;
 622         }
 623
 624         return(0);
 625 }
 626
 627 static void
 628 bge_free_jumbo_mem(struct bge_softc *sc)
 629 {
 630         if (sc->bge_cdata.bge_jumbo_buf)
 631                 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 632 }
 633
 634 /*
 635  * Allocate a jumbo buffer.
 636  */
 637 static struct bge_jslot *
 638 bge_jalloc(struct bge_softc *sc)
 639 {
 640         struct bge_jslot *entry;
 641
 642         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 643
 644         if (entry == NULL) {
 645                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 646                 return(NULL);
 647         }
 648
 649         SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 650         entry->bge_inuse = 1;
 651         return(entry);
 652 }
 653
 654 /*
 655  * Adjust usage count on a jumbo buffer.
 656  */
 657 static void
 658 bge_jref(void *arg)
 659 {
 660         struct bge_jslot *entry = (struct bge_jslot *)arg;
 661         struct bge_softc *sc = entry->bge_sc;
 662
 663         if (sc == NULL)
 664                 panic("bge_jref: can't find softc pointer!");
 665
 666         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 667                 panic("bge_jref: asked to reference buffer "
 668                     "that we don't manage!");
 669         else if (entry->bge_inuse == 0)
 670                 panic("bge_jref: buffer already free!");
 671         else
 672                 entry->bge_inuse++;
 673 }
 674
 675 /*
 676  * Release a jumbo buffer.
 677  */
 678 static void
 679 bge_jfree(void *arg)
 680 {
 681         struct bge_jslot *entry = (struct bge_jslot *)arg;
 682         struct bge_softc *sc = entry->bge_sc;
 683
 684         if (sc == NULL)
 685                 panic("bge_jfree: can't find softc pointer!");
 686
 687         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry)
 688                 panic("bge_jfree: asked to free buffer that we don't manage!");
 689         else if (entry->bge_inuse == 0)
 690                 panic("bge_jfree: buffer already free!");
 691         else if (--entry->bge_inuse == 0)
 692                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 693 }
 694
 695
 696 /*
 697  * Intialize a standard receive ring descriptor.
 698  */
 699 static int
 700 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 701 {
 702         struct mbuf *m_new = NULL;
 703         struct bge_rx_bd *r;
 704
 705         if (m == NULL) {
 706                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 707                 if (m_new == NULL)
 708                         return (ENOBUFS);
 709                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 710         } else {
 711                 m_new = m;
 712                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 713                 m_new->m_data = m_new->m_ext.ext_buf;
 714         }
 715
 716         if (!sc->bge_rx_alignment_bug)
 717                 m_adj(m_new, ETHER_ALIGN);
 718         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 719         r = &sc->bge_rdata->bge_rx_std_ring[i];
 720         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 721         r->bge_flags = BGE_RXBDFLAG_END;
 722         r->bge_len = m_new->m_len;
 723         r->bge_idx = i;
 724
 725         return(0);
 726 }
 727
 728 /*
 729  * Initialize a jumbo receive ring descriptor. This allocates
 730  * a jumbo buffer from the pool managed internally by the driver.
 731  */
 732 static int
 733 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 734 {
 735         struct mbuf *m_new = NULL;
 736         struct bge_rx_bd *r;
 737
 738         if (m == NULL) {
 739                 struct bge_jslot *buf;
 740
 741                 /* Allocate the mbuf. */
 742                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 743                 if (m_new == NULL)
 744                         return(ENOBUFS);
 745
 746                 /* Allocate the jumbo buffer */
 747                 buf = bge_jalloc(sc);
 748                 if (buf == NULL) {
 749                         m_freem(m_new);
 750                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 751                             "-- packet dropped!\n");
 752                         return(ENOBUFS);
 753                 }
 754
 755                 /* Attach the buffer to the mbuf. */
 756                 m_new->m_ext.ext_arg = buf;
 757                 m_new->m_ext.ext_buf = buf->bge_buf;
 758                 m_new->m_ext.ext_free = bge_jfree;
 759                 m_new->m_ext.ext_ref = bge_jref;
 760                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 761
 762                 m_new->m_data = m_new->m_ext.ext_buf;
 763                 m_new->m_flags |= M_EXT;
 764                 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 765         } else {
 766                 m_new = m;
 767                 m_new->m_data = m_new->m_ext.ext_buf;
 768                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 769         }
 770
 771         if (!sc->bge_rx_alignment_bug)
 772                 m_adj(m_new, ETHER_ALIGN);
 773         /* Set up the descriptor. */
 774         r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 775         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 776         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 777         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 778         r->bge_len = m_new->m_len;
 779         r->bge_idx = i;
 780
 781         return(0);
 782 }
 783
 784 /*
 785  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 786  * that's 1MB or memory, which is a lot. For now, we fill only the first
 787  * 256 ring entries and hope that our CPU is fast enough to keep up with
 788  * the NIC.
 789  */
 790 static int
 791 bge_init_rx_ring_std(struct bge_softc *sc)
 792 {
 793         int i;
 794
 795         for (i = 0; i < BGE_SSLOTS; i++) {
 796                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 797                         return(ENOBUFS);
 798         };
 799
 800         sc->bge_std = i - 1;
 801         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 802
 803         return(0);
 804 }
 805
 806 static void
 807 bge_free_rx_ring_std(struct bge_softc *sc)
 808 {
 809         int i;
 810
 811         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 812                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 813                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 814                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 815                 }
 816                 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
 817                     sizeof(struct bge_rx_bd));
 818         }
 819 }
 820
 821 static int
 822 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 823 {
 824         int i;
 825         struct bge_rcb *rcb;
 826
 827         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 828                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 829                         return(ENOBUFS);
 830         };
 831
 832         sc->bge_jumbo = i - 1;
 833
 834         rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 835         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 836         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 837
 838         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 839
 840         return(0);
 841 }
 842
 843 static void
 844 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 845 {
 846         int i;
 847
 848         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 849                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 850                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 851                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 852                 }
 853                 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
 854                     sizeof(struct bge_rx_bd));
 855         }
 856 }
 857
 858 static void
 859 bge_free_tx_ring(struct bge_softc *sc)
 860 {
 861         int i;
 862
 863         if (sc->bge_rdata->bge_tx_ring == NULL)
 864                 return;
 865
 866         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 867                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 868                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 869                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 870                 }
 871                 bzero(&sc->bge_rdata->bge_tx_ring[i],
 872                     sizeof(struct bge_tx_bd));
 873         }
 874 }
 875
 876 static int
 877 bge_init_tx_ring(struct bge_softc *sc)
 878 {
 879         sc->bge_txcnt = 0;
 880         sc->bge_tx_saved_considx = 0;
 881
 882         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 883         /* 5700 b2 errata */
 884         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 885                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 886
 887         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 888         /* 5700 b2 errata */
 889         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 890                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 891
 892         return(0);
 893 }
 894
 895 static void
 896 bge_setmulti(struct bge_softc *sc)
 897 {
 898         struct ifnet *ifp;
 899         struct ifmultiaddr *ifma;
 900         uint32_t hashes[4] = { 0, 0, 0, 0 };
 901         int h, i;
 902
 903         ifp = &sc->arpcom.ac_if;
 904
 905         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 906                 for (i = 0; i < 4; i++)
 907                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 908                 return;
 909         }
 910
 911         /* First, zot all the existing filters. */
 912         for (i = 0; i < 4; i++)
 913                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 914
 915         /* Now program new ones. */
 916         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 917                 if (ifma->ifma_addr->sa_family != AF_LINK)
 918                         continue;
 919                 h = ether_crc32_le(
 920                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 921                     ETHER_ADDR_LEN) & 0x7f;
 922                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 923         }
 924
 925         for (i = 0; i < 4; i++)
 926                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 927 }
 928
 929 /*
 930  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 931  * self-test results.
 932  */
 933 static int
 934 bge_chipinit(struct bge_softc *sc)
 935 {
 936         int i;
 937         uint32_t dma_rw_ctl;
 938
 939         /* Set endianness before we access any non-PCI registers. */
 940 #if BYTE_ORDER == BIG_ENDIAN
 941         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 942             BGE_BIGENDIAN_INIT, 4);
 943 #else
 944         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 945             BGE_LITTLEENDIAN_INIT, 4);
 946 #endif
 947
 948         /*
 949          * Check the 'ROM failed' bit on the RX CPU to see if
 950          * self-tests passed.
 951          */
 952         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 953                 if_printf(&sc->arpcom.ac_if,
 954                           "RX CPU self-diagnostics failed!\n");
 955                 return(ENODEV);
 956         }
 957
 958         /* Clear the MAC control register */
 959         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 960
 961         /*
 962          * Clear the MAC statistics block in the NIC's
 963          * internal memory.
 964          */
 965         for (i = BGE_STATS_BLOCK;
 966             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 967                 BGE_MEMWIN_WRITE(sc, i, 0);
 968
 969         for (i = BGE_STATUS_BLOCK;
 970             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 971                 BGE_MEMWIN_WRITE(sc, i, 0);
 972
 973         /* Set up the PCI DMA control register. */
 974         if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
 975             BGE_PCISTATE_PCI_BUSMODE) {
 976                 /* Conventional PCI bus */
 977                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 978                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 979                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 980                     (0x0F);
 981         } else {
 982                 /* PCI-X bus */
 983                 /*
 984                  * The 5704 uses a different encoding of read/write
 985                  * watermarks.
 986                  */
 987                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 988                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 989                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 990                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 991                 else
 992                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 993                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 994                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 995                             (0x0F);
 996
 997                 /*
 998                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 999                  * for hardware bugs.
1000                  */
1001                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1002                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1003                         uint32_t tmp;
1004
1005                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1006                         if (tmp == 0x6 || tmp == 0x7)
1007                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1008                 }
1009         }
1010
1011         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1012             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1013             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1014                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1015         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1016
1017         /*
1018          * Set up general mode register.
1019          */
1020         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1021             BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1022             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1023             BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1024
1025         /*
1026          * Disable memory write invalidate.  Apparently it is not supported
1027          * properly by these devices.
1028          */
1029         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1030
1031         /* Set the timer prescaler (always 66Mhz) */
1032         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1033
1034         return(0);
1035 }
1036
1037 static int
1038 bge_blockinit(struct bge_softc *sc)
1039 {
1040         struct bge_rcb *rcb;
1041         volatile struct bge_rcb *vrcb;
1042         int i;
1043
1044         /*
1045          * Initialize the memory window pointer register so that
1046          * we can access the first 32K of internal NIC RAM. This will
1047          * allow us to set up the TX send ring RCBs and the RX return
1048          * ring RCBs, plus other things which live in NIC memory.
1049          */
1050         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1051
1052         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1053
1054         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1055                 /* Configure mbuf memory pool */
1056                 if (sc->bge_extram) {
1057                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1058                             BGE_EXT_SSRAM);
1059                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1060                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1061                         else
1062                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1063                 } else {
1064                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1065                             BGE_BUFFPOOL_1);
1066                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1067                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1068                         else
1069                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1070                 }
1071
1072                 /* Configure DMA resource pool */
1073                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1074                     BGE_DMA_DESCRIPTORS);
1075                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1076         }
1077
1078         /* Configure mbuf pool watermarks */
1079         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
1080                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1081                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1082         } else {
1083                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1084                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1085         }
1086         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1087
1088         /* Configure DMA resource watermarks */
1089         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1090         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1091
1092         /* Enable buffer manager */
1093         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1094                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1095                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1096
1097                 /* Poll for buffer manager start indication */
1098                 for (i = 0; i < BGE_TIMEOUT; i++) {
1099                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1100                                 break;
1101                         DELAY(10);
1102                 }
1103
1104                 if (i == BGE_TIMEOUT) {
1105                         if_printf(&sc->arpcom.ac_if,
1106                                   "buffer manager failed to start\n");
1107                         return(ENXIO);
1108                 }
1109         }
1110
1111         /* Enable flow-through queues */
1112         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1113         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1114
1115         /* Wait until queue initialization is complete */
1116         for (i = 0; i < BGE_TIMEOUT; i++) {
1117                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1118                         break;
1119                 DELAY(10);
1120         }
1121
1122         if (i == BGE_TIMEOUT) {
1123                 if_printf(&sc->arpcom.ac_if,
1124                           "flow-through queue init failed\n");
1125                 return(ENXIO);
1126         }
1127
1128         /* Initialize the standard RX ring control block */
1129         rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1130         BGE_HOSTADDR(rcb->bge_hostaddr,
1131             vtophys(&sc->bge_rdata->bge_rx_std_ring));
1132         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1133                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1134         else
1135                 rcb->bge_maxlen_flags =
1136                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1137         if (sc->bge_extram)
1138                 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1139         else
1140                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1141         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1142         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1143         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1144         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1145
1146         /*
1147          * Initialize the jumbo RX ring control block
1148          * We set the 'ring disabled' bit in the flags
1149          * field until we're actually ready to start
1150          * using this ring (i.e. once we set the MTU
1151          * high enough to require it).
1152          */
1153         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1154                 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1155                 BGE_HOSTADDR(rcb->bge_hostaddr,
1156                     vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1157                 rcb->bge_maxlen_flags =
1158                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1159                     BGE_RCB_FLAG_RING_DISABLED);
1160                 if (sc->bge_extram)
1161                         rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1162                 else
1163                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1164                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1165                     rcb->bge_hostaddr.bge_addr_hi);
1166                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1167                     rcb->bge_hostaddr.bge_addr_lo);
1168                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1169                     rcb->bge_maxlen_flags);
1170                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1171
1172                 /* Set up dummy disabled mini ring RCB */
1173                 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1174                 rcb->bge_maxlen_flags =
1175                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1176                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1177                     rcb->bge_maxlen_flags);
1178         }
1179
1180         /*
1181          * Set the BD ring replentish thresholds. The recommended
1182          * values are 1/8th the number of descriptors allocated to
1183          * each ring.
1184          */
1185         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1186         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1187
1188         /*
1189          * Disable all unused send rings by setting the 'ring disabled'
1190          * bit in the flags field of all the TX send ring control blocks.
1191          * These are located in NIC memory.
1192          */
1193         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1194             BGE_SEND_RING_RCB);
1195         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1196                 vrcb->bge_maxlen_flags =
1197                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1198                 vrcb->bge_nicaddr = 0;
1199                 vrcb++;
1200         }
1201
1202         /* Configure TX RCB 0 (we use only the first ring) */
1203         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1204             BGE_SEND_RING_RCB);
1205         vrcb->bge_hostaddr.bge_addr_hi = 0;
1206         BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1207         vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1208         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1209                 vrcb->bge_maxlen_flags =
1210                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1211
1212         /* Disable all unused RX return rings */
1213         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1214             BGE_RX_RETURN_RING_RCB);
1215         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1216                 vrcb->bge_hostaddr.bge_addr_hi = 0;
1217                 vrcb->bge_hostaddr.bge_addr_lo = 0;
1218                 vrcb->bge_maxlen_flags =
1219                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1220                     BGE_RCB_FLAG_RING_DISABLED);
1221                 vrcb->bge_nicaddr = 0;
1222                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1223                     (i * (sizeof(uint64_t))), 0);
1224                 vrcb++;
1225         }
1226
1227         /* Initialize RX ring indexes */
1228         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1229         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1230         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1231
1232         /*
1233          * Set up RX return ring 0
1234          * Note that the NIC address for RX return rings is 0x00000000.
1235          * The return rings live entirely within the host, so the
1236          * nicaddr field in the RCB isn't used.
1237          */
1238         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1239             BGE_RX_RETURN_RING_RCB);
1240         vrcb->bge_hostaddr.bge_addr_hi = 0;
1241         BGE_HOSTADDR(vrcb->bge_hostaddr,
1242             vtophys(&sc->bge_rdata->bge_rx_return_ring));
1243         vrcb->bge_nicaddr = 0x00000000;
1244         vrcb->bge_maxlen_flags =
1245             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1246
1247         /* Set random backoff seed for TX */
1248         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1249             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1250             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1251             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1252             BGE_TX_BACKOFF_SEED_MASK);
1253
1254         /* Set inter-packet gap */
1255         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1256
1257         /*
1258          * Specify which ring to use for packets that don't match
1259          * any RX rules.
1260          */
1261         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1262
1263         /*
1264          * Configure number of RX lists. One interrupt distribution
1265          * list, sixteen active lists, one bad frames class.
1266          */
1267         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1268
1269         /* Inialize RX list placement stats mask. */
1270         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1271         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1272
1273         /* Disable host coalescing until we get it set up */
1274         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1275
1276         /* Poll to make sure it's shut down. */
1277         for (i = 0; i < BGE_TIMEOUT; i++) {
1278                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1279                         break;
1280                 DELAY(10);
1281         }
1282
1283         if (i == BGE_TIMEOUT) {
1284                 if_printf(&sc->arpcom.ac_if,
1285                           "host coalescing engine failed to idle\n");
1286                 return(ENXIO);
1287         }
1288
1289         /* Set up host coalescing defaults */
1290         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1291         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1292         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1293         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1294         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1295                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1296                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1297         }
1298         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1299         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1300
1301         /* Set up address of statistics block */
1302         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1303                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1304                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1305                     vtophys(&sc->bge_rdata->bge_info.bge_stats));
1306
1307                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1308                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1309                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1310         }
1311
1312         /* Set up address of status block */
1313         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1314         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1315             vtophys(&sc->bge_rdata->bge_status_block));
1316
1317         sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1318         sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1319
1320         /* Turn on host coalescing state machine */
1321         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1322
1323         /* Turn on RX BD completion state machine and enable attentions */
1324         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1325             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1326
1327         /* Turn on RX list placement state machine */
1328         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1329
1330         /* Turn on RX list selector state machine. */
1331         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1332                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1333
1334         /* Turn on DMA, clear stats */
1335         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1336             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1337             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1338             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1339             (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1340
1341         /* Set misc. local control, enable interrupts on attentions */
1342         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1343
1344 #ifdef notdef
1345         /* Assert GPIO pins for PHY reset */
1346         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1347             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1348         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1349             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1350 #endif
1351
1352         /* Turn on DMA completion state machine */
1353         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1354                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1355
1356         /* Turn on write DMA state machine */
1357         CSR_WRITE_4(sc, BGE_WDMA_MODE,
1358             BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1359
1360         /* Turn on read DMA state machine */
1361         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1362             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1363
1364         /* Turn on RX data completion state machine */
1365         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1366
1367         /* Turn on RX BD initiator state machine */
1368         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1369
1370         /* Turn on RX data and RX BD initiator state machine */
1371         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1372
1373         /* Turn on Mbuf cluster free state machine */
1374         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1375                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1376
1377         /* Turn on send BD completion state machine */
1378         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1379
1380         /* Turn on send data completion state machine */
1381         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1382
1383         /* Turn on send data initiator state machine */
1384         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1385
1386         /* Turn on send BD initiator state machine */
1387         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1388
1389         /* Turn on send BD selector state machine */
1390         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1391
1392         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1393         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1394             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1395
1396         /* ack/clear link change events */
1397         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1398             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1399             BGE_MACSTAT_LINK_CHANGED);
1400
1401         /* Enable PHY auto polling (for MII/GMII only) */
1402         if (sc->bge_tbi) {
1403                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1404         } else {
1405                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1406                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1407                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1408                             BGE_EVTENB_MI_INTERRUPT);
1409         }
1410
1411         /* Enable link state change attentions. */
1412         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1413
1414         return(0);
1415 }
1416
1417 /*
1418  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1419  * against our list and return its name if we find a match. Note
1420  * that since the Broadcom controller contains VPD support, we
1421  * can get the device name string from the controller itself instead
1422  * of the compiled-in string. This is a little slow, but it guarantees
1423  * we'll always announce the right product name.
1424  */
1425 static int
1426 bge_probe(device_t dev)
1427 {
1428         struct bge_softc *sc;
1429         struct bge_type *t;
1430         char *descbuf;
1431         uint16_t product, vendor;
1432
1433         product = pci_get_device(dev);
1434         vendor = pci_get_vendor(dev);
1435
1436         for (t = bge_devs; t->bge_name != NULL; t++) {
1437                 if (vendor == t->bge_vid && product == t->bge_did)
1438                         break;
1439         }
1440
1441         if (t->bge_name == NULL)
1442                 return(ENXIO);
1443
1444         sc = device_get_softc(dev);
1445 #ifdef notdef
1446         sc->bge_dev = dev;
1447
1448         bge_vpd_read(sc);
1449         device_set_desc(dev, sc->bge_vpd_prodname);
1450 #endif
1451         descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1452         snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1453             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1454         device_set_desc_copy(dev, descbuf);
1455         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1456                 sc->bge_no_3_led = 1;
1457         free(descbuf, M_TEMP);
1458         return(0);
1459 }
1460
1461 static int
1462 bge_attach(device_t dev)
1463 {
1464         struct ifnet *ifp;
1465         struct bge_softc *sc;
1466         uint32_t hwcfg = 0;
1467         uint32_t mac_addr = 0;
1468         int error = 0, rid;
1469         uint8_t ether_addr[ETHER_ADDR_LEN];
1470
1471         sc = device_get_softc(dev);
1472         sc->bge_dev = dev;
1473         callout_init(&sc->bge_stat_timer);
1474
1475         /*
1476          * Map control/status registers.
1477          */
1478         pci_enable_busmaster(dev);
1479
1480         rid = BGE_PCI_BAR0;
1481         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1482             RF_ACTIVE);
1483
1484         if (sc->bge_res == NULL) {
1485                 device_printf(dev, "couldn't map memory\n");
1486                 error = ENXIO;
1487                 return(error);
1488         }
1489
1490         sc->bge_btag = rman_get_bustag(sc->bge_res);
1491         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1492         sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1493
1494         /* Allocate interrupt */
1495         rid = 0;
1496
1497         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1498             RF_SHAREABLE | RF_ACTIVE);
1499
1500         if (sc->bge_irq == NULL) {
1501                 device_printf(dev, "couldn't map interrupt\n");
1502                 error = ENXIO;
1503                 goto fail;
1504         }
1505
1506         ifp = &sc->arpcom.ac_if;
1507         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1508
1509         /* Try to reset the chip. */
1510         bge_reset(sc);
1511
1512         if (bge_chipinit(sc)) {
1513                 device_printf(dev, "chip initialization failed\n");
1514                 error = ENXIO;
1515                 goto fail;
1516         }
1517
1518         /*
1519          * Get station address from the EEPROM.
1520          */
1521         mac_addr = bge_readmem_ind(sc, 0x0c14);
1522         if ((mac_addr >> 16) == 0x484b) {
1523                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1524                 ether_addr[1] = (uint8_t)mac_addr;
1525                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1526                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1527                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1528                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1529                 ether_addr[5] = (uint8_t)mac_addr;
1530         } else if (bge_read_eeprom(sc, ether_addr,
1531             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1532                 device_printf(dev, "failed to read station address\n");
1533                 error = ENXIO;
1534                 goto fail;
1535         }
1536
1537         /* Allocate the general information block and ring buffers. */
1538         sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1539             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1540
1541         if (sc->bge_rdata == NULL) {
1542                 error = ENXIO;
1543                 device_printf(dev, "no memory for list buffers!\n");
1544                 goto fail;
1545         }
1546
1547         bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1548
1549         /* Save ASIC rev. */
1550
1551         sc->bge_chipid =
1552             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1553             BGE_PCIMISCCTL_ASICREV;
1554         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1555         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1556
1557         /*
1558          * Try to allocate memory for jumbo buffers.
1559          * The 5705 does not appear to support jumbo frames.
1560          */
1561         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1562                 if (bge_alloc_jumbo_mem(sc)) {
1563                         device_printf(dev, "jumbo buffer allocation failed\n");
1564                         error = ENXIO;
1565                         goto fail;
1566                 }
1567         }
1568
1569         /* Set default tuneable values. */
1570         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1571         sc->bge_rx_coal_ticks = 150;
1572         sc->bge_tx_coal_ticks = 150;
1573         sc->bge_rx_max_coal_bds = 64;
1574         sc->bge_tx_max_coal_bds = 128;
1575
1576         /* 5705 limits RX return ring to 512 entries. */
1577         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1578                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1579         else
1580                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1581
1582         /* Set up ifnet structure */
1583         ifp->if_softc = sc;
1584         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1585         ifp->if_ioctl = bge_ioctl;
1586         ifp->if_start = bge_start;
1587         ifp->if_watchdog = bge_watchdog;
1588         ifp->if_init = bge_init;
1589         ifp->if_mtu = ETHERMTU;
1590         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1591         ifq_set_ready(&ifp->if_snd);
1592         ifp->if_hwassist = BGE_CSUM_FEATURES;
1593         ifp->if_capabilities = IFCAP_HWCSUM;
1594         ifp->if_capenable = ifp->if_capabilities;
1595
1596         /*
1597          * Figure out what sort of media we have by checking the
1598          * hardware config word in the first 32k of NIC internal memory,
1599          * or fall back to examining the EEPROM if necessary.
1600          * Note: on some BCM5700 cards, this value appears to be unset.
1601          * If that's the case, we have to rely on identifying the NIC
1602          * by its PCI subsystem ID, as we do below for the SysKonnect
1603          * SK-9D41.
1604          */
1605         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1606                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1607         else {
1608                 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1609                                 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1610                 hwcfg = ntohl(hwcfg);
1611         }
1612
1613         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1614                 sc->bge_tbi = 1;
1615
1616         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1617         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1618                 sc->bge_tbi = 1;
1619
1620         if (sc->bge_tbi) {
1621                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1622                     bge_ifmedia_upd, bge_ifmedia_sts);
1623                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1624                 ifmedia_add(&sc->bge_ifmedia,
1625                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1626                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1627                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1628         } else {
1629                 /*
1630                  * Do transceiver setup.
1631                  */
1632                 if (mii_phy_probe(dev, &sc->bge_miibus,
1633                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1634                         device_printf(dev, "MII without any PHY!\n");
1635                         error = ENXIO;
1636                         goto fail;
1637                 }
1638         }
1639
1640         /*
1641          * When using the BCM5701 in PCI-X mode, data corruption has
1642          * been observed in the first few bytes of some received packets.
1643          * Aligning the packet buffer in memory eliminates the corruption.
1644          * Unfortunately, this misaligns the packet payloads.  On platforms
1645          * which do not support unaligned accesses, we will realign the
1646          * payloads by copying the received packets.
1647          */
1648         switch (sc->bge_chipid) {
1649         case BGE_CHIPID_BCM5701_A0:
1650         case BGE_CHIPID_BCM5701_B0:
1651         case BGE_CHIPID_BCM5701_B2:
1652         case BGE_CHIPID_BCM5701_B5:
1653                 /* If in PCI-X mode, work around the alignment bug. */
1654                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1655                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1656                     BGE_PCISTATE_PCI_BUSSPEED)
1657                         sc->bge_rx_alignment_bug = 1;
1658                 break;
1659         }
1660
1661         /*
1662          * Call MI attach routine.
1663          */
1664         ether_ifattach(ifp, ether_addr);
1665
1666         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET,
1667                                bge_intr, sc, &sc->bge_intrhand, NULL);
1668         if (error) {
1669                 ether_ifdetach(ifp);
1670                 device_printf(dev, "couldn't set up irq\n");
1671                 goto fail;
1672         }
1673
1674         return(0);
1675
1676 fail:
1677         bge_detach(dev);
1678
1679         return(error);
1680 }
1681
1682 static int
1683 bge_detach(device_t dev)
1684 {
1685         struct bge_softc *sc = device_get_softc(dev);
1686         struct ifnet *ifp = &sc->arpcom.ac_if;
1687
1688         crit_enter();
1689
1690         if (device_is_attached(dev)) {
1691                 ether_ifdetach(ifp);
1692                 bge_stop(sc);
1693                 bge_reset(sc);
1694         }
1695
1696         if (sc->bge_tbi)
1697                 ifmedia_removeall(&sc->bge_ifmedia);
1698         if (sc->bge_miibus);
1699                 device_delete_child(dev, sc->bge_miibus);
1700         bus_generic_detach(dev);
1701
1702         bge_release_resources(sc);
1703
1704         crit_exit();
1705
1706         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1707                 bge_free_jumbo_mem(sc);
1708
1709         return(0);
1710 }
1711
1712 static void
1713 bge_release_resources(struct bge_softc *sc)
1714 {
1715         device_t dev;
1716
1717         dev = sc->bge_dev;
1718
1719         if (sc->bge_vpd_prodname != NULL)
1720                 free(sc->bge_vpd_prodname, M_DEVBUF);
1721
1722         if (sc->bge_vpd_readonly != NULL)
1723                 free(sc->bge_vpd_readonly, M_DEVBUF);
1724
1725         if (sc->bge_intrhand != NULL)
1726                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1727
1728         if (sc->bge_irq != NULL)
1729                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1730
1731         if (sc->bge_res != NULL)
1732                 bus_release_resource(dev, SYS_RES_MEMORY,
1733                     BGE_PCI_BAR0, sc->bge_res);
1734
1735         if (sc->bge_rdata != NULL)
1736                 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1737                            M_DEVBUF);
1738
1739         return;
1740 }
1741
1742 static void
1743 bge_reset(struct bge_softc *sc)
1744 {
1745         device_t dev;
1746         uint32_t cachesize, command, pcistate;
1747         int i, val = 0;
1748
1749         dev = sc->bge_dev;
1750
1751         /* Save some important PCI state. */
1752         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1753         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1754         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1755
1756         pci_write_config(dev, BGE_PCI_MISC_CTL,
1757             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1758             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1759
1760         /* Issue global reset */
1761         bge_writereg_ind(sc, BGE_MISC_CFG,
1762                          BGE_MISCCFG_RESET_CORE_CLOCKS | (65<<1));
1763
1764         DELAY(1000);
1765
1766         /* Reset some of the PCI state that got zapped by reset */
1767         pci_write_config(dev, BGE_PCI_MISC_CTL,
1768             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1769             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1770         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1771         pci_write_config(dev, BGE_PCI_CMD, command, 4);
1772         bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1773
1774         /*
1775          * Prevent PXE restart: write a magic number to the
1776          * general communications memory at 0xB50.
1777          */
1778         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1779         /*
1780          * Poll the value location we just wrote until
1781          * we see the 1's complement of the magic number.
1782          * This indicates that the firmware initialization
1783          * is complete.
1784          */
1785         for (i = 0; i < BGE_TIMEOUT; i++) {
1786                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1787                 if (val == ~BGE_MAGIC_NUMBER)
1788                         break;
1789                 DELAY(10);
1790         }
1791
1792         if (i == BGE_TIMEOUT) {
1793                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1794                 return;
1795         }
1796
1797         /*
1798          * XXX Wait for the value of the PCISTATE register to
1799          * return to its original pre-reset state. This is a
1800          * fairly good indicator of reset completion. If we don't
1801          * wait for the reset to fully complete, trying to read
1802          * from the device's non-PCI registers may yield garbage
1803          * results.
1804          */
1805         for (i = 0; i < BGE_TIMEOUT; i++) {
1806                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1807                         break;
1808                 DELAY(10);
1809         }
1810
1811         /* Enable memory arbiter. */
1812         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1813                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1814
1815         /* Fix up byte swapping */
1816         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1817             BGE_MODECTL_BYTESWAP_DATA);
1818
1819         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1820
1821         DELAY(10000);
1822
1823         return;
1824 }
1825
1826 /*
1827  * Frame reception handling. This is called if there's a frame
1828  * on the receive return list.
1829  *
1830  * Note: we have to be able to handle two possibilities here:
1831  * 1) the frame is from the jumbo recieve ring
1832  * 2) the frame is from the standard receive ring
1833  */
1834
1835 static void
1836 bge_rxeof(struct bge_softc *sc)
1837 {
1838         struct ifnet *ifp;
1839         int stdcnt = 0, jumbocnt = 0;
1840
1841         ifp = &sc->arpcom.ac_if;
1842
1843         while(sc->bge_rx_saved_considx !=
1844             sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1845                 struct bge_rx_bd        *cur_rx;
1846                 uint32_t                rxidx;
1847                 struct mbuf             *m = NULL;
1848                 uint16_t                vlan_tag = 0;
1849                 int                     have_tag = 0;
1850
1851                 cur_rx =
1852             &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1853
1854                 rxidx = cur_rx->bge_idx;
1855                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1856
1857                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1858                         have_tag = 1;
1859                         vlan_tag = cur_rx->bge_vlan_tag;
1860                 }
1861
1862                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1863                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1864                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1865                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1866                         jumbocnt++;
1867                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1868                                 ifp->if_ierrors++;
1869                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1870                                 continue;
1871                         }
1872                         if (bge_newbuf_jumbo(sc,
1873                             sc->bge_jumbo, NULL) == ENOBUFS) {
1874                                 ifp->if_ierrors++;
1875                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1876                                 continue;
1877                         }
1878                 } else {
1879                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1880                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1881                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
1882                         stdcnt++;
1883                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1884                                 ifp->if_ierrors++;
1885                                 bge_newbuf_std(sc, sc->bge_std, m);
1886                                 continue;
1887                         }
1888                         if (bge_newbuf_std(sc, sc->bge_std,
1889                             NULL) == ENOBUFS) {
1890                                 ifp->if_ierrors++;
1891                                 bge_newbuf_std(sc, sc->bge_std, m);
1892                                 continue;
1893                         }
1894                 }
1895
1896                 ifp->if_ipackets++;
1897 #ifndef __i386__
1898                 /*
1899                  * The i386 allows unaligned accesses, but for other
1900                  * platforms we must make sure the payload is aligned.
1901                  */
1902                 if (sc->bge_rx_alignment_bug) {
1903                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
1904                             cur_rx->bge_len);
1905                         m->m_data += ETHER_ALIGN;
1906                 }
1907 #endif
1908                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
1909                 m->m_pkthdr.rcvif = ifp;
1910
1911 #if 0 /* currently broken for some packets, possibly related to TCP options */
1912                 if (ifp->if_hwassist) {
1913                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1914                         if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
1915                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1916                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
1917                                 m->m_pkthdr.csum_data =
1918                                     cur_rx->bge_tcp_udp_csum;
1919                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1920                         }
1921                 }
1922 #endif
1923
1924                 /*
1925                  * If we received a packet with a vlan tag, pass it
1926                  * to vlan_input() instead of ether_input().
1927                  */
1928                 if (have_tag) {
1929                         VLAN_INPUT_TAG(m, vlan_tag);
1930                         have_tag = vlan_tag = 0;
1931                         continue;
1932                 }
1933
1934                 (*ifp->if_input)(ifp, m);
1935         }
1936
1937         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
1938         if (stdcnt)
1939                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1940         if (jumbocnt)
1941                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1942 }
1943
1944 static void
1945 bge_txeof(struct bge_softc *sc)
1946 {
1947         struct bge_tx_bd *cur_tx = NULL;
1948         struct ifnet *ifp;
1949
1950         ifp = &sc->arpcom.ac_if;
1951
1952         /*
1953          * Go through our tx ring and free mbufs for those
1954          * frames that have been sent.
1955          */
1956         while (sc->bge_tx_saved_considx !=
1957             sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
1958                 uint32_t                idx = 0;
1959
1960                 idx = sc->bge_tx_saved_considx;
1961                 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
1962                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
1963                         ifp->if_opackets++;
1964                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
1965                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
1966                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
1967                 }
1968                 sc->bge_txcnt--;
1969                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
1970                 ifp->if_timer = 0;
1971         }
1972
1973         if (cur_tx != NULL)
1974                 ifp->if_flags &= ~IFF_OACTIVE;
1975 }
1976
1977 static void
1978 bge_intr(void *xsc)
1979 {
1980         struct bge_softc *sc = xsc;
1981         struct ifnet *ifp = &sc->arpcom.ac_if;
1982         uint32_t status;
1983
1984 #ifdef notdef
1985         /* Avoid this for now -- checking this register is expensive. */
1986         /* Make sure this is really our interrupt. */
1987         if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
1988                 return;
1989 #endif
1990         /* Ack interrupt and stop others from occuring. */
1991         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
1992
1993         /*
1994          * Process link state changes.
1995          * Grrr. The link status word in the status block does
1996          * not work correctly on the BCM5700 rev AX and BX chips,
1997          * according to all available information. Hence, we have
1998          * to enable MII interrupts in order to properly obtain
1999          * async link changes. Unfortunately, this also means that
2000          * we have to read the MAC status register to detect link
2001          * changes, thereby adding an additional register access to
2002          * the interrupt handler.
2003          */
2004
2005         if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2006                 status = CSR_READ_4(sc, BGE_MAC_STS);
2007                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2008                         sc->bge_link = 0;
2009                         callout_stop(&sc->bge_stat_timer);
2010                         bge_tick(sc);
2011                         /* Clear the interrupt */
2012                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2013                             BGE_EVTENB_MI_INTERRUPT);
2014                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2015                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2016                             BRGPHY_INTRS);
2017                 }
2018         } else {
2019                 if ((sc->bge_rdata->bge_status_block.bge_status &
2020                     BGE_STATFLAG_UPDATED) &&
2021                     (sc->bge_rdata->bge_status_block.bge_status &
2022                     BGE_STATFLAG_LINKSTATE_CHANGED)) {
2023                         sc->bge_rdata->bge_status_block.bge_status &=
2024                                 ~(BGE_STATFLAG_UPDATED|
2025                                 BGE_STATFLAG_LINKSTATE_CHANGED);
2026                         /*
2027                          * Sometimes PCS encoding errors are detected in
2028                          * TBI mode (on fiber NICs), and for some reason
2029                          * the chip will signal them as link changes.
2030                          * If we get a link change event, but the 'PCS
2031                          * encoding error' bit in the MAC status register
2032                          * is set, don't bother doing a link check.
2033                          * This avoids spurious "gigabit link up" messages
2034                          * that sometimes appear on fiber NICs during
2035                          * periods of heavy traffic. (There should be no
2036                          * effect on copper NICs.)
2037                          */
2038                         status = CSR_READ_4(sc, BGE_MAC_STS);
2039                         if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|
2040                             BGE_MACSTAT_MI_COMPLETE))) {
2041                                 sc->bge_link = 0;
2042                                 callout_stop(&sc->bge_stat_timer);
2043                                 bge_tick(sc);
2044                         }
2045                         sc->bge_link = 0;
2046                         callout_stop(&sc->bge_stat_timer);
2047                         bge_tick(sc);
2048                         /* Clear the interrupt */
2049                         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2050                             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2051                             BGE_MACSTAT_LINK_CHANGED);
2052
2053                         /* Force flush the status block cached by PCI bridge */
2054                         CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2055                 }
2056         }
2057
2058         if (ifp->if_flags & IFF_RUNNING) {
2059                 /* Check RX return ring producer/consumer */
2060                 bge_rxeof(sc);
2061
2062                 /* Check TX ring producer/consumer */
2063                 bge_txeof(sc);
2064         }
2065
2066         bge_handle_events(sc);
2067
2068         /* Re-enable interrupts. */
2069         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2070
2071         if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2072                 (*ifp->if_start)(ifp);
2073 }
2074
2075 static void
2076 bge_tick(void *xsc)
2077 {
2078         struct bge_softc *sc = xsc;
2079         struct ifnet *ifp = &sc->arpcom.ac_if;
2080         struct mii_data *mii = NULL;
2081         struct ifmedia *ifm = NULL;
2082
2083         crit_enter();
2084
2085         if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
2086                 bge_stats_update_regs(sc);
2087         else
2088                 bge_stats_update(sc);
2089
2090         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2091
2092         if (sc->bge_link) {
2093                 crit_exit();
2094                 return;
2095         }
2096
2097         if (sc->bge_tbi) {
2098                 ifm = &sc->bge_ifmedia;
2099                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2100                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2101                         sc->bge_link++;
2102                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2103                         if_printf(ifp, "gigabit link up\n");
2104                         if (!ifq_is_empty(&ifp->if_snd))
2105                                 (*ifp->if_start)(ifp);
2106                 }
2107                 crit_exit();
2108                 return;
2109         }
2110
2111         mii = device_get_softc(sc->bge_miibus);
2112         mii_tick(mii);
2113
2114         if (!sc->bge_link) {
2115                 mii_pollstat(mii);
2116                 if (mii->mii_media_status & IFM_ACTIVE &&
2117                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2118                         sc->bge_link++;
2119                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2120                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2121                                 if_printf(ifp, "gigabit link up\n");
2122                         if (!ifq_is_empty(&ifp->if_snd))
2123                                 (*ifp->if_start)(ifp);
2124                 }
2125         }
2126
2127         crit_exit();
2128 }
2129
2130 static void
2131 bge_stats_update_regs(struct bge_softc *sc)
2132 {
2133         struct ifnet *ifp = &sc->arpcom.ac_if;
2134         struct bge_mac_stats_regs stats;
2135         uint32_t *s;
2136         int i;
2137
2138         s = (uint32_t *)&stats;
2139         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2140                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2141                 s++;
2142         }
2143
2144         ifp->if_collisions +=
2145            (stats.dot3StatsSingleCollisionFrames +
2146            stats.dot3StatsMultipleCollisionFrames +
2147            stats.dot3StatsExcessiveCollisions +
2148            stats.dot3StatsLateCollisions) -
2149            ifp->if_collisions;
2150 }
2151
2152 static void
2153 bge_stats_update(struct bge_softc *sc)
2154 {
2155         struct ifnet *ifp = &sc->arpcom.ac_if;
2156         struct bge_stats *stats;
2157
2158         stats = (struct bge_stats *)(sc->bge_vhandle +
2159             BGE_MEMWIN_START + BGE_STATS_BLOCK);
2160
2161         ifp->if_collisions +=
2162            (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2163            stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2164            stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2165            stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2166            ifp->if_collisions;
2167
2168 #ifdef notdef
2169         ifp->if_collisions +=
2170            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2171            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2172            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2173            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2174            ifp->if_collisions;
2175 #endif
2176 }
2177
2178 /*
2179  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2180  * pointers to descriptors.
2181  */
2182 static int
2183 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2184 {
2185         struct bge_tx_bd *f = NULL;
2186         struct mbuf *m;
2187         uint32_t frag, cur, cnt = 0;
2188         uint16_t csum_flags = 0;
2189         struct ifvlan *ifv = NULL;
2190
2191         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2192             m_head->m_pkthdr.rcvif != NULL &&
2193             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2194                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2195
2196         m = m_head;
2197         cur = frag = *txidx;
2198
2199         if (m_head->m_pkthdr.csum_flags) {
2200                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2201                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2202                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2203                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2204                 if (m_head->m_flags & M_LASTFRAG)
2205                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2206                 else if (m_head->m_flags & M_FRAG)
2207                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2208         }
2209         /*
2210          * Start packing the mbufs in this chain into
2211          * the fragment pointers. Stop when we run out
2212          * of fragments or hit the end of the mbuf chain.
2213          */
2214         for (m = m_head; m != NULL; m = m->m_next) {
2215                 if (m->m_len != 0) {
2216                         f = &sc->bge_rdata->bge_tx_ring[frag];
2217                         if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2218                                 break;
2219                         BGE_HOSTADDR(f->bge_addr,
2220                             vtophys(mtod(m, vm_offset_t)));
2221                         f->bge_len = m->m_len;
2222                         f->bge_flags = csum_flags;
2223                         if (ifv != NULL) {
2224                                 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2225                                 f->bge_vlan_tag = ifv->ifv_tag;
2226                         } else {
2227                                 f->bge_vlan_tag = 0;
2228                         }
2229                         /*
2230                          * Sanity check: avoid coming within 16 descriptors
2231                          * of the end of the ring.
2232                          */
2233                         if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2234                                 return(ENOBUFS);
2235                         cur = frag;
2236                         BGE_INC(frag, BGE_TX_RING_CNT);
2237                         cnt++;
2238                 }
2239         }
2240
2241         if (m != NULL)
2242                 return(ENOBUFS);
2243
2244         if (frag == sc->bge_tx_saved_considx)
2245                 return(ENOBUFS);
2246
2247         sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2248         sc->bge_cdata.bge_tx_chain[cur] = m_head;
2249         sc->bge_txcnt += cnt;
2250
2251         *txidx = frag;
2252
2253         return(0);
2254 }
2255
2256 /*
2257  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2258  * to the mbuf data regions directly in the transmit descriptors.
2259  */
2260 static void
2261 bge_start(struct ifnet *ifp)
2262 {
2263         struct bge_softc *sc;
2264         struct mbuf *m_head = NULL;
2265         uint32_t prodidx = 0;
2266
2267         sc = ifp->if_softc;
2268
2269         if (!sc->bge_link)
2270                 return;
2271
2272         prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2273
2274         while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2275                 m_head = ifq_poll(&ifp->if_snd);
2276                 if (m_head == NULL)
2277                         break;
2278
2279                 /*
2280                  * XXX
2281                  * safety overkill.  If this is a fragmented packet chain
2282                  * with delayed TCP/UDP checksums, then only encapsulate
2283                  * it if we have enough descriptors to handle the entire
2284                  * chain at once.
2285                  * (paranoia -- may not actually be needed)
2286                  */
2287                 if (m_head->m_flags & M_FIRSTFRAG &&
2288                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2289                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2290                             m_head->m_pkthdr.csum_data + 16) {
2291                                 ifp->if_flags |= IFF_OACTIVE;
2292                                 break;
2293                         }
2294                 }
2295
2296                 /*
2297                  * Pack the data into the transmit ring. If we
2298                  * don't have room, set the OACTIVE flag and wait
2299                  * for the NIC to drain the ring.
2300                  */
2301                 if (bge_encap(sc, m_head, &prodidx)) {
2302                         ifp->if_flags |= IFF_OACTIVE;
2303                         break;
2304                 }
2305                 m_head = ifq_dequeue(&ifp->if_snd);
2306
2307                 BPF_MTAP(ifp, m_head);
2308         }
2309
2310         /* Transmit */
2311         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2312         /* 5700 b2 errata */
2313         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2314                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2315
2316         /*
2317          * Set a timeout in case the chip goes out to lunch.
2318          */
2319         ifp->if_timer = 5;
2320 }
2321
2322 static void
2323 bge_init(void *xsc)
2324 {
2325         struct bge_softc *sc = xsc;
2326         struct ifnet *ifp = &sc->arpcom.ac_if;
2327         uint16_t *m;
2328
2329         crit_enter();
2330
2331         if (ifp->if_flags & IFF_RUNNING) {
2332                 crit_exit();
2333                 return;
2334         }
2335
2336         /* Cancel pending I/O and flush buffers. */
2337         bge_stop(sc);
2338         bge_reset(sc);
2339         bge_chipinit(sc);
2340
2341         /*
2342          * Init the various state machines, ring
2343          * control blocks and firmware.
2344          */
2345         if (bge_blockinit(sc)) {
2346                 if_printf(ifp, "initialization failure\n");
2347                 crit_exit();
2348                 return;
2349         }
2350
2351         /* Specify MTU. */
2352         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2353             ETHER_HDR_LEN + ETHER_CRC_LEN);
2354
2355         /* Load our MAC address. */
2356         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2357         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2358         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2359
2360         /* Enable or disable promiscuous mode as needed. */
2361         if (ifp->if_flags & IFF_PROMISC) {
2362                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2363         } else {
2364                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2365         }
2366
2367         /* Program multicast filter. */
2368         bge_setmulti(sc);
2369
2370         /* Init RX ring. */
2371         bge_init_rx_ring_std(sc);
2372
2373         /*
2374          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2375          * memory to insure that the chip has in fact read the first
2376          * entry of the ring.
2377          */
2378         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2379                 uint32_t                v, i;
2380                 for (i = 0; i < 10; i++) {
2381                         DELAY(20);
2382                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2383                         if (v == (MCLBYTES - ETHER_ALIGN))
2384                                 break;
2385                 }
2386                 if (i == 10)
2387                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2388         }
2389
2390         /* Init jumbo RX ring. */
2391         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2392                 bge_init_rx_ring_jumbo(sc);
2393
2394         /* Init our RX return ring index */
2395         sc->bge_rx_saved_considx = 0;
2396
2397         /* Init TX ring. */
2398         bge_init_tx_ring(sc);
2399
2400         /* Turn on transmitter */
2401         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2402
2403         /* Turn on receiver */
2404         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2405
2406         /* Tell firmware we're alive. */
2407         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2408
2409         /* Enable host interrupts. */
2410         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2411         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2412         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2413
2414         bge_ifmedia_upd(ifp);
2415
2416         ifp->if_flags |= IFF_RUNNING;
2417         ifp->if_flags &= ~IFF_OACTIVE;
2418
2419         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2420
2421         crit_exit();
2422 }
2423
2424 /*
2425  * Set media options.
2426  */
2427 static int
2428 bge_ifmedia_upd(struct ifnet *ifp)
2429 {
2430         struct bge_softc *sc = ifp->if_softc;
2431         struct ifmedia *ifm = &sc->bge_ifmedia;
2432         struct mii_data *mii;
2433
2434         /* If this is a 1000baseX NIC, enable the TBI port. */
2435         if (sc->bge_tbi) {
2436                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2437                         return(EINVAL);
2438                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2439                 case IFM_AUTO:
2440                         break;
2441                 case IFM_1000_SX:
2442                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2443                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2444                                     BGE_MACMODE_HALF_DUPLEX);
2445                         } else {
2446                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2447                                     BGE_MACMODE_HALF_DUPLEX);
2448                         }
2449                         break;
2450                 default:
2451                         return(EINVAL);
2452                 }
2453                 return(0);
2454         }
2455
2456         mii = device_get_softc(sc->bge_miibus);
2457         sc->bge_link = 0;
2458         if (mii->mii_instance) {
2459                 struct mii_softc *miisc;
2460                 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2461                     miisc = LIST_NEXT(miisc, mii_list))
2462                         mii_phy_reset(miisc);
2463         }
2464         mii_mediachg(mii);
2465
2466         return(0);
2467 }
2468
2469 /*
2470  * Report current media status.
2471  */
2472 static void
2473 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2474 {
2475         struct bge_softc *sc = ifp->if_softc;
2476         struct mii_data *mii;
2477
2478         if (sc->bge_tbi) {
2479                 ifmr->ifm_status = IFM_AVALID;
2480                 ifmr->ifm_active = IFM_ETHER;
2481                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2482                     BGE_MACSTAT_TBI_PCS_SYNCHED)
2483                         ifmr->ifm_status |= IFM_ACTIVE;
2484                 ifmr->ifm_active |= IFM_1000_SX;
2485                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2486                         ifmr->ifm_active |= IFM_HDX;
2487                 else
2488                         ifmr->ifm_active |= IFM_FDX;
2489                 return;
2490         }
2491
2492         mii = device_get_softc(sc->bge_miibus);
2493         mii_pollstat(mii);
2494         ifmr->ifm_active = mii->mii_media_active;
2495         ifmr->ifm_status = mii->mii_media_status;
2496 }
2497
2498 static int
2499 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2500 {
2501         struct bge_softc *sc = ifp->if_softc;
2502         struct ifreq *ifr = (struct ifreq *) data;
2503         int mask, error = 0;
2504         struct mii_data *mii;
2505
2506         crit_enter();
2507
2508         switch(command) {
2509         case SIOCSIFMTU:
2510                 /* Disallow jumbo frames on 5705. */
2511                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2512                     ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2513                         error = EINVAL;
2514                 else {
2515                         ifp->if_mtu = ifr->ifr_mtu;
2516                         ifp->if_flags &= ~IFF_RUNNING;
2517                         bge_init(sc);
2518                 }
2519                 break;
2520         case SIOCSIFFLAGS:
2521                 if (ifp->if_flags & IFF_UP) {
2522                         /*
2523                          * If only the state of the PROMISC flag changed,
2524                          * then just use the 'set promisc mode' command
2525                          * instead of reinitializing the entire NIC. Doing
2526                          * a full re-init means reloading the firmware and
2527                          * waiting for it to start up, which may take a
2528                          * second or two.
2529                          */
2530                         if (ifp->if_flags & IFF_RUNNING &&
2531                             ifp->if_flags & IFF_PROMISC &&
2532                             !(sc->bge_if_flags & IFF_PROMISC)) {
2533                                 BGE_SETBIT(sc, BGE_RX_MODE,
2534                                     BGE_RXMODE_RX_PROMISC);
2535                         } else if (ifp->if_flags & IFF_RUNNING &&
2536                             !(ifp->if_flags & IFF_PROMISC) &&
2537                             sc->bge_if_flags & IFF_PROMISC) {
2538                                 BGE_CLRBIT(sc, BGE_RX_MODE,
2539                                     BGE_RXMODE_RX_PROMISC);
2540                         } else
2541                                 bge_init(sc);
2542                 } else {
2543                         if (ifp->if_flags & IFF_RUNNING) {
2544                                 bge_stop(sc);
2545                         }
2546                 }
2547                 sc->bge_if_flags = ifp->if_flags;
2548                 error = 0;
2549                 break;
2550         case SIOCADDMULTI:
2551         case SIOCDELMULTI:
2552                 if (ifp->if_flags & IFF_RUNNING) {
2553                         bge_setmulti(sc);
2554                         error = 0;
2555                 }
2556                 break;
2557         case SIOCSIFMEDIA:
2558         case SIOCGIFMEDIA:
2559                 if (sc->bge_tbi) {
2560                         error = ifmedia_ioctl(ifp, ifr,
2561                             &sc->bge_ifmedia, command);
2562                 } else {
2563                         mii = device_get_softc(sc->bge_miibus);
2564                         error = ifmedia_ioctl(ifp, ifr,
2565                             &mii->mii_media, command);
2566                 }
2567                 break;
2568         case SIOCSIFCAP:
2569                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2570                 if (mask & IFCAP_HWCSUM) {
2571                         if (IFCAP_HWCSUM & ifp->if_capenable)
2572                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2573                         else
2574                                 ifp->if_capenable |= IFCAP_HWCSUM;
2575                 }
2576                 error = 0;
2577                 break;
2578         default:
2579                 error = ether_ioctl(ifp, command, data);
2580                 break;
2581         }
2582
2583         crit_exit();
2584
2585         return(error);
2586 }
2587
2588 static void
2589 bge_watchdog(struct ifnet *ifp)
2590 {
2591         struct bge_softc *sc = ifp->if_softc;
2592
2593         if_printf(ifp, "watchdog timeout -- resetting\n");
2594
2595         ifp->if_flags &= ~IFF_RUNNING;
2596         bge_init(sc);
2597
2598         ifp->if_oerrors++;
2599 }
2600
2601 /*
2602  * Stop the adapter and free any mbufs allocated to the
2603  * RX and TX lists.
2604  */
2605 static void
2606 bge_stop(struct bge_softc *sc)
2607 {
2608         struct ifnet *ifp = &sc->arpcom.ac_if;
2609         struct ifmedia_entry *ifm;
2610         struct mii_data *mii = NULL;
2611         int mtmp, itmp;
2612
2613         if (!sc->bge_tbi)
2614                 mii = device_get_softc(sc->bge_miibus);
2615
2616         callout_stop(&sc->bge_stat_timer);
2617
2618         /*
2619          * Disable all of the receiver blocks
2620          */
2621         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2622         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2623         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2624         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2625                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2626         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2627         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2628         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2629
2630         /*
2631          * Disable all of the transmit blocks
2632          */
2633         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2634         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2635         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2636         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2637         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2638         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2639                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2640         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2641
2642         /*
2643          * Shut down all of the memory managers and related
2644          * state machines.
2645          */
2646         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2647         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2648         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2649                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2650         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2651         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2652         if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2653                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2654                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2655         }
2656
2657         /* Disable host interrupts. */
2658         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2659         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2660
2661         /*
2662          * Tell firmware we're shutting down.
2663          */
2664         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2665
2666         /* Free the RX lists. */
2667         bge_free_rx_ring_std(sc);
2668
2669         /* Free jumbo RX list. */
2670         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2671                 bge_free_rx_ring_jumbo(sc);
2672
2673         /* Free TX buffers. */
2674         bge_free_tx_ring(sc);
2675
2676         /*
2677          * Isolate/power down the PHY, but leave the media selection
2678          * unchanged so that things will be put back to normal when
2679          * we bring the interface back up.
2680          */
2681         if (!sc->bge_tbi) {
2682                 itmp = ifp->if_flags;
2683                 ifp->if_flags |= IFF_UP;
2684                 ifm = mii->mii_media.ifm_cur;
2685                 mtmp = ifm->ifm_media;
2686                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2687                 mii_mediachg(mii);
2688                 ifm->ifm_media = mtmp;
2689                 ifp->if_flags = itmp;
2690         }
2691
2692         sc->bge_link = 0;
2693
2694         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2695
2696         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2697 }
2698
2699 /*
2700  * Stop all chip I/O so that the kernel's probe routines don't
2701  * get confused by errant DMAs when rebooting.
2702  */
2703 static void
2704 bge_shutdown(device_t dev)
2705 {
2706         struct bge_softc *sc = device_get_softc(dev);
2707
2708         bge_stop(sc);
2709         bge_reset(sc);
2710 }