2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.22 2004/08/13 08:27:02 joerg Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/md_var.h> /* For the Alpha */
58 #include <bus/pci/i386/pci_cfgreg.h>
61 #include <sys/pciio.h>
64 #include "pci_private.h"
69 #include <machine/rpb.h>
73 #include <machine/smp.h>
76 devclass_t pci_devclass;
78 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
81 u_int32_t devid; /* Vendor/device of the card */
83 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
88 struct pci_quirk pci_quirks[] = {
90 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
92 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
93 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
98 /* map register information */
99 #define PCI_MAPMEM 0x01 /* memory map */
100 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
101 #define PCI_MAPPORT 0x04 /* port map */
103 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
104 u_int32_t pci_numdevs = 0;
105 static u_int32_t pci_generation = 0;
108 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
110 struct pci_devinfo *dinfo;
112 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
113 if ((dinfo->cfg.bus == bus) &&
114 (dinfo->cfg.slot == slot) &&
115 (dinfo->cfg.func == func)) {
116 return (dinfo->cfg.dev);
124 pci_find_device (u_int16_t vendor, u_int16_t device)
126 struct pci_devinfo *dinfo;
128 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
129 if ((dinfo->cfg.vendor == vendor) &&
130 (dinfo->cfg.device == device)) {
131 return (dinfo->cfg.dev);
138 /* return base address of memory or port map */
141 pci_mapbase(unsigned mapreg)
144 if ((mapreg & 0x01) == 0)
146 return (mapreg & ~mask);
149 /* return map type of memory or port map */
152 pci_maptype(unsigned mapreg)
154 static u_int8_t maptype[0x10] = {
155 PCI_MAPMEM, PCI_MAPPORT,
157 PCI_MAPMEM, PCI_MAPPORT,
159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
160 PCI_MAPMEM|PCI_MAPMEMP, 0,
161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
165 return maptype[mapreg & 0x0f];
168 /* return log2 of map size decoded for memory or port map */
171 pci_mapsize(unsigned testval)
175 testval = pci_mapbase(testval);
178 while ((testval & 1) == 0)
187 /* return log2 of address range supported by map register */
190 pci_maprange(unsigned mapreg)
193 switch (mapreg & 0x07) {
209 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
212 pci_fixancient(pcicfgregs *cfg)
214 if (cfg->hdrtype != 0)
217 /* PCI to PCI bridges use header type 1 */
218 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
222 /* read config data specific to header type 1 device (PCI to PCI bridge) */
225 pci_readppb(device_t pcib, int b, int s, int f)
229 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
233 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
234 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
236 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
238 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
240 PCIB_READ_CONFIG(pcib, b, s, f,
242 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIB_READ_CONFIG(pcib, b, s, f,
245 PCIR_IOLIMITL_1, 1));
247 p->membase = PCI_PPBMEMBASE (0,
248 PCIB_READ_CONFIG(pcib, b, s, f,
250 p->memlimit = PCI_PPBMEMLIMIT (0,
251 PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_MEMLIMIT_1, 2));
254 p->pmembase = PCI_PPBMEMBASE (
255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
256 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
258 p->pmemlimit = PCI_PPBMEMLIMIT (
259 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
261 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
266 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
269 pci_readpcb(device_t pcib, int b, int s, int f)
273 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
277 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
278 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
280 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
282 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
283 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
284 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
285 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
287 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
288 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
289 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
290 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
292 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
296 /* extract header type specific config data */
299 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
301 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
302 switch (cfg->hdrtype) {
304 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
306 cfg->nummaps = PCI_MAXMAPS_0;
309 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
313 cfg->nummaps = PCI_MAXMAPS_1;
314 cfg->hdrspec = pci_readppb(pcib, b, s, f);
317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
319 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
320 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
321 cfg->nummaps = PCI_MAXMAPS_2;
322 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
328 /* read configuration header into pcicfgrect structure */
331 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
333 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
335 pcicfgregs *cfg = NULL;
336 struct pci_devinfo *devlist_entry;
337 struct devlist *devlist_head;
339 devlist_head = &pci_devq;
341 devlist_entry = NULL;
343 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
345 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
346 if (devlist_entry == NULL)
349 cfg = &devlist_entry->cfg;
354 cfg->vendor = REG(PCIR_VENDOR, 2);
355 cfg->device = REG(PCIR_DEVICE, 2);
356 cfg->cmdreg = REG(PCIR_COMMAND, 2);
357 cfg->statreg = REG(PCIR_STATUS, 2);
358 cfg->baseclass = REG(PCIR_CLASS, 1);
359 cfg->subclass = REG(PCIR_SUBCLASS, 1);
360 cfg->progif = REG(PCIR_PROGIF, 1);
361 cfg->revid = REG(PCIR_REVID, 1);
362 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
363 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
364 cfg->lattimer = REG(PCIR_LATTIMER, 1);
365 cfg->intpin = REG(PCIR_INTPIN, 1);
366 cfg->intline = REG(PCIR_INTLINE, 1);
368 alpha_platform_assign_pciintr(cfg);
372 if (cfg->intpin != 0) {
375 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
377 /* PCI specific entry found in MP table */
378 if (airq != cfg->intline) {
379 undirect_pci_irq(cfg->intline);
384 * PCI interrupts might be redirected to the
385 * ISA bus according to some MP tables. Use the
386 * same methods as used by the ISA devices
387 * devices to find the proper IOAPIC int pin.
389 airq = isa_apic_irq(cfg->intline);
390 if ((airq >= 0) && (airq != cfg->intline)) {
391 /* XXX: undirect_pci_irq() ? */
392 undirect_isa_irq(cfg->intline);
399 cfg->mingnt = REG(PCIR_MINGNT, 1);
400 cfg->maxlat = REG(PCIR_MAXLAT, 1);
402 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
403 cfg->hdrtype &= ~PCIM_MFDEV;
406 pci_hdrtypedata(pcib, b, s, f, cfg);
408 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
409 pci_read_extcap(pcib, cfg);
411 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
413 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
414 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
415 devlist_entry->conf.pc_sel.pc_func = cfg->func;
416 devlist_entry->conf.pc_hdr = cfg->hdrtype;
418 devlist_entry->conf.pc_subvendor = cfg->subvendor;
419 devlist_entry->conf.pc_subdevice = cfg->subdevice;
420 devlist_entry->conf.pc_vendor = cfg->vendor;
421 devlist_entry->conf.pc_device = cfg->device;
423 devlist_entry->conf.pc_class = cfg->baseclass;
424 devlist_entry->conf.pc_subclass = cfg->subclass;
425 devlist_entry->conf.pc_progif = cfg->progif;
426 devlist_entry->conf.pc_revid = cfg->revid;
431 return (devlist_entry);
436 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
438 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
439 int ptr, nextptr, ptrptr;
441 switch (cfg->hdrtype) {
449 return; /* no extended capabilities support */
451 nextptr = REG(ptrptr, 1); /* sanity check? */
454 * Read capability entries.
456 while (nextptr != 0) {
459 printf("illegal PCI extended capability offset %d\n",
463 /* Find the next entry */
465 nextptr = REG(ptr + 1, 1);
467 /* Process this entry */
468 switch (REG(ptr, 1)) {
469 case 0x01: /* PCI power management */
470 if (cfg->pp_cap == 0) {
471 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
472 cfg->pp_status = ptr + PCIR_POWER_STATUS;
473 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
474 if ((nextptr - ptr) > PCIR_POWER_DATA)
475 cfg->pp_data = ptr + PCIR_POWER_DATA;
485 /* free pcicfgregs structure and all depending data structures */
488 pci_freecfg(struct pci_devinfo *dinfo)
490 struct devlist *devlist_head;
492 devlist_head = &pci_devq;
494 if (dinfo->cfg.hdrspec != NULL)
495 free(dinfo->cfg.hdrspec, M_DEVBUF);
496 /* XXX this hasn't been tested */
497 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
498 free(dinfo, M_DEVBUF);
500 /* increment the generation count */
503 /* we're losing one device */
510 * PCI power manangement
513 pci_set_powerstate_method(device_t dev, device_t child, int state)
515 struct pci_devinfo *dinfo = device_get_ivars(child);
516 pcicfgregs *cfg = &dinfo->cfg;
520 if (cfg->pp_cap != 0) {
521 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
524 case PCI_POWERSTATE_D0:
525 status |= PCIM_PSTAT_D0;
527 case PCI_POWERSTATE_D1:
528 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
529 status |= PCIM_PSTAT_D1;
534 case PCI_POWERSTATE_D2:
535 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
536 status |= PCIM_PSTAT_D2;
541 case PCI_POWERSTATE_D3:
542 status |= PCIM_PSTAT_D3;
548 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
556 pci_get_powerstate_method(device_t dev, device_t child)
558 struct pci_devinfo *dinfo = device_get_ivars(child);
559 pcicfgregs *cfg = &dinfo->cfg;
563 if (cfg->pp_cap != 0) {
564 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
565 switch (status & PCIM_PSTAT_DMASK) {
567 result = PCI_POWERSTATE_D0;
570 result = PCI_POWERSTATE_D1;
573 result = PCI_POWERSTATE_D2;
576 result = PCI_POWERSTATE_D3;
579 result = PCI_POWERSTATE_UNKNOWN;
583 /* No support, device is always at D0 */
584 result = PCI_POWERSTATE_D0;
590 * Some convenience functions for PCI device drivers.
594 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
598 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
600 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
604 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
608 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
610 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
614 pci_enable_busmaster_method(device_t dev, device_t child)
616 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
621 pci_disable_busmaster_method(device_t dev, device_t child)
623 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
628 pci_enable_io_method(device_t dev, device_t child, int space)
639 bit = PCIM_CMD_PORTEN;
643 bit = PCIM_CMD_MEMEN;
649 pci_set_command_bit(dev, child, bit);
650 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
653 device_printf(child, "failed to enable %s mapping!\n", error);
658 pci_disable_io_method(device_t dev, device_t child, int space)
669 bit = PCIM_CMD_PORTEN;
673 bit = PCIM_CMD_MEMEN;
679 pci_clear_command_bit(dev, child, bit);
680 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
682 device_printf(child, "failed to disable %s mapping!\n", error);
689 * This is the user interface to PCI configuration space.
693 pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
695 if ((oflags & FWRITE) && securelevel > 0) {
702 pci_close(dev_t dev, int flag, int devtype, struct thread *td)
708 * Match a single pci_conf structure against an array of pci_match_conf
709 * structures. The first argument, 'matches', is an array of num_matches
710 * pci_match_conf structures. match_buf is a pointer to the pci_conf
711 * structure that will be compared to every entry in the matches array.
712 * This function returns 1 on failure, 0 on success.
715 pci_conf_match(struct pci_match_conf *matches, int num_matches,
716 struct pci_conf *match_buf)
720 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
723 for (i = 0; i < num_matches; i++) {
725 * I'm not sure why someone would do this...but...
727 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
731 * Look at each of the match flags. If it's set, do the
732 * comparison. If the comparison fails, we don't have a
733 * match, go on to the next item if there is one.
735 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
736 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
739 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
740 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
743 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
744 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
747 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
748 && (match_buf->pc_vendor != matches[i].pc_vendor))
751 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
752 && (match_buf->pc_device != matches[i].pc_device))
755 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
756 && (match_buf->pc_class != matches[i].pc_class))
759 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
760 && (match_buf->pd_unit != matches[i].pd_unit))
763 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
764 && (strncmp(matches[i].pd_name, match_buf->pd_name,
765 sizeof(match_buf->pd_name)) != 0))
775 * Locate the parent of a PCI device by scanning the PCI devlist
776 * and return the entry for the parent.
777 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
778 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
782 pci_devlist_get_parent(pcicfgregs *cfg)
784 struct devlist *devlist_head;
785 struct pci_devinfo *dinfo;
786 pcicfgregs *bridge_cfg;
789 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
791 /* If the device is on PCI bus 0, look for the host */
793 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
794 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
795 bridge_cfg = &dinfo->cfg;
796 if (bridge_cfg->baseclass == PCIC_BRIDGE
797 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
798 && bridge_cfg->bus == cfg->bus) {
804 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
806 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
807 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
808 bridge_cfg = &dinfo->cfg;
809 if (bridge_cfg->baseclass == PCIC_BRIDGE
810 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
811 && bridge_cfg->secondarybus == cfg->bus) {
821 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
828 if (!(flag & FWRITE))
835 struct pci_devinfo *dinfo;
836 struct pci_conf_io *cio;
837 struct devlist *devlist_head;
838 struct pci_match_conf *pattern_buf;
843 cio = (struct pci_conf_io *)data;
849 * Hopefully the user won't pass in a null pointer, but it
850 * can't hurt to check.
858 * If the user specified an offset into the device list,
859 * but the list has changed since they last called this
860 * ioctl, tell them that the list has changed. They will
861 * have to get the list from the beginning.
863 if ((cio->offset != 0)
864 && (cio->generation != pci_generation)){
865 cio->num_matches = 0;
866 cio->status = PCI_GETCONF_LIST_CHANGED;
872 * Check to see whether the user has asked for an offset
873 * past the end of our list.
875 if (cio->offset >= pci_numdevs) {
876 cio->num_matches = 0;
877 cio->status = PCI_GETCONF_LAST_DEVICE;
882 /* get the head of the device queue */
883 devlist_head = &pci_devq;
886 * Determine how much room we have for pci_conf structures.
887 * Round the user's buffer size down to the nearest
888 * multiple of sizeof(struct pci_conf) in case the user
889 * didn't specify a multiple of that size.
891 iolen = min(cio->match_buf_len -
892 (cio->match_buf_len % sizeof(struct pci_conf)),
893 pci_numdevs * sizeof(struct pci_conf));
896 * Since we know that iolen is a multiple of the size of
897 * the pciconf union, it's okay to do this.
899 ionum = iolen / sizeof(struct pci_conf);
902 * If this test is true, the user wants the pci_conf
903 * structures returned to match the supplied entries.
905 if ((cio->num_patterns > 0)
906 && (cio->pat_buf_len > 0)) {
908 * pat_buf_len needs to be:
909 * num_patterns * sizeof(struct pci_match_conf)
910 * While it is certainly possible the user just
911 * allocated a large buffer, but set the number of
912 * matches correctly, it is far more likely that
913 * their kernel doesn't match the userland utility
914 * they're using. It's also possible that the user
915 * forgot to initialize some variables. Yes, this
916 * may be overly picky, but I hazard to guess that
917 * it's far more likely to just catch folks that
918 * updated their kernel but not their userland.
920 if ((cio->num_patterns *
921 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
922 /* The user made a mistake, return an error*/
923 cio->status = PCI_GETCONF_ERROR;
924 printf("pci_ioctl: pat_buf_len %d != "
925 "num_patterns (%d) * sizeof(struct "
926 "pci_match_conf) (%d)\npci_ioctl: "
927 "pat_buf_len should be = %d\n",
928 cio->pat_buf_len, cio->num_patterns,
929 (int)sizeof(struct pci_match_conf),
930 (int)sizeof(struct pci_match_conf) *
932 printf("pci_ioctl: do your headers match your "
934 cio->num_matches = 0;
940 * Check the user's buffer to make sure it's readable.
942 if (!useracc((caddr_t)cio->patterns,
943 cio->pat_buf_len, VM_PROT_READ)) {
944 printf("pci_ioctl: pattern buffer %p, "
945 "length %u isn't user accessible for"
946 " READ\n", cio->patterns,
952 * Allocate a buffer to hold the patterns.
954 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
956 error = copyin(cio->patterns, pattern_buf,
960 num_patterns = cio->num_patterns;
962 } else if ((cio->num_patterns > 0)
963 || (cio->pat_buf_len > 0)) {
965 * The user made a mistake, spit out an error.
967 cio->status = PCI_GETCONF_ERROR;
968 cio->num_matches = 0;
969 printf("pci_ioctl: invalid GETCONF arguments\n");
976 * Make sure we can write to the match buffer.
978 if (!useracc((caddr_t)cio->matches,
979 cio->match_buf_len, VM_PROT_WRITE)) {
980 printf("pci_ioctl: match buffer %p, length %u "
981 "isn't user accessible for WRITE\n",
982 cio->matches, cio->match_buf_len);
988 * Go through the list of devices and copy out the devices
989 * that match the user's criteria.
991 for (cio->num_matches = 0, error = 0, i = 0,
992 dinfo = STAILQ_FIRST(devlist_head);
993 (dinfo != NULL) && (cio->num_matches < ionum)
994 && (error == 0) && (i < pci_numdevs);
995 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1000 /* Populate pd_name and pd_unit */
1002 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1003 name = device_get_name(dinfo->cfg.dev);
1005 strncpy(dinfo->conf.pd_name, name,
1006 sizeof(dinfo->conf.pd_name));
1007 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1008 dinfo->conf.pd_unit =
1009 device_get_unit(dinfo->cfg.dev);
1012 if ((pattern_buf == NULL) ||
1013 (pci_conf_match(pattern_buf, num_patterns,
1014 &dinfo->conf) == 0)) {
1017 * If we've filled up the user's buffer,
1018 * break out at this point. Since we've
1019 * got a match here, we'll pick right back
1020 * up at the matching entry. We can also
1021 * tell the user that there are more matches
1024 if (cio->num_matches >= ionum)
1027 error = copyout(&dinfo->conf,
1028 &cio->matches[cio->num_matches],
1029 sizeof(struct pci_conf));
1035 * Set the pointer into the list, so if the user is getting
1036 * n records at a time, where n < pci_numdevs,
1041 * Set the generation, the user will need this if they make
1042 * another ioctl call with offset != 0.
1044 cio->generation = pci_generation;
1047 * If this is the last device, inform the user so he won't
1048 * bother asking for more devices. If dinfo isn't NULL, we
1049 * know that there are more matches in the list because of
1050 * the way the traversal is done.
1053 cio->status = PCI_GETCONF_LAST_DEVICE;
1055 cio->status = PCI_GETCONF_MORE_DEVS;
1057 if (pattern_buf != NULL)
1058 free(pattern_buf, M_TEMP);
1063 io = (struct pci_io *)data;
1064 switch(io->pi_width) {
1069 * Assume that the user-level bus number is
1070 * actually the pciN instance number. We map
1071 * from that to the real pcib+bus combination.
1073 pci = devclass_get_device(pci_devclass,
1076 int b = pcib_get_bus(pci);
1077 pcib = device_get_parent(pci);
1079 PCIB_READ_CONFIG(pcib,
1097 io = (struct pci_io *)data;
1098 switch(io->pi_width) {
1103 * Assume that the user-level bus number is
1104 * actually the pciN instance number. We map
1105 * from that to the real pcib+bus combination.
1107 pci = devclass_get_device(pci_devclass,
1110 int b = pcib_get_bus(pci);
1111 pcib = device_get_parent(pci);
1112 PCIB_WRITE_CONFIG(pcib,
1140 static struct cdevsw pcicdev = {
1147 /* open */ pci_open,
1148 /* close */ pci_close,
1150 /* write */ nowrite,
1151 /* ioctl */ pci_ioctl,
1154 /* strategy */ nostrategy,
1162 * New style pci driver. Parent device is either a pci-host-bridge or a
1163 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1167 pci_print_verbose(struct pci_devinfo *dinfo)
1170 pcicfgregs *cfg = &dinfo->cfg;
1172 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1173 cfg->vendor, cfg->device, cfg->revid);
1174 printf("\tbus=%d, slot=%d, func=%d\n",
1175 cfg->bus, cfg->slot, cfg->func);
1176 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1177 cfg->baseclass, cfg->subclass, cfg->progif,
1178 cfg->hdrtype, cfg->mfdev);
1179 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1180 cfg->subordinatebus, cfg->secondarybus);
1182 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1183 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1184 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1185 cfg->lattimer, cfg->lattimer * 30,
1186 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1187 #endif /* PCI_DEBUG */
1188 if (cfg->intpin > 0)
1189 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1194 pci_porten(device_t pcib, int b, int s, int f)
1196 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1197 & PCIM_CMD_PORTEN) != 0;
1201 pci_memen(device_t pcib, int b, int s, int f)
1203 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1204 & PCIM_CMD_MEMEN) != 0;
1208 * Add a resource based on a pci map register. Return 1 if the map
1209 * register is a 32bit map register or 2 if it is a 64bit register.
1212 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1213 struct resource_list *rl)
1222 #ifdef PCI_ENABLE_IO_MODES
1227 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1229 if (map == 0 || map == 0xffffffff)
1230 return 1; /* skip invalid entry */
1232 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1233 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1234 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1236 base = pci_mapbase(map);
1237 if (pci_maptype(map) & PCI_MAPMEM)
1238 type = SYS_RES_MEMORY;
1240 type = SYS_RES_IOPORT;
1241 ln2size = pci_mapsize(testval);
1242 ln2range = pci_maprange(testval);
1243 if (ln2range == 64) {
1244 /* Read the other half of a 64bit map register */
1245 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1249 * This code theoretically does the right thing, but has
1250 * undesirable side effects in some cases where
1251 * peripherals respond oddly to having these bits
1252 * enabled. Leave them alone by default.
1254 #ifdef PCI_ENABLE_IO_MODES
1255 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1256 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1257 cmd |= PCIM_CMD_PORTEN;
1258 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1260 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1261 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1262 cmd |= PCIM_CMD_MEMEN;
1263 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1266 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1268 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1272 resource_list_add(rl, type, reg,
1273 base, base + (1 << ln2size) - 1,
1277 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1278 reg, pci_maptype(base), ln2range,
1279 (unsigned int) base, ln2size);
1282 return (ln2range == 64) ? 2 : 1;
1286 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1288 struct pci_devinfo *dinfo = device_get_ivars(dev);
1289 pcicfgregs *cfg = &dinfo->cfg;
1290 struct resource_list *rl = &dinfo->resources;
1291 struct pci_quirk *q;
1293 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1300 for (i = 0; i < cfg->nummaps;) {
1301 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1304 for (q = &pci_quirks[0]; q->devid; q++) {
1305 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1306 && q->type == PCI_QUIRK_MAP_REG)
1307 pci_add_map(pcib, b, s, f, q->arg1, rl);
1310 if (cfg->intpin > 0 && cfg->intline != 255)
1311 resource_list_add(rl, SYS_RES_IRQ, 0,
1312 cfg->intline, cfg->intline, 1);
1316 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1318 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1319 device_t pcib = device_get_parent(dev);
1320 struct pci_devinfo *dinfo;
1322 int s, f, pcifunchigh;
1325 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1327 maxslots = PCIB_MAXSLOTS(pcib);
1329 for (s = 0; s <= maxslots; s++) {
1332 hdrtype = REG(PCIR_HDRTYPE, 1);
1333 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1335 if (hdrtype & PCIM_MFDEV)
1336 pcifunchigh = PCI_FUNCMAX;
1337 for (f = 0; f <= pcifunchigh; f++) {
1338 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1339 if (dinfo != NULL) {
1340 pci_add_child(dev, dinfo);
1348 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1352 pcib = device_get_parent(bus);
1353 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1354 device_set_ivars(dinfo->cfg.dev, dinfo);
1355 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1356 pci_print_verbose(dinfo);
1360 * Probe the PCI bus. Note: probe code is not supposed to add children
1364 pci_probe(device_t dev)
1366 device_set_desc(dev, "PCI bus");
1368 /* Allow other subclasses to override this driver */
1373 pci_attach(device_t dev)
1376 int lunit = device_get_unit(dev);
1378 cdevsw_add(&pcicdev, -1, lunit);
1379 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1382 * Since there can be multiple independantly numbered PCI
1383 * busses on some large alpha systems, we can't use the unit
1384 * number to decide what bus we are probing. We ask the parent
1385 * pcib what our bus number is.
1387 busno = pcib_get_bus(dev);
1389 device_printf(dev, "physical bus=%d\n", busno);
1391 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1393 return (bus_generic_attach(dev));
1397 pci_print_resources(struct resource_list *rl, const char *name, int type,
1400 struct resource_list_entry *rle;
1401 int printed, retval;
1405 /* Yes, this is kinda cheating */
1406 SLIST_FOREACH(rle, rl, link) {
1407 if (rle->type == type) {
1409 retval += printf(" %s ", name);
1410 else if (printed > 0)
1411 retval += printf(",");
1413 retval += printf(format, rle->start);
1414 if (rle->count > 1) {
1415 retval += printf("-");
1416 retval += printf(format, rle->start +
1425 pci_print_child(device_t dev, device_t child)
1427 struct pci_devinfo *dinfo;
1428 struct resource_list *rl;
1432 dinfo = device_get_ivars(child);
1434 rl = &dinfo->resources;
1436 retval += bus_print_child_header(dev, child);
1438 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1439 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1440 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1441 if (device_get_flags(dev))
1442 retval += printf(" flags %#x", device_get_flags(dev));
1444 retval += printf(" at device %d.%d", pci_get_slot(child),
1445 pci_get_function(child));
1447 retval += bus_print_child_footer(dev, child);
1453 pci_probe_nomatch(device_t dev, device_t child)
1455 struct pci_devinfo *dinfo;
1461 dinfo = device_get_ivars(child);
1463 desc = pci_ata_match(child);
1464 if (!desc) desc = pci_usb_match(child);
1465 if (!desc) desc = pci_vga_match(child);
1466 if (!desc) desc = pci_chip_match(child);
1468 desc = "unknown card";
1471 device_printf(dev, "<%s>", desc);
1472 if (bootverbose || unknown) {
1473 printf(" (vendor=0x%04x, dev=0x%04x)",
1478 pci_get_slot(child),
1479 pci_get_function(child));
1480 if (cfg->intpin > 0 && cfg->intline != 255) {
1481 printf(" irq %d", cfg->intline);
1489 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1491 struct pci_devinfo *dinfo;
1494 dinfo = device_get_ivars(child);
1498 case PCI_IVAR_SUBVENDOR:
1499 *result = cfg->subvendor;
1501 case PCI_IVAR_SUBDEVICE:
1502 *result = cfg->subdevice;
1504 case PCI_IVAR_VENDOR:
1505 *result = cfg->vendor;
1507 case PCI_IVAR_DEVICE:
1508 *result = cfg->device;
1510 case PCI_IVAR_DEVID:
1511 *result = (cfg->device << 16) | cfg->vendor;
1513 case PCI_IVAR_CLASS:
1514 *result = cfg->baseclass;
1516 case PCI_IVAR_SUBCLASS:
1517 *result = cfg->subclass;
1519 case PCI_IVAR_PROGIF:
1520 *result = cfg->progif;
1522 case PCI_IVAR_REVID:
1523 *result = cfg->revid;
1525 case PCI_IVAR_INTPIN:
1526 *result = cfg->intpin;
1529 *result = cfg->intline;
1535 *result = cfg->slot;
1537 case PCI_IVAR_FUNCTION:
1538 *result = cfg->func;
1540 case PCI_IVAR_SECONDARYBUS:
1541 *result = cfg->secondarybus;
1543 case PCI_IVAR_SUBORDINATEBUS:
1544 *result = cfg->subordinatebus;
1546 case PCI_IVAR_ETHADDR:
1548 * The generic accessor doesn't deal with failure, so
1549 * we set the return value, then return an error.
1560 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1562 struct pci_devinfo *dinfo;
1565 dinfo = device_get_ivars(child);
1569 case PCI_IVAR_SUBVENDOR:
1570 case PCI_IVAR_SUBDEVICE:
1571 case PCI_IVAR_VENDOR:
1572 case PCI_IVAR_DEVICE:
1573 case PCI_IVAR_DEVID:
1574 case PCI_IVAR_CLASS:
1575 case PCI_IVAR_SUBCLASS:
1576 case PCI_IVAR_PROGIF:
1577 case PCI_IVAR_REVID:
1578 case PCI_IVAR_INTPIN:
1582 case PCI_IVAR_FUNCTION:
1583 case PCI_IVAR_ETHADDR:
1584 return EINVAL; /* disallow for now */
1586 case PCI_IVAR_SECONDARYBUS:
1587 cfg->secondarybus = value;
1589 case PCI_IVAR_SUBORDINATEBUS:
1590 cfg->subordinatebus = value;
1599 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1600 u_long start, u_long end, u_long count, u_int flags)
1602 struct pci_devinfo *dinfo = device_get_ivars(child);
1603 struct resource_list *rl = &dinfo->resources;
1606 pcicfgregs *cfg = &dinfo->cfg;
1608 * Perform lazy resource allocation
1610 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1612 if (device_get_parent(child) == dev) {
1614 * If device doesn't have an interrupt routed, and is
1615 * deserving of an interrupt, try to assign it one.
1617 if ((type == SYS_RES_IRQ) &&
1618 (cfg->intline == 255 || cfg->intline == 0) &&
1619 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1620 cfg->intline = PCIB_ROUTE_INTERRUPT(
1621 device_get_parent(dev), child,
1623 if (cfg->intline != 255) {
1624 pci_write_config(child, PCIR_INTLINE,
1626 resource_list_add(rl, SYS_RES_IRQ, 0,
1627 cfg->intline, cfg->intline, 1);
1632 return resource_list_alloc(rl, dev, child, type, rid,
1633 start, end, count, flags);
1637 pci_release_resource(device_t dev, device_t child, int type, int rid,
1640 struct pci_devinfo *dinfo = device_get_ivars(child);
1641 struct resource_list *rl = &dinfo->resources;
1643 return resource_list_release(rl, dev, child, type, rid, r);
1647 pci_set_resource(device_t dev, device_t child, int type, int rid,
1648 u_long start, u_long count)
1650 struct pci_devinfo *dinfo = device_get_ivars(child);
1651 struct resource_list *rl = &dinfo->resources;
1653 resource_list_add(rl, type, rid, start, start + count - 1, count);
1658 pci_get_resource(device_t dev, device_t child, int type, int rid,
1659 u_long *startp, u_long *countp)
1661 struct pci_devinfo *dinfo = device_get_ivars(child);
1662 struct resource_list *rl = &dinfo->resources;
1663 struct resource_list_entry *rle;
1665 rle = resource_list_find(rl, type, rid);
1670 *startp = rle->start;
1672 *countp = rle->count;
1678 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1680 printf("pci_delete_resource: PCI resources can not be deleted\n");
1683 struct resource_list *
1684 pci_get_resource_list (device_t dev, device_t child)
1686 struct pci_devinfo * dinfo = device_get_ivars(child);
1687 struct resource_list * rl = &dinfo->resources;
1696 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1698 struct pci_devinfo *dinfo = device_get_ivars(child);
1699 pcicfgregs *cfg = &dinfo->cfg;
1701 return PCIB_READ_CONFIG(device_get_parent(dev),
1702 cfg->bus, cfg->slot, cfg->func,
1707 pci_write_config_method(device_t dev, device_t child, int reg,
1708 u_int32_t val, int width)
1710 struct pci_devinfo *dinfo = device_get_ivars(child);
1711 pcicfgregs *cfg = &dinfo->cfg;
1713 PCIB_WRITE_CONFIG(device_get_parent(dev),
1714 cfg->bus, cfg->slot, cfg->func,
1719 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1722 struct pci_devinfo *dinfo;
1724 dinfo = device_get_ivars(child);
1725 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1726 pci_get_function(child));
1731 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1734 struct pci_devinfo *dinfo;
1737 dinfo = device_get_ivars(child);
1739 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1740 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1741 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1747 pci_assign_interrupt_method(device_t dev, device_t child)
1749 struct pci_devinfo *dinfo = device_get_ivars(child);
1750 pcicfgregs *cfg = &dinfo->cfg;
1752 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1757 pci_modevent(module_t mod, int what, void *arg)
1761 STAILQ_INIT(&pci_devq);
1771 pci_resume(device_t dev)
1777 struct pci_devinfo *dinfo;
1780 device_get_children(dev, &children, &numdevs);
1782 for (i = 0; i < numdevs; i++) {
1783 child = children[i];
1785 dinfo = device_get_ivars(child);
1787 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1788 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1789 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1790 pci_write_config(child, PCIR_INTLINE,
1796 free(children, M_TEMP);
1798 return (bus_generic_resume(dev));
1801 static device_method_t pci_methods[] = {
1802 /* Device interface */
1803 DEVMETHOD(device_probe, pci_probe),
1804 DEVMETHOD(device_attach, pci_attach),
1805 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1806 DEVMETHOD(device_suspend, bus_generic_suspend),
1807 DEVMETHOD(device_resume, pci_resume),
1810 DEVMETHOD(bus_print_child, pci_print_child),
1811 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1812 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1813 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1814 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1815 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1816 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1818 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
1819 DEVMETHOD(bus_set_resource, pci_set_resource),
1820 DEVMETHOD(bus_get_resource, pci_get_resource),
1821 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1822 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1823 DEVMETHOD(bus_release_resource, pci_release_resource),
1824 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1825 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1826 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1827 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
1830 DEVMETHOD(pci_read_config, pci_read_config_method),
1831 DEVMETHOD(pci_write_config, pci_write_config_method),
1832 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1833 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1834 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1835 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1836 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1837 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1838 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
1843 static driver_t pci_driver = {
1849 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
1850 MODULE_VERSION(pci, 1);