4 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
5 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
34 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
42 #include <sys/param.h>
43 #include <sys/systm.h>
48 #include <sys/dkstat.h>
49 #include <sys/fcntl.h>
50 #include <sys/interrupt.h>
51 #include <sys/kernel.h>
52 #include <sys/thread2.h>
53 #include <machine/clock.h>
55 #include <bus/isa/isa_device.h>
57 #include <machine_base/isa/ic/cd180.h>
61 static int rcprobe (struct isa_device *);
62 static int rcattach (struct isa_device *);
64 #define rcin(port) RC_IN (nec, port)
65 #define rcout(port,v) RC_OUT (nec, port, v)
67 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
68 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
70 #define RC_IBUFSIZE 256
71 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
72 #define RC_OBUFSIZE 512
73 #define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
74 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
75 #define LOTS_OF_EVENTS 64
77 #define RC_FAKEID 0x10
82 #define GET_UNIT(dev) (minor(dev) & 0x3F)
83 #define CALLOUT(dev) (minor(dev) & 0x80)
85 /* For isa routines */
86 struct isa_driver rcdriver = {
87 rcprobe, rcattach, "rc"
90 static d_open_t rcopen;
91 static d_close_t rcclose;
92 static d_ioctl_t rcioctl;
94 static struct dev_ops rc_ops = {
101 .d_kqfilter = ttykqfilter,
102 .d_revoke = ttyrevoke
105 /* Per-board structure */
106 static struct rc_softc {
107 u_int rcb_probed; /* 1 - probed, 2 - attached */
108 u_int rcb_addr; /* Base I/O addr */
109 u_int rcb_unit; /* unit # */
110 u_char rcb_dtr; /* DTR status */
111 struct rc_chans *rcb_baserc; /* base rc ptr */
114 /* Per-channel structure */
115 static struct rc_chans {
116 struct rc_softc *rc_rcb; /* back ptr */
117 u_short rc_flags; /* Misc. flags */
118 int rc_chan; /* Channel # */
119 u_char rc_ier; /* intr. enable reg */
120 u_char rc_msvr; /* modem sig. status */
121 u_char rc_cor2; /* options reg */
122 u_char rc_pendcmd; /* special cmd pending */
123 u_int rc_dtrwait; /* dtr timeout */
124 u_int rc_dcdwaits; /* how many waits DCD in open */
125 u_char rc_hotchar; /* end packed optimize */
126 struct tty *rc_tp; /* tty struct */
127 u_char *rc_iptr; /* Chars input buffer */
128 u_char *rc_hiwat; /* hi-water mark */
129 u_char *rc_bufend; /* end of buffer */
130 u_char *rc_optr; /* ptr in output buf */
131 u_char *rc_obufend; /* end of output buf */
132 struct callout rc_dtr_ch;
133 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
134 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
135 } rc_chans[NRC * CD180_NCHAN];
137 static int rc_scheduled_event = 0;
138 static struct callout rc_wakeup_ch;
141 static struct tty rc_tty[NRC * CD180_NCHAN];
142 static const int nrc_tty = NRC * CD180_NCHAN;
145 #define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
146 #define RC_ACTOUT 0x0002 /* Dial-out port active */
147 #define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
148 #define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
149 #define RC_DORXFER 0x0010 /* RXFER event planned */
150 #define RC_DOXXFER 0x0020 /* XXFER event planned */
151 #define RC_MODCHG 0x0040 /* Modem status changed */
152 #define RC_OSUSP 0x0080 /* Output suspended */
153 #define RC_OSBUSY 0x0100 /* start() routine in progress */
154 #define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
155 #define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
156 #define RC_SEND_RDY 0x0800 /* ready to send */
158 /* Table for translation of RCSR status bits to internal form */
159 static int rc_rcsrt[16] = {
161 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
162 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
163 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
164 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
165 TTY_BI|TTY_PE|TTY_FE|TTY_OE
168 /* Static prototypes */
169 static inthand2_t rcintr;
170 static void rc_hwreset (int, int, unsigned int);
171 static int rc_test (int, int);
172 static void rc_discard_output (struct rc_chans *);
173 static void rc_hardclose (struct rc_chans *);
174 static int rc_modctl (struct rc_chans *, int, int);
175 static void rc_start (struct tty *);
176 static void rc_stop (struct tty *, int rw);
177 static int rc_param (struct tty *, struct termios *);
178 static inthand2_t rcpoll;
179 static void rc_reinit (struct rc_softc *);
181 static void printrcflags();
183 static timeout_t rc_dtrwakeup;
184 static timeout_t rc_wakeup;
185 static void disc_optim (struct tty *tp, struct termios *t, struct rc_chans *);
186 static void rc_wait0 (int nec, int unit, int chan, int line);
188 /**********************************************/
190 /* Quick device probing */
192 rcprobe(struct isa_device *dvp)
194 int irq = ffs(dvp->id_irq) - 1;
195 int nec = dvp->id_iobase;
197 if (dvp->id_unit > NRC)
199 if (!RC_VALIDADDR(nec)) {
200 kprintf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
203 if (!RC_VALIDIRQ(irq)) {
204 kprintf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
207 lwkt_gettoken(&tty_token);
208 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
209 rcout(CD180_PPRH, 0x11);
210 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11) {
211 lwkt_reltoken(&tty_token);
214 /* Now, test the board more thoroughly, with diagnostic */
215 if (rc_test(nec, dvp->id_unit)) {
216 lwkt_reltoken(&tty_token);
219 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
220 lwkt_reltoken(&tty_token);
225 rcattach(struct isa_device *dvp)
227 int chan, nec = dvp->id_iobase;
228 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
229 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
230 static int rc_started = 0;
233 lwkt_gettoken(&tty_token);
234 dvp->id_intr = rcintr;
236 /* Thorooughly test the device */
237 if (rcb->rcb_probed != RC_PROBED) {
238 lwkt_reltoken(&tty_token);
243 rcb->rcb_baserc = rc;
244 rcb->rcb_unit = dvp->id_unit;
245 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
246 kprintf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
247 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
249 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
250 callout_init_mp(&rc->rc_dtr_ch);
253 rc->rc_iptr = rc->rc_ibuf;
254 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
255 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
256 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
257 rc->rc_cor2 = rc->rc_pendcmd = 0;
258 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
259 rc->rc_dtrwait = 3 * hz;
262 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
264 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
265 tp->t_cflag = TTYDEF_CFLAG;
266 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
268 rcb->rcb_probed = RC_ATTACHED;
270 register_swi_mp(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
271 callout_init_mp(&rc_wakeup_ch);
275 lwkt_reltoken(&tty_token);
279 /* RC interrupt handling */
281 rcintr(void *arg, void *frame)
284 struct rc_softc *rcb = &rc_softc[unit];
287 u_char val, iack, bsr, ucnt, *optr;
288 int good_data, t_state;
290 lwkt_gettoken(&tty_token);
291 if (rcb->rcb_probed != RC_ATTACHED) {
292 kprintf("rc%d: bogus interrupt\n", unit);
293 lwkt_reltoken(&tty_token);
298 bsr = ~(rcin(RC_BSR));
300 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
301 kprintf("rc%d: extra interrupt\n", unit);
302 rcout(CD180_EOIR, 0);
303 lwkt_reltoken(&tty_token);
307 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
308 #ifdef RCDEBUG_DETAILED
309 kprintf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
310 (bsr & RC_BSR_TOUT)?"TOUT ":"",
311 (bsr & RC_BSR_RXINT)?"RXINT ":"",
312 (bsr & RC_BSR_TXINT)?"TXINT ":"",
313 (bsr & RC_BSR_MOINT)?"MOINT":"");
315 if (bsr & RC_BSR_TOUT) {
316 kprintf("rc%d: hardware failure, reset board\n", unit);
319 lwkt_reltoken(&tty_token);
322 if (bsr & RC_BSR_RXINT) {
323 iack = rcin(RC_PILR_RX);
324 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
325 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
326 kprintf("rc%d: fake rxint: %02x\n", unit, iack);
329 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
330 t_state = rc->rc_tp->t_state;
331 /* Do RTS flow control stuff */
332 if ( (rc->rc_flags & RC_RTSFLOW)
333 || !(t_state & TS_ISOPEN)
335 if ( ( !(t_state & TS_ISOPEN)
336 || (t_state & TS_TBLOCK)
338 && (rc->rc_msvr & MSVR_RTS)
341 rc->rc_msvr &= ~MSVR_RTS);
342 else if (!(rc->rc_msvr & MSVR_RTS))
344 rc->rc_msvr |= MSVR_RTS);
346 ucnt = rcin(CD180_RDCR) & 0xF;
349 if (t_state & TS_ISOPEN) {
350 /* check for input buffer overflow */
351 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
353 ucnt = rc->rc_bufend - rc->rc_iptr;
355 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
356 rc->rc_flags |= RC_WAS_BUFOVFL;
357 rc_scheduled_event++;
361 /* check foor good data */
364 val = rcin(CD180_RDR);
366 optr[INPUT_FLAGS_SHIFT] = 0;
368 rc_scheduled_event++;
369 if (val != 0 && val == rc->rc_hotchar)
373 /* Store also status data */
375 iack = rcin(CD180_RCSR);
376 if (iack & RCSR_Timeout)
378 if ( (iack & RCSR_OE)
379 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
380 rc->rc_flags |= RC_WAS_SILOVFL;
381 rc_scheduled_event++;
383 val = rcin(CD180_RDR);
385 Don't store PE if IGNPAR and BREAK if IGNBRK,
386 this hack allows "raw" tty optimization
387 works even if IGN* is set.
389 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
390 || ((!(iack & (RCSR_PE|RCSR_FE))
391 || !(rc->rc_tp->t_iflag & IGNPAR))
392 && (!(iack & RCSR_Break)
393 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
394 if ( (iack & (RCSR_PE|RCSR_FE))
395 && (t_state & TS_CAN_BYPASS_L_RINT)
398 && (rc->rc_tp->t_iflag & INPCK))))
400 else if (val != 0 && val == rc->rc_hotchar)
403 optr[INPUT_FLAGS_SHIFT] = iack;
405 rc_scheduled_event++;
410 rc->rc_flags |= RC_DORXFER;
413 /* Clear FIFO if necessary */
414 while (resid-- > 0) {
416 iack = rcin(CD180_RCSR);
419 if (iack & RCSR_Timeout)
421 (void) rcin(CD180_RDR);
425 if (bsr & RC_BSR_MOINT) {
426 iack = rcin(RC_PILR_MODEM);
427 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
428 kprintf("rc%d: fake moint: %02x\n", unit, iack);
431 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
432 iack = rcin(CD180_MCR);
433 rc->rc_msvr = rcin(CD180_MSVR);
436 printrcflags(rc, "moint");
438 if (rc->rc_flags & RC_CTSFLOW) {
439 if (rc->rc_msvr & MSVR_CTS)
440 rc->rc_flags |= RC_SEND_RDY;
442 rc->rc_flags &= ~RC_SEND_RDY;
444 rc->rc_flags |= RC_SEND_RDY;
445 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
446 rc_scheduled_event += LOTS_OF_EVENTS;
447 rc->rc_flags |= RC_MODCHG;
452 if (bsr & RC_BSR_TXINT) {
453 iack = rcin(RC_PILR_TX);
454 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
455 kprintf("rc%d: fake txint: %02x\n", unit, iack);
458 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
459 if ( (rc->rc_flags & RC_OSUSP)
460 || !(rc->rc_flags & RC_SEND_RDY)
463 /* Handle breaks and other stuff */
464 if (rc->rc_pendcmd) {
465 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
466 rcout(CD180_TDR, CD180_C_ESC);
467 rcout(CD180_TDR, rc->rc_pendcmd);
468 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
473 resid = rc->rc_obufend - optr;
474 if (resid > CD180_NFIFO)
477 rcout(CD180_TDR, *optr++);
480 /* output completed? */
481 if (optr >= rc->rc_obufend) {
482 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
484 kprintf("rc%d/%d: output completed\n", unit, rc->rc_chan);
486 if (!(rc->rc_flags & RC_DOXXFER)) {
487 rc_scheduled_event += LOTS_OF_EVENTS;
488 rc->rc_flags |= RC_DOXXFER;
494 rcout(CD180_EOIR, 0); /* end of interrupt */
496 bsr = ~(rcin(RC_BSR));
498 lwkt_reltoken(&tty_token);
501 /* Feed characters to output buffer */
503 rc_start(struct tty *tp)
505 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
506 int nec = rc->rc_rcb->rcb_addr;
508 lwkt_gettoken(&tty_token);
509 if (rc->rc_flags & RC_OSBUSY) {
510 lwkt_reltoken(&tty_token);
514 rc->rc_flags |= RC_OSBUSY;
516 if (tp->t_state & TS_TTSTOP)
517 rc->rc_flags |= RC_OSUSP;
519 rc->rc_flags &= ~RC_OSUSP;
520 /* Do RTS flow control stuff */
521 if ( (rc->rc_flags & RC_RTSFLOW)
522 && (tp->t_state & TS_TBLOCK)
523 && (rc->rc_msvr & MSVR_RTS)
525 rcout(CD180_CAR, rc->rc_chan);
526 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
527 } else if (!(rc->rc_msvr & MSVR_RTS)) {
528 rcout(CD180_CAR, rc->rc_chan);
529 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
532 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
535 printrcflags(rc, "rcstart");
539 kprintf("rcstart: outq = %d obuf = %d\n",
540 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
542 if (tp->t_state & TS_BUSY)
543 goto out; /* output still in progress ... */
545 if (tp->t_outq.c_cc > 0) {
548 tp->t_state |= TS_BUSY;
549 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
551 rc->rc_optr = rc->rc_obuf;
552 rc->rc_obufend = rc->rc_optr + ocnt;
554 if (!(rc->rc_ier & IER_TxRdy)) {
556 kprintf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
558 rcout(CD180_CAR, rc->rc_chan);
559 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
563 rc->rc_flags &= ~RC_OSBUSY;
565 lwkt_reltoken(&tty_token);
568 /* Handle delayed events. */
570 rcpoll(void *dummy, void *frame)
573 struct rc_softc *rcb;
576 int chan, icnt, nec, unit;
578 lwkt_gettoken(&tty_token);
579 if (rc_scheduled_event == 0) {
580 lwkt_reltoken(&tty_token);
584 for (unit = 0; unit < NRC; unit++) {
585 rcb = &rc_softc[unit];
586 rc = rcb->rcb_baserc;
587 nec = rc->rc_rcb->rcb_addr;
588 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
591 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
592 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
593 printrcflags(rc, "rcevent");
595 if (rc->rc_flags & RC_WAS_BUFOVFL) {
597 rc->rc_flags &= ~RC_WAS_BUFOVFL;
598 rc_scheduled_event--;
600 kprintf("rc%d/%d: interrupt-level buffer overflow\n",
603 if (rc->rc_flags & RC_WAS_SILOVFL) {
605 rc->rc_flags &= ~RC_WAS_SILOVFL;
606 rc_scheduled_event--;
608 kprintf("rc%d/%d: silo overflow\n",
611 if (rc->rc_flags & RC_MODCHG) {
613 rc->rc_flags &= ~RC_MODCHG;
614 rc_scheduled_event -= LOTS_OF_EVENTS;
616 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
618 if (rc->rc_flags & RC_DORXFER) {
620 rc->rc_flags &= ~RC_DORXFER;
622 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
623 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
628 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
629 rc->rc_iptr = rc->rc_ibuf;
630 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
631 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
633 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
634 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
636 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
638 if ( (rc->rc_flags & RC_RTSFLOW)
639 && (tp->t_state & TS_ISOPEN)
640 && !(tp->t_state & TS_TBLOCK)
641 && !(rc->rc_msvr & MSVR_RTS)
643 rcout(CD180_CAR, chan);
645 rc->rc_msvr |= MSVR_RTS);
647 rc_scheduled_event -= icnt;
651 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
654 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
655 && !(tp->t_state & TS_LOCAL)) {
656 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
657 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
658 && !(tp->t_state & TS_TBLOCK))
663 if (b_to_q(tptr, icnt, &tp->t_rawq))
664 kprintf("rc%d/%d: tty-level buffer overflow\n",
667 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
668 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
669 tp->t_state &= ~TS_TTSTOP;
670 tp->t_lflag &= ~FLUSHO;
674 for (; tptr < eptr; tptr++)
675 (*linesw[tp->t_line].l_rint)
677 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
681 if (rc->rc_flags & RC_DOXXFER) {
683 rc_scheduled_event -= LOTS_OF_EVENTS;
684 rc->rc_flags &= ~RC_DOXXFER;
685 rc->rc_tp->t_state &= ~TS_BUSY;
687 (*linesw[tp->t_line].l_start)(tp);
690 if (rc_scheduled_event == 0)
693 if (rc_scheduled_event >= LOTS_OF_EVENTS)
695 lwkt_reltoken(&tty_token);
699 rc_stop(struct tty *tp, int rw)
701 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
704 lwkt_gettoken(&tty_token);
706 kprintf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
707 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
710 rc_discard_output(rc);
713 rc->rc_flags &= ~RC_DORXFER;
715 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
716 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
717 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
720 rc->rc_iptr = rc->rc_ibuf;
722 rc_scheduled_event -= eptr - tptr;
724 if (tp->t_state & TS_TTSTOP)
725 rc->rc_flags |= RC_OSUSP;
727 rc->rc_flags &= ~RC_OSUSP;
729 lwkt_reltoken(&tty_token);
733 rcopen(struct dev_open_args *ap)
735 cdev_t dev = ap->a_head.a_dev;
738 int unit, nec, error = 0;
740 lwkt_gettoken(&tty_token);
741 unit = GET_UNIT(dev);
742 if (unit >= NRC * CD180_NCHAN) {
743 lwkt_reltoken(&tty_token);
746 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED) {
747 lwkt_reltoken(&tty_token);
750 rc = &rc_chans[unit];
753 nec = rc->rc_rcb->rcb_addr;
755 kprintf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
760 while (rc->rc_flags & RC_DTR_OFF) {
761 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
765 if (tp->t_state & TS_ISOPEN) {
767 if (!(rc->rc_flags & RC_ACTOUT)) {
772 if (rc->rc_flags & RC_ACTOUT) {
773 if (ap->a_oflags & O_NONBLOCK) {
777 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
783 if (tp->t_state & TS_XCLUDE &&
784 priv_check_cred(ap->a_cred, PRIV_ROOT, 0)) {
789 tp->t_oproc = rc_start;
790 tp->t_param = rc_param;
791 tp->t_stop = rc_stop;
795 tp->t_cflag |= CLOCAL;
797 tp->t_cflag &= ~CLOCAL;
799 error = rc_param(tp, &tp->t_termios);
802 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
804 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
805 (*linesw[tp->t_line].l_modem)(tp, 1);
807 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
808 && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
810 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
816 error = (*linesw[tp->t_line].l_open)(dev, tp);
817 disc_optim(tp, &tp->t_termios, rc);
818 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
819 rc->rc_flags |= RC_ACTOUT;
823 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
826 lwkt_reltoken(&tty_token);
831 rcclose(struct dev_close_args *ap)
833 cdev_t dev = ap->a_head.a_dev;
836 int unit = GET_UNIT(dev);
838 lwkt_gettoken(&tty_token);
839 if (unit >= NRC * CD180_NCHAN) {
840 lwkt_reltoken(&tty_token);
843 rc = &rc_chans[unit];
846 kprintf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
849 (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
850 disc_optim(tp, &tp->t_termios, rc);
851 rc_stop(tp, FREAD | FWRITE);
855 lwkt_reltoken(&tty_token);
860 * NOTE: Must be called with tty_token held
863 rc_hardclose(struct rc_chans *rc)
865 int nec = rc->rc_rcb->rcb_addr;
866 struct tty *tp = rc->rc_tp;
868 ASSERT_LWKT_TOKEN_HELD(&tty_token);
870 rcout(CD180_CAR, rc->rc_chan);
872 /* Disable rx/tx intrs */
873 rcout(CD180_IER, rc->rc_ier = 0);
874 if ( (tp->t_cflag & HUPCL)
875 || (!(rc->rc_flags & RC_ACTOUT)
876 && !(rc->rc_msvr & MSVR_CD)
877 && !(tp->t_cflag & CLOCAL))
878 || !(tp->t_state & TS_ISOPEN)
880 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
881 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
882 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
883 if (rc->rc_dtrwait) {
884 callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
886 rc->rc_flags |= RC_DTR_OFF;
889 rc->rc_flags &= ~RC_ACTOUT;
890 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
891 wakeup(TSA_CARR_ON(tp));
895 /* Reset the bastard */
897 * NOTE: Must be called with tty_token held
900 rc_hwreset(int unit, int nec, unsigned int chipid)
902 ASSERT_LWKT_TOKEN_HELD(&tty_token);
903 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
905 WAITFORCCR(unit, -1);
907 rcout(RC_CTOUT, 0); /* Clear timeout */
908 rcout(CD180_GIVR, chipid);
909 rcout(CD180_GICR, 0);
911 /* Set Prescaler Registers (1 msec) */
912 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
913 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
915 /* Initialize Priority Interrupt Level Registers */
916 rcout(CD180_PILR1, RC_PILR_MODEM);
917 rcout(CD180_PILR2, RC_PILR_TX);
918 rcout(CD180_PILR3, RC_PILR_RX);
924 /* Set channel parameters */
926 rc_param(struct tty *tp, struct termios *ts)
928 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
929 int nec = rc->rc_rcb->rcb_addr;
930 int idivs, odivs, val, cflag, iflag, lflag, inpflow;
932 lwkt_gettoken(&tty_token);
934 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
935 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
937 lwkt_reltoken(&tty_token);
940 if (ts->c_ispeed == 0)
941 ts->c_ispeed = ts->c_ospeed;
942 odivs = RC_BRD(ts->c_ospeed);
943 idivs = RC_BRD(ts->c_ispeed);
948 rcout(CD180_CAR, rc->rc_chan);
950 /* If speed == 0, hangup line */
951 if (ts->c_ospeed == 0) {
952 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
953 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
954 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
957 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
963 rcout(CD180_RBPRL, idivs & 0xFF);
964 rcout(CD180_RBPRH, idivs >> 8);
967 rcout(CD180_TBPRL, odivs & 0xFF);
968 rcout(CD180_TBPRH, odivs >> 8);
971 /* set timeout value */
972 if (ts->c_ispeed > 0) {
973 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
975 if ( !(lflag & ICANON)
976 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
977 && ts->c_cc[VTIME] * 10 > itm)
978 itm = ts->c_cc[VTIME] * 10;
980 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
983 switch (cflag & CSIZE) {
984 case CS5: val = COR1_5BITS; break;
985 case CS6: val = COR1_6BITS; break;
986 case CS7: val = COR1_7BITS; break;
988 case CS8: val = COR1_8BITS; break;
990 if (cflag & PARENB) {
994 if (!(cflag & INPCK))
1000 rcout(CD180_COR1, val);
1002 /* Set FIFO threshold */
1003 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
1005 if ( (iflag & IXOFF)
1006 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
1007 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
1013 val |= COR3_SCDE|COR3_FCT;
1015 rcout(CD180_COR3, val);
1017 /* Initialize on-chip automatic flow control */
1019 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
1020 if (cflag & CCTS_OFLOW) {
1021 rc->rc_flags |= RC_CTSFLOW;
1024 rc->rc_flags |= RC_SEND_RDY;
1025 if (tp->t_state & TS_TTSTOP)
1026 rc->rc_flags |= RC_OSUSP;
1028 rc->rc_flags &= ~RC_OSUSP;
1029 if (cflag & CRTS_IFLOW)
1030 rc->rc_flags |= RC_RTSFLOW;
1032 rc->rc_flags &= ~RC_RTSFLOW;
1035 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1036 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1037 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1043 rcout(CD180_COR2, rc->rc_cor2 = val);
1045 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1046 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1048 disc_optim(tp, ts, rc);
1051 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1052 if (cflag & CCTS_OFLOW)
1054 rcout(CD180_MCOR1, val);
1056 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1057 if (cflag & CCTS_OFLOW)
1059 rcout(CD180_MCOR2, val);
1061 /* enable i/o and interrupts */
1062 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1063 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1064 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1066 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1067 if (cflag & CCTS_OFLOW)
1068 rc->rc_ier |= IER_CTS;
1070 rc->rc_ier |= IER_RxData;
1071 if (tp->t_state & TS_BUSY)
1072 rc->rc_ier |= IER_TxRdy;
1073 if (ts->c_ospeed != 0)
1074 rc_modctl(rc, TIOCM_DTR, DMBIS);
1075 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1076 rc->rc_flags |= RC_SEND_RDY;
1077 rcout(CD180_IER, rc->rc_ier);
1079 lwkt_reltoken(&tty_token);
1083 /* Re-initialize board after bogus interrupts */
1085 * NOTE: Must be called with tty_token held
1088 rc_reinit(struct rc_softc *rcb)
1090 struct rc_chans *rc, *rce;
1093 ASSERT_LWKT_TOKEN_HELD(&tty_token);
1094 nec = rcb->rcb_addr;
1095 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1096 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1097 rce = rc + CD180_NCHAN;
1098 for (; rc < rce; rc++)
1099 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1103 rcioctl(struct dev_ioctl_args *ap)
1105 cdev_t dev = ap->a_head.a_dev;
1106 struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
1108 struct tty *tp = rc->rc_tp;
1110 lwkt_gettoken(&tty_token);
1111 error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1112 ap->a_fflag, ap->a_cred);
1113 if (error != ENOIOCTL) {
1114 lwkt_reltoken(&tty_token);
1117 error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
1118 disc_optim(tp, &tp->t_termios, rc);
1119 if (error != ENOIOCTL) {
1120 lwkt_reltoken(&tty_token);
1125 switch (ap->a_cmd) {
1127 rc->rc_pendcmd = CD180_C_SBRK;
1131 rc->rc_pendcmd = CD180_C_EBRK;
1135 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1139 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1143 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
1147 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
1151 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
1155 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
1159 error = priv_check_cred(ap->a_cred, PRIV_ROOT, 0);
1162 lwkt_reltoken(&tty_token);
1165 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
1169 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
1174 lwkt_reltoken(&tty_token);
1178 lwkt_reltoken(&tty_token);
1183 /* Modem control routines */
1185 * NOTE: Must be called with tty_token held
1188 rc_modctl(struct rc_chans *rc, int bits, int cmd)
1190 int nec = rc->rc_rcb->rcb_addr;
1191 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1193 ASSERT_LWKT_TOKEN_HELD(&tty_token);
1194 rcout(CD180_CAR, rc->rc_chan);
1198 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1199 ~(*dtr |= 1 << rc->rc_chan) :
1200 ~(*dtr &= ~(1 << rc->rc_chan)));
1201 msvr = rcin(CD180_MSVR);
1202 if (bits & TIOCM_RTS)
1206 if (bits & TIOCM_DTR)
1210 rcout(CD180_MSVR, msvr);
1214 if (bits & TIOCM_DTR)
1215 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1216 msvr = rcin(CD180_MSVR);
1217 if (bits & TIOCM_RTS)
1219 if (bits & TIOCM_DTR)
1221 rcout(CD180_MSVR, msvr);
1226 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1228 if (msvr & MSVR_RTS)
1230 if (msvr & MSVR_CTS)
1232 if (msvr & MSVR_DSR)
1234 if (msvr & MSVR_DTR)
1238 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1243 if (bits & TIOCM_DTR)
1244 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1245 msvr = rcin(CD180_MSVR);
1246 if (bits & TIOCM_RTS)
1248 if (bits & TIOCM_DTR)
1250 rcout(CD180_MSVR, msvr);
1253 rc->rc_msvr = rcin(CD180_MSVR);
1257 /* Test the board. */
1259 rc_test(int nec, int unit)
1263 unsigned int iack, chipid;
1264 unsigned short divs;
1265 static u_char ctest[] = "\377\125\252\045\244\0\377";
1268 kprintf("rc%d: ", unit); kprintf s ; kprintf("\n"); \
1269 crit_exit(); return 1; }
1272 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1273 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1274 int rxptr; /* RX pointer */
1275 int txptr; /* TX pointer */
1276 } tchans[CD180_NCHAN];
1278 lwkt_gettoken(&tty_token);
1283 /* First, reset board to inital state */
1284 rc_hwreset(unit, nec, chipid);
1286 divs = RC_BRD(19200);
1288 /* Initialize channels */
1289 for (chan = 0; chan < CD180_NCHAN; chan++) {
1291 /* Select and reset channel */
1292 rcout(CD180_CAR, chan);
1293 CCRCMD(unit, chan, CCR_ResetChan);
1294 WAITFORCCR(unit, chan);
1297 rcout(CD180_RBPRL, divs & 0xFF);
1298 rcout(CD180_RBPRH, divs >> 8);
1299 rcout(CD180_TBPRL, divs & 0xFF);
1300 rcout(CD180_TBPRH, divs >> 8);
1302 /* set timeout value */
1303 rcout(CD180_RTPR, 0);
1305 /* Establish local loopback */
1306 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1307 rcout(CD180_COR2, COR2_LLM);
1308 rcout(CD180_COR3, CD180_NFIFO);
1309 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1310 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1311 WAITFORCCR(unit, chan);
1312 rcout(CD180_MSVR, MSVR_RTS);
1314 /* Fill TXBUF with test data */
1315 for (i = 0; i < CD180_NFIFO; i++) {
1316 tchans[chan].txbuf[i] = ctest[i];
1317 tchans[chan].rxbuf[i] = 0;
1319 tchans[chan].txptr = tchans[chan].rxptr = 0;
1321 /* Now, start transmit */
1322 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1324 /* Pseudo-interrupt poll stuff */
1325 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1326 i = ~(rcin(RC_BSR));
1327 if (i & RC_BSR_TOUT)
1328 ERR(("BSR timeout bit set\n"))
1329 else if (i & RC_BSR_TXINT) {
1330 iack = rcin(RC_PILR_TX);
1331 if (iack != (GIVR_IT_TDI | chipid))
1332 ERR(("Bad TX intr ack (%02x != %02x)\n",
1333 iack, GIVR_IT_TDI | chipid));
1334 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1335 /* If no more data to transmit, disable TX intr */
1336 if (tchans[chan].txptr >= CD180_NFIFO) {
1337 iack = rcin(CD180_IER);
1338 rcout(CD180_IER, iack & ~IER_TxMpty);
1340 for (iack = tchans[chan].txptr;
1341 iack < CD180_NFIFO; iack++)
1343 tchans[chan].txbuf[iack]);
1344 tchans[chan].txptr = iack;
1346 rcout(CD180_EOIR, 0);
1347 } else if (i & RC_BSR_RXINT) {
1350 iack = rcin(RC_PILR_RX);
1351 if (iack != (GIVR_IT_RGDI | chipid) &&
1352 iack != (GIVR_IT_REI | chipid))
1353 ERR(("Bad RX intr ack (%02x != %02x)\n",
1354 iack, GIVR_IT_RGDI | chipid))
1355 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1356 ucnt = rcin(CD180_RDCR) & 0xF;
1357 while (ucnt-- > 0) {
1358 iack = rcin(CD180_RCSR);
1359 if (iack & RCSR_Timeout)
1362 ERR(("Bad char chan %d (RCSR = %02X)\n",
1364 if (tchans[chan].rxptr > CD180_NFIFO)
1365 ERR(("Got extra chars chan %d\n",
1367 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1370 rcout(CD180_EOIR, 0);
1373 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1374 if (tchans[chan].rxptr >= CD180_NFIFO)
1376 if (iack == CD180_NCHAN)
1379 for (chan = 0; chan < CD180_NCHAN; chan++) {
1380 /* Select and reset channel */
1381 rcout(CD180_CAR, chan);
1382 CCRCMD(unit, chan, CCR_ResetChan);
1386 ERR(("looses characters during local loopback\n"))
1387 /* Now, check data */
1388 for (chan = 0; chan < CD180_NCHAN; chan++)
1389 for (i = 0; i < CD180_NFIFO; i++)
1390 if (ctest[i] != tchans[chan].rxbuf[i])
1391 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1392 chan, i, ctest[i], tchans[chan].rxbuf[i]))
1394 lwkt_reltoken(&tty_token);
1400 printrcflags(struct rc_chans *rc, char *comment)
1402 u_short f = rc->rc_flags;
1403 int nec = rc->rc_rcb->rcb_addr;
1405 kprintf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1406 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1407 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1408 (f & RC_ACTOUT) ?"ACTOUT " :"",
1409 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1410 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1411 (f & RC_DORXFER)?"DORXFER " :"",
1412 (f & RC_DOXXFER)?"DOXXFER " :"",
1413 (f & RC_MODCHG) ?"MODCHG " :"",
1414 (f & RC_OSUSP) ?"OSUSP " :"",
1415 (f & RC_OSBUSY) ?"OSBUSY " :"",
1416 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1417 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1418 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1420 rcout(CD180_CAR, rc->rc_chan);
1422 kprintf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1423 rc->rc_rcb->rcb_unit, rc->rc_chan,
1428 #endif /* RCDEBUG */
1431 rc_dtrwakeup(void *chan)
1433 struct rc_chans *rc;
1435 lwkt_gettoken(&tty_token);
1436 rc = (struct rc_chans *)chan;
1437 rc->rc_flags &= ~RC_DTR_OFF;
1438 wakeup(&rc->rc_dtrwait);
1439 lwkt_reltoken(&tty_token);
1443 rc_discard_output(struct rc_chans *rc)
1445 lwkt_gettoken(&tty_token);
1447 if (rc->rc_flags & RC_DOXXFER) {
1448 rc_scheduled_event -= LOTS_OF_EVENTS;
1449 rc->rc_flags &= ~RC_DOXXFER;
1451 rc->rc_optr = rc->rc_obufend;
1452 rc->rc_tp->t_state &= ~TS_BUSY;
1454 ttwwakeup(rc->rc_tp);
1455 lwkt_reltoken(&tty_token);
1459 rc_wakeup(void *chan)
1461 lwkt_gettoken(&tty_token);
1462 if (rc_scheduled_event != 0) {
1467 callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1468 lwkt_reltoken(&tty_token);
1472 disc_optim(struct tty *tp, struct termios *t, struct rc_chans *rc)
1475 lwkt_gettoken(&tty_token);
1476 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1477 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1478 && (!(t->c_iflag & PARMRK)
1479 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1480 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1481 && linesw[tp->t_line].l_rint == ttyinput)
1482 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1484 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1485 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1486 lwkt_reltoken(&tty_token);
1490 rc_wait0(int nec, int unit, int chan, int line)
1494 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1497 kprintf("rc%d/%d: channel command timeout, rc.c line: %d\n",