2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/ig_hal/e1000_dragonfly.h>
112 #include <dev/netif/emx/if_emx.h>
117 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
119 if (sc->rss_debug >= lvl) \
120 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
122 #else /* !EMX_RSS_DEBUG */
123 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
124 #endif /* EMX_RSS_DEBUG */
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 EMX_DEVICE(PCH_LPT_I217_LM),
166 EMX_DEVICE(PCH_LPT_I217_V),
167 EMX_DEVICE(PCH_LPTLP_I218_LM),
168 EMX_DEVICE(PCH_LPTLP_I218_V),
169 EMX_DEVICE(PCH_I218_LM2),
170 EMX_DEVICE(PCH_I218_V2),
171 EMX_DEVICE(PCH_I218_LM3),
172 EMX_DEVICE(PCH_I218_V3),
174 /* required last entry */
178 static int emx_probe(device_t);
179 static int emx_attach(device_t);
180 static int emx_detach(device_t);
181 static int emx_shutdown(device_t);
182 static int emx_suspend(device_t);
183 static int emx_resume(device_t);
185 static void emx_init(void *);
186 static void emx_stop(struct emx_softc *);
187 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
188 static void emx_start(struct ifnet *, struct ifaltq_subque *);
190 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
191 static void emx_npoll_status(struct ifnet *);
192 static void emx_npoll_tx(struct ifnet *, void *, int);
193 static void emx_npoll_rx(struct ifnet *, void *, int);
195 static void emx_watchdog(struct ifaltq_subque *);
196 static void emx_media_status(struct ifnet *, struct ifmediareq *);
197 static int emx_media_change(struct ifnet *);
198 static void emx_timer(void *);
199 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
200 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
201 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
203 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
207 static void emx_intr(void *);
208 static void emx_intr_mask(void *);
209 static void emx_intr_body(struct emx_softc *, boolean_t);
210 static void emx_rxeof(struct emx_rxdata *, int);
211 static void emx_txeof(struct emx_txdata *);
212 static void emx_tx_collect(struct emx_txdata *);
213 static void emx_tx_purge(struct emx_softc *);
214 static void emx_enable_intr(struct emx_softc *);
215 static void emx_disable_intr(struct emx_softc *);
217 static int emx_dma_alloc(struct emx_softc *);
218 static void emx_dma_free(struct emx_softc *);
219 static void emx_init_tx_ring(struct emx_txdata *);
220 static int emx_init_rx_ring(struct emx_rxdata *);
221 static void emx_free_tx_ring(struct emx_txdata *);
222 static void emx_free_rx_ring(struct emx_rxdata *);
223 static int emx_create_tx_ring(struct emx_txdata *);
224 static int emx_create_rx_ring(struct emx_rxdata *);
225 static void emx_destroy_tx_ring(struct emx_txdata *, int);
226 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
227 static int emx_newbuf(struct emx_rxdata *, int, int);
228 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
229 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
230 uint32_t *, uint32_t *);
231 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
232 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
233 uint32_t *, uint32_t *);
234 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
236 static int emx_is_valid_eaddr(const uint8_t *);
237 static int emx_reset(struct emx_softc *);
238 static void emx_setup_ifp(struct emx_softc *);
239 static void emx_init_tx_unit(struct emx_softc *);
240 static void emx_init_rx_unit(struct emx_softc *);
241 static void emx_update_stats(struct emx_softc *);
242 static void emx_set_promisc(struct emx_softc *);
243 static void emx_disable_promisc(struct emx_softc *);
244 static void emx_set_multi(struct emx_softc *);
245 static void emx_update_link_status(struct emx_softc *);
246 static void emx_smartspeed(struct emx_softc *);
247 static void emx_set_itr(struct emx_softc *, uint32_t);
248 static void emx_disable_aspm(struct emx_softc *);
250 static void emx_print_debug_info(struct emx_softc *);
251 static void emx_print_nvm_info(struct emx_softc *);
252 static void emx_print_hw_stats(struct emx_softc *);
254 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
255 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
256 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
257 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
258 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
261 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
263 static void emx_add_sysctl(struct emx_softc *);
265 static void emx_serialize_skipmain(struct emx_softc *);
266 static void emx_deserialize_skipmain(struct emx_softc *);
268 /* Management and WOL Support */
269 static void emx_get_mgmt(struct emx_softc *);
270 static void emx_rel_mgmt(struct emx_softc *);
271 static void emx_get_hw_control(struct emx_softc *);
272 static void emx_rel_hw_control(struct emx_softc *);
273 static void emx_enable_wol(device_t);
275 static device_method_t emx_methods[] = {
276 /* Device interface */
277 DEVMETHOD(device_probe, emx_probe),
278 DEVMETHOD(device_attach, emx_attach),
279 DEVMETHOD(device_detach, emx_detach),
280 DEVMETHOD(device_shutdown, emx_shutdown),
281 DEVMETHOD(device_suspend, emx_suspend),
282 DEVMETHOD(device_resume, emx_resume),
286 static driver_t emx_driver = {
289 sizeof(struct emx_softc),
292 static devclass_t emx_devclass;
294 DECLARE_DUMMY_MODULE(if_emx);
295 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
296 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
301 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
302 static int emx_rxd = EMX_DEFAULT_RXD;
303 static int emx_txd = EMX_DEFAULT_TXD;
304 static int emx_smart_pwr_down = 0;
305 static int emx_rxr = 0;
306 static int emx_txr = 1;
308 /* Controls whether promiscuous also shows bad packets */
309 static int emx_debug_sbp = 0;
311 static int emx_82573_workaround = 1;
312 static int emx_msi_enable = 1;
314 static char emx_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE;
316 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
317 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
318 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
319 TUNABLE_INT("hw.emx.txd", &emx_txd);
320 TUNABLE_INT("hw.emx.txr", &emx_txr);
321 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
322 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
323 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
324 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
325 TUNABLE_STR("hw.emx.flow_ctrl", emx_flowctrl, sizeof(emx_flowctrl));
327 /* Global used in WOL setup with multiport cards */
328 static int emx_global_quad_port_a = 0;
330 /* Set this to one to display debug statistics */
331 static int emx_display_debug_stats = 0;
333 #if !defined(KTR_IF_EMX)
334 #define KTR_IF_EMX KTR_ALL
336 KTR_INFO_MASTER(if_emx);
337 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
338 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
339 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
340 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
341 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
342 #define logif(name) KTR_LOG(if_emx_ ## name)
345 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
347 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
348 /* DD bit must be cleared */
349 rxd->rxd_staterr = 0;
353 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
355 /* Ignore Checksum bit is set */
356 if (staterr & E1000_RXD_STAT_IXSM)
359 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
361 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
363 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
364 E1000_RXD_STAT_TCPCS) {
365 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
367 CSUM_FRAG_NOT_CHECKED;
368 mp->m_pkthdr.csum_data = htons(0xffff);
372 static __inline struct pktinfo *
373 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
374 uint32_t mrq, uint32_t hash, uint32_t staterr)
376 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
377 case EMX_RXDMRQ_IPV4_TCP:
378 pi->pi_netisr = NETISR_IP;
380 pi->pi_l3proto = IPPROTO_TCP;
383 case EMX_RXDMRQ_IPV6_TCP:
384 pi->pi_netisr = NETISR_IPV6;
386 pi->pi_l3proto = IPPROTO_TCP;
389 case EMX_RXDMRQ_IPV4:
390 if (staterr & E1000_RXD_STAT_IXSM)
394 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
395 E1000_RXD_STAT_TCPCS) {
396 pi->pi_netisr = NETISR_IP;
398 pi->pi_l3proto = IPPROTO_UDP;
406 m->m_flags |= M_HASH;
407 m->m_pkthdr.hash = toeplitz_hash(hash);
412 emx_probe(device_t dev)
414 const struct emx_device *d;
417 vid = pci_get_vendor(dev);
418 did = pci_get_device(dev);
420 for (d = emx_devices; d->desc != NULL; ++d) {
421 if (vid == d->vid && did == d->did) {
422 device_set_desc(dev, d->desc);
423 device_set_async_attach(dev, TRUE);
431 emx_attach(device_t dev)
433 struct emx_softc *sc = device_get_softc(dev);
434 int error = 0, i, throttle, msi_enable, tx_ring_max;
436 uint16_t eeprom_data, device_id, apme_mask;
437 driver_intr_t *intr_func;
438 char flowctrl[IFM_ETH_FC_STRLEN];
440 int offset, offset_def;
446 for (i = 0; i < EMX_NRX_RING; ++i) {
447 sc->rx_data[i].sc = sc;
448 sc->rx_data[i].idx = i;
454 for (i = 0; i < EMX_NTX_RING; ++i) {
455 sc->tx_data[i].sc = sc;
456 sc->tx_data[i].idx = i;
460 * Initialize serializers
462 lwkt_serialize_init(&sc->main_serialize);
463 for (i = 0; i < EMX_NTX_RING; ++i)
464 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
465 for (i = 0; i < EMX_NRX_RING; ++i)
466 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
469 * Initialize serializer array
473 KKASSERT(i < EMX_NSERIALIZE);
474 sc->serializes[i++] = &sc->main_serialize;
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
478 KKASSERT(i < EMX_NSERIALIZE);
479 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
481 KKASSERT(i < EMX_NSERIALIZE);
482 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
483 KKASSERT(i < EMX_NSERIALIZE);
484 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
486 KKASSERT(i == EMX_NSERIALIZE);
488 ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK,
489 emx_media_change, emx_media_status);
490 callout_init_mp(&sc->timer);
492 sc->dev = sc->osdep.dev = dev;
495 * Determine hardware and mac type
497 sc->hw.vendor_id = pci_get_vendor(dev);
498 sc->hw.device_id = pci_get_device(dev);
499 sc->hw.revision_id = pci_get_revid(dev);
500 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
501 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
503 if (e1000_set_mac_type(&sc->hw))
506 /* Enable bus mastering */
507 pci_enable_busmaster(dev);
512 sc->memory_rid = EMX_BAR_MEM;
513 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
514 &sc->memory_rid, RF_ACTIVE);
515 if (sc->memory == NULL) {
516 device_printf(dev, "Unable to allocate bus resource: memory\n");
520 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
521 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
523 /* XXX This is quite goofy, it is not actually used */
524 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
527 * Don't enable MSI-X on 82574, see:
528 * 82574 specification update errata #15
530 * Don't enable MSI on 82571/82572, see:
531 * 82571/82572 specification update errata #63
533 msi_enable = emx_msi_enable;
535 (sc->hw.mac.type == e1000_82571 ||
536 sc->hw.mac.type == e1000_82572))
542 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
543 &sc->intr_rid, &intr_flags);
545 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
548 unshared = device_getenv_int(dev, "irq.unshared", 0);
550 sc->flags |= EMX_FLAG_SHARED_INTR;
552 device_printf(dev, "IRQ shared\n");
554 intr_flags &= ~RF_SHAREABLE;
556 device_printf(dev, "IRQ unshared\n");
560 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
562 if (sc->intr_res == NULL) {
563 device_printf(dev, "Unable to allocate bus resource: "
569 /* Save PCI command register for Shared Code */
570 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
571 sc->hw.back = &sc->osdep;
574 * For I217/I218, we need to map the flash memory and this
575 * must happen after the MAC is identified.
577 if (sc->hw.mac.type == e1000_pch_lpt) {
578 sc->flash_rid = EMX_BAR_FLASH;
580 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
581 &sc->flash_rid, RF_ACTIVE);
582 if (sc->flash == NULL) {
583 device_printf(dev, "Mapping of Flash failed\n");
587 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
588 sc->osdep.flash_bus_space_handle =
589 rman_get_bushandle(sc->flash);
592 * This is used in the shared code
593 * XXX this goof is actually not used.
595 sc->hw.flash_address = (uint8_t *)sc->flash;
598 /* Do Shared Code initialization */
599 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
600 device_printf(dev, "Setup of Shared code failed\n");
604 e1000_get_bus_info(&sc->hw);
606 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
607 sc->hw.phy.autoneg_wait_to_complete = FALSE;
608 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
611 * Interrupt throttle rate
613 throttle = device_getenv_int(dev, "int_throttle_ceil",
614 emx_int_throttle_ceil);
616 sc->int_throttle_ceil = 0;
619 throttle = EMX_DEFAULT_ITR;
621 /* Recalculate the tunable value to get the exact frequency. */
622 throttle = 1000000000 / 256 / throttle;
624 /* Upper 16bits of ITR is reserved and should be zero */
625 if (throttle & 0xffff0000)
626 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
628 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
631 e1000_init_script_state_82541(&sc->hw, TRUE);
632 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
635 if (sc->hw.phy.media_type == e1000_media_type_copper) {
636 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
637 sc->hw.phy.disable_polarity_correction = FALSE;
638 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
641 /* Set the frame limits assuming standard ethernet sized frames. */
642 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
644 /* This controls when hardware reports transmit completion status. */
645 sc->hw.mac.report_tx_early = 1;
647 /* Calculate # of RX rings */
648 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
649 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
652 * Calculate # of TX rings
655 * I217/I218 claims to have 2 TX queues
658 * Don't enable multiple TX queues on 82574; it always gives
659 * watchdog timeout on TX queue0, when multiple TCP streams are
660 * received. It was originally suspected that the hardware TX
661 * checksum offloading caused this watchdog timeout, since only
662 * TCP ACKs are sent during TCP receiving tests. However, even
663 * if the hardware TX checksum offloading is disable, TX queue0
664 * still will give watchdog.
667 if (sc->hw.mac.type == e1000_82571 ||
668 sc->hw.mac.type == e1000_82572 ||
669 sc->hw.mac.type == e1000_80003es2lan ||
670 sc->hw.mac.type == e1000_pch_lpt ||
671 sc->hw.mac.type == e1000_82574)
672 tx_ring_max = EMX_NTX_RING;
673 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
674 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
676 /* Allocate RX/TX rings' busdma(9) stuffs */
677 error = emx_dma_alloc(sc);
681 /* Allocate multicast array memory. */
682 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
685 /* Indicate SOL/IDER usage */
686 if (e1000_check_reset_block(&sc->hw)) {
688 "PHY reset is blocked due to SOL/IDER session.\n");
691 /* Disable EEE on I217/I218 */
692 sc->hw.dev_spec.ich8lan.eee_disable = 1;
695 * Start from a known state, this is important in reading the
696 * nvm and mac from that.
698 e1000_reset_hw(&sc->hw);
700 /* Make sure we have a good EEPROM before we read from it */
701 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
703 * Some PCI-E parts fail the first check due to
704 * the link being in sleep state, call it again,
705 * if it fails a second time its a real issue.
707 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
709 "The EEPROM Checksum Is Not Valid\n");
715 /* Copy the permanent MAC address out of the EEPROM */
716 if (e1000_read_mac_addr(&sc->hw) < 0) {
717 device_printf(dev, "EEPROM read error while reading MAC"
722 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
723 device_printf(dev, "Invalid MAC address\n");
728 /* Disable ULP support */
729 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
731 /* Determine if we have to control management hardware */
732 if (e1000_enable_mng_pass_thru(&sc->hw))
733 sc->flags |= EMX_FLAG_HAS_MGMT;
738 apme_mask = EMX_EEPROM_APME;
740 switch (sc->hw.mac.type) {
742 sc->flags |= EMX_FLAG_HAS_AMT;
747 case e1000_80003es2lan:
748 if (sc->hw.bus.func == 1) {
749 e1000_read_nvm(&sc->hw,
750 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
752 e1000_read_nvm(&sc->hw,
753 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
758 e1000_read_nvm(&sc->hw,
759 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
762 if (eeprom_data & apme_mask)
763 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
766 * We have the eeprom settings, now apply the special cases
767 * where the eeprom may be wrong or the board won't support
768 * wake on lan on a particular port
770 device_id = pci_get_device(dev);
772 case E1000_DEV_ID_82571EB_FIBER:
774 * Wake events only supported on port A for dual fiber
775 * regardless of eeprom setting
777 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
782 case E1000_DEV_ID_82571EB_QUAD_COPPER:
783 case E1000_DEV_ID_82571EB_QUAD_FIBER:
784 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
785 /* if quad port sc, disable WoL on all but port A */
786 if (emx_global_quad_port_a != 0)
788 /* Reset for multiple quad port adapters */
789 if (++emx_global_quad_port_a == 4)
790 emx_global_quad_port_a = 0;
794 /* XXX disable wol */
799 * NPOLLING RX CPU offset
801 if (sc->rx_ring_cnt == ncpus2) {
804 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
805 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
806 if (offset >= ncpus2 ||
807 offset % sc->rx_ring_cnt != 0) {
808 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
813 sc->rx_npoll_off = offset;
816 * NPOLLING TX CPU offset
818 if (sc->tx_ring_cnt == ncpus2) {
821 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
822 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
823 if (offset >= ncpus2 ||
824 offset % sc->tx_ring_cnt != 0) {
825 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
830 sc->tx_npoll_off = offset;
832 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
834 /* Setup flow control. */
835 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
837 sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
839 /* Setup OS specific network interface */
842 /* Add sysctl tree, must after em_setup_ifp() */
845 /* Reset the hardware */
846 error = emx_reset(sc);
849 * Some 82573 parts fail the first reset, call it again,
850 * if it fails a second time its a real issue.
852 error = emx_reset(sc);
854 device_printf(dev, "Unable to reset the hardware\n");
855 ether_ifdetach(&sc->arpcom.ac_if);
860 /* Initialize statistics */
861 emx_update_stats(sc);
863 sc->hw.mac.get_link_status = 1;
864 emx_update_link_status(sc);
866 /* Non-AMT based hardware can now take control from firmware */
867 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
869 emx_get_hw_control(sc);
872 * Missing Interrupt Following ICR read:
874 * 82571/82572 specification update errata #76
875 * 82573 specification update errata #31
876 * 82574 specification update errata #12
878 intr_func = emx_intr;
879 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
880 (sc->hw.mac.type == e1000_82571 ||
881 sc->hw.mac.type == e1000_82572 ||
882 sc->hw.mac.type == e1000_82573 ||
883 sc->hw.mac.type == e1000_82574))
884 intr_func = emx_intr_mask;
886 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
887 &sc->intr_tag, &sc->main_serialize);
889 device_printf(dev, "Failed to register interrupt handler");
890 ether_ifdetach(&sc->arpcom.ac_if);
900 emx_detach(device_t dev)
902 struct emx_softc *sc = device_get_softc(dev);
904 if (device_is_attached(dev)) {
905 struct ifnet *ifp = &sc->arpcom.ac_if;
907 ifnet_serialize_all(ifp);
911 e1000_phy_hw_reset(&sc->hw);
914 emx_rel_hw_control(sc);
917 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
918 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
922 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
924 ifnet_deserialize_all(ifp);
927 } else if (sc->memory != NULL) {
928 emx_rel_hw_control(sc);
931 ifmedia_removeall(&sc->media);
932 bus_generic_detach(dev);
934 if (sc->intr_res != NULL) {
935 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
939 if (sc->intr_type == PCI_INTR_TYPE_MSI)
940 pci_release_msi(dev);
942 if (sc->memory != NULL) {
943 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
947 if (sc->flash != NULL) {
948 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
955 kfree(sc->mta, M_DEVBUF);
961 emx_shutdown(device_t dev)
963 return emx_suspend(dev);
967 emx_suspend(device_t dev)
969 struct emx_softc *sc = device_get_softc(dev);
970 struct ifnet *ifp = &sc->arpcom.ac_if;
972 ifnet_serialize_all(ifp);
977 emx_rel_hw_control(sc);
980 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
981 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
985 ifnet_deserialize_all(ifp);
987 return bus_generic_suspend(dev);
991 emx_resume(device_t dev)
993 struct emx_softc *sc = device_get_softc(dev);
994 struct ifnet *ifp = &sc->arpcom.ac_if;
997 ifnet_serialize_all(ifp);
1001 for (i = 0; i < sc->tx_ring_inuse; ++i)
1002 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1004 ifnet_deserialize_all(ifp);
1006 return bus_generic_resume(dev);
1010 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1012 struct emx_softc *sc = ifp->if_softc;
1013 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1014 struct mbuf *m_head;
1015 int idx = -1, nsegs = 0;
1017 KKASSERT(tdata->ifsq == ifsq);
1018 ASSERT_SERIALIZED(&tdata->tx_serialize);
1020 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1023 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1028 while (!ifsq_is_empty(ifsq)) {
1029 /* Now do we at least have a minimal? */
1030 if (EMX_IS_OACTIVE(tdata)) {
1031 emx_tx_collect(tdata);
1032 if (EMX_IS_OACTIVE(tdata)) {
1033 ifsq_set_oactive(ifsq);
1039 m_head = ifsq_dequeue(ifsq);
1043 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1044 IFNET_STAT_INC(ifp, oerrors, 1);
1045 emx_tx_collect(tdata);
1050 * TX interrupt are aggressively aggregated, so increasing
1051 * opackets at TX interrupt time will make the opackets
1052 * statistics vastly inaccurate; we do the opackets increment
1055 IFNET_STAT_INC(ifp, opackets, 1);
1057 if (nsegs >= tdata->tx_wreg_nsegs) {
1058 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1063 /* Send a copy of the frame to the BPF listener */
1064 ETHER_BPF_MTAP(ifp, m_head);
1066 /* Set timeout in case hardware has problems transmitting. */
1067 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1070 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1074 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1076 struct emx_softc *sc = ifp->if_softc;
1077 struct ifreq *ifr = (struct ifreq *)data;
1078 uint16_t eeprom_data = 0;
1079 int max_frame_size, mask, reinit;
1082 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1086 switch (sc->hw.mac.type) {
1089 * 82573 only supports jumbo frames
1090 * if ASPM is disabled.
1092 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1094 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1095 max_frame_size = ETHER_MAX_LEN;
1100 /* Limit Jumbo Frame size */
1105 case e1000_80003es2lan:
1106 max_frame_size = 9234;
1110 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1113 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1119 ifp->if_mtu = ifr->ifr_mtu;
1120 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1123 if (ifp->if_flags & IFF_RUNNING)
1128 if (ifp->if_flags & IFF_UP) {
1129 if ((ifp->if_flags & IFF_RUNNING)) {
1130 if ((ifp->if_flags ^ sc->if_flags) &
1131 (IFF_PROMISC | IFF_ALLMULTI)) {
1132 emx_disable_promisc(sc);
1133 emx_set_promisc(sc);
1138 } else if (ifp->if_flags & IFF_RUNNING) {
1141 sc->if_flags = ifp->if_flags;
1146 if (ifp->if_flags & IFF_RUNNING) {
1147 emx_disable_intr(sc);
1149 #ifdef IFPOLL_ENABLE
1150 if (!(ifp->if_flags & IFF_NPOLLING))
1152 emx_enable_intr(sc);
1157 /* Check SOL/IDER usage */
1158 if (e1000_check_reset_block(&sc->hw)) {
1159 device_printf(sc->dev, "Media change is"
1160 " blocked due to SOL/IDER session.\n");
1166 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1171 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1172 if (mask & IFCAP_RXCSUM) {
1173 ifp->if_capenable ^= IFCAP_RXCSUM;
1176 if (mask & IFCAP_VLAN_HWTAGGING) {
1177 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1180 if (mask & IFCAP_TXCSUM) {
1181 ifp->if_capenable ^= IFCAP_TXCSUM;
1182 if (ifp->if_capenable & IFCAP_TXCSUM)
1183 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1185 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1187 if (mask & IFCAP_TSO) {
1188 ifp->if_capenable ^= IFCAP_TSO;
1189 if (ifp->if_capenable & IFCAP_TSO)
1190 ifp->if_hwassist |= CSUM_TSO;
1192 ifp->if_hwassist &= ~CSUM_TSO;
1194 if (mask & IFCAP_RSS)
1195 ifp->if_capenable ^= IFCAP_RSS;
1196 if (reinit && (ifp->if_flags & IFF_RUNNING))
1201 error = ether_ioctl(ifp, command, data);
1208 emx_watchdog(struct ifaltq_subque *ifsq)
1210 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1211 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1212 struct emx_softc *sc = ifp->if_softc;
1215 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1218 * The timer is set to 5 every time start queues a packet.
1219 * Then txeof keeps resetting it as long as it cleans at
1220 * least one descriptor.
1221 * Finally, anytime all descriptors are clean the timer is
1225 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1226 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1228 * If we reach here, all TX jobs are completed and
1229 * the TX engine should have been idled for some time.
1230 * We don't need to call ifsq_devstart_sched() here.
1232 ifsq_clr_oactive(ifsq);
1233 tdata->tx_watchdog.wd_timer = 0;
1238 * If we are in this routine because of pause frames, then
1239 * don't reset the hardware.
1241 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1242 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1246 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1248 IFNET_STAT_INC(ifp, oerrors, 1);
1251 for (i = 0; i < sc->tx_ring_inuse; ++i)
1252 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1258 struct emx_softc *sc = xsc;
1259 struct ifnet *ifp = &sc->arpcom.ac_if;
1260 device_t dev = sc->dev;
1264 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1268 /* Get the latest mac address, User can use a LAA */
1269 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1271 /* Put the address into the Receive Address Array */
1272 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1275 * With the 82571 sc, RAR[0] may be overwritten
1276 * when the other port is reset, we make a duplicate
1277 * in RAR[14] for that eventuality, this assures
1278 * the interface continues to function.
1280 if (sc->hw.mac.type == e1000_82571) {
1281 e1000_set_laa_state_82571(&sc->hw, TRUE);
1282 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1283 E1000_RAR_ENTRIES - 1);
1286 /* Initialize the hardware */
1287 if (emx_reset(sc)) {
1288 device_printf(dev, "Unable to reset the hardware\n");
1289 /* XXX emx_stop()? */
1292 emx_update_link_status(sc);
1294 /* Setup VLAN support, basic and offload if available */
1295 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1297 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1300 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1301 ctrl |= E1000_CTRL_VME;
1302 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1305 /* Configure for OS presence */
1309 #ifdef IFPOLL_ENABLE
1310 if (ifp->if_flags & IFF_NPOLLING)
1313 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1314 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1316 /* Prepare transmit descriptors and buffers */
1317 for (i = 0; i < sc->tx_ring_inuse; ++i)
1318 emx_init_tx_ring(&sc->tx_data[i]);
1319 emx_init_tx_unit(sc);
1321 /* Setup Multicast table */
1324 /* Prepare receive descriptors and buffers */
1325 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1326 if (emx_init_rx_ring(&sc->rx_data[i])) {
1328 "Could not setup receive structures\n");
1333 emx_init_rx_unit(sc);
1335 /* Don't lose promiscuous settings */
1336 emx_set_promisc(sc);
1338 ifp->if_flags |= IFF_RUNNING;
1339 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1340 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1341 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1344 callout_reset(&sc->timer, hz, emx_timer, sc);
1345 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1347 /* MSI/X configuration for 82574 */
1348 if (sc->hw.mac.type == e1000_82574) {
1351 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1352 tmp |= E1000_CTRL_EXT_PBA_CLR;
1353 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1356 * Set the IVAR - interrupt vector routing.
1357 * Each nibble represents a vector, high bit
1358 * is enable, other 3 bits are the MSIX table
1359 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1360 * Link (other) to 2, hence the magic number.
1362 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1366 * Only enable interrupts if we are not polling, make sure
1367 * they are off otherwise.
1370 emx_disable_intr(sc);
1372 emx_enable_intr(sc);
1374 /* AMT based hardware can now take control from firmware */
1375 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1376 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1377 emx_get_hw_control(sc);
1383 emx_intr_body(xsc, TRUE);
1387 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1389 struct ifnet *ifp = &sc->arpcom.ac_if;
1393 ASSERT_SERIALIZED(&sc->main_serialize);
1395 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1397 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1403 * XXX: some laptops trigger several spurious interrupts
1404 * on emx(4) when in the resume cycle. The ICR register
1405 * reports all-ones value in this case. Processing such
1406 * interrupts would lead to a freeze. I don't know why.
1408 if (reg_icr == 0xffffffff) {
1413 if (ifp->if_flags & IFF_RUNNING) {
1415 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1418 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1419 lwkt_serialize_enter(
1420 &sc->rx_data[i].rx_serialize);
1421 emx_rxeof(&sc->rx_data[i], -1);
1422 lwkt_serialize_exit(
1423 &sc->rx_data[i].rx_serialize);
1426 if (reg_icr & E1000_ICR_TXDW) {
1427 struct emx_txdata *tdata = &sc->tx_data[0];
1429 lwkt_serialize_enter(&tdata->tx_serialize);
1431 if (!ifsq_is_empty(tdata->ifsq))
1432 ifsq_devstart(tdata->ifsq);
1433 lwkt_serialize_exit(&tdata->tx_serialize);
1437 /* Link status change */
1438 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1439 emx_serialize_skipmain(sc);
1441 callout_stop(&sc->timer);
1442 sc->hw.mac.get_link_status = 1;
1443 emx_update_link_status(sc);
1445 /* Deal with TX cruft when link lost */
1448 callout_reset(&sc->timer, hz, emx_timer, sc);
1450 emx_deserialize_skipmain(sc);
1453 if (reg_icr & E1000_ICR_RXO)
1460 emx_intr_mask(void *xsc)
1462 struct emx_softc *sc = xsc;
1464 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1467 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1468 * so don't check it.
1470 emx_intr_body(sc, FALSE);
1471 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1475 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1477 struct emx_softc *sc = ifp->if_softc;
1479 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1481 emx_update_link_status(sc);
1483 ifmr->ifm_status = IFM_AVALID;
1484 ifmr->ifm_active = IFM_ETHER;
1486 if (!sc->link_active) {
1487 if (sc->hw.mac.autoneg)
1488 ifmr->ifm_active |= IFM_NONE;
1490 ifmr->ifm_active |= sc->media.ifm_media;
1494 ifmr->ifm_status |= IFM_ACTIVE;
1495 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1496 ifmr->ifm_active |= sc->ifm_flowctrl;
1498 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1499 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1500 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1502 switch (sc->link_speed) {
1504 ifmr->ifm_active |= IFM_10_T;
1507 ifmr->ifm_active |= IFM_100_TX;
1511 ifmr->ifm_active |= IFM_1000_T;
1514 if (sc->link_duplex == FULL_DUPLEX)
1515 ifmr->ifm_active |= IFM_FDX;
1517 ifmr->ifm_active |= IFM_HDX;
1519 if (ifmr->ifm_active & IFM_FDX)
1520 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode);
1524 emx_media_change(struct ifnet *ifp)
1526 struct emx_softc *sc = ifp->if_softc;
1527 struct ifmedia *ifm = &sc->media;
1529 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1531 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1534 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1536 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1537 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1542 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1543 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1547 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1548 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1550 if (IFM_OPTIONS(ifm->ifm_media) &
1551 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1553 if_printf(ifp, "Flow control is not "
1554 "allowed for half-duplex\n");
1558 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1560 sc->hw.mac.autoneg = FALSE;
1561 sc->hw.phy.autoneg_advertised = 0;
1565 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1566 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1568 if (IFM_OPTIONS(ifm->ifm_media) &
1569 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1571 if_printf(ifp, "Flow control is not "
1572 "allowed for half-duplex\n");
1576 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1578 sc->hw.mac.autoneg = FALSE;
1579 sc->hw.phy.autoneg_advertised = 0;
1584 if_printf(ifp, "Unsupported media type %d\n",
1585 IFM_SUBTYPE(ifm->ifm_media));
1589 sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
1591 if (ifp->if_flags & IFF_RUNNING)
1598 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1599 int *segs_used, int *idx)
1601 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1603 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1604 struct e1000_tx_desc *ctxd = NULL;
1605 struct mbuf *m_head = *m_headp;
1606 uint32_t txd_upper, txd_lower, cmd = 0;
1607 int maxsegs, nsegs, i, j, first, last = 0, error;
1609 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1610 error = emx_tso_pullup(tdata, m_headp);
1616 txd_upper = txd_lower = 0;
1619 * Capture the first descriptor index, this descriptor
1620 * will have the index of the EOP which is the only one
1621 * that now gets a DONE bit writeback.
1623 first = tdata->next_avail_tx_desc;
1624 tx_buffer = &tdata->tx_buf[first];
1625 tx_buffer_mapped = tx_buffer;
1626 map = tx_buffer->map;
1628 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1629 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1630 if (maxsegs > EMX_MAX_SCATTER)
1631 maxsegs = EMX_MAX_SCATTER;
1633 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1634 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1640 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1643 tdata->tx_nsegs += nsegs;
1644 *segs_used += nsegs;
1646 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1647 /* TSO will consume one TX desc */
1648 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1649 tdata->tx_nsegs += i;
1651 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1652 /* TX csum offloading will consume one TX desc */
1653 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1654 tdata->tx_nsegs += i;
1658 /* Handle VLAN tag */
1659 if (m_head->m_flags & M_VLANTAG) {
1660 /* Set the vlan id. */
1661 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1662 /* Tell hardware to add tag */
1663 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1666 i = tdata->next_avail_tx_desc;
1668 /* Set up our transmit descriptors */
1669 for (j = 0; j < nsegs; j++) {
1670 tx_buffer = &tdata->tx_buf[i];
1671 ctxd = &tdata->tx_desc_base[i];
1673 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1674 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1675 txd_lower | segs[j].ds_len);
1676 ctxd->upper.data = htole32(txd_upper);
1679 if (++i == tdata->num_tx_desc)
1683 tdata->next_avail_tx_desc = i;
1685 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1686 tdata->num_tx_desc_avail -= nsegs;
1688 tx_buffer->m_head = m_head;
1689 tx_buffer_mapped->map = tx_buffer->map;
1690 tx_buffer->map = map;
1692 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1693 tdata->tx_nsegs = 0;
1696 * Report Status (RS) is turned on
1697 * every tx_intr_nsegs descriptors.
1699 cmd = E1000_TXD_CMD_RS;
1702 * Keep track of the descriptor, which will
1703 * be written back by hardware.
1705 tdata->tx_dd[tdata->tx_dd_tail] = last;
1706 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1707 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1711 * Last Descriptor of Packet needs End Of Packet (EOP)
1713 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1716 * Defer TDT updating, until enough descriptors are setup
1720 #ifdef EMX_TSS_DEBUG
1728 emx_set_promisc(struct emx_softc *sc)
1730 struct ifnet *ifp = &sc->arpcom.ac_if;
1733 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1735 if (ifp->if_flags & IFF_PROMISC) {
1736 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1737 /* Turn this on if you want to see bad packets */
1739 reg_rctl |= E1000_RCTL_SBP;
1740 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1741 } else if (ifp->if_flags & IFF_ALLMULTI) {
1742 reg_rctl |= E1000_RCTL_MPE;
1743 reg_rctl &= ~E1000_RCTL_UPE;
1744 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1749 emx_disable_promisc(struct emx_softc *sc)
1753 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1755 reg_rctl &= ~E1000_RCTL_UPE;
1756 reg_rctl &= ~E1000_RCTL_MPE;
1757 reg_rctl &= ~E1000_RCTL_SBP;
1758 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1762 emx_set_multi(struct emx_softc *sc)
1764 struct ifnet *ifp = &sc->arpcom.ac_if;
1765 struct ifmultiaddr *ifma;
1766 uint32_t reg_rctl = 0;
1771 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1773 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1774 if (ifma->ifma_addr->sa_family != AF_LINK)
1777 if (mcnt == EMX_MCAST_ADDR_MAX)
1780 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1781 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1785 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1786 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1787 reg_rctl |= E1000_RCTL_MPE;
1788 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1790 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1795 * This routine checks for link status and updates statistics.
1798 emx_timer(void *xsc)
1800 struct emx_softc *sc = xsc;
1801 struct ifnet *ifp = &sc->arpcom.ac_if;
1803 lwkt_serialize_enter(&sc->main_serialize);
1805 emx_update_link_status(sc);
1806 emx_update_stats(sc);
1808 /* Reset LAA into RAR[0] on 82571 */
1809 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1810 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1812 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1813 emx_print_hw_stats(sc);
1817 callout_reset(&sc->timer, hz, emx_timer, sc);
1819 lwkt_serialize_exit(&sc->main_serialize);
1823 emx_update_link_status(struct emx_softc *sc)
1825 struct e1000_hw *hw = &sc->hw;
1826 struct ifnet *ifp = &sc->arpcom.ac_if;
1827 device_t dev = sc->dev;
1828 uint32_t link_check = 0;
1830 /* Get the cached link value or read phy for real */
1831 switch (hw->phy.media_type) {
1832 case e1000_media_type_copper:
1833 if (hw->mac.get_link_status) {
1834 /* Do the work to read phy */
1835 e1000_check_for_link(hw);
1836 link_check = !hw->mac.get_link_status;
1837 if (link_check) /* ESB2 fix */
1838 e1000_cfg_on_link_up(hw);
1844 case e1000_media_type_fiber:
1845 e1000_check_for_link(hw);
1846 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1849 case e1000_media_type_internal_serdes:
1850 e1000_check_for_link(hw);
1851 link_check = sc->hw.mac.serdes_has_link;
1854 case e1000_media_type_unknown:
1859 /* Now check for a transition */
1860 if (link_check && sc->link_active == 0) {
1861 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1865 * Check if we should enable/disable SPEED_MODE bit on
1868 if (sc->link_speed != SPEED_1000 &&
1869 (hw->mac.type == e1000_82571 ||
1870 hw->mac.type == e1000_82572)) {
1873 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1874 tarc0 &= ~EMX_TARC_SPEED_MODE;
1875 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1878 char flowctrl[IFM_ETH_FC_STRLEN];
1880 e1000_fc2str(hw->fc.current_mode, flowctrl,
1882 device_printf(dev, "Link is up %d Mbps %s, "
1883 "Flow control: %s\n",
1885 (sc->link_duplex == FULL_DUPLEX) ?
1886 "Full Duplex" : "Half Duplex",
1889 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1890 e1000_force_flowctrl(hw, sc->ifm_flowctrl);
1891 sc->link_active = 1;
1893 ifp->if_baudrate = sc->link_speed * 1000000;
1894 ifp->if_link_state = LINK_STATE_UP;
1895 if_link_state_change(ifp);
1896 } else if (!link_check && sc->link_active == 1) {
1897 ifp->if_baudrate = sc->link_speed = 0;
1898 sc->link_duplex = 0;
1900 device_printf(dev, "Link is Down\n");
1901 sc->link_active = 0;
1902 ifp->if_link_state = LINK_STATE_DOWN;
1903 if_link_state_change(ifp);
1908 emx_stop(struct emx_softc *sc)
1910 struct ifnet *ifp = &sc->arpcom.ac_if;
1913 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1915 emx_disable_intr(sc);
1917 callout_stop(&sc->timer);
1919 ifp->if_flags &= ~IFF_RUNNING;
1920 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1921 struct emx_txdata *tdata = &sc->tx_data[i];
1923 ifsq_clr_oactive(tdata->ifsq);
1924 ifsq_watchdog_stop(&tdata->tx_watchdog);
1925 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1929 * Disable multiple receive queues.
1932 * We should disable multiple receive queues before
1933 * resetting the hardware.
1935 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1937 e1000_reset_hw(&sc->hw);
1938 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1940 for (i = 0; i < sc->tx_ring_cnt; ++i)
1941 emx_free_tx_ring(&sc->tx_data[i]);
1942 for (i = 0; i < sc->rx_ring_cnt; ++i)
1943 emx_free_rx_ring(&sc->rx_data[i]);
1947 emx_reset(struct emx_softc *sc)
1949 device_t dev = sc->dev;
1950 uint16_t rx_buffer_size;
1953 /* Set up smart power down as default off on newer adapters. */
1954 if (!emx_smart_pwr_down &&
1955 (sc->hw.mac.type == e1000_82571 ||
1956 sc->hw.mac.type == e1000_82572)) {
1957 uint16_t phy_tmp = 0;
1959 /* Speed up time to link by disabling smart power down. */
1960 e1000_read_phy_reg(&sc->hw,
1961 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1962 phy_tmp &= ~IGP02E1000_PM_SPD;
1963 e1000_write_phy_reg(&sc->hw,
1964 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1968 * Packet Buffer Allocation (PBA)
1969 * Writing PBA sets the receive portion of the buffer
1970 * the remainder is used for the transmit buffer.
1972 switch (sc->hw.mac.type) {
1973 /* Total Packet Buffer on these is 48K */
1976 case e1000_80003es2lan:
1977 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1980 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1981 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1985 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1989 pba = E1000_PBA_26K;
1993 /* Devices before 82547 had a Packet Buffer of 64K. */
1994 if (sc->hw.mac.max_frame_size > 8192)
1995 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1997 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1999 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
2002 * These parameters control the automatic generation (Tx) and
2003 * response (Rx) to Ethernet PAUSE frames.
2004 * - High water mark should allow for at least two frames to be
2005 * received after sending an XOFF.
2006 * - Low water mark works best when it is very near the high water mark.
2007 * This allows the receiver to restart by sending XON when it has
2008 * drained a bit. Here we use an arbitary value of 1500 which will
2009 * restart after one full frame is pulled from the buffer. There
2010 * could be several smaller frames in the buffer and if so they will
2011 * not trigger the XON until their total number reduces the buffer
2013 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2015 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
2017 sc->hw.fc.high_water = rx_buffer_size -
2018 roundup2(sc->hw.mac.max_frame_size, 1024);
2019 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
2021 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
2022 sc->hw.fc.send_xon = TRUE;
2023 sc->hw.fc.requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl);
2026 * Device specific overrides/settings
2028 if (sc->hw.mac.type == e1000_pch_lpt) {
2029 sc->hw.fc.high_water = 0x5C20;
2030 sc->hw.fc.low_water = 0x5048;
2031 sc->hw.fc.pause_time = 0x0650;
2032 sc->hw.fc.refresh_time = 0x0400;
2033 /* Jumbos need adjusted PBA */
2034 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
2035 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
2037 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
2038 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2039 sc->hw.fc.pause_time = 0xFFFF;
2042 /* Issue a global reset */
2043 e1000_reset_hw(&sc->hw);
2044 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
2045 emx_disable_aspm(sc);
2047 if (e1000_init_hw(&sc->hw) < 0) {
2048 device_printf(dev, "Hardware Initialization Failed\n");
2052 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
2053 e1000_get_phy_info(&sc->hw);
2054 e1000_check_for_link(&sc->hw);
2060 emx_setup_ifp(struct emx_softc *sc)
2062 struct ifnet *ifp = &sc->arpcom.ac_if;
2065 if_initname(ifp, device_get_name(sc->dev),
2066 device_get_unit(sc->dev));
2068 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2069 ifp->if_init = emx_init;
2070 ifp->if_ioctl = emx_ioctl;
2071 ifp->if_start = emx_start;
2072 #ifdef IFPOLL_ENABLE
2073 ifp->if_npoll = emx_npoll;
2075 ifp->if_serialize = emx_serialize;
2076 ifp->if_deserialize = emx_deserialize;
2077 ifp->if_tryserialize = emx_tryserialize;
2079 ifp->if_serialize_assert = emx_serialize_assert;
2082 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc;
2084 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2085 ifq_set_ready(&ifp->if_snd);
2086 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2088 ifp->if_mapsubq = ifq_mapsubq_mask;
2089 ifq_set_subq_mask(&ifp->if_snd, 0);
2091 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2093 ifp->if_capabilities = IFCAP_HWCSUM |
2094 IFCAP_VLAN_HWTAGGING |
2097 if (sc->rx_ring_cnt > 1)
2098 ifp->if_capabilities |= IFCAP_RSS;
2099 ifp->if_capenable = ifp->if_capabilities;
2100 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2103 * Tell the upper layer(s) we support long frames.
2105 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2107 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2108 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2109 struct emx_txdata *tdata = &sc->tx_data[i];
2111 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2112 ifsq_set_priv(ifsq, tdata);
2113 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2116 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2120 * Specify the media types supported by this sc and register
2121 * callbacks to update media and link information
2123 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2124 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2125 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2128 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2129 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2131 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2132 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2134 if (sc->hw.phy.type != e1000_phy_ife) {
2135 ifmedia_add(&sc->media,
2136 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2139 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2140 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl);
2144 * Workaround for SmartSpeed on 82541 and 82547 controllers
2147 emx_smartspeed(struct emx_softc *sc)
2151 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2152 sc->hw.mac.autoneg == 0 ||
2153 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2156 if (sc->smartspeed == 0) {
2158 * If Master/Slave config fault is asserted twice,
2159 * we assume back-to-back
2161 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2162 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2164 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2165 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2166 e1000_read_phy_reg(&sc->hw,
2167 PHY_1000T_CTRL, &phy_tmp);
2168 if (phy_tmp & CR_1000T_MS_ENABLE) {
2169 phy_tmp &= ~CR_1000T_MS_ENABLE;
2170 e1000_write_phy_reg(&sc->hw,
2171 PHY_1000T_CTRL, phy_tmp);
2173 if (sc->hw.mac.autoneg &&
2174 !e1000_phy_setup_autoneg(&sc->hw) &&
2175 !e1000_read_phy_reg(&sc->hw,
2176 PHY_CONTROL, &phy_tmp)) {
2177 phy_tmp |= MII_CR_AUTO_NEG_EN |
2178 MII_CR_RESTART_AUTO_NEG;
2179 e1000_write_phy_reg(&sc->hw,
2180 PHY_CONTROL, phy_tmp);
2185 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2186 /* If still no link, perhaps using 2/3 pair cable */
2187 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2188 phy_tmp |= CR_1000T_MS_ENABLE;
2189 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2190 if (sc->hw.mac.autoneg &&
2191 !e1000_phy_setup_autoneg(&sc->hw) &&
2192 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2193 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2194 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2198 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2199 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2204 emx_create_tx_ring(struct emx_txdata *tdata)
2206 device_t dev = tdata->sc->dev;
2207 struct emx_txbuf *tx_buffer;
2208 int error, i, tsize, ntxd;
2211 * Validate number of transmit descriptors. It must not exceed
2212 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2214 ntxd = device_getenv_int(dev, "txd", emx_txd);
2215 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2216 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2217 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2218 EMX_DEFAULT_TXD, ntxd);
2219 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2221 tdata->num_tx_desc = ntxd;
2225 * Allocate Transmit Descriptor ring
2227 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2229 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2230 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2231 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2232 &tdata->tx_desc_paddr);
2233 if (tdata->tx_desc_base == NULL) {
2234 device_printf(dev, "Unable to allocate tx_desc memory\n");
2238 tsize = __VM_CACHELINE_ALIGN(
2239 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2240 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2243 * Create DMA tags for tx buffers
2245 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2246 1, 0, /* alignment, bounds */
2247 BUS_SPACE_MAXADDR, /* lowaddr */
2248 BUS_SPACE_MAXADDR, /* highaddr */
2249 NULL, NULL, /* filter, filterarg */
2250 EMX_TSO_SIZE, /* maxsize */
2251 EMX_MAX_SCATTER, /* nsegments */
2252 EMX_MAX_SEGSIZE, /* maxsegsize */
2253 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2254 BUS_DMA_ONEBPAGE, /* flags */
2257 device_printf(dev, "Unable to allocate TX DMA tag\n");
2258 kfree(tdata->tx_buf, M_DEVBUF);
2259 tdata->tx_buf = NULL;
2264 * Create DMA maps for tx buffers
2266 for (i = 0; i < tdata->num_tx_desc; i++) {
2267 tx_buffer = &tdata->tx_buf[i];
2269 error = bus_dmamap_create(tdata->txtag,
2270 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2273 device_printf(dev, "Unable to create TX DMA map\n");
2274 emx_destroy_tx_ring(tdata, i);
2280 * Setup TX parameters
2282 tdata->spare_tx_desc = EMX_TX_SPARE;
2283 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2286 * Keep following relationship between spare_tx_desc, oact_tx_desc
2287 * and tx_intr_nsegs:
2288 * (spare_tx_desc + EMX_TX_RESERVED) <=
2289 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2291 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2292 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2293 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2294 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2295 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2297 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2298 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2299 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2302 * Pullup extra 4bytes into the first data segment for TSO, see:
2303 * 82571/82572 specification update errata #7
2305 * Same applies to I217 (and maybe I218).
2308 * 4bytes instead of 2bytes, which are mentioned in the errata,
2309 * are pulled; mainly to keep rest of the data properly aligned.
2311 if (tdata->sc->hw.mac.type == e1000_82571 ||
2312 tdata->sc->hw.mac.type == e1000_82572 ||
2313 tdata->sc->hw.mac.type == e1000_pch_lpt)
2314 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2320 emx_init_tx_ring(struct emx_txdata *tdata)
2322 /* Clear the old ring contents */
2323 bzero(tdata->tx_desc_base,
2324 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2327 tdata->next_avail_tx_desc = 0;
2328 tdata->next_tx_to_clean = 0;
2329 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2331 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2332 if (tdata->sc->tx_ring_inuse > 1) {
2333 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2335 if_printf(&tdata->sc->arpcom.ac_if,
2336 "TX %d force ctx setup\n", tdata->idx);
2342 emx_init_tx_unit(struct emx_softc *sc)
2344 uint32_t tctl, tarc, tipg = 0, txdctl;
2347 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2348 struct emx_txdata *tdata = &sc->tx_data[i];
2351 /* Setup the Base and Length of the Tx Descriptor Ring */
2352 bus_addr = tdata->tx_desc_paddr;
2353 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2354 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2355 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2356 (uint32_t)(bus_addr >> 32));
2357 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2358 (uint32_t)bus_addr);
2359 /* Setup the HW Tx Head and Tail descriptor pointers */
2360 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2361 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2364 /* Set the default values for the Tx Inter Packet Gap timer */
2365 switch (sc->hw.mac.type) {
2366 case e1000_80003es2lan:
2367 tipg = DEFAULT_82543_TIPG_IPGR1;
2368 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2369 E1000_TIPG_IPGR2_SHIFT;
2373 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2374 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2375 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2377 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2378 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2379 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2383 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2385 /* NOTE: 0 is not allowed for TIDV */
2386 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2387 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2390 * Errata workaround (obtained from Linux). This is necessary
2391 * to make multiple TX queues work on 82574.
2392 * XXX can't find it in any published errata though.
2394 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2395 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2397 if (sc->hw.mac.type == e1000_82571 ||
2398 sc->hw.mac.type == e1000_82572) {
2399 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2400 tarc |= EMX_TARC_SPEED_MODE;
2401 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2402 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2403 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2405 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2406 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2408 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2411 /* Program the Transmit Control Register */
2412 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2413 tctl &= ~E1000_TCTL_CT;
2414 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2415 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2416 tctl |= E1000_TCTL_MULR;
2418 /* This write will effectively turn on the transmit unit. */
2419 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2421 if (sc->hw.mac.type == e1000_82571 ||
2422 sc->hw.mac.type == e1000_82572 ||
2423 sc->hw.mac.type == e1000_80003es2lan) {
2424 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2425 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2427 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2430 if (sc->tx_ring_inuse > 1) {
2431 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2432 tarc &= ~EMX_TARC_COUNT_MASK;
2434 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2436 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2437 tarc &= ~EMX_TARC_COUNT_MASK;
2439 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2444 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2446 struct emx_txbuf *tx_buffer;
2449 /* Free Transmit Descriptor ring */
2450 if (tdata->tx_desc_base) {
2451 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2452 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2453 tdata->tx_desc_dmap);
2454 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2456 tdata->tx_desc_base = NULL;
2459 if (tdata->tx_buf == NULL)
2462 for (i = 0; i < ndesc; i++) {
2463 tx_buffer = &tdata->tx_buf[i];
2465 KKASSERT(tx_buffer->m_head == NULL);
2466 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2468 bus_dma_tag_destroy(tdata->txtag);
2470 kfree(tdata->tx_buf, M_DEVBUF);
2471 tdata->tx_buf = NULL;
2475 * The offload context needs to be set when we transfer the first
2476 * packet of a particular protocol (TCP/UDP). This routine has been
2477 * enhanced to deal with inserted VLAN headers.
2479 * If the new packet's ether header length, ip header length and
2480 * csum offloading type are same as the previous packet, we should
2481 * avoid allocating a new csum context descriptor; mainly to take
2482 * advantage of the pipeline effect of the TX data read request.
2484 * This function returns number of TX descrptors allocated for
2488 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2489 uint32_t *txd_upper, uint32_t *txd_lower)
2491 struct e1000_context_desc *TXD;
2492 int curr_txd, ehdrlen, csum_flags;
2493 uint32_t cmd, hdr_len, ip_hlen;
2495 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2496 ip_hlen = mp->m_pkthdr.csum_iphlen;
2497 ehdrlen = mp->m_pkthdr.csum_lhlen;
2499 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2500 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2501 tdata->csum_flags == csum_flags) {
2503 * Same csum offload context as the previous packets;
2506 *txd_upper = tdata->csum_txd_upper;
2507 *txd_lower = tdata->csum_txd_lower;
2512 * Setup a new csum offload context.
2515 curr_txd = tdata->next_avail_tx_desc;
2516 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2520 /* Setup of IP header checksum. */
2521 if (csum_flags & CSUM_IP) {
2523 * Start offset for header checksum calculation.
2524 * End offset for header checksum calculation.
2525 * Offset of place to put the checksum.
2527 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2528 TXD->lower_setup.ip_fields.ipcse =
2529 htole16(ehdrlen + ip_hlen - 1);
2530 TXD->lower_setup.ip_fields.ipcso =
2531 ehdrlen + offsetof(struct ip, ip_sum);
2532 cmd |= E1000_TXD_CMD_IP;
2533 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2535 hdr_len = ehdrlen + ip_hlen;
2537 if (csum_flags & CSUM_TCP) {
2539 * Start offset for payload checksum calculation.
2540 * End offset for payload checksum calculation.
2541 * Offset of place to put the checksum.
2543 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2544 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2545 TXD->upper_setup.tcp_fields.tucso =
2546 hdr_len + offsetof(struct tcphdr, th_sum);
2547 cmd |= E1000_TXD_CMD_TCP;
2548 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2549 } else if (csum_flags & CSUM_UDP) {
2551 * Start offset for header checksum calculation.
2552 * End offset for header checksum calculation.
2553 * Offset of place to put the checksum.
2555 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2556 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2557 TXD->upper_setup.tcp_fields.tucso =
2558 hdr_len + offsetof(struct udphdr, uh_sum);
2559 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2562 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2563 E1000_TXD_DTYP_D; /* Data descr */
2565 /* Save the information for this csum offloading context */
2566 tdata->csum_lhlen = ehdrlen;
2567 tdata->csum_iphlen = ip_hlen;
2568 tdata->csum_flags = csum_flags;
2569 tdata->csum_txd_upper = *txd_upper;
2570 tdata->csum_txd_lower = *txd_lower;
2572 TXD->tcp_seg_setup.data = htole32(0);
2573 TXD->cmd_and_length =
2574 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2576 if (++curr_txd == tdata->num_tx_desc)
2579 KKASSERT(tdata->num_tx_desc_avail > 0);
2580 tdata->num_tx_desc_avail--;
2582 tdata->next_avail_tx_desc = curr_txd;
2587 emx_txeof(struct emx_txdata *tdata)
2589 struct emx_txbuf *tx_buffer;
2590 int first, num_avail;
2592 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2595 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2598 num_avail = tdata->num_tx_desc_avail;
2599 first = tdata->next_tx_to_clean;
2601 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2602 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2603 struct e1000_tx_desc *tx_desc;
2605 tx_desc = &tdata->tx_desc_base[dd_idx];
2606 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2607 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2609 if (++dd_idx == tdata->num_tx_desc)
2612 while (first != dd_idx) {
2617 tx_buffer = &tdata->tx_buf[first];
2618 if (tx_buffer->m_head) {
2619 bus_dmamap_unload(tdata->txtag,
2621 m_freem(tx_buffer->m_head);
2622 tx_buffer->m_head = NULL;
2625 if (++first == tdata->num_tx_desc)
2632 tdata->next_tx_to_clean = first;
2633 tdata->num_tx_desc_avail = num_avail;
2635 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2636 tdata->tx_dd_head = 0;
2637 tdata->tx_dd_tail = 0;
2640 if (!EMX_IS_OACTIVE(tdata)) {
2641 ifsq_clr_oactive(tdata->ifsq);
2643 /* All clean, turn off the timer */
2644 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2645 tdata->tx_watchdog.wd_timer = 0;
2650 emx_tx_collect(struct emx_txdata *tdata)
2652 struct emx_txbuf *tx_buffer;
2653 int tdh, first, num_avail, dd_idx = -1;
2655 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2658 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2659 if (tdh == tdata->next_tx_to_clean)
2662 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2663 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2665 num_avail = tdata->num_tx_desc_avail;
2666 first = tdata->next_tx_to_clean;
2668 while (first != tdh) {
2673 tx_buffer = &tdata->tx_buf[first];
2674 if (tx_buffer->m_head) {
2675 bus_dmamap_unload(tdata->txtag,
2677 m_freem(tx_buffer->m_head);
2678 tx_buffer->m_head = NULL;
2681 if (first == dd_idx) {
2682 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2683 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2684 tdata->tx_dd_head = 0;
2685 tdata->tx_dd_tail = 0;
2688 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2692 if (++first == tdata->num_tx_desc)
2695 tdata->next_tx_to_clean = first;
2696 tdata->num_tx_desc_avail = num_avail;
2698 if (!EMX_IS_OACTIVE(tdata)) {
2699 ifsq_clr_oactive(tdata->ifsq);
2701 /* All clean, turn off the timer */
2702 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2703 tdata->tx_watchdog.wd_timer = 0;
2708 * When Link is lost sometimes there is work still in the TX ring
2709 * which will result in a watchdog, rather than allow that do an
2710 * attempted cleanup and then reinit here. Note that this has been
2711 * seens mostly with fiber adapters.
2714 emx_tx_purge(struct emx_softc *sc)
2718 if (sc->link_active)
2721 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2722 struct emx_txdata *tdata = &sc->tx_data[i];
2724 if (tdata->tx_watchdog.wd_timer) {
2725 emx_tx_collect(tdata);
2726 if (tdata->tx_watchdog.wd_timer) {
2727 if_printf(&sc->arpcom.ac_if,
2728 "Link lost, TX pending, reinit\n");
2737 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2740 bus_dma_segment_t seg;
2742 struct emx_rxbuf *rx_buffer;
2745 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2748 if_printf(&rdata->sc->arpcom.ac_if,
2749 "Unable to allocate RX mbuf\n");
2753 m->m_len = m->m_pkthdr.len = MCLBYTES;
2755 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2756 m_adj(m, ETHER_ALIGN);
2758 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2759 rdata->rx_sparemap, m,
2760 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2764 if_printf(&rdata->sc->arpcom.ac_if,
2765 "Unable to load RX mbuf\n");
2770 rx_buffer = &rdata->rx_buf[i];
2771 if (rx_buffer->m_head != NULL)
2772 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2774 map = rx_buffer->map;
2775 rx_buffer->map = rdata->rx_sparemap;
2776 rdata->rx_sparemap = map;
2778 rx_buffer->m_head = m;
2779 rx_buffer->paddr = seg.ds_addr;
2781 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2786 emx_create_rx_ring(struct emx_rxdata *rdata)
2788 device_t dev = rdata->sc->dev;
2789 struct emx_rxbuf *rx_buffer;
2790 int i, error, rsize, nrxd;
2793 * Validate number of receive descriptors. It must not exceed
2794 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2796 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2797 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2798 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2799 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2800 EMX_DEFAULT_RXD, nrxd);
2801 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2803 rdata->num_rx_desc = nrxd;
2807 * Allocate Receive Descriptor ring
2809 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2811 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2812 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2813 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2814 &rdata->rx_desc_paddr);
2815 if (rdata->rx_desc == NULL) {
2816 device_printf(dev, "Unable to allocate rx_desc memory\n");
2820 rsize = __VM_CACHELINE_ALIGN(
2821 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2822 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2825 * Create DMA tag for rx buffers
2827 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2828 1, 0, /* alignment, bounds */
2829 BUS_SPACE_MAXADDR, /* lowaddr */
2830 BUS_SPACE_MAXADDR, /* highaddr */
2831 NULL, NULL, /* filter, filterarg */
2832 MCLBYTES, /* maxsize */
2834 MCLBYTES, /* maxsegsize */
2835 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2838 device_printf(dev, "Unable to allocate RX DMA tag\n");
2839 kfree(rdata->rx_buf, M_DEVBUF);
2840 rdata->rx_buf = NULL;
2845 * Create spare DMA map for rx buffers
2847 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2848 &rdata->rx_sparemap);
2850 device_printf(dev, "Unable to create spare RX DMA map\n");
2851 bus_dma_tag_destroy(rdata->rxtag);
2852 kfree(rdata->rx_buf, M_DEVBUF);
2853 rdata->rx_buf = NULL;
2858 * Create DMA maps for rx buffers
2860 for (i = 0; i < rdata->num_rx_desc; i++) {
2861 rx_buffer = &rdata->rx_buf[i];
2863 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2866 device_printf(dev, "Unable to create RX DMA map\n");
2867 emx_destroy_rx_ring(rdata, i);
2875 emx_free_rx_ring(struct emx_rxdata *rdata)
2879 for (i = 0; i < rdata->num_rx_desc; i++) {
2880 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2882 if (rx_buffer->m_head != NULL) {
2883 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2884 m_freem(rx_buffer->m_head);
2885 rx_buffer->m_head = NULL;
2889 if (rdata->fmp != NULL)
2890 m_freem(rdata->fmp);
2896 emx_free_tx_ring(struct emx_txdata *tdata)
2900 for (i = 0; i < tdata->num_tx_desc; i++) {
2901 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2903 if (tx_buffer->m_head != NULL) {
2904 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2905 m_freem(tx_buffer->m_head);
2906 tx_buffer->m_head = NULL;
2910 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2912 tdata->csum_flags = 0;
2913 tdata->csum_lhlen = 0;
2914 tdata->csum_iphlen = 0;
2915 tdata->csum_thlen = 0;
2916 tdata->csum_mss = 0;
2917 tdata->csum_pktlen = 0;
2919 tdata->tx_dd_head = 0;
2920 tdata->tx_dd_tail = 0;
2921 tdata->tx_nsegs = 0;
2925 emx_init_rx_ring(struct emx_rxdata *rdata)
2929 /* Reset descriptor ring */
2930 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2932 /* Allocate new ones. */
2933 for (i = 0; i < rdata->num_rx_desc; i++) {
2934 error = emx_newbuf(rdata, i, 1);
2939 /* Setup our descriptor pointers */
2940 rdata->next_rx_desc_to_check = 0;
2946 emx_init_rx_unit(struct emx_softc *sc)
2948 struct ifnet *ifp = &sc->arpcom.ac_if;
2950 uint32_t rctl, itr, rfctl;
2954 * Make sure receives are disabled while setting
2955 * up the descriptor ring
2957 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2958 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2961 * Set the interrupt throttling rate. Value is calculated
2962 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2964 if (sc->int_throttle_ceil)
2965 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2968 emx_set_itr(sc, itr);
2970 /* Use extended RX descriptor */
2971 rfctl = E1000_RFCTL_EXTEN;
2973 /* Disable accelerated ackknowledge */
2974 if (sc->hw.mac.type == e1000_82574)
2975 rfctl |= E1000_RFCTL_ACK_DIS;
2977 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2980 * Receive Checksum Offload for TCP and UDP
2982 * Checksum offloading is also enabled if multiple receive
2983 * queue is to be supported, since we need it to figure out
2986 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2987 sc->rx_ring_cnt > 1) {
2990 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2994 * PCSD must be enabled to enable multiple
2997 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2999 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
3003 * Configure multiple receive queue (RSS)
3005 if (sc->rx_ring_cnt > 1) {
3006 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
3009 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
3010 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
3014 * When we reach here, RSS has already been disabled
3015 * in emx_stop(), so we could safely configure RSS key
3016 * and redirect table.
3022 toeplitz_get_key(key, sizeof(key));
3023 for (i = 0; i < EMX_NRSSRK; ++i) {
3026 rssrk = EMX_RSSRK_VAL(key, i);
3027 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
3029 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
3033 * Configure RSS redirect table in following fashion:
3034 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3037 for (i = 0; i < EMX_RETA_SIZE; ++i) {
3040 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
3041 reta |= q << (8 * i);
3043 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
3045 for (i = 0; i < EMX_NRETA; ++i)
3046 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3049 * Enable multiple receive queues.
3050 * Enable IPv4 RSS standard hash functions.
3051 * Disable RSS interrupt.
3053 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3054 E1000_MRQC_ENABLE_RSS_2Q |
3055 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3056 E1000_MRQC_RSS_FIELD_IPV4);
3060 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3061 * long latencies are observed, like Lenovo X60. This
3062 * change eliminates the problem, but since having positive
3063 * values in RDTR is a known source of problems on other
3064 * platforms another solution is being sought.
3066 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3067 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3068 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3071 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3072 struct emx_rxdata *rdata = &sc->rx_data[i];
3075 * Setup the Base and Length of the Rx Descriptor Ring
3077 bus_addr = rdata->rx_desc_paddr;
3078 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3079 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3080 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3081 (uint32_t)(bus_addr >> 32));
3082 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3083 (uint32_t)bus_addr);
3086 * Setup the HW Rx Head and Tail Descriptor Pointers
3088 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3089 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3090 sc->rx_data[i].num_rx_desc - 1);
3093 if (sc->hw.mac.type >= e1000_pch2lan) {
3094 if (ifp->if_mtu > ETHERMTU)
3095 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3097 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3100 /* Setup the Receive Control Register */
3101 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3102 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3103 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3104 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3106 /* Make sure VLAN Filters are off */
3107 rctl &= ~E1000_RCTL_VFE;
3109 /* Don't store bad paket */
3110 rctl &= ~E1000_RCTL_SBP;
3113 rctl |= E1000_RCTL_SZ_2048;
3115 if (ifp->if_mtu > ETHERMTU)
3116 rctl |= E1000_RCTL_LPE;
3118 rctl &= ~E1000_RCTL_LPE;
3120 /* Enable Receives */
3121 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3125 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3127 struct emx_rxbuf *rx_buffer;
3130 /* Free Receive Descriptor ring */
3131 if (rdata->rx_desc) {
3132 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3133 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3134 rdata->rx_desc_dmap);
3135 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3137 rdata->rx_desc = NULL;
3140 if (rdata->rx_buf == NULL)
3143 for (i = 0; i < ndesc; i++) {
3144 rx_buffer = &rdata->rx_buf[i];
3146 KKASSERT(rx_buffer->m_head == NULL);
3147 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3149 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3150 bus_dma_tag_destroy(rdata->rxtag);
3152 kfree(rdata->rx_buf, M_DEVBUF);
3153 rdata->rx_buf = NULL;
3157 emx_rxeof(struct emx_rxdata *rdata, int count)
3159 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3161 emx_rxdesc_t *current_desc;
3163 int i, cpuid = mycpuid;
3165 i = rdata->next_rx_desc_to_check;
3166 current_desc = &rdata->rx_desc[i];
3167 staterr = le32toh(current_desc->rxd_staterr);
3169 if (!(staterr & E1000_RXD_STAT_DD))
3172 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3173 struct pktinfo *pi = NULL, pi0;
3174 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3175 struct mbuf *m = NULL;
3180 mp = rx_buf->m_head;
3183 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3184 * needs to access the last received byte in the mbuf.
3186 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3187 BUS_DMASYNC_POSTREAD);
3189 len = le16toh(current_desc->rxd_length);
3190 if (staterr & E1000_RXD_STAT_EOP) {
3197 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3199 uint32_t mrq, rss_hash;
3202 * Save several necessary information,
3203 * before emx_newbuf() destroy it.
3205 if ((staterr & E1000_RXD_STAT_VP) && eop)
3206 vlan = le16toh(current_desc->rxd_vlan);
3208 mrq = le32toh(current_desc->rxd_mrq);
3209 rss_hash = le32toh(current_desc->rxd_rss);
3211 EMX_RSS_DPRINTF(rdata->sc, 10,
3212 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3213 rdata->idx, mrq, rss_hash);
3215 if (emx_newbuf(rdata, i, 0) != 0) {
3216 IFNET_STAT_INC(ifp, iqdrops, 1);
3220 /* Assign correct length to the current fragment */
3223 if (rdata->fmp == NULL) {
3224 mp->m_pkthdr.len = len;
3225 rdata->fmp = mp; /* Store the first mbuf */
3229 * Chain mbuf's together
3231 rdata->lmp->m_next = mp;
3232 rdata->lmp = rdata->lmp->m_next;
3233 rdata->fmp->m_pkthdr.len += len;
3237 rdata->fmp->m_pkthdr.rcvif = ifp;
3238 IFNET_STAT_INC(ifp, ipackets, 1);
3240 if (ifp->if_capenable & IFCAP_RXCSUM)
3241 emx_rxcsum(staterr, rdata->fmp);
3243 if (staterr & E1000_RXD_STAT_VP) {
3244 rdata->fmp->m_pkthdr.ether_vlantag =
3246 rdata->fmp->m_flags |= M_VLANTAG;
3252 if (ifp->if_capenable & IFCAP_RSS) {
3253 pi = emx_rssinfo(m, &pi0, mrq,
3256 #ifdef EMX_RSS_DEBUG
3261 IFNET_STAT_INC(ifp, ierrors, 1);
3263 emx_setup_rxdesc(current_desc, rx_buf);
3264 if (rdata->fmp != NULL) {
3265 m_freem(rdata->fmp);
3273 ifp->if_input(ifp, m, pi, cpuid);
3275 /* Advance our pointers to the next descriptor. */
3276 if (++i == rdata->num_rx_desc)
3279 current_desc = &rdata->rx_desc[i];
3280 staterr = le32toh(current_desc->rxd_staterr);
3282 rdata->next_rx_desc_to_check = i;
3284 /* Advance the E1000's Receive Queue "Tail Pointer". */
3286 i = rdata->num_rx_desc - 1;
3287 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3291 emx_enable_intr(struct emx_softc *sc)
3293 uint32_t ims_mask = IMS_ENABLE_MASK;
3295 lwkt_serialize_handler_enable(&sc->main_serialize);
3298 if (sc->hw.mac.type == e1000_82574) {
3299 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3300 ims_mask |= EM_MSIX_MASK;
3303 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3307 emx_disable_intr(struct emx_softc *sc)
3309 if (sc->hw.mac.type == e1000_82574)
3310 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3311 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3313 lwkt_serialize_handler_disable(&sc->main_serialize);
3317 * Bit of a misnomer, what this really means is
3318 * to enable OS management of the system... aka
3319 * to disable special hardware management features
3322 emx_get_mgmt(struct emx_softc *sc)
3324 /* A shared code workaround */
3325 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3326 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3327 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3329 /* disable hardware interception of ARP */
3330 manc &= ~(E1000_MANC_ARP_EN);
3332 /* enable receiving management packets to the host */
3333 manc |= E1000_MANC_EN_MNG2HOST;
3334 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3335 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3336 manc2h |= E1000_MNG2HOST_PORT_623;
3337 manc2h |= E1000_MNG2HOST_PORT_664;
3338 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3340 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3345 * Give control back to hardware management
3346 * controller if there is one.
3349 emx_rel_mgmt(struct emx_softc *sc)
3351 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3352 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3354 /* re-enable hardware interception of ARP */
3355 manc |= E1000_MANC_ARP_EN;
3356 manc &= ~E1000_MANC_EN_MNG2HOST;
3358 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3363 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3364 * For ASF and Pass Through versions of f/w this means that
3365 * the driver is loaded. For AMT version (only with 82573)
3366 * of the f/w this means that the network i/f is open.
3369 emx_get_hw_control(struct emx_softc *sc)
3371 /* Let firmware know the driver has taken over */
3372 if (sc->hw.mac.type == e1000_82573) {
3375 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3376 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3377 swsm | E1000_SWSM_DRV_LOAD);
3381 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3382 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3383 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3385 sc->flags |= EMX_FLAG_HW_CTRL;
3389 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3390 * For ASF and Pass Through versions of f/w this means that the
3391 * driver is no longer loaded. For AMT version (only with 82573)
3392 * of the f/w this means that the network i/f is closed.
3395 emx_rel_hw_control(struct emx_softc *sc)
3397 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3399 sc->flags &= ~EMX_FLAG_HW_CTRL;
3401 /* Let firmware taken over control of h/w */
3402 if (sc->hw.mac.type == e1000_82573) {
3405 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3406 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3407 swsm & ~E1000_SWSM_DRV_LOAD);
3411 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3412 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3413 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3418 emx_is_valid_eaddr(const uint8_t *addr)
3420 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3422 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3429 * Enable PCI Wake On Lan capability
3432 emx_enable_wol(device_t dev)
3434 uint16_t cap, status;
3437 /* First find the capabilities pointer*/
3438 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3440 /* Read the PM Capabilities */
3441 id = pci_read_config(dev, cap, 1);
3442 if (id != PCIY_PMG) /* Something wrong */
3446 * OK, we have the power capabilities,
3447 * so now get the status register
3449 cap += PCIR_POWER_STATUS;
3450 status = pci_read_config(dev, cap, 2);
3451 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3452 pci_write_config(dev, cap, status, 2);
3456 emx_update_stats(struct emx_softc *sc)
3458 struct ifnet *ifp = &sc->arpcom.ac_if;
3460 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3461 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3462 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3463 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3465 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3466 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3467 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3468 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3470 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3471 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3472 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3473 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3474 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3475 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3476 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3477 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3478 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3479 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3480 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3481 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3482 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3483 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3484 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3485 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3486 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3487 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3488 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3489 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3491 /* For the 64-bit byte counters the low dword must be read first. */
3492 /* Both registers clear on the read of the high dword */
3494 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3495 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3497 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3498 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3499 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3500 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3501 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3503 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3504 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3506 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3507 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3508 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3509 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3510 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3511 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3512 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3513 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3514 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3515 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3517 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3518 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3519 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3520 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3521 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3522 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3524 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3527 IFNET_STAT_SET(ifp, ierrors,
3528 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3529 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3532 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3536 emx_print_debug_info(struct emx_softc *sc)
3538 device_t dev = sc->dev;
3539 uint8_t *hw_addr = sc->hw.hw_addr;
3542 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3543 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3544 E1000_READ_REG(&sc->hw, E1000_CTRL),
3545 E1000_READ_REG(&sc->hw, E1000_RCTL));
3546 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3547 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3548 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3549 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3550 sc->hw.fc.high_water, sc->hw.fc.low_water);
3551 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3552 E1000_READ_REG(&sc->hw, E1000_TIDV),
3553 E1000_READ_REG(&sc->hw, E1000_TADV));
3554 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3555 E1000_READ_REG(&sc->hw, E1000_RDTR),
3556 E1000_READ_REG(&sc->hw, E1000_RADV));
3558 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3559 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3560 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3561 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3563 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3564 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3565 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3566 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3569 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3570 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3571 sc->tx_data[i].num_tx_desc_avail);
3572 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3573 sc->tx_data[i].tso_segments);
3574 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3575 sc->tx_data[i].tso_ctx_reused);
3580 emx_print_hw_stats(struct emx_softc *sc)
3582 device_t dev = sc->dev;
3584 device_printf(dev, "Excessive collisions = %lld\n",
3585 (long long)sc->stats.ecol);
3586 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3587 device_printf(dev, "Symbol errors = %lld\n",
3588 (long long)sc->stats.symerrs);
3590 device_printf(dev, "Sequence errors = %lld\n",
3591 (long long)sc->stats.sec);
3592 device_printf(dev, "Defer count = %lld\n",
3593 (long long)sc->stats.dc);
3594 device_printf(dev, "Missed Packets = %lld\n",
3595 (long long)sc->stats.mpc);
3596 device_printf(dev, "Receive No Buffers = %lld\n",
3597 (long long)sc->stats.rnbc);
3598 /* RLEC is inaccurate on some hardware, calculate our own. */
3599 device_printf(dev, "Receive Length Errors = %lld\n",
3600 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3601 device_printf(dev, "Receive errors = %lld\n",
3602 (long long)sc->stats.rxerrc);
3603 device_printf(dev, "Crc errors = %lld\n",
3604 (long long)sc->stats.crcerrs);
3605 device_printf(dev, "Alignment errors = %lld\n",
3606 (long long)sc->stats.algnerrc);
3607 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3608 (long long)sc->stats.cexterr);
3609 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3610 device_printf(dev, "XON Rcvd = %lld\n",
3611 (long long)sc->stats.xonrxc);
3612 device_printf(dev, "XON Xmtd = %lld\n",
3613 (long long)sc->stats.xontxc);
3614 device_printf(dev, "XOFF Rcvd = %lld\n",
3615 (long long)sc->stats.xoffrxc);
3616 device_printf(dev, "XOFF Xmtd = %lld\n",
3617 (long long)sc->stats.xofftxc);
3618 device_printf(dev, "Good Packets Rcvd = %lld\n",
3619 (long long)sc->stats.gprc);
3620 device_printf(dev, "Good Packets Xmtd = %lld\n",
3621 (long long)sc->stats.gptc);
3625 emx_print_nvm_info(struct emx_softc *sc)
3627 uint16_t eeprom_data;
3630 /* Its a bit crude, but it gets the job done */
3631 kprintf("\nInterface EEPROM Dump:\n");
3632 kprintf("Offset\n0x0000 ");
3633 for (i = 0, j = 0; i < 32; i++, j++) {
3634 if (j == 8) { /* Make the offset block */
3636 kprintf("\n0x00%x0 ",row);
3638 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3639 kprintf("%04x ", eeprom_data);
3645 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3647 struct emx_softc *sc;
3652 error = sysctl_handle_int(oidp, &result, 0, req);
3653 if (error || !req->newptr)
3656 sc = (struct emx_softc *)arg1;
3657 ifp = &sc->arpcom.ac_if;
3659 ifnet_serialize_all(ifp);
3662 emx_print_debug_info(sc);
3665 * This value will cause a hex dump of the
3666 * first 32 16-bit words of the EEPROM to
3670 emx_print_nvm_info(sc);
3672 ifnet_deserialize_all(ifp);
3678 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3683 error = sysctl_handle_int(oidp, &result, 0, req);
3684 if (error || !req->newptr)
3688 struct emx_softc *sc = (struct emx_softc *)arg1;
3689 struct ifnet *ifp = &sc->arpcom.ac_if;
3691 ifnet_serialize_all(ifp);
3692 emx_print_hw_stats(sc);
3693 ifnet_deserialize_all(ifp);
3699 emx_add_sysctl(struct emx_softc *sc)
3701 struct sysctl_ctx_list *ctx;
3702 struct sysctl_oid *tree;
3703 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3708 ctx = device_get_sysctl_ctx(sc->dev);
3709 tree = device_get_sysctl_tree(sc->dev);
3710 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3711 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3712 emx_sysctl_debug_info, "I", "Debug Information");
3714 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3715 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3716 emx_sysctl_stats, "I", "Statistics");
3718 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3719 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3721 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3722 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3725 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3726 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3727 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3728 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3729 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3730 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3731 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3732 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3733 emx_sysctl_tx_wreg_nsegs, "I",
3734 "# segments sent before write to hardware register");
3736 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3737 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3739 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3740 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3742 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3743 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3744 "# of TX rings used");
3746 #ifdef IFPOLL_ENABLE
3747 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3748 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3749 sc, 0, emx_sysctl_npoll_rxoff, "I",
3750 "NPOLLING RX cpu offset");
3751 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3752 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3753 sc, 0, emx_sysctl_npoll_txoff, "I",
3754 "NPOLLING TX cpu offset");
3757 #ifdef EMX_RSS_DEBUG
3758 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3759 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3760 0, "RSS debug level");
3761 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3762 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3763 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3764 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3768 #ifdef EMX_TSS_DEBUG
3769 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3770 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3771 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3772 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3779 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3781 struct emx_softc *sc = (void *)arg1;
3782 struct ifnet *ifp = &sc->arpcom.ac_if;
3783 int error, throttle;
3785 throttle = sc->int_throttle_ceil;
3786 error = sysctl_handle_int(oidp, &throttle, 0, req);
3787 if (error || req->newptr == NULL)
3789 if (throttle < 0 || throttle > 1000000000 / 256)
3794 * Set the interrupt throttling rate in 256ns increments,
3795 * recalculate sysctl value assignment to get exact frequency.
3797 throttle = 1000000000 / 256 / throttle;
3799 /* Upper 16bits of ITR is reserved and should be zero */
3800 if (throttle & 0xffff0000)
3804 ifnet_serialize_all(ifp);
3807 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3809 sc->int_throttle_ceil = 0;
3811 if (ifp->if_flags & IFF_RUNNING)
3812 emx_set_itr(sc, throttle);
3814 ifnet_deserialize_all(ifp);
3817 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3818 sc->int_throttle_ceil);
3824 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3826 struct emx_softc *sc = (void *)arg1;
3827 struct ifnet *ifp = &sc->arpcom.ac_if;
3828 struct emx_txdata *tdata = &sc->tx_data[0];
3831 segs = tdata->tx_intr_nsegs;
3832 error = sysctl_handle_int(oidp, &segs, 0, req);
3833 if (error || req->newptr == NULL)
3838 ifnet_serialize_all(ifp);
3841 * Don't allow tx_intr_nsegs to become:
3842 * o Less the oact_tx_desc
3843 * o Too large that no TX desc will cause TX interrupt to
3844 * be generated (OACTIVE will never recover)
3845 * o Too small that will cause tx_dd[] overflow
3847 if (segs < tdata->oact_tx_desc ||
3848 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3849 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3855 for (i = 0; i < sc->tx_ring_cnt; ++i)
3856 sc->tx_data[i].tx_intr_nsegs = segs;
3859 ifnet_deserialize_all(ifp);
3865 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3867 struct emx_softc *sc = (void *)arg1;
3868 struct ifnet *ifp = &sc->arpcom.ac_if;
3869 int error, nsegs, i;
3871 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3872 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3873 if (error || req->newptr == NULL)
3876 ifnet_serialize_all(ifp);
3877 for (i = 0; i < sc->tx_ring_cnt; ++i)
3878 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3879 ifnet_deserialize_all(ifp);
3884 #ifdef IFPOLL_ENABLE
3887 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3889 struct emx_softc *sc = (void *)arg1;
3890 struct ifnet *ifp = &sc->arpcom.ac_if;
3893 off = sc->rx_npoll_off;
3894 error = sysctl_handle_int(oidp, &off, 0, req);
3895 if (error || req->newptr == NULL)
3900 ifnet_serialize_all(ifp);
3901 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3905 sc->rx_npoll_off = off;
3907 ifnet_deserialize_all(ifp);
3913 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3915 struct emx_softc *sc = (void *)arg1;
3916 struct ifnet *ifp = &sc->arpcom.ac_if;
3919 off = sc->tx_npoll_off;
3920 error = sysctl_handle_int(oidp, &off, 0, req);
3921 if (error || req->newptr == NULL)
3926 ifnet_serialize_all(ifp);
3927 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3931 sc->tx_npoll_off = off;
3933 ifnet_deserialize_all(ifp);
3938 #endif /* IFPOLL_ENABLE */
3941 emx_dma_alloc(struct emx_softc *sc)
3946 * Create top level busdma tag
3948 error = bus_dma_tag_create(NULL, 1, 0,
3949 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3951 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3952 0, &sc->parent_dtag);
3954 device_printf(sc->dev, "could not create top level DMA tag\n");
3959 * Allocate transmit descriptors ring and buffers
3961 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3962 error = emx_create_tx_ring(&sc->tx_data[i]);
3964 device_printf(sc->dev,
3965 "Could not setup transmit structures\n");
3971 * Allocate receive descriptors ring and buffers
3973 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3974 error = emx_create_rx_ring(&sc->rx_data[i]);
3976 device_printf(sc->dev,
3977 "Could not setup receive structures\n");
3985 emx_dma_free(struct emx_softc *sc)
3989 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3990 emx_destroy_tx_ring(&sc->tx_data[i],
3991 sc->tx_data[i].num_tx_desc);
3994 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3995 emx_destroy_rx_ring(&sc->rx_data[i],
3996 sc->rx_data[i].num_rx_desc);
3999 /* Free top level busdma tag */
4000 if (sc->parent_dtag != NULL)
4001 bus_dma_tag_destroy(sc->parent_dtag);
4005 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4007 struct emx_softc *sc = ifp->if_softc;
4009 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
4013 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4015 struct emx_softc *sc = ifp->if_softc;
4017 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
4021 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4023 struct emx_softc *sc = ifp->if_softc;
4025 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
4029 emx_serialize_skipmain(struct emx_softc *sc)
4031 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
4035 emx_deserialize_skipmain(struct emx_softc *sc)
4037 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
4043 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4044 boolean_t serialized)
4046 struct emx_softc *sc = ifp->if_softc;
4048 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
4052 #endif /* INVARIANTS */
4054 #ifdef IFPOLL_ENABLE
4057 emx_npoll_status(struct ifnet *ifp)
4059 struct emx_softc *sc = ifp->if_softc;
4062 ASSERT_SERIALIZED(&sc->main_serialize);
4064 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4065 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4066 callout_stop(&sc->timer);
4067 sc->hw.mac.get_link_status = 1;
4068 emx_update_link_status(sc);
4069 callout_reset(&sc->timer, hz, emx_timer, sc);
4074 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4076 struct emx_txdata *tdata = arg;
4078 ASSERT_SERIALIZED(&tdata->tx_serialize);
4081 if (!ifsq_is_empty(tdata->ifsq))
4082 ifsq_devstart(tdata->ifsq);
4086 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4088 struct emx_rxdata *rdata = arg;
4090 ASSERT_SERIALIZED(&rdata->rx_serialize);
4092 emx_rxeof(rdata, cycle);
4096 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4098 struct emx_softc *sc = ifp->if_softc;
4101 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4106 info->ifpi_status.status_func = emx_npoll_status;
4107 info->ifpi_status.serializer = &sc->main_serialize;
4109 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4110 off = sc->tx_npoll_off;
4111 for (i = 0; i < txr_cnt; ++i) {
4112 struct emx_txdata *tdata = &sc->tx_data[i];
4115 KKASSERT(idx < ncpus2);
4116 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4117 info->ifpi_tx[idx].arg = tdata;
4118 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4119 ifsq_set_cpuid(tdata->ifsq, idx);
4122 off = sc->rx_npoll_off;
4123 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4124 struct emx_rxdata *rdata = &sc->rx_data[i];
4127 KKASSERT(idx < ncpus2);
4128 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4129 info->ifpi_rx[idx].arg = rdata;
4130 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4133 if (ifp->if_flags & IFF_RUNNING) {
4134 if (txr_cnt == sc->tx_ring_inuse)
4135 emx_disable_intr(sc);
4140 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4141 struct emx_txdata *tdata = &sc->tx_data[i];
4143 ifsq_set_cpuid(tdata->ifsq,
4144 rman_get_cpuid(sc->intr_res));
4147 if (ifp->if_flags & IFF_RUNNING) {
4148 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4149 if (txr_cnt == sc->tx_ring_inuse)
4150 emx_enable_intr(sc);
4157 #endif /* IFPOLL_ENABLE */
4160 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4162 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4163 if (sc->hw.mac.type == e1000_82574) {
4167 * When using MSIX interrupts we need to
4168 * throttle using the EITR register
4170 for (i = 0; i < 4; ++i)
4171 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4176 * Disable the L0s, 82574L Errata #20
4179 emx_disable_aspm(struct emx_softc *sc)
4181 uint16_t link_cap, link_ctrl, disable;
4182 uint8_t pcie_ptr, reg;
4183 device_t dev = sc->dev;
4185 switch (sc->hw.mac.type) {
4190 * 82573 specification update
4191 * errata #8 disable L0s
4192 * errata #41 disable L1
4194 * 82571/82572 specification update
4195 # errata #13 disable L1
4196 * errata #68 disable L0s
4198 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4203 * 82574 specification update errata #20
4205 * There is no need to disable L1
4207 disable = PCIEM_LNKCTL_ASPM_L0S;
4214 pcie_ptr = pci_get_pciecap_ptr(dev);
4218 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4219 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4223 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4225 reg = pcie_ptr + PCIER_LINKCTRL;
4226 link_ctrl = pci_read_config(dev, reg, 2);
4227 link_ctrl &= ~disable;
4228 pci_write_config(dev, reg, link_ctrl, 2);
4232 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4234 int iphlen, hoff, thoff, ex = 0;
4239 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4241 iphlen = m->m_pkthdr.csum_iphlen;
4242 thoff = m->m_pkthdr.csum_thlen;
4243 hoff = m->m_pkthdr.csum_lhlen;
4245 KASSERT(iphlen > 0, ("invalid ip hlen"));
4246 KASSERT(thoff > 0, ("invalid tcp hlen"));
4247 KASSERT(hoff > 0, ("invalid ether hlen"));
4249 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4252 if (m->m_len < hoff + iphlen + thoff + ex) {
4253 m = m_pullup(m, hoff + iphlen + thoff + ex);
4260 ip = mtodoff(m, struct ip *, hoff);
4267 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4268 uint32_t *txd_upper, uint32_t *txd_lower)
4270 struct e1000_context_desc *TXD;
4271 int hoff, iphlen, thoff, hlen;
4272 int mss, pktlen, curr_txd;
4274 #ifdef EMX_TSO_DEBUG
4275 tdata->tso_segments++;
4278 iphlen = mp->m_pkthdr.csum_iphlen;
4279 thoff = mp->m_pkthdr.csum_thlen;
4280 hoff = mp->m_pkthdr.csum_lhlen;
4281 mss = mp->m_pkthdr.tso_segsz;
4282 pktlen = mp->m_pkthdr.len;
4284 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4285 tdata->csum_flags == CSUM_TSO &&
4286 tdata->csum_iphlen == iphlen &&
4287 tdata->csum_lhlen == hoff &&
4288 tdata->csum_thlen == thoff &&
4289 tdata->csum_mss == mss &&
4290 tdata->csum_pktlen == pktlen) {
4291 *txd_upper = tdata->csum_txd_upper;
4292 *txd_lower = tdata->csum_txd_lower;
4293 #ifdef EMX_TSO_DEBUG
4294 tdata->tso_ctx_reused++;
4298 hlen = hoff + iphlen + thoff;
4301 * Setup a new TSO context.
4304 curr_txd = tdata->next_avail_tx_desc;
4305 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4307 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4308 E1000_TXD_DTYP_D | /* Data descr type */
4309 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4311 /* IP and/or TCP header checksum calculation and insertion. */
4312 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4315 * Start offset for header checksum calculation.
4316 * End offset for header checksum calculation.
4317 * Offset of place put the checksum.
4319 TXD->lower_setup.ip_fields.ipcss = hoff;
4320 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4321 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4324 * Start offset for payload checksum calculation.
4325 * End offset for payload checksum calculation.
4326 * Offset of place to put the checksum.
4328 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4329 TXD->upper_setup.tcp_fields.tucse = 0;
4330 TXD->upper_setup.tcp_fields.tucso =
4331 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4334 * Payload size per packet w/o any headers.
4335 * Length of all headers up to payload.
4337 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4338 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4339 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4340 E1000_TXD_CMD_DEXT | /* Extended descr */
4341 E1000_TXD_CMD_TSE | /* TSE context */
4342 E1000_TXD_CMD_IP | /* Do IP csum */
4343 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4344 (pktlen - hlen)); /* Total len */
4346 /* Save the information for this TSO context */
4347 tdata->csum_flags = CSUM_TSO;
4348 tdata->csum_lhlen = hoff;
4349 tdata->csum_iphlen = iphlen;
4350 tdata->csum_thlen = thoff;
4351 tdata->csum_mss = mss;
4352 tdata->csum_pktlen = pktlen;
4353 tdata->csum_txd_upper = *txd_upper;
4354 tdata->csum_txd_lower = *txd_lower;
4356 if (++curr_txd == tdata->num_tx_desc)
4359 KKASSERT(tdata->num_tx_desc_avail > 0);
4360 tdata->num_tx_desc_avail--;
4362 tdata->next_avail_tx_desc = curr_txd;
4367 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4370 return sc->tx_ring_cnt;