jme: Let the software to check hardware supplied hash
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28  */
29
30 #include "opt_polling.h"
31 #include "opt_jme.h"
32
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
39 #include <sys/proc.h>
40 #include <sys/rman.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46
47 #include <net/ethernet.h>
48 #include <net/if.h>
49 #include <net/bpf.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
58
59 #include <netinet/in.h>
60
61 #include <dev/netif/mii_layer/miivar.h>
62 #include <dev/netif/mii_layer/jmphyreg.h>
63
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
67
68 #include <dev/netif/jme/if_jmereg.h>
69 #include <dev/netif/jme/if_jmevar.h>
70
71 #include "miibus_if.h"
72
73 #define JME_TX_SERIALIZE        1
74 #define JME_RX_SERIALIZE        2
75
76 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
77
78 #ifdef JME_RSS_DEBUG
79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
80 do { \
81         if ((sc)->jme_rss_debug >= (lvl)) \
82                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
83 } while (0)
84 #else   /* !JME_RSS_DEBUG */
85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
86 #endif  /* JME_RSS_DEBUG */
87
88 static int      jme_probe(device_t);
89 static int      jme_attach(device_t);
90 static int      jme_detach(device_t);
91 static int      jme_shutdown(device_t);
92 static int      jme_suspend(device_t);
93 static int      jme_resume(device_t);
94
95 static int      jme_miibus_readreg(device_t, int, int);
96 static int      jme_miibus_writereg(device_t, int, int, int);
97 static void     jme_miibus_statchg(device_t);
98
99 static void     jme_init(void *);
100 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101 static void     jme_start(struct ifnet *);
102 static void     jme_watchdog(struct ifnet *);
103 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
104 static int      jme_mediachange(struct ifnet *);
105 #ifdef DEVICE_POLLING
106 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
107 #endif
108 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
109 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
110 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
111 #ifdef INVARIANTS
112 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
113                     boolean_t);
114 #endif
115
116 static void     jme_intr(void *);
117 static void     jme_msix_tx(void *);
118 static void     jme_msix_rx(void *);
119 static void     jme_txeof(struct jme_softc *);
120 static void     jme_rxeof(struct jme_rxdata *, int);
121 static void     jme_rx_intr(struct jme_softc *, uint32_t);
122
123 static int      jme_msix_setup(device_t);
124 static void     jme_msix_teardown(device_t, int);
125 static int      jme_intr_setup(device_t);
126 static void     jme_intr_teardown(device_t);
127 static void     jme_msix_try_alloc(device_t);
128 static void     jme_msix_free(device_t);
129 static int      jme_intr_alloc(device_t);
130 static void     jme_intr_free(device_t);
131 static int      jme_dma_alloc(struct jme_softc *);
132 static void     jme_dma_free(struct jme_softc *);
133 static int      jme_init_rx_ring(struct jme_rxdata *);
134 static void     jme_init_tx_ring(struct jme_softc *);
135 static void     jme_init_ssb(struct jme_softc *);
136 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
137 static int      jme_encap(struct jme_softc *, struct mbuf **);
138 static void     jme_rxpkt(struct jme_rxdata *);
139 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
140 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
141 static int      jme_rxbuf_dma_filter(void *, bus_addr_t);
142
143 static void     jme_tick(void *);
144 static void     jme_stop(struct jme_softc *);
145 static void     jme_reset(struct jme_softc *);
146 static void     jme_set_msinum(struct jme_softc *);
147 static void     jme_set_vlan(struct jme_softc *);
148 static void     jme_set_filter(struct jme_softc *);
149 static void     jme_stop_tx(struct jme_softc *);
150 static void     jme_stop_rx(struct jme_softc *);
151 static void     jme_mac_config(struct jme_softc *);
152 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
153 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
154 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
155 #ifdef notyet
156 static void     jme_setwol(struct jme_softc *);
157 static void     jme_setlinkspeed(struct jme_softc *);
158 #endif
159 static void     jme_set_tx_coal(struct jme_softc *);
160 static void     jme_set_rx_coal(struct jme_softc *);
161 static void     jme_enable_rss(struct jme_softc *);
162 static void     jme_disable_rss(struct jme_softc *);
163 static void     jme_serialize_skipmain(struct jme_softc *);
164 static void     jme_deserialize_skipmain(struct jme_softc *);
165
166 static void     jme_sysctl_node(struct jme_softc *);
167 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
168 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
169 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
170 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
171
172 /*
173  * Devices supported by this driver.
174  */
175 static const struct jme_dev {
176         uint16_t        jme_vendorid;
177         uint16_t        jme_deviceid;
178         uint32_t        jme_caps;
179         const char      *jme_name;
180 } jme_devs[] = {
181         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
182             JME_CAP_JUMBO,
183             "JMicron Inc, JMC250 Gigabit Ethernet" },
184         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
185             JME_CAP_FASTETH,
186             "JMicron Inc, JMC260 Fast Ethernet" },
187         { 0, 0, 0, NULL }
188 };
189
190 static device_method_t jme_methods[] = {
191         /* Device interface. */
192         DEVMETHOD(device_probe,         jme_probe),
193         DEVMETHOD(device_attach,        jme_attach),
194         DEVMETHOD(device_detach,        jme_detach),
195         DEVMETHOD(device_shutdown,      jme_shutdown),
196         DEVMETHOD(device_suspend,       jme_suspend),
197         DEVMETHOD(device_resume,        jme_resume),
198
199         /* Bus interface. */
200         DEVMETHOD(bus_print_child,      bus_generic_print_child),
201         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
202
203         /* MII interface. */
204         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
205         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
206         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
207
208         { NULL, NULL }
209 };
210
211 static driver_t jme_driver = {
212         "jme",
213         jme_methods,
214         sizeof(struct jme_softc)
215 };
216
217 static devclass_t jme_devclass;
218
219 DECLARE_DUMMY_MODULE(if_jme);
220 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
221 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
222 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
223
224 static const struct {
225         uint32_t        jme_coal;
226         uint32_t        jme_comp;
227         uint32_t        jme_empty;
228 } jme_rx_status[JME_NRXRING_MAX] = {
229         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
230           INTR_RXQ0_DESC_EMPTY },
231         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
232           INTR_RXQ1_DESC_EMPTY },
233         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
234           INTR_RXQ2_DESC_EMPTY },
235         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
236           INTR_RXQ3_DESC_EMPTY }
237 };
238
239 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
240 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
241 static int      jme_rx_ring_count = 0;
242 static int      jme_msi_enable = 1;
243 static int      jme_msix_enable = 1;
244
245 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
246 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
247 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
248 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
249 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
250
251 static __inline void
252 jme_setup_rxdesc(struct jme_rxdesc *rxd)
253 {
254         struct jme_desc *desc;
255
256         desc = rxd->rx_desc;
257         desc->buflen = htole32(MCLBYTES);
258         desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
259         desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
260         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
261 }
262
263 /*
264  *      Read a PHY register on the MII of the JMC250.
265  */
266 static int
267 jme_miibus_readreg(device_t dev, int phy, int reg)
268 {
269         struct jme_softc *sc = device_get_softc(dev);
270         uint32_t val;
271         int i;
272
273         /* For FPGA version, PHY address 0 should be ignored. */
274         if (sc->jme_caps & JME_CAP_FPGA) {
275                 if (phy == 0)
276                         return (0);
277         } else {
278                 if (sc->jme_phyaddr != phy)
279                         return (0);
280         }
281
282         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
283             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
284
285         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
286                 DELAY(1);
287                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
288                         break;
289         }
290         if (i == 0) {
291                 device_printf(sc->jme_dev, "phy read timeout: "
292                               "phy %d, reg %d\n", phy, reg);
293                 return (0);
294         }
295
296         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
297 }
298
299 /*
300  *      Write a PHY register on the MII of the JMC250.
301  */
302 static int
303 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
304 {
305         struct jme_softc *sc = device_get_softc(dev);
306         int i;
307
308         /* For FPGA version, PHY address 0 should be ignored. */
309         if (sc->jme_caps & JME_CAP_FPGA) {
310                 if (phy == 0)
311                         return (0);
312         } else {
313                 if (sc->jme_phyaddr != phy)
314                         return (0);
315         }
316
317         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
318             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
319             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
320
321         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
322                 DELAY(1);
323                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
324                         break;
325         }
326         if (i == 0) {
327                 device_printf(sc->jme_dev, "phy write timeout: "
328                               "phy %d, reg %d\n", phy, reg);
329         }
330
331         return (0);
332 }
333
334 /*
335  *      Callback from MII layer when media changes.
336  */
337 static void
338 jme_miibus_statchg(device_t dev)
339 {
340         struct jme_softc *sc = device_get_softc(dev);
341         struct ifnet *ifp = &sc->arpcom.ac_if;
342         struct mii_data *mii;
343         struct jme_txdesc *txd;
344         bus_addr_t paddr;
345         int i, r;
346
347         if (sc->jme_in_tick)
348                 jme_serialize_skipmain(sc);
349         ASSERT_IFNET_SERIALIZED_ALL(ifp);
350
351         if ((ifp->if_flags & IFF_RUNNING) == 0)
352                 goto done;
353
354         mii = device_get_softc(sc->jme_miibus);
355
356         sc->jme_has_link = FALSE;
357         if ((mii->mii_media_status & IFM_AVALID) != 0) {
358                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
359                 case IFM_10_T:
360                 case IFM_100_TX:
361                         sc->jme_has_link = TRUE;
362                         break;
363                 case IFM_1000_T:
364                         if (sc->jme_caps & JME_CAP_FASTETH)
365                                 break;
366                         sc->jme_has_link = TRUE;
367                         break;
368                 default:
369                         break;
370                 }
371         }
372
373         /*
374          * Disabling Rx/Tx MACs have a side-effect of resetting
375          * JME_TXNDA/JME_RXNDA register to the first address of
376          * Tx/Rx descriptor address. So driver should reset its
377          * internal procucer/consumer pointer and reclaim any
378          * allocated resources.  Note, just saving the value of
379          * JME_TXNDA and JME_RXNDA registers before stopping MAC
380          * and restoring JME_TXNDA/JME_RXNDA register is not
381          * sufficient to make sure correct MAC state because
382          * stopping MAC operation can take a while and hardware
383          * might have updated JME_TXNDA/JME_RXNDA registers
384          * during the stop operation.
385          */
386
387         /* Disable interrupts */
388         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
389
390         /* Stop driver */
391         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
392         ifp->if_timer = 0;
393         callout_stop(&sc->jme_tick_ch);
394
395         /* Stop receiver/transmitter. */
396         jme_stop_rx(sc);
397         jme_stop_tx(sc);
398
399         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
400                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
401
402                 jme_rxeof(rdata, -1);
403                 if (rdata->jme_rxhead != NULL)
404                         m_freem(rdata->jme_rxhead);
405                 JME_RXCHAIN_RESET(rdata);
406
407                 /*
408                  * Reuse configured Rx descriptors and reset
409                  * procuder/consumer index.
410                  */
411                 rdata->jme_rx_cons = 0;
412         }
413         if (JME_ENABLE_HWRSS(sc))
414                 jme_enable_rss(sc);
415         else
416                 jme_disable_rss(sc);
417
418         jme_txeof(sc);
419         if (sc->jme_cdata.jme_tx_cnt != 0) {
420                 /* Remove queued packets for transmit. */
421                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
422                         txd = &sc->jme_cdata.jme_txdesc[i];
423                         if (txd->tx_m != NULL) {
424                                 bus_dmamap_unload(
425                                     sc->jme_cdata.jme_tx_tag,
426                                     txd->tx_dmamap);
427                                 m_freem(txd->tx_m);
428                                 txd->tx_m = NULL;
429                                 txd->tx_ndesc = 0;
430                                 ifp->if_oerrors++;
431                         }
432                 }
433         }
434         jme_init_tx_ring(sc);
435
436         /* Initialize shadow status block. */
437         jme_init_ssb(sc);
438
439         /* Program MAC with resolved speed/duplex/flow-control. */
440         if (sc->jme_has_link) {
441                 jme_mac_config(sc);
442
443                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
444
445                 /* Set Tx ring address to the hardware. */
446                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
447                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
448                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
449
450                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
451                         CSR_WRITE_4(sc, JME_RXCSR,
452                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
453
454                         /* Set Rx ring address to the hardware. */
455                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
456                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
457                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
458                 }
459
460                 /* Restart receiver/transmitter. */
461                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
462                     RXCSR_RXQ_START);
463                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
464         }
465
466         ifp->if_flags |= IFF_RUNNING;
467         ifp->if_flags &= ~IFF_OACTIVE;
468         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
469
470 #ifdef DEVICE_POLLING
471         if (!(ifp->if_flags & IFF_POLLING))
472 #endif
473         /* Reenable interrupts. */
474         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
475
476 done:
477         if (sc->jme_in_tick)
478                 jme_deserialize_skipmain(sc);
479 }
480
481 /*
482  *      Get the current interface media status.
483  */
484 static void
485 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
486 {
487         struct jme_softc *sc = ifp->if_softc;
488         struct mii_data *mii = device_get_softc(sc->jme_miibus);
489
490         ASSERT_IFNET_SERIALIZED_ALL(ifp);
491
492         mii_pollstat(mii);
493         ifmr->ifm_status = mii->mii_media_status;
494         ifmr->ifm_active = mii->mii_media_active;
495 }
496
497 /*
498  *      Set hardware to newly-selected media.
499  */
500 static int
501 jme_mediachange(struct ifnet *ifp)
502 {
503         struct jme_softc *sc = ifp->if_softc;
504         struct mii_data *mii = device_get_softc(sc->jme_miibus);
505         int error;
506
507         ASSERT_IFNET_SERIALIZED_ALL(ifp);
508
509         if (mii->mii_instance != 0) {
510                 struct mii_softc *miisc;
511
512                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
513                         mii_phy_reset(miisc);
514         }
515         error = mii_mediachg(mii);
516
517         return (error);
518 }
519
520 static int
521 jme_probe(device_t dev)
522 {
523         const struct jme_dev *sp;
524         uint16_t vid, did;
525
526         vid = pci_get_vendor(dev);
527         did = pci_get_device(dev);
528         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
529                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
530                         struct jme_softc *sc = device_get_softc(dev);
531
532                         sc->jme_caps = sp->jme_caps;
533                         device_set_desc(dev, sp->jme_name);
534                         return (0);
535                 }
536         }
537         return (ENXIO);
538 }
539
540 static int
541 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
542 {
543         uint32_t reg;
544         int i;
545
546         *val = 0;
547         for (i = JME_TIMEOUT; i > 0; i--) {
548                 reg = CSR_READ_4(sc, JME_SMBCSR);
549                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
550                         break;
551                 DELAY(1);
552         }
553
554         if (i == 0) {
555                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
556                 return (ETIMEDOUT);
557         }
558
559         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
560         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
561         for (i = JME_TIMEOUT; i > 0; i--) {
562                 DELAY(1);
563                 reg = CSR_READ_4(sc, JME_SMBINTF);
564                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
565                         break;
566         }
567
568         if (i == 0) {
569                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
570                 return (ETIMEDOUT);
571         }
572
573         reg = CSR_READ_4(sc, JME_SMBINTF);
574         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
575
576         return (0);
577 }
578
579 static int
580 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
581 {
582         uint8_t fup, reg, val;
583         uint32_t offset;
584         int match;
585
586         offset = 0;
587         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
588             fup != JME_EEPROM_SIG0)
589                 return (ENOENT);
590         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
591             fup != JME_EEPROM_SIG1)
592                 return (ENOENT);
593         match = 0;
594         do {
595                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
596                         break;
597                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
598                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
599                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
600                                 break;
601                         if (reg >= JME_PAR0 &&
602                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
603                                 if (jme_eeprom_read_byte(sc, offset + 2,
604                                     &val) != 0)
605                                         break;
606                                 eaddr[reg - JME_PAR0] = val;
607                                 match++;
608                         }
609                 }
610                 /* Check for the end of EEPROM descriptor. */
611                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
612                         break;
613                 /* Try next eeprom descriptor. */
614                 offset += JME_EEPROM_DESC_BYTES;
615         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
616
617         if (match == ETHER_ADDR_LEN)
618                 return (0);
619
620         return (ENOENT);
621 }
622
623 static void
624 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
625 {
626         uint32_t par0, par1;
627
628         /* Read station address. */
629         par0 = CSR_READ_4(sc, JME_PAR0);
630         par1 = CSR_READ_4(sc, JME_PAR1);
631         par1 &= 0xFFFF;
632         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
633                 device_printf(sc->jme_dev,
634                     "generating fake ethernet address.\n");
635                 par0 = karc4random();
636                 /* Set OUI to JMicron. */
637                 eaddr[0] = 0x00;
638                 eaddr[1] = 0x1B;
639                 eaddr[2] = 0x8C;
640                 eaddr[3] = (par0 >> 16) & 0xff;
641                 eaddr[4] = (par0 >> 8) & 0xff;
642                 eaddr[5] = par0 & 0xff;
643         } else {
644                 eaddr[0] = (par0 >> 0) & 0xFF;
645                 eaddr[1] = (par0 >> 8) & 0xFF;
646                 eaddr[2] = (par0 >> 16) & 0xFF;
647                 eaddr[3] = (par0 >> 24) & 0xFF;
648                 eaddr[4] = (par1 >> 0) & 0xFF;
649                 eaddr[5] = (par1 >> 8) & 0xFF;
650         }
651 }
652
653 static int
654 jme_attach(device_t dev)
655 {
656         struct jme_softc *sc = device_get_softc(dev);
657         struct ifnet *ifp = &sc->arpcom.ac_if;
658         uint32_t reg;
659         uint16_t did;
660         uint8_t pcie_ptr, rev;
661         int error = 0, i, j, rx_desc_cnt;
662         uint8_t eaddr[ETHER_ADDR_LEN];
663
664         device_printf(dev, "rxdata %zu, chain_data %zu\n",
665             sizeof(struct jme_rxdata), sizeof(struct jme_chain_data));
666
667         lwkt_serialize_init(&sc->jme_serialize);
668         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
669         for (i = 0; i < JME_NRXRING_MAX; ++i) {
670                 lwkt_serialize_init(
671                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
672         }
673
674         rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
675             jme_rx_desc_count);
676         rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
677         if (rx_desc_cnt > JME_NDESC_MAX)
678                 rx_desc_cnt = JME_NDESC_MAX;
679
680         sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
681             jme_tx_desc_count);
682         sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
683             JME_NDESC_ALIGN);
684         if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
685                 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
686
687         /*
688          * Calculate rx rings
689          */
690         sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
691             jme_rx_ring_count);
692         sc->jme_cdata.jme_rx_ring_cnt =
693             if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
694
695         i = 0;
696         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
697
698         KKASSERT(i == JME_TX_SERIALIZE);
699         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
700
701         KKASSERT(i == JME_RX_SERIALIZE);
702         for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
703                 sc->jme_serialize_arr[i++] =
704                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
705         }
706         KKASSERT(i <= JME_NSERIALIZE);
707         sc->jme_serialize_cnt = i;
708
709         sc->jme_cdata.jme_sc = sc;
710         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
711                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
712
713                 rdata->jme_sc = sc;
714                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
715                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
716                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
717                 rdata->jme_rx_idx = i;
718                 rdata->jme_rx_desc_cnt = rx_desc_cnt;
719         }
720
721         sc->jme_dev = dev;
722         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
723
724         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
725
726         callout_init(&sc->jme_tick_ch);
727
728 #ifndef BURN_BRIDGES
729         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
730                 uint32_t irq, mem;
731
732                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
733                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
734
735                 device_printf(dev, "chip is in D%d power mode "
736                     "-- setting to D0\n", pci_get_powerstate(dev));
737
738                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
739
740                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
741                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
742         }
743 #endif  /* !BURN_BRIDGE */
744
745         /* Enable bus mastering */
746         pci_enable_busmaster(dev);
747
748         /*
749          * Allocate IO memory
750          *
751          * JMC250 supports both memory mapped and I/O register space
752          * access.  Because I/O register access should use different
753          * BARs to access registers it's waste of time to use I/O
754          * register spce access.  JMC250 uses 16K to map entire memory
755          * space.
756          */
757         sc->jme_mem_rid = JME_PCIR_BAR;
758         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
759                                                  &sc->jme_mem_rid, RF_ACTIVE);
760         if (sc->jme_mem_res == NULL) {
761                 device_printf(dev, "can't allocate IO memory\n");
762                 return ENXIO;
763         }
764         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
765         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
766
767         /*
768          * Allocate IRQ
769          */
770         error = jme_intr_alloc(dev);
771         if (error)
772                 goto fail;
773
774         /*
775          * Extract revisions
776          */
777         reg = CSR_READ_4(sc, JME_CHIPMODE);
778         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
779             CHIPMODE_NOT_FPGA) {
780                 sc->jme_caps |= JME_CAP_FPGA;
781                 if (bootverbose) {
782                         device_printf(dev, "FPGA revision: 0x%04x\n",
783                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
784                                       CHIPMODE_FPGA_REV_SHIFT);
785                 }
786         }
787
788         /* NOTE: FM revision is put in the upper 4 bits */
789         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
790         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
791         if (bootverbose)
792                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
793
794         did = pci_get_device(dev);
795         switch (did) {
796         case PCI_PRODUCT_JMICRON_JMC250:
797                 if (rev == JME_REV1_A2)
798                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
799                 break;
800
801         case PCI_PRODUCT_JMICRON_JMC260:
802                 if (rev == JME_REV2)
803                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
804                 break;
805
806         default:
807                 panic("unknown device id 0x%04x", did);
808         }
809         if (rev >= JME_REV2) {
810                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
811                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
812                                       GHC_TXMAC_CLKSRC_1000;
813         }
814
815         /* Reset the ethernet controller. */
816         jme_reset(sc);
817
818         /* Map MSI/MSI-X vectors */
819         jme_set_msinum(sc);
820
821         /* Get station address. */
822         reg = CSR_READ_4(sc, JME_SMBCSR);
823         if (reg & SMBCSR_EEPROM_PRESENT)
824                 error = jme_eeprom_macaddr(sc, eaddr);
825         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
826                 if (error != 0 && (bootverbose)) {
827                         device_printf(dev, "ethernet hardware address "
828                                       "not found in EEPROM.\n");
829                 }
830                 jme_reg_macaddr(sc, eaddr);
831         }
832
833         /*
834          * Save PHY address.
835          * Integrated JR0211 has fixed PHY address whereas FPGA version
836          * requires PHY probing to get correct PHY address.
837          */
838         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
839                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
840                     GPREG0_PHY_ADDR_MASK;
841                 if (bootverbose) {
842                         device_printf(dev, "PHY is at address %d.\n",
843                             sc->jme_phyaddr);
844                 }
845         } else {
846                 sc->jme_phyaddr = 0;
847         }
848
849         /* Set max allowable DMA size. */
850         pcie_ptr = pci_get_pciecap_ptr(dev);
851         if (pcie_ptr != 0) {
852                 uint16_t ctrl;
853
854                 sc->jme_caps |= JME_CAP_PCIE;
855                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
856                 if (bootverbose) {
857                         device_printf(dev, "Read request size : %d bytes.\n",
858                             128 << ((ctrl >> 12) & 0x07));
859                         device_printf(dev, "TLP payload size : %d bytes.\n",
860                             128 << ((ctrl >> 5) & 0x07));
861                 }
862                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
863                 case PCIEM_DEVCTL_MAX_READRQ_128:
864                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
865                         break;
866                 case PCIEM_DEVCTL_MAX_READRQ_256:
867                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
868                         break;
869                 default:
870                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
871                         break;
872                 }
873                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
874         } else {
875                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
876                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
877         }
878
879 #ifdef notyet
880         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
881                 sc->jme_caps |= JME_CAP_PMCAP;
882 #endif
883
884         /*
885          * Create sysctl tree
886          */
887         jme_sysctl_node(sc);
888
889         /* Allocate DMA stuffs */
890         error = jme_dma_alloc(sc);
891         if (error)
892                 goto fail;
893
894         ifp->if_softc = sc;
895         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
896         ifp->if_init = jme_init;
897         ifp->if_ioctl = jme_ioctl;
898         ifp->if_start = jme_start;
899 #ifdef DEVICE_POLLING
900         ifp->if_poll = jme_poll;
901 #endif
902         ifp->if_watchdog = jme_watchdog;
903         ifp->if_serialize = jme_serialize;
904         ifp->if_deserialize = jme_deserialize;
905         ifp->if_tryserialize = jme_tryserialize;
906 #ifdef INVARIANTS
907         ifp->if_serialize_assert = jme_serialize_assert;
908 #endif
909         ifq_set_maxlen(&ifp->if_snd,
910             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
911         ifq_set_ready(&ifp->if_snd);
912
913         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
914         ifp->if_capabilities = IFCAP_HWCSUM |
915                                IFCAP_VLAN_MTU |
916                                IFCAP_VLAN_HWTAGGING;
917         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
918                 ifp->if_capabilities |= IFCAP_RSS;
919         ifp->if_capenable = ifp->if_capabilities;
920
921         /*
922          * Disable TXCSUM by default to improve bulk data
923          * transmit performance (+20Mbps improvement).
924          */
925         ifp->if_capenable &= ~IFCAP_TXCSUM;
926
927         if (ifp->if_capenable & IFCAP_TXCSUM)
928                 ifp->if_hwassist = JME_CSUM_FEATURES;
929
930         /* Set up MII bus. */
931         error = mii_phy_probe(dev, &sc->jme_miibus,
932                               jme_mediachange, jme_mediastatus);
933         if (error) {
934                 device_printf(dev, "no PHY found!\n");
935                 goto fail;
936         }
937
938         /*
939          * Save PHYADDR for FPGA mode PHY.
940          */
941         if (sc->jme_caps & JME_CAP_FPGA) {
942                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
943
944                 if (mii->mii_instance != 0) {
945                         struct mii_softc *miisc;
946
947                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
948                                 if (miisc->mii_phy != 0) {
949                                         sc->jme_phyaddr = miisc->mii_phy;
950                                         break;
951                                 }
952                         }
953                         if (sc->jme_phyaddr != 0) {
954                                 device_printf(sc->jme_dev,
955                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
956                                 /* vendor magic. */
957                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
958                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
959
960                                 /* XXX should we clear JME_WA_EXTFIFO */
961                         }
962                 }
963         }
964
965         ether_ifattach(ifp, eaddr, NULL);
966
967         /* Tell the upper layer(s) we support long frames. */
968         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
969
970         error = jme_intr_setup(dev);
971         if (error) {
972                 ether_ifdetach(ifp);
973                 goto fail;
974         }
975
976         return 0;
977 fail:
978         jme_detach(dev);
979         return (error);
980 }
981
982 static int
983 jme_detach(device_t dev)
984 {
985         struct jme_softc *sc = device_get_softc(dev);
986
987         if (device_is_attached(dev)) {
988                 struct ifnet *ifp = &sc->arpcom.ac_if;
989
990                 ifnet_serialize_all(ifp);
991                 jme_stop(sc);
992                 jme_intr_teardown(dev);
993                 ifnet_deserialize_all(ifp);
994
995                 ether_ifdetach(ifp);
996         }
997
998         if (sc->jme_sysctl_tree != NULL)
999                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1000
1001         if (sc->jme_miibus != NULL)
1002                 device_delete_child(dev, sc->jme_miibus);
1003         bus_generic_detach(dev);
1004
1005         jme_intr_free(dev);
1006
1007         if (sc->jme_mem_res != NULL) {
1008                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1009                                      sc->jme_mem_res);
1010         }
1011
1012         jme_dma_free(sc);
1013
1014         return (0);
1015 }
1016
1017 static void
1018 jme_sysctl_node(struct jme_softc *sc)
1019 {
1020         int coal_max;
1021 #ifdef JME_RSS_DEBUG
1022         int r;
1023 #endif
1024
1025         sysctl_ctx_init(&sc->jme_sysctl_ctx);
1026         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1027                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1028                                 device_get_nameunit(sc->jme_dev),
1029                                 CTLFLAG_RD, 0, "");
1030         if (sc->jme_sysctl_tree == NULL) {
1031                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1032                 return;
1033         }
1034
1035         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1036             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1038             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1039
1040         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1041             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1042             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1043             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1044
1045         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1046             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1047             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1048             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1049
1050         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1051             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1052             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1053             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1054
1055         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1057                        "rx_desc_count", CTLFLAG_RD,
1058                        &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1059                        0, "RX desc count");
1060         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1062                        "tx_desc_count", CTLFLAG_RD,
1063                        &sc->jme_cdata.jme_tx_desc_cnt,
1064                        0, "TX desc count");
1065         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1066                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1067                        "rx_ring_count", CTLFLAG_RD,
1068                        &sc->jme_cdata.jme_rx_ring_cnt,
1069                        0, "RX ring count");
1070 #ifdef JME_RSS_DEBUG
1071         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1072                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1073                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1074                        0, "RSS debug level");
1075         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1076                 char rx_ring_pkt[32];
1077
1078                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1079                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1080                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1081                     rx_ring_pkt, CTLFLAG_RW,
1082                     &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1083         }
1084 #endif
1085
1086         /*
1087          * Set default coalesce valves
1088          */
1089         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1090         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1091         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1092         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1093
1094         /*
1095          * Adjust coalesce valves, in case that the number of TX/RX
1096          * descs are set to small values by users.
1097          *
1098          * NOTE: coal_max will not be zero, since number of descs
1099          * must aligned by JME_NDESC_ALIGN (16 currently)
1100          */
1101         coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1102         if (coal_max < sc->jme_tx_coal_pkt)
1103                 sc->jme_tx_coal_pkt = coal_max;
1104
1105         coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1106         if (coal_max < sc->jme_rx_coal_pkt)
1107                 sc->jme_rx_coal_pkt = coal_max;
1108 }
1109
1110 static int
1111 jme_dma_alloc(struct jme_softc *sc)
1112 {
1113         struct jme_txdesc *txd;
1114         bus_dmamem_t dmem;
1115         int error, i, asize;
1116
1117         sc->jme_cdata.jme_txdesc =
1118         kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1119                 M_DEVBUF, M_WAITOK | M_ZERO);
1120         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1121                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1122
1123                 rdata->jme_rxdesc =
1124                 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1125                         M_DEVBUF, M_WAITOK | M_ZERO);
1126         }
1127
1128         /* Create parent ring tag. */
1129         error = bus_dma_tag_create(NULL,/* parent */
1130             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1131             sc->jme_lowaddr,            /* lowaddr */
1132             BUS_SPACE_MAXADDR,          /* highaddr */
1133             NULL, NULL,                 /* filter, filterarg */
1134             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1135             0,                          /* nsegments */
1136             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1137             0,                          /* flags */
1138             &sc->jme_cdata.jme_ring_tag);
1139         if (error) {
1140                 device_printf(sc->jme_dev,
1141                     "could not create parent ring DMA tag.\n");
1142                 return error;
1143         }
1144
1145         /*
1146          * Create DMA stuffs for TX ring
1147          */
1148         asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1149         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1150                         JME_TX_RING_ALIGN, 0,
1151                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1152                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1153         if (error) {
1154                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1155                 return error;
1156         }
1157         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1158         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1159         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1160         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1161
1162         /*
1163          * Create DMA stuffs for RX rings
1164          */
1165         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1166                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1167                 if (error)
1168                         return error;
1169         }
1170
1171         /* Create parent buffer tag. */
1172         error = bus_dma_tag_create(NULL,/* parent */
1173             1, 0,                       /* algnmnt, boundary */
1174             sc->jme_lowaddr,            /* lowaddr */
1175             BUS_SPACE_MAXADDR,          /* highaddr */
1176             NULL, NULL,                 /* filter, filterarg */
1177             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1178             0,                          /* nsegments */
1179             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1180             0,                          /* flags */
1181             &sc->jme_cdata.jme_buffer_tag);
1182         if (error) {
1183                 device_printf(sc->jme_dev,
1184                     "could not create parent buffer DMA tag.\n");
1185                 return error;
1186         }
1187
1188         /*
1189          * Create DMA stuffs for shadow status block
1190          */
1191         asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1192         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1193                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1194                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1195         if (error) {
1196                 device_printf(sc->jme_dev,
1197                     "could not create shadow status block.\n");
1198                 return error;
1199         }
1200         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1201         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1202         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1203         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1204
1205         /*
1206          * Create DMA stuffs for TX buffers
1207          */
1208
1209         /* Create tag for Tx buffers. */
1210         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1211             1, 0,                       /* algnmnt, boundary */
1212             BUS_SPACE_MAXADDR,          /* lowaddr */
1213             BUS_SPACE_MAXADDR,          /* highaddr */
1214             NULL, NULL,                 /* filter, filterarg */
1215             JME_JUMBO_FRAMELEN,         /* maxsize */
1216             JME_MAXTXSEGS,              /* nsegments */
1217             JME_MAXSEGSIZE,             /* maxsegsize */
1218             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1219             &sc->jme_cdata.jme_tx_tag);
1220         if (error != 0) {
1221                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1222                 return error;
1223         }
1224
1225         /* Create DMA maps for Tx buffers. */
1226         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1227                 txd = &sc->jme_cdata.jme_txdesc[i];
1228                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1229                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1230                                 &txd->tx_dmamap);
1231                 if (error) {
1232                         int j;
1233
1234                         device_printf(sc->jme_dev,
1235                             "could not create %dth Tx dmamap.\n", i);
1236
1237                         for (j = 0; j < i; ++j) {
1238                                 txd = &sc->jme_cdata.jme_txdesc[j];
1239                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1240                                                    txd->tx_dmamap);
1241                         }
1242                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1243                         sc->jme_cdata.jme_tx_tag = NULL;
1244                         return error;
1245                 }
1246         }
1247
1248         /*
1249          * Create DMA stuffs for RX buffers
1250          */
1251         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1252                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1253                 if (error)
1254                         return error;
1255         }
1256         return 0;
1257 }
1258
1259 static void
1260 jme_dma_free(struct jme_softc *sc)
1261 {
1262         struct jme_txdesc *txd;
1263         struct jme_rxdesc *rxd;
1264         struct jme_rxdata *rdata;
1265         int i, r;
1266
1267         /* Tx ring */
1268         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1269                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1270                     sc->jme_cdata.jme_tx_ring_map);
1271                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1272                     sc->jme_cdata.jme_tx_ring,
1273                     sc->jme_cdata.jme_tx_ring_map);
1274                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1275                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1276         }
1277
1278         /* Rx ring */
1279         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1280                 rdata = &sc->jme_cdata.jme_rx_data[r];
1281                 if (rdata->jme_rx_ring_tag != NULL) {
1282                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1283                                           rdata->jme_rx_ring_map);
1284                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1285                                         rdata->jme_rx_ring,
1286                                         rdata->jme_rx_ring_map);
1287                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1288                         rdata->jme_rx_ring_tag = NULL;
1289                 }
1290         }
1291
1292         /* Tx buffers */
1293         if (sc->jme_cdata.jme_tx_tag != NULL) {
1294                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1295                         txd = &sc->jme_cdata.jme_txdesc[i];
1296                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1297                             txd->tx_dmamap);
1298                 }
1299                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1300                 sc->jme_cdata.jme_tx_tag = NULL;
1301         }
1302
1303         /* Rx buffers */
1304         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1305                 rdata = &sc->jme_cdata.jme_rx_data[r];
1306                 if (rdata->jme_rx_tag != NULL) {
1307                         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1308                                 rxd = &rdata->jme_rxdesc[i];
1309                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1310                                                    rxd->rx_dmamap);
1311                         }
1312                         bus_dmamap_destroy(rdata->jme_rx_tag,
1313                                            rdata->jme_rx_sparemap);
1314                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1315                         rdata->jme_rx_tag = NULL;
1316                 }
1317         }
1318
1319         /* Shadow status block. */
1320         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1321                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1322                     sc->jme_cdata.jme_ssb_map);
1323                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1324                     sc->jme_cdata.jme_ssb_block,
1325                     sc->jme_cdata.jme_ssb_map);
1326                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1327                 sc->jme_cdata.jme_ssb_tag = NULL;
1328         }
1329
1330         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1331                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1332                 sc->jme_cdata.jme_buffer_tag = NULL;
1333         }
1334         if (sc->jme_cdata.jme_ring_tag != NULL) {
1335                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1336                 sc->jme_cdata.jme_ring_tag = NULL;
1337         }
1338
1339         if (sc->jme_cdata.jme_txdesc != NULL) {
1340                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1341                 sc->jme_cdata.jme_txdesc = NULL;
1342         }
1343         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1344                 rdata = &sc->jme_cdata.jme_rx_data[r];
1345                 if (rdata->jme_rxdesc != NULL) {
1346                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1347                         rdata->jme_rxdesc = NULL;
1348                 }
1349         }
1350 }
1351
1352 /*
1353  *      Make sure the interface is stopped at reboot time.
1354  */
1355 static int
1356 jme_shutdown(device_t dev)
1357 {
1358         return jme_suspend(dev);
1359 }
1360
1361 #ifdef notyet
1362 /*
1363  * Unlike other ethernet controllers, JMC250 requires
1364  * explicit resetting link speed to 10/100Mbps as gigabit
1365  * link will cunsume more power than 375mA.
1366  * Note, we reset the link speed to 10/100Mbps with
1367  * auto-negotiation but we don't know whether that operation
1368  * would succeed or not as we have no control after powering
1369  * off. If the renegotiation fail WOL may not work. Running
1370  * at 1Gbps draws more power than 375mA at 3.3V which is
1371  * specified in PCI specification and that would result in
1372  * complete shutdowning power to ethernet controller.
1373  *
1374  * TODO
1375  *  Save current negotiated media speed/duplex/flow-control
1376  *  to softc and restore the same link again after resuming.
1377  *  PHY handling such as power down/resetting to 100Mbps
1378  *  may be better handled in suspend method in phy driver.
1379  */
1380 static void
1381 jme_setlinkspeed(struct jme_softc *sc)
1382 {
1383         struct mii_data *mii;
1384         int aneg, i;
1385
1386         JME_LOCK_ASSERT(sc);
1387
1388         mii = device_get_softc(sc->jme_miibus);
1389         mii_pollstat(mii);
1390         aneg = 0;
1391         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1392                 switch IFM_SUBTYPE(mii->mii_media_active) {
1393                 case IFM_10_T:
1394                 case IFM_100_TX:
1395                         return;
1396                 case IFM_1000_T:
1397                         aneg++;
1398                 default:
1399                         break;
1400                 }
1401         }
1402         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1403         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1404             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1405         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1406             BMCR_AUTOEN | BMCR_STARTNEG);
1407         DELAY(1000);
1408         if (aneg != 0) {
1409                 /* Poll link state until jme(4) get a 10/100 link. */
1410                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1411                         mii_pollstat(mii);
1412                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1413                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1414                                 case IFM_10_T:
1415                                 case IFM_100_TX:
1416                                         jme_mac_config(sc);
1417                                         return;
1418                                 default:
1419                                         break;
1420                                 }
1421                         }
1422                         JME_UNLOCK(sc);
1423                         pause("jmelnk", hz);
1424                         JME_LOCK(sc);
1425                 }
1426                 if (i == MII_ANEGTICKS_GIGE)
1427                         device_printf(sc->jme_dev, "establishing link failed, "
1428                             "WOL may not work!");
1429         }
1430         /*
1431          * No link, force MAC to have 100Mbps, full-duplex link.
1432          * This is the last resort and may/may not work.
1433          */
1434         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1435         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1436         jme_mac_config(sc);
1437 }
1438
1439 static void
1440 jme_setwol(struct jme_softc *sc)
1441 {
1442         struct ifnet *ifp = &sc->arpcom.ac_if;
1443         uint32_t gpr, pmcs;
1444         uint16_t pmstat;
1445         int pmc;
1446
1447         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1448                 /* No PME capability, PHY power down. */
1449                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1450                     MII_BMCR, BMCR_PDOWN);
1451                 return;
1452         }
1453
1454         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1455         pmcs = CSR_READ_4(sc, JME_PMCS);
1456         pmcs &= ~PMCS_WOL_ENB_MASK;
1457         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1458                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1459                 /* Enable PME message. */
1460                 gpr |= GPREG0_PME_ENB;
1461                 /* For gigabit controllers, reset link speed to 10/100. */
1462                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1463                         jme_setlinkspeed(sc);
1464         }
1465
1466         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1467         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1468
1469         /* Request PME. */
1470         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1471         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1472         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1473                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1474         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1475         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1476                 /* No WOL, PHY power down. */
1477                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1478                     MII_BMCR, BMCR_PDOWN);
1479         }
1480 }
1481 #endif
1482
1483 static int
1484 jme_suspend(device_t dev)
1485 {
1486         struct jme_softc *sc = device_get_softc(dev);
1487         struct ifnet *ifp = &sc->arpcom.ac_if;
1488
1489         ifnet_serialize_all(ifp);
1490         jme_stop(sc);
1491 #ifdef notyet
1492         jme_setwol(sc);
1493 #endif
1494         ifnet_deserialize_all(ifp);
1495
1496         return (0);
1497 }
1498
1499 static int
1500 jme_resume(device_t dev)
1501 {
1502         struct jme_softc *sc = device_get_softc(dev);
1503         struct ifnet *ifp = &sc->arpcom.ac_if;
1504 #ifdef notyet
1505         int pmc;
1506 #endif
1507
1508         ifnet_serialize_all(ifp);
1509
1510 #ifdef notyet
1511         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1512                 uint16_t pmstat;
1513
1514                 pmstat = pci_read_config(sc->jme_dev,
1515                     pmc + PCIR_POWER_STATUS, 2);
1516                 /* Disable PME clear PME status. */
1517                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1518                 pci_write_config(sc->jme_dev,
1519                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1520         }
1521 #endif
1522
1523         if (ifp->if_flags & IFF_UP)
1524                 jme_init(sc);
1525
1526         ifnet_deserialize_all(ifp);
1527
1528         return (0);
1529 }
1530
1531 static int
1532 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1533 {
1534         struct jme_txdesc *txd;
1535         struct jme_desc *desc;
1536         struct mbuf *m;
1537         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1538         int maxsegs, nsegs;
1539         int error, i, prod, symbol_desc;
1540         uint32_t cflags, flag64;
1541
1542         M_ASSERTPKTHDR((*m_head));
1543
1544         prod = sc->jme_cdata.jme_tx_prod;
1545         txd = &sc->jme_cdata.jme_txdesc[prod];
1546
1547         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1548                 symbol_desc = 1;
1549         else
1550                 symbol_desc = 0;
1551
1552         maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1553                   (JME_TXD_RSVD + symbol_desc);
1554         if (maxsegs > JME_MAXTXSEGS)
1555                 maxsegs = JME_MAXTXSEGS;
1556         KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1557                 ("not enough segments %d", maxsegs));
1558
1559         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1560                         txd->tx_dmamap, m_head,
1561                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1562         if (error)
1563                 goto fail;
1564
1565         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1566                         BUS_DMASYNC_PREWRITE);
1567
1568         m = *m_head;
1569         cflags = 0;
1570
1571         /* Configure checksum offload. */
1572         if (m->m_pkthdr.csum_flags & CSUM_IP)
1573                 cflags |= JME_TD_IPCSUM;
1574         if (m->m_pkthdr.csum_flags & CSUM_TCP)
1575                 cflags |= JME_TD_TCPCSUM;
1576         if (m->m_pkthdr.csum_flags & CSUM_UDP)
1577                 cflags |= JME_TD_UDPCSUM;
1578
1579         /* Configure VLAN. */
1580         if (m->m_flags & M_VLANTAG) {
1581                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1582                 cflags |= JME_TD_VLAN_TAG;
1583         }
1584
1585         desc = &sc->jme_cdata.jme_tx_ring[prod];
1586         desc->flags = htole32(cflags);
1587         desc->addr_hi = htole32(m->m_pkthdr.len);
1588         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1589                 /*
1590                  * Use 64bits TX desc chain format.
1591                  *
1592                  * The first TX desc of the chain, which is setup here,
1593                  * is just a symbol TX desc carrying no payload.
1594                  */
1595                 flag64 = JME_TD_64BIT;
1596                 desc->buflen = 0;
1597                 desc->addr_lo = 0;
1598
1599                 /* No effective TX desc is consumed */
1600                 i = 0;
1601         } else {
1602                 /*
1603                  * Use 32bits TX desc chain format.
1604                  *
1605                  * The first TX desc of the chain, which is setup here,
1606                  * is an effective TX desc carrying the first segment of
1607                  * the mbuf chain.
1608                  */
1609                 flag64 = 0;
1610                 desc->buflen = htole32(txsegs[0].ds_len);
1611                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1612
1613                 /* One effective TX desc is consumed */
1614                 i = 1;
1615         }
1616         sc->jme_cdata.jme_tx_cnt++;
1617         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1618                  sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1619         JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1620
1621         txd->tx_ndesc = 1 - i;
1622         for (; i < nsegs; i++) {
1623                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1624                 desc->buflen = htole32(txsegs[i].ds_len);
1625                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1626                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1627                 desc->flags = htole32(JME_TD_OWN | flag64);
1628
1629                 sc->jme_cdata.jme_tx_cnt++;
1630                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1631                          sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1632                 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1633         }
1634
1635         /* Update producer index. */
1636         sc->jme_cdata.jme_tx_prod = prod;
1637         /*
1638          * Finally request interrupt and give the first descriptor
1639          * owenership to hardware.
1640          */
1641         desc = txd->tx_desc;
1642         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1643
1644         txd->tx_m = m;
1645         txd->tx_ndesc += nsegs;
1646
1647         return 0;
1648 fail:
1649         m_freem(*m_head);
1650         *m_head = NULL;
1651         return error;
1652 }
1653
1654 static void
1655 jme_start(struct ifnet *ifp)
1656 {
1657         struct jme_softc *sc = ifp->if_softc;
1658         struct mbuf *m_head;
1659         int enq = 0;
1660
1661         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1662
1663         if (!sc->jme_has_link) {
1664                 ifq_purge(&ifp->if_snd);
1665                 return;
1666         }
1667
1668         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1669                 return;
1670
1671         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1672                 jme_txeof(sc);
1673
1674         while (!ifq_is_empty(&ifp->if_snd)) {
1675                 /*
1676                  * Check number of available TX descs, always
1677                  * leave JME_TXD_RSVD free TX descs.
1678                  */
1679                 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1680                     sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1681                         ifp->if_flags |= IFF_OACTIVE;
1682                         break;
1683                 }
1684
1685                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1686                 if (m_head == NULL)
1687                         break;
1688
1689                 /*
1690                  * Pack the data into the transmit ring. If we
1691                  * don't have room, set the OACTIVE flag and wait
1692                  * for the NIC to drain the ring.
1693                  */
1694                 if (jme_encap(sc, &m_head)) {
1695                         KKASSERT(m_head == NULL);
1696                         ifp->if_oerrors++;
1697                         ifp->if_flags |= IFF_OACTIVE;
1698                         break;
1699                 }
1700                 enq++;
1701
1702                 /*
1703                  * If there's a BPF listener, bounce a copy of this frame
1704                  * to him.
1705                  */
1706                 ETHER_BPF_MTAP(ifp, m_head);
1707         }
1708
1709         if (enq > 0) {
1710                 /*
1711                  * Reading TXCSR takes very long time under heavy load
1712                  * so cache TXCSR value and writes the ORed value with
1713                  * the kick command to the TXCSR. This saves one register
1714                  * access cycle.
1715                  */
1716                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1717                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1718                 /* Set a timeout in case the chip goes out to lunch. */
1719                 ifp->if_timer = JME_TX_TIMEOUT;
1720         }
1721 }
1722
1723 static void
1724 jme_watchdog(struct ifnet *ifp)
1725 {
1726         struct jme_softc *sc = ifp->if_softc;
1727
1728         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1729
1730         if (!sc->jme_has_link) {
1731                 if_printf(ifp, "watchdog timeout (missed link)\n");
1732                 ifp->if_oerrors++;
1733                 jme_init(sc);
1734                 return;
1735         }
1736
1737         jme_txeof(sc);
1738         if (sc->jme_cdata.jme_tx_cnt == 0) {
1739                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1740                           "-- recovering\n");
1741                 if (!ifq_is_empty(&ifp->if_snd))
1742                         if_devstart(ifp);
1743                 return;
1744         }
1745
1746         if_printf(ifp, "watchdog timeout\n");
1747         ifp->if_oerrors++;
1748         jme_init(sc);
1749         if (!ifq_is_empty(&ifp->if_snd))
1750                 if_devstart(ifp);
1751 }
1752
1753 static int
1754 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1755 {
1756         struct jme_softc *sc = ifp->if_softc;
1757         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1758         struct ifreq *ifr = (struct ifreq *)data;
1759         int error = 0, mask;
1760
1761         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1762
1763         switch (cmd) {
1764         case SIOCSIFMTU:
1765                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1766                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1767                      ifr->ifr_mtu > JME_MAX_MTU)) {
1768                         error = EINVAL;
1769                         break;
1770                 }
1771
1772                 if (ifp->if_mtu != ifr->ifr_mtu) {
1773                         /*
1774                          * No special configuration is required when interface
1775                          * MTU is changed but availability of Tx checksum
1776                          * offload should be chcked against new MTU size as
1777                          * FIFO size is just 2K.
1778                          */
1779                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1780                                 ifp->if_capenable &= ~IFCAP_TXCSUM;
1781                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1782                         }
1783                         ifp->if_mtu = ifr->ifr_mtu;
1784                         if (ifp->if_flags & IFF_RUNNING)
1785                                 jme_init(sc);
1786                 }
1787                 break;
1788
1789         case SIOCSIFFLAGS:
1790                 if (ifp->if_flags & IFF_UP) {
1791                         if (ifp->if_flags & IFF_RUNNING) {
1792                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1793                                     (IFF_PROMISC | IFF_ALLMULTI))
1794                                         jme_set_filter(sc);
1795                         } else {
1796                                 jme_init(sc);
1797                         }
1798                 } else {
1799                         if (ifp->if_flags & IFF_RUNNING)
1800                                 jme_stop(sc);
1801                 }
1802                 sc->jme_if_flags = ifp->if_flags;
1803                 break;
1804
1805         case SIOCADDMULTI:
1806         case SIOCDELMULTI:
1807                 if (ifp->if_flags & IFF_RUNNING)
1808                         jme_set_filter(sc);
1809                 break;
1810
1811         case SIOCSIFMEDIA:
1812         case SIOCGIFMEDIA:
1813                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1814                 break;
1815
1816         case SIOCSIFCAP:
1817                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1818
1819                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1820                         ifp->if_capenable ^= IFCAP_TXCSUM;
1821                         if (IFCAP_TXCSUM & ifp->if_capenable)
1822                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1823                         else
1824                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1825                 }
1826                 if (mask & IFCAP_RXCSUM) {
1827                         uint32_t reg;
1828
1829                         ifp->if_capenable ^= IFCAP_RXCSUM;
1830                         reg = CSR_READ_4(sc, JME_RXMAC);
1831                         reg &= ~RXMAC_CSUM_ENB;
1832                         if (ifp->if_capenable & IFCAP_RXCSUM)
1833                                 reg |= RXMAC_CSUM_ENB;
1834                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1835                 }
1836
1837                 if (mask & IFCAP_VLAN_HWTAGGING) {
1838                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1839                         jme_set_vlan(sc);
1840                 }
1841
1842                 if (mask & IFCAP_RSS)
1843                         ifp->if_capenable ^= IFCAP_RSS;
1844                 break;
1845
1846         default:
1847                 error = ether_ioctl(ifp, cmd, data);
1848                 break;
1849         }
1850         return (error);
1851 }
1852
1853 static void
1854 jme_mac_config(struct jme_softc *sc)
1855 {
1856         struct mii_data *mii;
1857         uint32_t ghc, rxmac, txmac, txpause, gp1;
1858         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1859
1860         mii = device_get_softc(sc->jme_miibus);
1861
1862         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1863         DELAY(10);
1864         CSR_WRITE_4(sc, JME_GHC, 0);
1865         ghc = 0;
1866         rxmac = CSR_READ_4(sc, JME_RXMAC);
1867         rxmac &= ~RXMAC_FC_ENB;
1868         txmac = CSR_READ_4(sc, JME_TXMAC);
1869         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1870         txpause = CSR_READ_4(sc, JME_TXPFC);
1871         txpause &= ~TXPFC_PAUSE_ENB;
1872         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1873                 ghc |= GHC_FULL_DUPLEX;
1874                 rxmac &= ~RXMAC_COLL_DET_ENB;
1875                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1876                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1877                     TXMAC_FRAME_BURST);
1878 #ifdef notyet
1879                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1880                         txpause |= TXPFC_PAUSE_ENB;
1881                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1882                         rxmac |= RXMAC_FC_ENB;
1883 #endif
1884                 /* Disable retry transmit timer/retry limit. */
1885                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1886                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1887         } else {
1888                 rxmac |= RXMAC_COLL_DET_ENB;
1889                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1890                 /* Enable retry transmit timer/retry limit. */
1891                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1892                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1893         }
1894
1895         /*
1896          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1897          */
1898         gp1 = CSR_READ_4(sc, JME_GPREG1);
1899         gp1 &= ~GPREG1_WA_HDX;
1900
1901         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1902                 hdx = 1;
1903
1904         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1905         case IFM_10_T:
1906                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1907                 if (hdx)
1908                         gp1 |= GPREG1_WA_HDX;
1909                 break;
1910
1911         case IFM_100_TX:
1912                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1913                 if (hdx)
1914                         gp1 |= GPREG1_WA_HDX;
1915
1916                 /*
1917                  * Use extended FIFO depth to workaround CRC errors
1918                  * emitted by chips before JMC250B
1919                  */
1920                 phyconf = JMPHY_CONF_EXTFIFO;
1921                 break;
1922
1923         case IFM_1000_T:
1924                 if (sc->jme_caps & JME_CAP_FASTETH)
1925                         break;
1926
1927                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1928                 if (hdx)
1929                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1930                 break;
1931
1932         default:
1933                 break;
1934         }
1935         CSR_WRITE_4(sc, JME_GHC, ghc);
1936         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1937         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1938         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1939
1940         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1941                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1942                                     JMPHY_CONF, phyconf);
1943         }
1944         if (sc->jme_workaround & JME_WA_HDX)
1945                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1946 }
1947
1948 static void
1949 jme_intr(void *xsc)
1950 {
1951         struct jme_softc *sc = xsc;
1952         struct ifnet *ifp = &sc->arpcom.ac_if;
1953         uint32_t status;
1954         int r;
1955
1956         ASSERT_SERIALIZED(&sc->jme_serialize);
1957
1958         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1959         if (status == 0 || status == 0xFFFFFFFF)
1960                 return;
1961
1962         /* Disable interrupts. */
1963         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1964
1965         status = CSR_READ_4(sc, JME_INTR_STATUS);
1966         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1967                 goto back;
1968
1969         /* Reset PCC counter/timer and Ack interrupts. */
1970         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1971
1972         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1973                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1974
1975         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1976                 if (status & jme_rx_status[r].jme_coal) {
1977                         status |= jme_rx_status[r].jme_coal |
1978                                   jme_rx_status[r].jme_comp;
1979                 }
1980         }
1981
1982         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1983
1984         if (ifp->if_flags & IFF_RUNNING) {
1985                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1986                         jme_rx_intr(sc, status);
1987
1988                 if (status & INTR_RXQ_DESC_EMPTY) {
1989                         /*
1990                          * Notify hardware availability of new Rx buffers.
1991                          * Reading RXCSR takes very long time under heavy
1992                          * load so cache RXCSR value and writes the ORed
1993                          * value with the kick command to the RXCSR. This
1994                          * saves one register access cycle.
1995                          */
1996                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1997                             RXCSR_RX_ENB | RXCSR_RXQ_START);
1998                 }
1999
2000                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2001                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
2002                         jme_txeof(sc);
2003                         if (!ifq_is_empty(&ifp->if_snd))
2004                                 if_devstart(ifp);
2005                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
2006                 }
2007         }
2008 back:
2009         /* Reenable interrupts. */
2010         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2011 }
2012
2013 static void
2014 jme_txeof(struct jme_softc *sc)
2015 {
2016         struct ifnet *ifp = &sc->arpcom.ac_if;
2017         int cons;
2018
2019         cons = sc->jme_cdata.jme_tx_cons;
2020         if (cons == sc->jme_cdata.jme_tx_prod)
2021                 return;
2022
2023         /*
2024          * Go through our Tx list and free mbufs for those
2025          * frames which have been transmitted.
2026          */
2027         while (cons != sc->jme_cdata.jme_tx_prod) {
2028                 struct jme_txdesc *txd, *next_txd;
2029                 uint32_t status, next_status;
2030                 int next_cons, nsegs;
2031
2032                 txd = &sc->jme_cdata.jme_txdesc[cons];
2033                 KASSERT(txd->tx_m != NULL,
2034                         ("%s: freeing NULL mbuf!", __func__));
2035
2036                 status = le32toh(txd->tx_desc->flags);
2037                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2038                         break;
2039
2040                 /*
2041                  * NOTE:
2042                  * This chip will always update the TX descriptor's
2043                  * buflen field and this updating always happens
2044                  * after clearing the OWN bit, so even if the OWN
2045                  * bit is cleared by the chip, we still don't sure
2046                  * about whether the buflen field has been updated
2047                  * by the chip or not.  To avoid this race, we wait
2048                  * for the next TX descriptor's OWN bit to be cleared
2049                  * by the chip before reusing this TX descriptor.
2050                  */
2051                 next_cons = cons;
2052                 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2053                     sc->jme_cdata.jme_tx_desc_cnt);
2054                 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2055                 if (next_txd->tx_m == NULL)
2056                         break;
2057                 next_status = le32toh(next_txd->tx_desc->flags);
2058                 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2059                         break;
2060
2061                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2062                         ifp->if_oerrors++;
2063                 } else {
2064                         ifp->if_opackets++;
2065                         if (status & JME_TD_COLLISION) {
2066                                 ifp->if_collisions +=
2067                                     le32toh(txd->tx_desc->buflen) &
2068                                     JME_TD_BUF_LEN_MASK;
2069                         }
2070                 }
2071
2072                 /*
2073                  * Only the first descriptor of multi-descriptor
2074                  * transmission is updated so driver have to skip entire
2075                  * chained buffers for the transmiited frame. In other
2076                  * words, JME_TD_OWN bit is valid only at the first
2077                  * descriptor of a multi-descriptor transmission.
2078                  */
2079                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2080                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2081                         JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2082                 }
2083
2084                 /* Reclaim transferred mbufs. */
2085                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2086                 m_freem(txd->tx_m);
2087                 txd->tx_m = NULL;
2088                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2089                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2090                         ("%s: Active Tx desc counter was garbled", __func__));
2091                 txd->tx_ndesc = 0;
2092         }
2093         sc->jme_cdata.jme_tx_cons = cons;
2094
2095         if (sc->jme_cdata.jme_tx_cnt < JME_MAXTXSEGS + 1)
2096                 ifp->if_timer = 0;
2097
2098         if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2099             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2100                 ifp->if_flags &= ~IFF_OACTIVE;
2101 }
2102
2103 static __inline void
2104 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2105 {
2106         int i;
2107
2108         for (i = 0; i < count; ++i) {
2109                 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2110                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2111         }
2112 }
2113
2114 static __inline struct pktinfo *
2115 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2116 {
2117         if (flags & JME_RD_IPV4)
2118                 pi->pi_netisr = NETISR_IP;
2119         else if (flags & JME_RD_IPV6)
2120                 pi->pi_netisr = NETISR_IPV6;
2121         else
2122                 return NULL;
2123
2124         pi->pi_flags = 0;
2125         pi->pi_l3proto = IPPROTO_UNKNOWN;
2126
2127         if (flags & JME_RD_MORE_FRAG)
2128                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2129         else if (flags & JME_RD_TCP)
2130                 pi->pi_l3proto = IPPROTO_TCP;
2131         else if (flags & JME_RD_UDP)
2132                 pi->pi_l3proto = IPPROTO_UDP;
2133         else
2134                 pi = NULL;
2135         return pi;
2136 }
2137
2138 /* Receive a frame. */
2139 static void
2140 jme_rxpkt(struct jme_rxdata *rdata)
2141 {
2142         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2143         struct jme_desc *desc;
2144         struct jme_rxdesc *rxd;
2145         struct mbuf *mp, *m;
2146         uint32_t flags, status, hash, hashinfo;
2147         int cons, count, nsegs;
2148
2149         cons = rdata->jme_rx_cons;
2150         desc = &rdata->jme_rx_ring[cons];
2151
2152         flags = le32toh(desc->flags);
2153         status = le32toh(desc->buflen);
2154         hash = le32toh(desc->addr_hi);
2155         hashinfo = le32toh(desc->addr_lo);
2156         nsegs = JME_RX_NSEGS(status);
2157
2158         if (nsegs > 1) {
2159                 /* Skip the first descriptor. */
2160                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2161
2162                 /*
2163                  * Clear the OWN bit of the following RX descriptors;
2164                  * hardware will not clear the OWN bit except the first
2165                  * RX descriptor.
2166                  *
2167                  * Since the first RX descriptor is setup, i.e. OWN bit
2168                  * on, before its followins RX descriptors, leaving the
2169                  * OWN bit on the following RX descriptors will trick
2170                  * the hardware into thinking that the following RX
2171                  * descriptors are ready to be used too.
2172                  */
2173                 for (count = 1; count < nsegs; count++,
2174                      JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2175                         rdata->jme_rx_ring[cons].flags = 0;
2176
2177                 cons = rdata->jme_rx_cons;
2178         }
2179
2180         JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2181                         "hash 0x%08x, hash info 0x%08x\n",
2182                         rdata->jme_rx_idx, flags, hash, hashinfo);
2183
2184         if (status & JME_RX_ERR_STAT) {
2185                 ifp->if_ierrors++;
2186                 jme_discard_rxbufs(rdata, cons, nsegs);
2187 #ifdef JME_SHOW_ERRORS
2188                 if_printf(ifp, "%s : receive error = 0x%b\n",
2189                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2190 #endif
2191                 rdata->jme_rx_cons += nsegs;
2192                 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2193                 return;
2194         }
2195
2196         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2197         for (count = 0; count < nsegs; count++,
2198              JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2199                 rxd = &rdata->jme_rxdesc[cons];
2200                 mp = rxd->rx_m;
2201
2202                 /* Add a new receive buffer to the ring. */
2203                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2204                         ifp->if_iqdrops++;
2205                         /* Reuse buffer. */
2206                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2207                         if (rdata->jme_rxhead != NULL) {
2208                                 m_freem(rdata->jme_rxhead);
2209                                 JME_RXCHAIN_RESET(rdata);
2210                         }
2211                         break;
2212                 }
2213
2214                 /*
2215                  * Assume we've received a full sized frame.
2216                  * Actual size is fixed when we encounter the end of
2217                  * multi-segmented frame.
2218                  */
2219                 mp->m_len = MCLBYTES;
2220
2221                 /* Chain received mbufs. */
2222                 if (rdata->jme_rxhead == NULL) {
2223                         rdata->jme_rxhead = mp;
2224                         rdata->jme_rxtail = mp;
2225                 } else {
2226                         /*
2227                          * Receive processor can receive a maximum frame
2228                          * size of 65535 bytes.
2229                          */
2230                         rdata->jme_rxtail->m_next = mp;
2231                         rdata->jme_rxtail = mp;
2232                 }
2233
2234                 if (count == nsegs - 1) {
2235                         struct pktinfo pi0, *pi;
2236
2237                         /* Last desc. for this frame. */
2238                         m = rdata->jme_rxhead;
2239                         m->m_pkthdr.len = rdata->jme_rxlen;
2240                         if (nsegs > 1) {
2241                                 /* Set first mbuf size. */
2242                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2243                                 /* Set last mbuf size. */
2244                                 mp->m_len = rdata->jme_rxlen -
2245                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2246                                     (MCLBYTES * (nsegs - 2)));
2247                         } else {
2248                                 m->m_len = rdata->jme_rxlen;
2249                         }
2250                         m->m_pkthdr.rcvif = ifp;
2251
2252                         /*
2253                          * Account for 10bytes auto padding which is used
2254                          * to align IP header on 32bit boundary. Also note,
2255                          * CRC bytes is automatically removed by the
2256                          * hardware.
2257                          */
2258                         m->m_data += JME_RX_PAD_BYTES;
2259
2260                         /* Set checksum information. */
2261                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2262                             (flags & JME_RD_IPV4)) {
2263                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2264                                 if (flags & JME_RD_IPCSUM)
2265                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2266                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2267                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2268                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2269                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2270                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2271                                         m->m_pkthdr.csum_flags |=
2272                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2273                                         m->m_pkthdr.csum_data = 0xffff;
2274                                 }
2275                         }
2276
2277                         /* Check for VLAN tagged packets. */
2278                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2279                             (flags & JME_RD_VLAN_TAG)) {
2280                                 m->m_pkthdr.ether_vlantag =
2281                                     flags & JME_RD_VLAN_MASK;
2282                                 m->m_flags |= M_VLANTAG;
2283                         }
2284
2285                         ifp->if_ipackets++;
2286
2287                         if (ifp->if_capenable & IFCAP_RSS)
2288                                 pi = jme_pktinfo(&pi0, flags);
2289                         else
2290                                 pi = NULL;
2291
2292                         if (pi != NULL &&
2293                             (hashinfo & JME_RD_HASH_FN_MASK) ==
2294                             JME_RD_HASH_FN_TOEPLITZ) {
2295                                 m->m_flags |= (M_HASH | M_CKHASH);
2296                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2297                         }
2298
2299 #ifdef JME_RSS_DEBUG
2300                         if (pi != NULL) {
2301                                 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2302                                     "isr %d flags %08x, l3 %d %s\n",
2303                                     pi->pi_netisr, pi->pi_flags,
2304                                     pi->pi_l3proto,
2305                                     (m->m_flags & M_HASH) ? "hash" : "");
2306                         }
2307 #endif
2308
2309                         /* Pass it on. */
2310                         ether_input_pkt(ifp, m, pi);
2311
2312                         /* Reset mbuf chains. */
2313                         JME_RXCHAIN_RESET(rdata);
2314 #ifdef JME_RSS_DEBUG
2315                         rdata->jme_rx_pkt++;
2316 #endif
2317                 }
2318         }
2319
2320         rdata->jme_rx_cons += nsegs;
2321         rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2322 }
2323
2324 static void
2325 jme_rxeof(struct jme_rxdata *rdata, int count)
2326 {
2327         struct jme_desc *desc;
2328         int nsegs, pktlen;
2329
2330         for (;;) {
2331 #ifdef DEVICE_POLLING
2332                 if (count >= 0 && count-- == 0)
2333                         break;
2334 #endif
2335                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2336                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2337                         break;
2338                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2339                         break;
2340
2341                 /*
2342                  * Check number of segments against received bytes.
2343                  * Non-matching value would indicate that hardware
2344                  * is still trying to update Rx descriptors. I'm not
2345                  * sure whether this check is needed.
2346                  */
2347                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2348                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2349                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2350                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2351                             "RX fragment count(%d) and "
2352                             "packet size(%d) mismach\n", nsegs, pktlen);
2353                         break;
2354                 }
2355
2356                 /*
2357                  * NOTE:
2358                  * RSS hash and hash information may _not_ be set by the
2359                  * hardware even if the OWN bit is cleared and VALID bit
2360                  * is set.
2361                  *
2362                  * If the RSS information is not delivered by the hardware
2363                  * yet, we MUST NOT accept this packet, let alone reusing
2364                  * its RX descriptor.  If this packet was accepted and its
2365                  * RX descriptor was reused before hardware delivering the
2366                  * RSS information, the RX buffer's address would be trashed
2367                  * by the RSS information delivered by the hardware.
2368                  */
2369                 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2370                         struct jme_rxdesc *rxd;
2371                         uint32_t hashinfo;
2372
2373                         hashinfo = le32toh(desc->addr_lo);
2374                         rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2375
2376                         /*
2377                          * This test should be enough to detect the pending
2378                          * RSS information delivery, given:
2379                          * - If RSS hash is not calculated, the hashinfo
2380                          *   will be 0.  Howvever, the lower 32bits of RX
2381                          *   buffers' physical address will never be 0.
2382                          *   (see jme_rxbuf_dma_filter)
2383                          * - If RSS hash is calculated, the lowest 4 bits
2384                          *   of hashinfo will be set, while the RX buffers
2385                          *   are at least 2K aligned.
2386                          */
2387                         if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2388 #ifdef JME_SHOW_RSSWB
2389                                 if_printf(&rdata->jme_sc->arpcom.ac_if,
2390                                     "RSS is not written back yet\n");
2391 #endif
2392                                 break;
2393                         }
2394                 }
2395
2396                 /* Received a frame. */
2397                 jme_rxpkt(rdata);
2398         }
2399 }
2400
2401 static void
2402 jme_tick(void *xsc)
2403 {
2404         struct jme_softc *sc = xsc;
2405         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2406
2407         lwkt_serialize_enter(&sc->jme_serialize);
2408
2409         sc->jme_in_tick = TRUE;
2410         mii_tick(mii);
2411         sc->jme_in_tick = FALSE;
2412
2413         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2414
2415         lwkt_serialize_exit(&sc->jme_serialize);
2416 }
2417
2418 static void
2419 jme_reset(struct jme_softc *sc)
2420 {
2421         uint32_t val;
2422
2423         /* Make sure that TX and RX are stopped */
2424         jme_stop_tx(sc);
2425         jme_stop_rx(sc);
2426
2427         /* Start reset */
2428         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2429         DELAY(20);
2430
2431         /*
2432          * Hold reset bit before stop reset
2433          */
2434
2435         /* Disable TXMAC and TXOFL clock sources */
2436         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2437         /* Disable RXMAC clock source */
2438         val = CSR_READ_4(sc, JME_GPREG1);
2439         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2440         /* Flush */
2441         CSR_READ_4(sc, JME_GHC);
2442
2443         /* Stop reset */
2444         CSR_WRITE_4(sc, JME_GHC, 0);
2445         /* Flush */
2446         CSR_READ_4(sc, JME_GHC);
2447
2448         /*
2449          * Clear reset bit after stop reset
2450          */
2451
2452         /* Enable TXMAC and TXOFL clock sources */
2453         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2454         /* Enable RXMAC clock source */
2455         val = CSR_READ_4(sc, JME_GPREG1);
2456         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2457         /* Flush */
2458         CSR_READ_4(sc, JME_GHC);
2459
2460         /* Disable TXMAC and TXOFL clock sources */
2461         CSR_WRITE_4(sc, JME_GHC, 0);
2462         /* Disable RXMAC clock source */
2463         val = CSR_READ_4(sc, JME_GPREG1);
2464         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2465         /* Flush */
2466         CSR_READ_4(sc, JME_GHC);
2467
2468         /* Enable TX and RX */
2469         val = CSR_READ_4(sc, JME_TXCSR);
2470         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2471         val = CSR_READ_4(sc, JME_RXCSR);
2472         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2473         /* Flush */
2474         CSR_READ_4(sc, JME_TXCSR);
2475         CSR_READ_4(sc, JME_RXCSR);
2476
2477         /* Enable TXMAC and TXOFL clock sources */
2478         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2479         /* Eisable RXMAC clock source */
2480         val = CSR_READ_4(sc, JME_GPREG1);
2481         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2482         /* Flush */
2483         CSR_READ_4(sc, JME_GHC);
2484
2485         /* Stop TX and RX */
2486         jme_stop_tx(sc);
2487         jme_stop_rx(sc);
2488 }
2489
2490 static void
2491 jme_init(void *xsc)
2492 {
2493         struct jme_softc *sc = xsc;
2494         struct ifnet *ifp = &sc->arpcom.ac_if;
2495         struct mii_data *mii;
2496         uint8_t eaddr[ETHER_ADDR_LEN];
2497         bus_addr_t paddr;
2498         uint32_t reg;
2499         int error, r;
2500
2501         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2502
2503         /*
2504          * Cancel any pending I/O.
2505          */
2506         jme_stop(sc);
2507
2508         /*
2509          * Reset the chip to a known state.
2510          */
2511         jme_reset(sc);
2512
2513         /*
2514          * Setup MSI/MSI-X vectors to interrupts mapping
2515          */
2516         jme_set_msinum(sc);
2517
2518         sc->jme_txd_spare =
2519         howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2520         KKASSERT(sc->jme_txd_spare >= 1);
2521
2522         /*
2523          * If we use 64bit address mode for transmitting, each Tx request
2524          * needs one more symbol descriptor.
2525          */
2526         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2527                 sc->jme_txd_spare += 1;
2528
2529         if (JME_ENABLE_HWRSS(sc))
2530                 jme_enable_rss(sc);
2531         else
2532                 jme_disable_rss(sc);
2533
2534         /* Init RX descriptors */
2535         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2536                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2537                 if (error) {
2538                         if_printf(ifp, "initialization failed: "
2539                                   "no memory for %dth RX ring.\n", r);
2540                         jme_stop(sc);
2541                         return;
2542                 }
2543         }
2544
2545         /* Init TX descriptors */
2546         jme_init_tx_ring(sc);
2547
2548         /* Initialize shadow status block. */
2549         jme_init_ssb(sc);
2550
2551         /* Reprogram the station address. */
2552         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2553         CSR_WRITE_4(sc, JME_PAR0,
2554             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2555         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2556
2557         /*
2558          * Configure Tx queue.
2559          *  Tx priority queue weight value : 0
2560          *  Tx FIFO threshold for processing next packet : 16QW
2561          *  Maximum Tx DMA length : 512
2562          *  Allow Tx DMA burst.
2563          */
2564         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2565         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2566         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2567         sc->jme_txcsr |= sc->jme_tx_dma_size;
2568         sc->jme_txcsr |= TXCSR_DMA_BURST;
2569         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2570
2571         /* Set Tx descriptor counter. */
2572         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2573
2574         /* Set Tx ring address to the hardware. */
2575         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2576         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2577         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2578
2579         /* Configure TxMAC parameters. */
2580         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2581         reg |= TXMAC_THRESH_1_PKT;
2582         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2583         CSR_WRITE_4(sc, JME_TXMAC, reg);
2584
2585         /*
2586          * Configure Rx queue.
2587          *  FIFO full threshold for transmitting Tx pause packet : 128T
2588          *  FIFO threshold for processing next packet : 128QW
2589          *  Rx queue 0 select
2590          *  Max Rx DMA length : 128
2591          *  Rx descriptor retry : 32
2592          *  Rx descriptor retry time gap : 256ns
2593          *  Don't receive runt/bad frame.
2594          */
2595         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2596 #if 0
2597         /*
2598          * Since Rx FIFO size is 4K bytes, receiving frames larger
2599          * than 4K bytes will suffer from Rx FIFO overruns. So
2600          * decrease FIFO threshold to reduce the FIFO overruns for
2601          * frames larger than 4000 bytes.
2602          * For best performance of standard MTU sized frames use
2603          * maximum allowable FIFO threshold, 128QW.
2604          */
2605         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2606             JME_RX_FIFO_SIZE)
2607                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2608         else
2609                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2610 #else
2611         /* Improve PCI Express compatibility */
2612         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2613 #endif
2614         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2615         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2616         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2617         /* XXX TODO DROP_BAD */
2618
2619         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2620                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2621
2622                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2623
2624                 /* Set Rx descriptor counter. */
2625                 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2626
2627                 /* Set Rx ring address to the hardware. */
2628                 paddr = rdata->jme_rx_ring_paddr;
2629                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2630                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2631         }
2632
2633         /* Clear receive filter. */
2634         CSR_WRITE_4(sc, JME_RXMAC, 0);
2635
2636         /* Set up the receive filter. */
2637         jme_set_filter(sc);
2638         jme_set_vlan(sc);
2639
2640         /*
2641          * Disable all WOL bits as WOL can interfere normal Rx
2642          * operation. Also clear WOL detection status bits.
2643          */
2644         reg = CSR_READ_4(sc, JME_PMCS);
2645         reg &= ~PMCS_WOL_ENB_MASK;
2646         CSR_WRITE_4(sc, JME_PMCS, reg);
2647
2648         /*
2649          * Pad 10bytes right before received frame. This will greatly
2650          * help Rx performance on strict-alignment architectures as
2651          * it does not need to copy the frame to align the payload.
2652          */
2653         reg = CSR_READ_4(sc, JME_RXMAC);
2654         reg |= RXMAC_PAD_10BYTES;
2655
2656         if (ifp->if_capenable & IFCAP_RXCSUM)
2657                 reg |= RXMAC_CSUM_ENB;
2658         CSR_WRITE_4(sc, JME_RXMAC, reg);
2659
2660         /* Configure general purpose reg0 */
2661         reg = CSR_READ_4(sc, JME_GPREG0);
2662         reg &= ~GPREG0_PCC_UNIT_MASK;
2663         /* Set PCC timer resolution to micro-seconds unit. */
2664         reg |= GPREG0_PCC_UNIT_US;
2665         /*
2666          * Disable all shadow register posting as we have to read
2667          * JME_INTR_STATUS register in jme_intr. Also it seems
2668          * that it's hard to synchronize interrupt status between
2669          * hardware and software with shadow posting due to
2670          * requirements of bus_dmamap_sync(9).
2671          */
2672         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2673             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2674             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2675             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2676         /* Disable posting of DW0. */
2677         reg &= ~GPREG0_POST_DW0_ENB;
2678         /* Clear PME message. */
2679         reg &= ~GPREG0_PME_ENB;
2680         /* Set PHY address. */
2681         reg &= ~GPREG0_PHY_ADDR_MASK;
2682         reg |= sc->jme_phyaddr;
2683         CSR_WRITE_4(sc, JME_GPREG0, reg);
2684
2685         /* Configure Tx queue 0 packet completion coalescing. */
2686         jme_set_tx_coal(sc);
2687
2688         /* Configure Rx queues packet completion coalescing. */
2689         jme_set_rx_coal(sc);
2690
2691         /* Configure shadow status block but don't enable posting. */
2692         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2693         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2694         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2695
2696         /* Disable Timer 1 and Timer 2. */
2697         CSR_WRITE_4(sc, JME_TIMER1, 0);
2698         CSR_WRITE_4(sc, JME_TIMER2, 0);
2699
2700         /* Configure retry transmit period, retry limit value. */
2701         CSR_WRITE_4(sc, JME_TXTRHD,
2702             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2703             TXTRHD_RT_PERIOD_MASK) |
2704             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2705             TXTRHD_RT_LIMIT_SHIFT));
2706
2707 #ifdef DEVICE_POLLING
2708         if (!(ifp->if_flags & IFF_POLLING))
2709 #endif
2710         /* Initialize the interrupt mask. */
2711         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2712         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2713
2714         /*
2715          * Enabling Tx/Rx DMA engines and Rx queue processing is
2716          * done after detection of valid link in jme_miibus_statchg.
2717          */
2718         sc->jme_has_link = FALSE;
2719
2720         /* Set the current media. */
2721         mii = device_get_softc(sc->jme_miibus);
2722         mii_mediachg(mii);
2723
2724         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2725
2726         ifp->if_flags |= IFF_RUNNING;
2727         ifp->if_flags &= ~IFF_OACTIVE;
2728 }
2729
2730 static void
2731 jme_stop(struct jme_softc *sc)
2732 {
2733         struct ifnet *ifp = &sc->arpcom.ac_if;
2734         struct jme_txdesc *txd;
2735         struct jme_rxdesc *rxd;
2736         struct jme_rxdata *rdata;
2737         int i, r;
2738
2739         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2740
2741         /*
2742          * Mark the interface down and cancel the watchdog timer.
2743          */
2744         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2745         ifp->if_timer = 0;
2746
2747         callout_stop(&sc->jme_tick_ch);
2748         sc->jme_has_link = FALSE;
2749
2750         /*
2751          * Disable interrupts.
2752          */
2753         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2754         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2755
2756         /* Disable updating shadow status block. */
2757         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2758             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2759
2760         /* Stop receiver, transmitter. */
2761         jme_stop_rx(sc);
2762         jme_stop_tx(sc);
2763
2764         /*
2765          * Free partial finished RX segments
2766          */
2767         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2768                 rdata = &sc->jme_cdata.jme_rx_data[r];
2769                 if (rdata->jme_rxhead != NULL)
2770                         m_freem(rdata->jme_rxhead);
2771                 JME_RXCHAIN_RESET(rdata);
2772         }
2773
2774         /*
2775          * Free RX and TX mbufs still in the queues.
2776          */
2777         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2778                 rdata = &sc->jme_cdata.jme_rx_data[r];
2779                 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2780                         rxd = &rdata->jme_rxdesc[i];
2781                         if (rxd->rx_m != NULL) {
2782                                 bus_dmamap_unload(rdata->jme_rx_tag,
2783                                                   rxd->rx_dmamap);
2784                                 m_freem(rxd->rx_m);
2785                                 rxd->rx_m = NULL;
2786                         }
2787                 }
2788         }
2789         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2790                 txd = &sc->jme_cdata.jme_txdesc[i];
2791                 if (txd->tx_m != NULL) {
2792                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2793                             txd->tx_dmamap);
2794                         m_freem(txd->tx_m);
2795                         txd->tx_m = NULL;
2796                         txd->tx_ndesc = 0;
2797                 }
2798         }
2799 }
2800
2801 static void
2802 jme_stop_tx(struct jme_softc *sc)
2803 {
2804         uint32_t reg;
2805         int i;
2806
2807         reg = CSR_READ_4(sc, JME_TXCSR);
2808         if ((reg & TXCSR_TX_ENB) == 0)
2809                 return;
2810         reg &= ~TXCSR_TX_ENB;
2811         CSR_WRITE_4(sc, JME_TXCSR, reg);
2812         for (i = JME_TIMEOUT; i > 0; i--) {
2813                 DELAY(1);
2814                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2815                         break;
2816         }
2817         if (i == 0)
2818                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2819 }
2820
2821 static void
2822 jme_stop_rx(struct jme_softc *sc)
2823 {
2824         uint32_t reg;
2825         int i;
2826
2827         reg = CSR_READ_4(sc, JME_RXCSR);
2828         if ((reg & RXCSR_RX_ENB) == 0)
2829                 return;
2830         reg &= ~RXCSR_RX_ENB;
2831         CSR_WRITE_4(sc, JME_RXCSR, reg);
2832         for (i = JME_TIMEOUT; i > 0; i--) {
2833                 DELAY(1);
2834                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2835                         break;
2836         }
2837         if (i == 0)
2838                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2839 }
2840
2841 static void
2842 jme_init_tx_ring(struct jme_softc *sc)
2843 {
2844         struct jme_chain_data *cd;
2845         struct jme_txdesc *txd;
2846         int i;
2847
2848         sc->jme_cdata.jme_tx_prod = 0;
2849         sc->jme_cdata.jme_tx_cons = 0;
2850         sc->jme_cdata.jme_tx_cnt = 0;
2851
2852         cd = &sc->jme_cdata;
2853         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2854         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2855                 txd = &sc->jme_cdata.jme_txdesc[i];
2856                 txd->tx_m = NULL;
2857                 txd->tx_desc = &cd->jme_tx_ring[i];
2858                 txd->tx_ndesc = 0;
2859         }
2860 }
2861
2862 static void
2863 jme_init_ssb(struct jme_softc *sc)
2864 {
2865         struct jme_chain_data *cd;
2866
2867         cd = &sc->jme_cdata;
2868         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2869 }
2870
2871 static int
2872 jme_init_rx_ring(struct jme_rxdata *rdata)
2873 {
2874         struct jme_rxdesc *rxd;
2875         int i;
2876
2877         KKASSERT(rdata->jme_rxhead == NULL &&
2878                  rdata->jme_rxtail == NULL &&
2879                  rdata->jme_rxlen == 0);
2880         rdata->jme_rx_cons = 0;
2881
2882         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2883         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2884                 int error;
2885
2886                 rxd = &rdata->jme_rxdesc[i];
2887                 rxd->rx_m = NULL;
2888                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2889                 error = jme_newbuf(rdata, rxd, 1);
2890                 if (error)
2891                         return error;
2892         }
2893         return 0;
2894 }
2895
2896 static int
2897 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2898 {
2899         struct mbuf *m;
2900         bus_dma_segment_t segs;
2901         bus_dmamap_t map;
2902         int error, nsegs;
2903
2904         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2905         if (m == NULL)
2906                 return ENOBUFS;
2907         /*
2908          * JMC250 has 64bit boundary alignment limitation so jme(4)
2909          * takes advantage of 10 bytes padding feature of hardware
2910          * in order not to copy entire frame to align IP header on
2911          * 32bit boundary.
2912          */
2913         m->m_len = m->m_pkthdr.len = MCLBYTES;
2914
2915         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2916                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2917                         BUS_DMA_NOWAIT);
2918         if (error) {
2919                 m_freem(m);
2920                 if (init) {
2921                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2922                             "can't load RX mbuf\n");
2923                 }
2924                 return error;
2925         }
2926
2927         if (rxd->rx_m != NULL) {
2928                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2929                                 BUS_DMASYNC_POSTREAD);
2930                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2931         }
2932         map = rxd->rx_dmamap;
2933         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2934         rdata->jme_rx_sparemap = map;
2935         rxd->rx_m = m;
2936         rxd->rx_paddr = segs.ds_addr;
2937
2938         jme_setup_rxdesc(rxd);
2939         return 0;
2940 }
2941
2942 static void
2943 jme_set_vlan(struct jme_softc *sc)
2944 {
2945         struct ifnet *ifp = &sc->arpcom.ac_if;
2946         uint32_t reg;
2947
2948         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2949
2950         reg = CSR_READ_4(sc, JME_RXMAC);
2951         reg &= ~RXMAC_VLAN_ENB;
2952         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2953                 reg |= RXMAC_VLAN_ENB;
2954         CSR_WRITE_4(sc, JME_RXMAC, reg);
2955 }
2956
2957 static void
2958 jme_set_filter(struct jme_softc *sc)
2959 {
2960         struct ifnet *ifp = &sc->arpcom.ac_if;
2961         struct ifmultiaddr *ifma;
2962         uint32_t crc;
2963         uint32_t mchash[2];
2964         uint32_t rxcfg;
2965
2966         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2967
2968         rxcfg = CSR_READ_4(sc, JME_RXMAC);
2969         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2970             RXMAC_ALLMULTI);
2971
2972         /*
2973          * Always accept frames destined to our station address.
2974          * Always accept broadcast frames.
2975          */
2976         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2977
2978         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2979                 if (ifp->if_flags & IFF_PROMISC)
2980                         rxcfg |= RXMAC_PROMISC;
2981                 if (ifp->if_flags & IFF_ALLMULTI)
2982                         rxcfg |= RXMAC_ALLMULTI;
2983                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2984                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2985                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2986                 return;
2987         }
2988
2989         /*
2990          * Set up the multicast address filter by passing all multicast
2991          * addresses through a CRC generator, and then using the low-order
2992          * 6 bits as an index into the 64 bit multicast hash table.  The
2993          * high order bits select the register, while the rest of the bits
2994          * select the bit within the register.
2995          */
2996         rxcfg |= RXMAC_MULTICAST;
2997         bzero(mchash, sizeof(mchash));
2998
2999         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3000                 if (ifma->ifma_addr->sa_family != AF_LINK)
3001                         continue;
3002                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3003                     ifma->ifma_addr), ETHER_ADDR_LEN);
3004
3005                 /* Just want the 6 least significant bits. */
3006                 crc &= 0x3f;
3007
3008                 /* Set the corresponding bit in the hash table. */
3009                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3010         }
3011
3012         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3013         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3014         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3015 }
3016
3017 static int
3018 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3019 {
3020         struct jme_softc *sc = arg1;
3021         struct ifnet *ifp = &sc->arpcom.ac_if;
3022         int error, v;
3023
3024         ifnet_serialize_all(ifp);
3025
3026         v = sc->jme_tx_coal_to;
3027         error = sysctl_handle_int(oidp, &v, 0, req);
3028         if (error || req->newptr == NULL)
3029                 goto back;
3030
3031         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3032                 error = EINVAL;
3033                 goto back;
3034         }
3035
3036         if (v != sc->jme_tx_coal_to) {
3037                 sc->jme_tx_coal_to = v;
3038                 if (ifp->if_flags & IFF_RUNNING)
3039                         jme_set_tx_coal(sc);
3040         }
3041 back:
3042         ifnet_deserialize_all(ifp);
3043         return error;
3044 }
3045
3046 static int
3047 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3048 {
3049         struct jme_softc *sc = arg1;
3050         struct ifnet *ifp = &sc->arpcom.ac_if;
3051         int error, v;
3052
3053         ifnet_serialize_all(ifp);
3054
3055         v = sc->jme_tx_coal_pkt;
3056         error = sysctl_handle_int(oidp, &v, 0, req);
3057         if (error || req->newptr == NULL)
3058                 goto back;
3059
3060         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3061                 error = EINVAL;
3062                 goto back;
3063         }
3064
3065         if (v != sc->jme_tx_coal_pkt) {
3066                 sc->jme_tx_coal_pkt = v;
3067                 if (ifp->if_flags & IFF_RUNNING)
3068                         jme_set_tx_coal(sc);
3069         }
3070 back:
3071         ifnet_deserialize_all(ifp);
3072         return error;
3073 }
3074
3075 static int
3076 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3077 {
3078         struct jme_softc *sc = arg1;
3079         struct ifnet *ifp = &sc->arpcom.ac_if;
3080         int error, v;
3081
3082         ifnet_serialize_all(ifp);
3083
3084         v = sc->jme_rx_coal_to;
3085         error = sysctl_handle_int(oidp, &v, 0, req);
3086         if (error || req->newptr == NULL)
3087                 goto back;
3088
3089         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3090                 error = EINVAL;
3091                 goto back;
3092         }
3093
3094         if (v != sc->jme_rx_coal_to) {
3095                 sc->jme_rx_coal_to = v;
3096                 if (ifp->if_flags & IFF_RUNNING)
3097                         jme_set_rx_coal(sc);
3098         }
3099 back:
3100         ifnet_deserialize_all(ifp);
3101         return error;
3102 }
3103
3104 static int
3105 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3106 {
3107         struct jme_softc *sc = arg1;
3108         struct ifnet *ifp = &sc->arpcom.ac_if;
3109         int error, v;
3110
3111         ifnet_serialize_all(ifp);
3112
3113         v = sc->jme_rx_coal_pkt;
3114         error = sysctl_handle_int(oidp, &v, 0, req);
3115         if (error || req->newptr == NULL)
3116                 goto back;
3117
3118         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3119                 error = EINVAL;
3120                 goto back;
3121         }
3122
3123         if (v != sc->jme_rx_coal_pkt) {
3124                 sc->jme_rx_coal_pkt = v;
3125                 if (ifp->if_flags & IFF_RUNNING)
3126                         jme_set_rx_coal(sc);
3127         }
3128 back:
3129         ifnet_deserialize_all(ifp);
3130         return error;
3131 }
3132
3133 static void
3134 jme_set_tx_coal(struct jme_softc *sc)
3135 {
3136         uint32_t reg;
3137
3138         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3139             PCCTX_COAL_TO_MASK;
3140         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3141             PCCTX_COAL_PKT_MASK;
3142         reg |= PCCTX_COAL_TXQ0;
3143         CSR_WRITE_4(sc, JME_PCCTX, reg);
3144 }
3145
3146 static void
3147 jme_set_rx_coal(struct jme_softc *sc)
3148 {
3149         uint32_t reg;
3150         int r;
3151
3152         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3153             PCCRX_COAL_TO_MASK;
3154         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3155             PCCRX_COAL_PKT_MASK;
3156         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3157                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3158 }
3159
3160 #ifdef DEVICE_POLLING
3161
3162 static void
3163 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3164 {
3165         struct jme_softc *sc = ifp->if_softc;
3166         uint32_t status;
3167         int r;
3168
3169         ASSERT_SERIALIZED(&sc->jme_serialize);
3170
3171         switch (cmd) {
3172         case POLL_REGISTER:
3173                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3174                 break;
3175
3176         case POLL_DEREGISTER:
3177                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3178                 break;
3179
3180         case POLL_AND_CHECK_STATUS:
3181         case POLL_ONLY:
3182                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3183
3184                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3185                         struct jme_rxdata *rdata =
3186                             &sc->jme_cdata.jme_rx_data[r];
3187
3188                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3189                         jme_rxeof(rdata, count);
3190                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3191                 }
3192
3193                 if (status & INTR_RXQ_DESC_EMPTY) {
3194                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3195                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3196                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3197                 }
3198
3199                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3200                 jme_txeof(sc);
3201                 if (!ifq_is_empty(&ifp->if_snd))
3202                         if_devstart(ifp);
3203                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3204                 break;
3205         }
3206 }
3207
3208 #endif  /* DEVICE_POLLING */
3209
3210 static int
3211 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3212 {
3213         bus_dmamem_t dmem;
3214         int error, asize;
3215
3216         asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3217         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3218                         JME_RX_RING_ALIGN, 0,
3219                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3220                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3221         if (error) {
3222                 device_printf(rdata->jme_sc->jme_dev,
3223                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3224                 return error;
3225         }
3226         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3227         rdata->jme_rx_ring_map = dmem.dmem_map;
3228         rdata->jme_rx_ring = dmem.dmem_addr;
3229         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3230
3231         return 0;
3232 }
3233
3234 static int
3235 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3236 {
3237         if ((paddr & 0xffffffff) == 0) {
3238                 /*
3239                  * Don't allow lower 32bits of the RX buffer's
3240                  * physical address to be 0, else it will break
3241                  * hardware pending RSS information delivery
3242                  * detection on RX path.
3243                  */
3244                 return 1;
3245         }
3246         return 0;
3247 }
3248
3249 static int
3250 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3251 {
3252         bus_addr_t lowaddr;
3253         int i, error;
3254
3255         lowaddr = BUS_SPACE_MAXADDR;
3256         if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3257                 /* jme_rxbuf_dma_filter will be called */
3258                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3259         }
3260
3261         /* Create tag for Rx buffers. */
3262         error = bus_dma_tag_create(
3263             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3264             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3265             lowaddr,                    /* lowaddr */
3266             BUS_SPACE_MAXADDR,          /* highaddr */
3267             jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3268             MCLBYTES,                   /* maxsize */
3269             1,                          /* nsegments */
3270             MCLBYTES,                   /* maxsegsize */
3271             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3272             &rdata->jme_rx_tag);
3273         if (error) {
3274                 device_printf(rdata->jme_sc->jme_dev,
3275                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3276                 return error;
3277         }
3278
3279         /* Create DMA maps for Rx buffers. */
3280         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3281                                   &rdata->jme_rx_sparemap);
3282         if (error) {
3283                 device_printf(rdata->jme_sc->jme_dev,
3284                     "could not create %dth spare Rx dmamap.\n",
3285                     rdata->jme_rx_idx);
3286                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3287                 rdata->jme_rx_tag = NULL;
3288                 return error;
3289         }
3290         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3291                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3292
3293                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3294                                           &rxd->rx_dmamap);
3295                 if (error) {
3296                         int j;
3297
3298                         device_printf(rdata->jme_sc->jme_dev,
3299                             "could not create %dth Rx dmamap "
3300                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3301
3302                         for (j = 0; j < i; ++j) {
3303                                 rxd = &rdata->jme_rxdesc[j];
3304                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3305                                                    rxd->rx_dmamap);
3306                         }
3307                         bus_dmamap_destroy(rdata->jme_rx_tag,
3308                                            rdata->jme_rx_sparemap);
3309                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3310                         rdata->jme_rx_tag = NULL;
3311                         return error;
3312                 }
3313         }
3314         return 0;
3315 }
3316
3317 static void
3318 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3319 {
3320         int r;
3321
3322         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3323                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3324
3325                 if (status & rdata->jme_rx_coal) {
3326                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3327                         jme_rxeof(rdata, -1);
3328                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3329                 }
3330         }
3331 }
3332
3333 static void
3334 jme_enable_rss(struct jme_softc *sc)
3335 {
3336         uint32_t rssc, ind;
3337         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3338         int i;
3339
3340         KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3341                 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3342                 ("%s: invalid # of RX rings (%d)",
3343                  sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3344
3345         rssc = RSSC_HASH_64_ENTRY;
3346         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3347         rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3348         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3349         CSR_WRITE_4(sc, JME_RSSC, rssc);
3350
3351         toeplitz_get_key(key, sizeof(key));
3352         for (i = 0; i < RSSKEY_NREGS; ++i) {
3353                 uint32_t keyreg;
3354
3355                 keyreg = RSSKEY_REGVAL(key, i);
3356                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3357
3358                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3359         }
3360
3361         /*
3362          * Create redirect table in following fashion:
3363          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3364          */
3365         ind = 0;
3366         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3367                 int q;
3368
3369                 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3370                 ind |= q << (i * 8);
3371         }
3372         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3373
3374         for (i = 0; i < RSSTBL_NREGS; ++i)
3375                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3376 }
3377
3378 static void
3379 jme_disable_rss(struct jme_softc *sc)
3380 {
3381         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3382 }
3383
3384 static void
3385 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3386 {
3387         struct jme_softc *sc = ifp->if_softc;
3388
3389         ifnet_serialize_array_enter(sc->jme_serialize_arr,
3390             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3391 }
3392
3393 static void
3394 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3395 {
3396         struct jme_softc *sc = ifp->if_softc;
3397
3398         ifnet_serialize_array_exit(sc->jme_serialize_arr,
3399             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3400 }
3401
3402 static int
3403 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3404 {
3405         struct jme_softc *sc = ifp->if_softc;
3406
3407         return ifnet_serialize_array_try(sc->jme_serialize_arr,
3408             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3409 }
3410
3411 #ifdef INVARIANTS
3412
3413 static void
3414 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3415     boolean_t serialized)
3416 {
3417         struct jme_softc *sc = ifp->if_softc;
3418
3419         ifnet_serialize_array_assert(sc->jme_serialize_arr,
3420             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3421             slz, serialized);
3422 }
3423
3424 #endif  /* INVARIANTS */
3425
3426 static void
3427 jme_msix_try_alloc(device_t dev)
3428 {
3429         struct jme_softc *sc = device_get_softc(dev);
3430         struct jme_msix_data *msix;
3431         int error, i, r, msix_enable, msix_count;
3432
3433         msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3434         KKASSERT(msix_count <= JME_NMSIX);
3435
3436         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3437
3438         /*
3439          * We leave the 1st MSI-X vector unused, so we
3440          * actually need msix_count + 1 MSI-X vectors.
3441          */
3442         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3443                 return;
3444
3445         for (i = 0; i < msix_count; ++i)
3446                 sc->jme_msix[i].jme_msix_rid = -1;
3447
3448         i = 0;
3449
3450         msix = &sc->jme_msix[i++];
3451         msix->jme_msix_cpuid = 0;               /* XXX Put TX to cpu0 */
3452         msix->jme_msix_arg = &sc->jme_cdata;
3453         msix->jme_msix_func = jme_msix_tx;
3454         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3455         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3456         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3457             device_get_nameunit(dev));
3458
3459         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3460                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3461
3462                 msix = &sc->jme_msix[i++];
3463                 msix->jme_msix_cpuid = r;       /* XXX Put RX to cpuX */
3464                 msix->jme_msix_arg = rdata;
3465                 msix->jme_msix_func = jme_msix_rx;
3466                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3467                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3468                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3469                     "%s rx%d", device_get_nameunit(dev), r);
3470         }
3471
3472         KKASSERT(i == msix_count);
3473
3474         error = pci_setup_msix(dev);
3475         if (error)
3476                 return;
3477
3478         /* Setup jme_msix_cnt early, so we could cleanup */
3479         sc->jme_msix_cnt = msix_count;
3480
3481         for (i = 0; i < msix_count; ++i) {
3482                 msix = &sc->jme_msix[i];
3483
3484                 msix->jme_msix_vector = i + 1;
3485                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3486                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3487                 if (error)
3488                         goto back;
3489
3490                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3491                     &msix->jme_msix_rid, RF_ACTIVE);
3492                 if (msix->jme_msix_res == NULL) {
3493                         error = ENOMEM;
3494                         goto back;
3495                 }
3496         }
3497
3498         for (i = 0; i < JME_INTR_CNT; ++i) {
3499                 uint32_t intr_mask = (1 << i);
3500                 int x;
3501
3502                 if ((JME_INTRS & intr_mask) == 0)
3503                         continue;
3504
3505                 for (x = 0; x < msix_count; ++x) {
3506                         msix = &sc->jme_msix[x];
3507                         if (msix->jme_msix_intrs & intr_mask) {
3508                                 int reg, shift;
3509
3510                                 reg = i / JME_MSINUM_FACTOR;
3511                                 KKASSERT(reg < JME_MSINUM_CNT);
3512
3513                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3514
3515                                 sc->jme_msinum[reg] |=
3516                                     (msix->jme_msix_vector << shift);
3517
3518                                 break;
3519                         }
3520                 }
3521         }
3522
3523         if (bootverbose) {
3524                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3525                         device_printf(dev, "MSINUM%d: %#x\n", i,
3526                             sc->jme_msinum[i]);
3527                 }
3528         }
3529
3530         pci_enable_msix(dev);
3531         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3532
3533 back:
3534         if (error)
3535                 jme_msix_free(dev);
3536 }
3537
3538 static int
3539 jme_intr_alloc(device_t dev)
3540 {
3541         struct jme_softc *sc = device_get_softc(dev);
3542         u_int irq_flags;
3543
3544         jme_msix_try_alloc(dev);
3545
3546         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3547                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3548                     &sc->jme_irq_rid, &irq_flags);
3549
3550                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3551                     &sc->jme_irq_rid, irq_flags);
3552                 if (sc->jme_irq_res == NULL) {
3553                         device_printf(dev, "can't allocate irq\n");
3554                         return ENXIO;
3555                 }
3556         }
3557         return 0;
3558 }
3559
3560 static void
3561 jme_msix_free(device_t dev)
3562 {
3563         struct jme_softc *sc = device_get_softc(dev);
3564         int i;
3565
3566         KKASSERT(sc->jme_msix_cnt > 1);
3567
3568         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3569                 struct jme_msix_data *msix = &sc->jme_msix[i];
3570
3571                 if (msix->jme_msix_res != NULL) {
3572                         bus_release_resource(dev, SYS_RES_IRQ,
3573                             msix->jme_msix_rid, msix->jme_msix_res);
3574                         msix->jme_msix_res = NULL;
3575                 }
3576                 if (msix->jme_msix_rid >= 0) {
3577                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3578                         msix->jme_msix_rid = -1;
3579                 }
3580         }
3581         pci_teardown_msix(dev);
3582 }
3583
3584 static void
3585 jme_intr_free(device_t dev)
3586 {
3587         struct jme_softc *sc = device_get_softc(dev);
3588
3589         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3590                 if (sc->jme_irq_res != NULL) {
3591                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3592                                              sc->jme_irq_res);
3593                 }
3594                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3595                         pci_release_msi(dev);
3596         } else {
3597                 jme_msix_free(dev);
3598         }
3599 }
3600
3601 static void
3602 jme_msix_tx(void *xcd)
3603 {
3604         struct jme_chain_data *cd = xcd;
3605         struct jme_softc *sc = cd->jme_sc;
3606         struct ifnet *ifp = &sc->arpcom.ac_if;
3607
3608         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3609
3610         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3611
3612         CSR_WRITE_4(sc, JME_INTR_STATUS,
3613             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3614
3615         if (ifp->if_flags & IFF_RUNNING) {
3616                 jme_txeof(sc);
3617                 if (!ifq_is_empty(&ifp->if_snd))
3618                         if_devstart(ifp);
3619         }
3620
3621         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3622 }
3623
3624 static void
3625 jme_msix_rx(void *xrdata)
3626 {
3627         struct jme_rxdata *rdata = xrdata;
3628         struct jme_softc *sc = rdata->jme_sc;
3629         struct ifnet *ifp = &sc->arpcom.ac_if;
3630         uint32_t status;
3631
3632         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3633
3634         CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3635             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3636
3637         status = CSR_READ_4(sc, JME_INTR_STATUS);
3638         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3639
3640         if (status & rdata->jme_rx_coal)
3641                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3642         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3643
3644         if (ifp->if_flags & IFF_RUNNING) {
3645                 if (status & rdata->jme_rx_coal)
3646                         jme_rxeof(rdata, -1);
3647
3648                 if (status & rdata->jme_rx_empty) {
3649                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3650                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3651                 }
3652         }
3653
3654         CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3655             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3656 }
3657
3658 static void
3659 jme_set_msinum(struct jme_softc *sc)
3660 {
3661         int i;
3662
3663         for (i = 0; i < JME_MSINUM_CNT; ++i)
3664                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3665 }
3666
3667 static int
3668 jme_intr_setup(device_t dev)
3669 {
3670         struct jme_softc *sc = device_get_softc(dev);
3671         struct ifnet *ifp = &sc->arpcom.ac_if;
3672         int error;
3673
3674         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3675                 return jme_msix_setup(dev);
3676
3677         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3678             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3679         if (error) {
3680                 device_printf(dev, "could not set up interrupt handler.\n");
3681                 return error;
3682         }
3683
3684         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3685         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3686         return 0;
3687 }
3688
3689 static void
3690 jme_intr_teardown(device_t dev)
3691 {
3692         struct jme_softc *sc = device_get_softc(dev);
3693
3694         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3695                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3696         else
3697                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3698 }
3699
3700 static int
3701 jme_msix_setup(device_t dev)
3702 {
3703         struct jme_softc *sc = device_get_softc(dev);
3704         struct ifnet *ifp = &sc->arpcom.ac_if;
3705         int x;
3706
3707         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3708                 struct jme_msix_data *msix = &sc->jme_msix[x];
3709                 int error;
3710
3711                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3712                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3713                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3714                     msix->jme_msix_desc);
3715                 if (error) {
3716                         device_printf(dev, "could not set up %s "
3717                             "interrupt handler.\n", msix->jme_msix_desc);
3718                         jme_msix_teardown(dev, x);
3719                         return error;
3720                 }
3721         }
3722         ifp->if_cpuid = 0; /* XXX */
3723         return 0;
3724 }
3725
3726 static void
3727 jme_msix_teardown(device_t dev, int msix_count)
3728 {
3729         struct jme_softc *sc = device_get_softc(dev);
3730         int x;
3731
3732         for (x = 0; x < msix_count; ++x) {
3733                 struct jme_msix_data *msix = &sc->jme_msix[x];
3734
3735                 bus_teardown_intr(dev, msix->jme_msix_res,
3736                     msix->jme_msix_handle);
3737         }
3738 }
3739
3740 static void
3741 jme_serialize_skipmain(struct jme_softc *sc)
3742 {
3743         lwkt_serialize_array_enter(sc->jme_serialize_arr,
3744             sc->jme_serialize_cnt, 1);
3745 }
3746
3747 static void
3748 jme_deserialize_skipmain(struct jme_softc *sc)
3749 {
3750         lwkt_serialize_array_exit(sc->jme_serialize_arr,
3751             sc->jme_serialize_cnt, 1);
3752 }