2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.26 2005/06/14 14:19:22 joerg Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
50 #include <sys/thread2.h>
53 #include <net/ifq_var.h>
54 #include <net/if_arp.h>
55 #include <net/ethernet.h>
56 #include <net/if_dl.h>
57 #include <net/if_media.h>
61 #include <net/vlan/if_vlan_var.h>
63 #include <vm/vm.h> /* for vtophys */
64 #include <vm/pmap.h> /* for vtophys */
65 #include <machine/bus_memio.h>
66 #include <machine/bus_pio.h>
67 #include <machine/bus.h>
68 #include <machine/resource.h>
72 #include <bus/pci/pcireg.h>
73 #include <bus/pci/pcivar.h>
75 #include "../mii_layer/mii.h"
76 #include "../mii_layer/miivar.h"
77 #include "../mii_layer/miidevs.h"
78 #include "../mii_layer/lxtphyreg.h"
80 #include "miibus_if.h"
85 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
86 static void epic_intr(void *);
87 static void epic_tx_underrun(epic_softc_t *);
88 static int epic_common_attach(epic_softc_t *);
89 static void epic_ifstart(struct ifnet *);
90 static void epic_ifwatchdog(struct ifnet *);
91 static void epic_stats_update(void *);
92 static int epic_init(epic_softc_t *);
93 static void epic_stop(epic_softc_t *);
94 static void epic_rx_done(epic_softc_t *);
95 static void epic_tx_done(epic_softc_t *);
96 static int epic_init_rings(epic_softc_t *);
97 static void epic_free_rings(epic_softc_t *);
98 static void epic_stop_activity(epic_softc_t *);
99 static int epic_queue_last_packet(epic_softc_t *);
100 static void epic_start_activity(epic_softc_t *);
101 static void epic_set_rx_mode(epic_softc_t *);
102 static void epic_set_tx_mode(epic_softc_t *);
103 static void epic_set_mc_table(epic_softc_t *);
104 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
105 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
106 static u_int16_t epic_input_eepromw(epic_softc_t *);
107 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
108 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
109 static u_int8_t epic_read_eepromreg(epic_softc_t *);
111 static int epic_read_phy_reg(epic_softc_t *, int, int);
112 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
114 static int epic_miibus_readreg(device_t, int, int);
115 static int epic_miibus_writereg(device_t, int, int, int);
116 static void epic_miibus_statchg(device_t);
117 static void epic_miibus_mediainit(device_t);
119 static int epic_ifmedia_upd(struct ifnet *);
120 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
122 static int epic_probe(device_t);
123 static int epic_attach(device_t);
124 static void epic_shutdown(device_t);
125 static int epic_detach(device_t);
126 static struct epic_type *epic_devtype(device_t);
128 static device_method_t epic_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, epic_probe),
131 DEVMETHOD(device_attach, epic_attach),
132 DEVMETHOD(device_detach, epic_detach),
133 DEVMETHOD(device_shutdown, epic_shutdown),
136 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
137 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
138 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
139 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
144 static driver_t epic_driver = {
150 static devclass_t epic_devclass;
152 DECLARE_DUMMY_MODULE(if_tx);
153 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
154 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
155 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
157 static struct epic_type epic_devs[] = {
158 { SMC_VENDORID, SMC_DEVICEID_83C170,
159 "SMC EtherPower II 10/100" },
169 t = epic_devtype(dev);
172 device_set_desc(dev, t->name);
179 static struct epic_type *
187 while(t->name != NULL) {
188 if ((pci_get_vendor(dev) == t->ven_id) &&
189 (pci_get_device(dev) == t->dev_id)) {
197 #if defined(EPIC_USEIOSPACE)
198 #define EPIC_RES SYS_RES_IOPORT
199 #define EPIC_RID PCIR_BASEIO
201 #define EPIC_RES SYS_RES_MEMORY
202 #define EPIC_RID PCIR_BASEMEM
206 * Attach routine: map registers, allocate softc, rings and descriptors.
207 * Reset to known state.
218 sc = device_get_softc(dev);
220 /* Preinitialize softc structure */
221 bzero(sc, sizeof(epic_softc_t));
223 callout_init(&sc->tx_stat_timer);
225 /* Fill ifnet structure */
227 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
229 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
230 ifp->if_ioctl = epic_ifioctl;
231 ifp->if_start = epic_ifstart;
232 ifp->if_watchdog = epic_ifwatchdog;
233 ifp->if_init = (if_init_f_t*)epic_init;
235 ifp->if_baudrate = 10000000;
236 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
237 ifq_set_ready(&ifp->if_snd);
239 pci_enable_busmaster(dev);
242 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
244 if (sc->res == NULL) {
245 device_printf(dev, "couldn't map ports/memory\n");
250 sc->sc_st = rman_get_bustag(sc->res);
251 sc->sc_sh = rman_get_bushandle(sc->res);
253 /* Allocate interrupt */
255 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
256 RF_SHAREABLE | RF_ACTIVE);
258 if (sc->irq == NULL) {
259 device_printf(dev, "couldn't map interrupt\n");
264 /* Do OS independent part, including chip wakeup and reset */
265 error = epic_common_attach(sc);
271 /* Do ifmedia setup */
272 if (mii_phy_probe(dev, &sc->miibus,
273 epic_ifmedia_upd, epic_ifmedia_sts)) {
274 device_printf(dev, "ERROR! MII without any PHY!?\n");
279 /* board type and ... */
281 for(i=0x2c;i<0x32;i++) {
282 tmp = epic_read_eeprom(sc, i);
283 if (' ' == (u_int8_t)tmp) break;
284 printf("%c", (u_int8_t)tmp);
286 if (' ' == (u_int8_t)tmp) break;
287 printf("%c", (u_int8_t)tmp);
291 /* Attach to OS's managers */
292 ether_ifattach(ifp, sc->sc_macaddr);
293 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
295 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
296 epic_intr, sc, &sc->sc_ih, NULL);
299 device_printf(dev, "couldn't set up irq\n");
312 * Detach driver and free resources
321 sc = device_get_softc(dev);
322 ifp = &sc->arpcom.ac_if;
326 if (device_is_attached(dev)) {
332 device_delete_child(dev, sc->miibus);
333 bus_generic_detach(dev);
336 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
341 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
343 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
346 free(sc->tx_flist, M_DEVBUF);
348 free(sc->tx_desc, M_DEVBUF);
350 free(sc->rx_desc, M_DEVBUF);
359 * Stop all chip I/O so that the kernel's probe routines don't
360 * get confused by errant DMAs when rebooting.
368 sc = device_get_softc(dev);
376 * This is if_ioctl handler.
379 epic_ifioctl(ifp, command, data, cr)
385 epic_softc_t *sc = ifp->if_softc;
386 struct mii_data *mii;
387 struct ifreq *ifr = (struct ifreq *) data;
394 if (ifp->if_mtu == ifr->ifr_mtu)
397 /* XXX Though the datasheet doesn't imply any
398 * limitations on RX and TX sizes beside max 64Kb
399 * DMA transfer, seems we can't send more then 1600
400 * data bytes per ethernet packet. (Transmitter hangs
401 * up if more data is sent)
403 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
404 ifp->if_mtu = ifr->ifr_mtu;
413 * If the interface is marked up and stopped, then start it.
414 * If it is marked down and running, then stop it.
416 if (ifp->if_flags & IFF_UP) {
417 if ((ifp->if_flags & IFF_RUNNING) == 0) {
422 if (ifp->if_flags & IFF_RUNNING) {
428 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
429 epic_stop_activity(sc);
430 epic_set_mc_table(sc);
431 epic_set_rx_mode(sc);
432 epic_start_activity(sc);
437 epic_set_mc_table(sc);
443 mii = device_get_softc(sc->miibus);
444 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
448 error = ether_ioctl(ifp, command, data);
457 * OS-independed part of attach process. allocate memory for descriptors
458 * and frag lists, wake up chip, read MAC address and PHY identyfier.
459 * Return -1 on failure.
462 epic_common_attach(sc)
467 sc->tx_flist = malloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
468 M_DEVBUF, M_WAITOK | M_ZERO);
469 sc->tx_desc = malloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
470 M_DEVBUF, M_WAITOK | M_ZERO);
471 sc->rx_desc = malloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
472 M_DEVBUF, M_WAITOK | M_ZERO);
474 /* Bring the chip out of low-power mode. */
475 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
478 /* Workaround for Application Note 7-15 */
479 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
481 /* Read mac address from EEPROM */
482 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
483 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
485 /* Set Non-Volatile Control Register from EEPROM */
486 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
489 sc->tx_threshold = TRANSMIT_THRESHOLD;
490 sc->txcon = TXCON_DEFAULT;
491 sc->miicfg = MIICFG_SMI_ENABLE;
492 sc->phyid = EPIC_UNKN_PHY;
496 sc->cardvend = pci_get_subvendor(sc->dev);
497 sc->cardid = pci_get_subdevice(sc->dev);
499 if (sc->cardvend != SMC_VENDORID)
500 device_printf(sc->dev, "unknown card vendor %04xh\n", sc->cardvend);
506 * This is if_start handler. It takes mbufs from if_snd queue
507 * and queue them for transmit, one by one, until TX ring become full
508 * or queue become empty.
514 epic_softc_t *sc = ifp->if_softc;
515 struct epic_tx_buffer *buf;
516 struct epic_tx_desc *desc;
517 struct epic_frag_list *flist;
522 while (sc->pending_txs < TX_RING_SIZE) {
523 buf = sc->tx_buffer + sc->cur_tx;
524 desc = sc->tx_desc + sc->cur_tx;
525 flist = sc->tx_flist + sc->cur_tx;
527 /* Get next packet to send */
528 m0 = ifq_dequeue(&ifp->if_snd);
530 /* If nothing to send, return */
534 /* Fill fragments list */
536 (NULL != m) && (i < EPIC_MAX_FRAGS);
537 m = m->m_next, i++) {
538 flist->frag[i].fraglen = m->m_len;
539 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
543 /* If packet was more than EPIC_MAX_FRAGS parts, */
544 /* recopy packet to new allocated mbuf cluster */
553 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
554 flist->frag[0].fraglen =
555 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
556 m->m_pkthdr.rcvif = ifp;
559 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
566 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
567 desc->control = 0x01;
569 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
570 desc->status = 0x8000;
571 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
573 /* Set watchdog timer */
579 ifp->if_flags |= IFF_OACTIVE;
586 * Synopsis: Finish all received frames.
593 struct ifnet *ifp = &sc->sc_if;
594 struct epic_rx_buffer *buf;
595 struct epic_rx_desc *desc;
598 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
599 buf = sc->rx_buffer + sc->cur_rx;
600 desc = sc->rx_desc + sc->cur_rx;
602 /* Switch to next descriptor */
603 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
606 * Check for RX errors. This should only happen if
607 * SAVE_ERRORED_PACKETS is set. RX errors generate
608 * RXE interrupt usually.
610 if ((desc->status & 1) == 0) {
611 sc->sc_if.if_ierrors++;
612 desc->status = 0x8000;
616 /* Save packet length and mbuf contained packet */
617 len = desc->rxlength - ETHER_CRC_LEN;
620 /* Try to get mbuf cluster */
621 EPIC_MGETCLUSTER(buf->mbuf);
622 if (NULL == buf->mbuf) {
624 desc->status = 0x8000;
629 /* Point to new mbuf, and give descriptor to chip */
630 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
631 desc->status = 0x8000;
633 /* First mbuf in packet holds the ethernet and packet headers */
634 m->m_pkthdr.rcvif = ifp;
635 m->m_pkthdr.len = m->m_len = len;
637 /* Give mbuf to OS */
638 (*ifp->if_input)(ifp, m);
640 /* Successfuly received frame */
648 * Synopsis: Do last phase of transmission. I.e. if desc is
649 * transmitted, decrease pending_txs counter, free mbuf contained
650 * packet, switch to next descriptor and repeat until no packets
651 * are pending or descriptor is not transmitted yet.
657 struct epic_tx_buffer *buf;
658 struct epic_tx_desc *desc;
661 while (sc->pending_txs > 0) {
662 buf = sc->tx_buffer + sc->dirty_tx;
663 desc = sc->tx_desc + sc->dirty_tx;
664 status = desc->status;
666 /* If packet is not transmitted, thou followed */
667 /* packets are not transmitted too */
668 if (status & 0x8000) break;
670 /* Packet is transmitted. Switch to next and */
673 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
677 /* Check for errors and collisions */
678 if (status & 0x0001) sc->sc_if.if_opackets++;
679 else sc->sc_if.if_oerrors++;
680 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
681 #if defined(EPIC_DIAG)
682 if ((status & 0x1001) == 0x1001) {
683 if_printf(&sc->sc_if,
684 "Tx ERROR: excessive coll. number\n");
689 if (sc->pending_txs < TX_RING_SIZE)
690 sc->sc_if.if_flags &= ~IFF_OACTIVE;
700 epic_softc_t * sc = (epic_softc_t *) arg;
703 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
704 CSR_WRITE_4(sc, INTSTAT, status);
706 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
708 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
709 #if defined(EPIC_DIAG)
710 if (status & INTSTAT_OVW)
711 if_printf(&sc->sc_if, "RX buffer overflow\n");
712 if (status & INTSTAT_RQE)
713 if_printf(&sc->sc_if, "RX FIFO overflow\n");
715 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
716 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
717 sc->sc_if.if_ierrors++;
721 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
723 if (!ifq_is_empty(&sc->sc_if.if_snd))
724 epic_ifstart(&sc->sc_if);
727 /* Check for rare errors */
728 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
729 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
730 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
731 INTSTAT_APE|INTSTAT_DPE)) {
732 if_printf(&sc->sc_if, "PCI fatal errors occured: %s%s%s%s\n",
733 (status&INTSTAT_PMA)?"PMA ":"",
734 (status&INTSTAT_PTA)?"PTA ":"",
735 (status&INTSTAT_APE)?"APE ":"",
736 (status&INTSTAT_DPE)?"DPE":""
745 if (status & INTSTAT_RXE) {
746 #if defined(EPIC_DIAG)
747 if_printf(sc->sc_if, "CRC/Alignment error\n");
749 sc->sc_if.if_ierrors++;
752 if (status & INTSTAT_TXU) {
753 epic_tx_underrun(sc);
754 sc->sc_if.if_oerrors++;
759 /* If no packets are pending, then no timeouts */
760 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
766 * Handle the TX underrun error: increase the TX threshold
767 * and restart the transmitter.
773 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
774 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
775 #if defined(EPIC_DIAG)
776 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
779 sc->tx_threshold += 0x40;
780 #if defined(EPIC_DIAG)
781 if_printf(&sc->sc_if, "Tx UNDERRUN: "
782 "TX threshold increased to %d\n", sc->tx_threshold);
786 /* We must set TXUGO to reset the stuck transmitter */
787 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
789 /* Update the TX threshold */
790 epic_stop_activity(sc);
791 epic_set_tx_mode(sc);
792 epic_start_activity(sc);
798 * Synopsis: This one is called if packets wasn't transmitted
799 * during timeout. Try to deallocate transmitted packets, and
800 * if success continue to work.
806 epic_softc_t *sc = ifp->if_softc;
810 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
812 /* Try to finish queued packets */
815 /* If not successful */
816 if (sc->pending_txs > 0) {
818 ifp->if_oerrors+=sc->pending_txs;
820 /* Reinitialize board */
821 if_printf(ifp, "reinitialization\n");
826 if_printf(ifp, "seems we can continue normaly\n");
829 if (!ifq_is_empty(&ifp->if_snd))
836 * Despite the name of this function, it doesn't update statistics, it only
837 * helps in autonegotiation process.
840 epic_stats_update(void *xsc)
842 epic_softc_t *sc = xsc;
843 struct mii_data * mii;
847 mii = device_get_softc(sc->miibus);
850 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
859 epic_ifmedia_upd(ifp)
863 struct mii_data *mii;
865 struct mii_softc *miisc;
869 mii = device_get_softc(sc->miibus);
870 ifm = &mii->mii_media;
871 media = ifm->ifm_cur->ifm_media;
873 /* Do not do anything if interface is not up */
874 if ((ifp->if_flags & IFF_UP) == 0)
878 * Lookup current selected PHY
880 if (IFM_INST(media) == sc->serinst) {
881 sc->phyid = EPIC_SERIAL;
884 /* If we're not selecting serial interface, select MII mode */
885 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
886 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
888 /* Default to unknown PHY */
889 sc->phyid = EPIC_UNKN_PHY;
891 /* Lookup selected PHY */
892 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
893 miisc = LIST_NEXT(miisc, mii_list)) {
894 if (IFM_INST(media) == miisc->mii_inst) {
900 /* Identify selected PHY */
902 int id1, id2, model, oui;
904 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
905 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
907 oui = MII_OUI(id1, id2);
908 model = MII_MODEL(id2);
910 case MII_OUI_QUALSEMI:
911 if (model == MII_MODEL_QUALSEMI_QS6612)
912 sc->phyid = EPIC_QS6612_PHY;
914 case MII_OUI_xxALTIMA:
915 if (model == MII_MODEL_xxALTIMA_AC101)
916 sc->phyid = EPIC_AC101_PHY;
918 case MII_OUI_xxLEVEL1:
919 if (model == MII_MODEL_xxLEVEL1_LXT970)
920 sc->phyid = EPIC_LXT970_PHY;
927 * Do PHY specific card setup
930 /* Call this, to isolate all not selected PHYs and
935 /* Do our own setup */
937 case EPIC_QS6612_PHY:
940 /* We have to powerup fiber tranceivers */
941 if (IFM_SUBTYPE(media) == IFM_100_FX)
942 sc->miicfg |= MIICFG_694_ENABLE;
944 sc->miicfg &= ~MIICFG_694_ENABLE;
945 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
948 case EPIC_LXT970_PHY:
949 /* We have to powerup fiber tranceivers */
950 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
951 if (IFM_SUBTYPE(media) == IFM_100_FX)
952 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
954 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
955 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
959 /* Select serial PHY, (10base2/BNC usually) */
960 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
961 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
963 /* There is no driver to fill this */
964 mii->mii_media_active = media;
965 mii->mii_media_status = 0;
967 /* We need to call this manualy as i wasn't called
970 epic_miibus_statchg(sc->dev);
974 if_printf(ifp, "ERROR! Unknown PHY selected\n");
982 * Report current media status.
985 epic_ifmedia_sts(ifp, ifmr)
987 struct ifmediareq *ifmr;
990 struct mii_data *mii;
994 mii = device_get_softc(sc->miibus);
995 ifm = &mii->mii_media;
997 /* Nothing should be selected if interface is down */
998 if ((ifp->if_flags & IFF_UP) == 0) {
999 ifmr->ifm_active = IFM_NONE;
1000 ifmr->ifm_status = 0;
1005 /* Call underlying pollstat, if not serial PHY */
1006 if (sc->phyid != EPIC_SERIAL)
1009 /* Simply copy media info */
1010 ifmr->ifm_active = mii->mii_media_active;
1011 ifmr->ifm_status = mii->mii_media_status;
1017 * Callback routine, called on media change.
1020 epic_miibus_statchg(dev)
1024 struct mii_data *mii;
1027 sc = device_get_softc(dev);
1028 mii = device_get_softc(sc->miibus);
1029 media = mii->mii_media_active;
1031 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1033 /* If we are in full-duplex mode or loopback operation,
1034 * we need to decouple receiver and transmitter.
1036 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1037 sc->txcon |= TXCON_FULL_DUPLEX;
1039 /* On some cards we need manualy set fullduplex led */
1040 if (sc->cardid == SMC9432FTX ||
1041 sc->cardid == SMC9432FTX_SC) {
1042 if (IFM_OPTIONS(media) & IFM_FDX)
1043 sc->miicfg |= MIICFG_694_ENABLE;
1045 sc->miicfg &= ~MIICFG_694_ENABLE;
1047 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1050 /* Update baudrate */
1051 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1052 IFM_SUBTYPE(media) == IFM_100_FX)
1053 sc->sc_if.if_baudrate = 100000000;
1055 sc->sc_if.if_baudrate = 10000000;
1057 epic_stop_activity(sc);
1058 epic_set_tx_mode(sc);
1059 epic_start_activity(sc);
1065 epic_miibus_mediainit(dev)
1069 struct mii_data *mii;
1070 struct ifmedia *ifm;
1073 sc = device_get_softc(dev);
1074 mii = device_get_softc(sc->miibus);
1075 ifm = &mii->mii_media;
1077 /* Add Serial Media Interface if present, this applies to
1080 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1081 /* Store its instance */
1082 sc->serinst = mii->mii_instance++;
1084 /* Add as 10base2/BNC media */
1085 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1086 ifmedia_add(ifm, media, 0, NULL);
1088 /* Report to user */
1089 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
1096 * Reset chip, allocate rings, and update media.
1102 struct ifnet *ifp = &sc->sc_if;
1107 /* If interface is already running, then we need not do anything */
1108 if (ifp->if_flags & IFF_RUNNING) {
1113 /* Soft reset the chip (we have to power up card before) */
1114 CSR_WRITE_4(sc, GENCTL, 0);
1115 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1118 * Reset takes 15 pci ticks which depends on PCI bus speed.
1119 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1124 CSR_WRITE_4(sc, GENCTL, 0);
1126 /* Workaround for Application Note 7-15 */
1127 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1129 /* Initialize rings */
1130 if (epic_init_rings(sc)) {
1131 if_printf(ifp, "failed to init rings\n");
1136 /* Give rings to EPIC */
1137 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1138 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1140 /* Put node address to EPIC */
1141 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1142 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1143 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1145 /* Set tx mode, includeing transmit threshold */
1146 epic_set_tx_mode(sc);
1148 /* Compute and set RXCON. */
1149 epic_set_rx_mode(sc);
1151 /* Set multicast table */
1152 epic_set_mc_table(sc);
1154 /* Enable interrupts by setting the interrupt mask. */
1155 CSR_WRITE_4(sc, INTMASK,
1156 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1157 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1160 /* Acknowledge all pending interrupts */
1161 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1163 /* Enable interrupts, set for PCI read multiple and etc */
1164 CSR_WRITE_4(sc, GENCTL,
1165 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1166 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1168 /* Mark interface running ... */
1169 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1170 else ifp->if_flags &= ~IFF_RUNNING;
1173 ifp->if_flags &= ~IFF_OACTIVE;
1175 /* Start Rx process */
1176 epic_start_activity(sc);
1178 /* Set appropriate media */
1179 epic_ifmedia_upd(ifp);
1181 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1189 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1193 epic_set_rx_mode(sc)
1196 u_int32_t flags = sc->sc_if.if_flags;
1197 u_int32_t rxcon = RXCON_DEFAULT;
1199 #if defined(EPIC_EARLY_RX)
1200 rxcon |= RXCON_EARLY_RX;
1203 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1205 CSR_WRITE_4(sc, RXCON, rxcon);
1211 * Synopsis: Set transmit control register. Chip must be in idle state to
1215 epic_set_tx_mode(sc)
1218 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1219 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1221 CSR_WRITE_4(sc, TXCON, sc->txcon);
1225 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1226 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1227 * individual frames, multicast filter must be manually programmed)
1229 * Note: EPIC must be in idle state.
1232 epic_set_mc_table(sc)
1235 struct ifnet *ifp = &sc->sc_if;
1236 struct ifmultiaddr *ifma;
1237 u_int16_t filter[4];
1240 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1241 CSR_WRITE_4(sc, MC0, 0xFFFF);
1242 CSR_WRITE_4(sc, MC1, 0xFFFF);
1243 CSR_WRITE_4(sc, MC2, 0xFFFF);
1244 CSR_WRITE_4(sc, MC3, 0xFFFF);
1254 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1255 if (ifma->ifma_addr->sa_family != AF_LINK)
1257 h = (ether_crc32_be(
1258 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1259 ETHER_ADDR_LEN) >> 26) & 0x3f;
1260 filter[h >> 4] |= 1 << (h & 0xF);
1263 CSR_WRITE_4(sc, MC0, filter[0]);
1264 CSR_WRITE_4(sc, MC1, filter[1]);
1265 CSR_WRITE_4(sc, MC2, filter[2]);
1266 CSR_WRITE_4(sc, MC3, filter[3]);
1272 * Synopsis: Start receive process and transmit one, if they need.
1275 epic_start_activity(sc)
1278 /* Start rx process */
1279 CSR_WRITE_4(sc, COMMAND,
1280 COMMAND_RXQUEUED | COMMAND_START_RX |
1281 (sc->pending_txs?COMMAND_TXQUEUED:0));
1285 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1286 * packet needs to be queued to stop Tx DMA.
1289 epic_stop_activity(sc)
1294 /* Stop Tx and Rx DMA */
1295 CSR_WRITE_4(sc, COMMAND,
1296 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1298 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1299 for (i=0; i<0x1000; i++) {
1300 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1301 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1306 /* Catch all finished packets */
1310 status = CSR_READ_4(sc, INTSTAT);
1312 if ((status & INTSTAT_RXIDLE) == 0)
1313 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
1315 if ((status & INTSTAT_TXIDLE) == 0)
1316 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
1319 * May need to queue one more packet if TQE, this is rare
1320 * but existing case.
1322 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1323 (void) epic_queue_last_packet(sc);
1328 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1329 * a packet from current descriptor will be copied to internal RAM. We
1330 * compose a dummy packet here and queue it for transmission.
1332 * XXX the packet will then be actually sent over network...
1335 epic_queue_last_packet(sc)
1338 struct epic_tx_desc *desc;
1339 struct epic_frag_list *flist;
1340 struct epic_tx_buffer *buf;
1344 if_printf(&sc->sc_if, "queue last packet\n");
1346 desc = sc->tx_desc + sc->cur_tx;
1347 flist = sc->tx_flist + sc->cur_tx;
1348 buf = sc->tx_buffer + sc->cur_tx;
1350 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1353 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1358 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1359 flist->frag[0].fraglen = m0->m_len;
1360 m0->m_pkthdr.len = m0->m_len;
1361 m0->m_pkthdr.rcvif = &sc->sc_if;
1362 bzero(mtod(m0,caddr_t), m0->m_len);
1364 /* Fill fragments list */
1365 flist->frag[0].fraglen = m0->m_len;
1366 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1367 flist->numfrags = 1;
1369 /* Fill in descriptor */
1372 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1373 desc->control = 0x01;
1374 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1375 desc->status = 0x8000;
1377 /* Launch transmition */
1378 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1380 /* Wait Tx DMA to stop (for how long??? XXX) */
1381 for (i=0; i<1000; i++) {
1382 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1387 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1388 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
1396 * Synopsis: Shut down board and deallocates rings.
1405 sc->sc_if.if_timer = 0;
1407 callout_stop(&sc->tx_stat_timer);
1409 /* Disable interrupts */
1410 CSR_WRITE_4(sc, INTMASK, 0);
1411 CSR_WRITE_4(sc, GENCTL, 0);
1413 /* Try to stop Rx and TX processes */
1414 epic_stop_activity(sc);
1417 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1420 /* Make chip go to bed */
1421 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1423 /* Free memory allocated for rings */
1424 epic_free_rings(sc);
1426 /* Mark as stoped */
1427 sc->sc_if.if_flags &= ~IFF_RUNNING;
1434 * Synopsis: This function should free all memory allocated for rings.
1442 for (i=0; i<RX_RING_SIZE; i++) {
1443 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1444 struct epic_rx_desc *desc = sc->rx_desc + i;
1447 desc->buflength = 0;
1450 if (buf->mbuf) m_freem(buf->mbuf);
1454 for (i=0; i<TX_RING_SIZE; i++) {
1455 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1456 struct epic_tx_desc *desc = sc->tx_desc + i;
1459 desc->buflength = 0;
1462 if (buf->mbuf) m_freem(buf->mbuf);
1468 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1469 * Point Tx descs to fragment lists. Check that all descs and fraglists
1470 * are bounded and aligned properly.
1478 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1480 for (i = 0; i < RX_RING_SIZE; i++) {
1481 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1482 struct epic_rx_desc *desc = sc->rx_desc + i;
1484 desc->status = 0; /* Owned by driver */
1485 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1487 if ((desc->next & 3) ||
1488 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1489 epic_free_rings(sc);
1493 EPIC_MGETCLUSTER(buf->mbuf);
1494 if (NULL == buf->mbuf) {
1495 epic_free_rings(sc);
1498 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1500 desc->buflength = MCLBYTES; /* Max RX buffer length */
1501 desc->status = 0x8000; /* Set owner bit to NIC */
1504 for (i = 0; i < TX_RING_SIZE; i++) {
1505 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1506 struct epic_tx_desc *desc = sc->tx_desc + i;
1509 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1511 if ((desc->next & 3) ||
1512 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1513 epic_free_rings(sc);
1518 desc->bufaddr = vtophys(sc->tx_flist + i);
1520 if ((desc->bufaddr & 3) ||
1521 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1522 epic_free_rings(sc);
1531 * EEPROM operation functions
1534 epic_write_eepromreg(sc, val)
1540 CSR_WRITE_1(sc, EECTL, val);
1542 for (i=0; i<0xFF; i++)
1543 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1549 epic_read_eepromreg(sc)
1552 return CSR_READ_1(sc, EECTL);
1556 epic_eeprom_clock(sc, val)
1560 epic_write_eepromreg(sc, val);
1561 epic_write_eepromreg(sc, (val | 0x4));
1562 epic_write_eepromreg(sc, val);
1564 return epic_read_eepromreg(sc);
1568 epic_output_eepromw(sc, val)
1574 for (i = 0xF; i >= 0; i--) {
1576 epic_eeprom_clock(sc, 0x0B);
1578 epic_eeprom_clock(sc, 0x03);
1583 epic_input_eepromw(sc)
1586 u_int16_t retval = 0;
1589 for (i = 0xF; i >= 0; i--) {
1590 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1598 epic_read_eeprom(sc, loc)
1605 epic_write_eepromreg(sc, 3);
1607 if (epic_read_eepromreg(sc) & 0x40)
1608 read_cmd = (loc & 0x3F) | 0x180;
1610 read_cmd = (loc & 0xFF) | 0x600;
1612 epic_output_eepromw(sc, read_cmd);
1614 dataval = epic_input_eepromw(sc);
1616 epic_write_eepromreg(sc, 1);
1622 * Here goes MII read/write routines
1625 epic_read_phy_reg(sc, phy, reg)
1631 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1633 for (i = 0; i < 0x100; i++) {
1634 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1638 return (CSR_READ_4(sc, MIIDATA));
1642 epic_write_phy_reg(sc, phy, reg, val)
1648 CSR_WRITE_4(sc, MIIDATA, val);
1649 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1651 for(i=0;i<0x100;i++) {
1652 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1660 epic_miibus_readreg(dev, phy, reg)
1666 sc = device_get_softc(dev);
1668 return (PHY_READ_2(sc, phy, reg));
1672 epic_miibus_writereg(dev, phy, reg, data)
1678 sc = device_get_softc(dev);
1680 PHY_WRITE_2(sc, phy, reg, data);