2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/cputypes.h>
36 #include <machine/md_var.h>
37 #include <machine/pmap.h>
38 #include <machine_base/apic/lapic.h>
39 #include <machine_base/apic/ioapic.h>
40 #include <machine_base/apic/ioapic_abi.h>
41 #include <machine_base/apic/apicvar.h>
42 #include <machine_base/icu/icu_var.h>
43 #include <machine/segments.h>
44 #include <sys/thread2.h>
46 #include <machine/intr_machdep.h>
50 volatile lapic_t *lapic;
52 static void lapic_timer_calibrate(void);
53 static void lapic_timer_set_divisor(int);
54 static void lapic_timer_fixup_handler(void *);
55 static void lapic_timer_restart_handler(void *);
57 void lapic_timer_process(void);
58 void lapic_timer_process_frame(struct intrframe *);
60 static int lapic_timer_enable = 1;
61 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
63 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
64 static void lapic_timer_intr_enable(struct cputimer_intr *);
65 static void lapic_timer_intr_restart(struct cputimer_intr *);
66 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
68 static struct cputimer_intr lapic_cputimer_intr = {
70 .reload = lapic_timer_intr_reload,
71 .enable = lapic_timer_intr_enable,
72 .config = cputimer_intr_default_config,
73 .restart = lapic_timer_intr_restart,
74 .pmfixup = lapic_timer_intr_pmfixup,
75 .initclock = cputimer_intr_default_initclock,
76 .next = SLIST_ENTRY_INITIALIZER,
78 .type = CPUTIMER_INTR_LAPIC,
79 .prio = CPUTIMER_INTR_PRIO_LAPIC,
80 .caps = CPUTIMER_INTR_CAP_NONE
83 static int lapic_timer_divisor_idx = -1;
84 static const uint32_t lapic_timer_divisors[] = {
85 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
86 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
88 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
91 * APIC ID <-> CPU ID mapping structures.
93 int cpu_id_to_apic_id[NAPICID];
94 int apic_id_to_cpu_id[NAPICID];
98 * Enable LAPIC, configure interrupts.
101 lapic_init(boolean_t bsp)
109 * Since IDT is shared between BSP and APs, these vectors
110 * only need to be installed once; we do it on BSP.
113 /* Install a 'Spurious INTerrupt' vector */
114 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
115 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
117 /* Install a timer vector */
118 setidt(XTIMER_OFFSET, Xtimer,
119 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
122 /* Install an inter-CPU IPI for TLB invalidation */
123 setidt(XINVLTLB_OFFSET, Xinvltlb,
124 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
126 /* Install an inter-CPU IPI for IPIQ messaging */
127 setidt(XIPIQ_OFFSET, Xipiq,
128 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
130 /* Install an inter-CPU IPI for CPU stop/restart */
131 setidt(XCPUSTOP_OFFSET, Xcpustop,
132 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
137 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
138 * aggregate interrupt input from the 8259. The INTA cycle
139 * will be routed to the external controller (the 8259) which
140 * is expected to supply the vector.
142 * Must be setup edge triggered, active high.
144 * Disable LINT0 on BSP, if I/O APIC is enabled.
146 * Disable LINT0 on the APs. It doesn't matter what delivery
147 * mode we use because we leave it masked.
149 temp = lapic->lvt_lint0;
150 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
151 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
153 temp |= APIC_LVT_DM_EXTINT;
155 temp |= APIC_LVT_MASKED;
157 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
159 lapic->lvt_lint0 = temp;
162 * Setup LINT1 as NMI.
164 * Must be setup edge trigger, active high.
166 * Enable LINT1 on BSP, if I/O APIC is enabled.
168 * Disable LINT1 on the APs.
170 temp = lapic->lvt_lint1;
171 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
172 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
173 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
174 if (bsp && ioapic_enable)
175 temp &= ~APIC_LVT_MASKED;
176 lapic->lvt_lint1 = temp;
179 * Mask the LAPIC error interrupt, LAPIC performance counter
182 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
183 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
186 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
188 timer = lapic->lvt_timer;
189 timer &= ~APIC_LVTT_VECTOR;
190 timer |= XTIMER_OFFSET;
191 timer |= APIC_LVTT_MASKED;
192 lapic->lvt_timer = timer;
195 * Set the Task Priority Register as needed. At the moment allow
196 * interrupts on all cpus (the APs will remain CLId until they are
200 temp &= ~APIC_TPR_PRIO; /* clear priority field */
207 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
208 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
211 * Set the spurious interrupt vector. The low 4 bits of the vector
214 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
215 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
216 temp &= ~APIC_SVR_VECTOR;
217 temp |= XSPURIOUSINT_OFFSET;
222 * Pump out a few EOIs to clean out interrupts that got through
223 * before we were able to set the TPR.
230 lapic_timer_calibrate();
231 if (lapic_timer_enable) {
232 cputimer_intr_register(&lapic_cputimer_intr);
233 cputimer_intr_select(&lapic_cputimer_intr, 0);
236 lapic_timer_set_divisor(lapic_timer_divisor_idx);
240 apic_dump("apic_initialize()");
244 lapic_timer_set_divisor(int divisor_idx)
246 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
247 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
251 lapic_timer_oneshot(u_int count)
255 value = lapic->lvt_timer;
256 value &= ~APIC_LVTT_PERIODIC;
257 lapic->lvt_timer = value;
258 lapic->icr_timer = count;
262 lapic_timer_oneshot_quick(u_int count)
264 lapic->icr_timer = count;
268 lapic_timer_calibrate(void)
272 /* Try to calibrate the local APIC timer. */
273 for (lapic_timer_divisor_idx = 0;
274 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
275 lapic_timer_divisor_idx++) {
276 lapic_timer_set_divisor(lapic_timer_divisor_idx);
277 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
279 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
280 if (value != APIC_TIMER_MAX_COUNT)
283 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
284 panic("lapic: no proper timer divisor?!\n");
285 lapic_cputimer_intr.freq = value / 2;
287 kprintf("lapic: divisor index %d, frequency %u Hz\n",
288 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
292 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
296 gd->gd_timer_running = 0;
298 count = sys_cputimer->count();
299 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
300 systimer_intr(&count, 0, frame);
304 lapic_timer_process(void)
306 lapic_timer_process_oncpu(mycpu, NULL);
310 lapic_timer_process_frame(struct intrframe *frame)
312 lapic_timer_process_oncpu(mycpu, frame);
316 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
318 struct globaldata *gd = mycpu;
320 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
324 if (gd->gd_timer_running) {
325 if (reload < lapic->ccr_timer)
326 lapic_timer_oneshot_quick(reload);
328 gd->gd_timer_running = 1;
329 lapic_timer_oneshot_quick(reload);
334 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
338 timer = lapic->lvt_timer;
339 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
340 lapic->lvt_timer = timer;
342 lapic_timer_fixup_handler(NULL);
346 lapic_timer_fixup_handler(void *arg)
353 if (cpu_vendor_id == CPU_VENDOR_AMD) {
355 * Detect the presence of C1E capability mostly on latest
356 * dual-cores (or future) k8 family. This feature renders
357 * the local APIC timer dead, so we disable it by reading
358 * the Interrupt Pending Message register and clearing both
359 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
362 * "BIOS and Kernel Developer's Guide for AMD NPT
363 * Family 0Fh Processors"
364 * #32559 revision 3.00
366 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
367 (cpu_id & 0x0fff0000) >= 0x00040000) {
370 msr = rdmsr(0xc0010055);
371 if (msr & 0x18000000) {
372 struct globaldata *gd = mycpu;
374 kprintf("cpu%d: AMD C1E detected\n",
376 wrmsr(0xc0010055, msr & ~0x18000000ULL);
379 * We are kinda stalled;
382 gd->gd_timer_running = 1;
383 lapic_timer_oneshot_quick(2);
393 lapic_timer_restart_handler(void *dummy __unused)
397 lapic_timer_fixup_handler(&started);
399 struct globaldata *gd = mycpu;
401 gd->gd_timer_running = 1;
402 lapic_timer_oneshot_quick(2);
407 * This function is called only by ACPI-CA code currently:
408 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
409 * module controls PM. So once ACPI-CA is attached, we try
410 * to apply the fixup to prevent LAPIC timer from hanging.
413 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
416 lwkt_send_ipiq_mask(smp_active_mask,
417 lapic_timer_fixup_handler, NULL);
419 lapic_timer_fixup_handler(NULL);
424 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
427 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
429 lapic_timer_restart_handler(NULL);
435 * dump contents of local APIC registers
440 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
441 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
442 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
448 * Inter Processor Interrupt functions.
452 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
454 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
455 * vector is any valid SYSTEM INT vector
456 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
458 * A backlog of requests can create a deadlock between cpus. To avoid this
459 * we have to be able to accept IPIs at the same time we are trying to send
460 * them. The critical section prevents us from attempting to send additional
461 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
462 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
463 * to occur but fortunately it does not happen too often.
466 apic_ipi(int dest_type, int vector, int delivery_mode)
471 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
472 unsigned int eflags = read_eflags();
474 DEBUG_PUSH_INFO("apic_ipi");
475 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
479 write_eflags(eflags);
482 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
483 delivery_mode | vector;
484 lapic->icr_lo = icr_lo;
490 single_apic_ipi(int cpu, int vector, int delivery_mode)
496 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
497 unsigned int eflags = read_eflags();
499 DEBUG_PUSH_INFO("single_apic_ipi");
500 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
504 write_eflags(eflags);
506 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
507 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
508 lapic->icr_hi = icr_hi;
511 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
512 | APIC_DEST_DESTFLD | delivery_mode | vector;
515 lapic->icr_lo = icr_lo;
522 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
524 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
525 * to the target, and the scheduler does not 'poll' for IPI messages.
528 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
534 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
538 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
539 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
540 lapic->icr_hi = icr_hi;
543 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
544 | APIC_DEST_DESTFLD | delivery_mode | vector;
547 lapic->icr_lo = icr_lo;
555 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
557 * target is a bitmask of destination cpus. Vector is any
558 * valid system INT vector. Delivery mode may be either
559 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
562 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
566 int n = BSFCPUMASK(target);
567 target &= ~CPUMASK(n);
568 single_apic_ipi(n, vector, delivery_mode);
576 * Timer code, in development...
577 * - suggested by rgrimes@gndrsh.aac.dev.com
580 get_apic_timer_frequency(void)
582 return(lapic_cputimer_intr.freq);
586 * Load a 'downcount time' in uSeconds.
589 set_apic_timer(int us)
594 * When we reach here, lapic timer's frequency
595 * must have been calculated as well as the
596 * divisor (lapic.dcr_timer is setup during the
597 * divisor calculation).
599 KKASSERT(lapic_cputimer_intr.freq != 0 &&
600 lapic_timer_divisor_idx >= 0);
602 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
603 lapic_timer_oneshot(count);
608 * Read remaining time in timer.
611 read_apic_timer(void)
614 /** XXX FIXME: we need to return the actual remaining time,
615 * for now we just return the remaining count.
618 return lapic->ccr_timer;
624 * Spin-style delay, set delay time in uS, spin till it drains.
629 set_apic_timer(count);
630 while (read_apic_timer())
635 lapic_unused_apic_id(int start)
639 for (i = start; i < NAPICID; ++i) {
640 if (APICID_TO_CPUID(i) == -1)
647 lapic_map(vm_paddr_t lapic_addr)
649 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
652 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
653 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
658 struct lapic_enumerator *e;
659 int error, i, ap_max;
661 KKASSERT(lapic_enable);
663 for (i = 0; i < NAPICID; ++i)
664 APICID_TO_CPUID(i) = -1;
666 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
667 error = e->lapic_probe(e);
672 kprintf("LAPIC: Can't find LAPIC\n");
676 e->lapic_enumerate(e);
679 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
680 if (ap_max > MAXCPU - 1)
684 kprintf("LAPIC: Warning use only %d out of %d "
685 "available APs\n", ap_max, naps);
693 lapic_enumerator_register(struct lapic_enumerator *ne)
695 struct lapic_enumerator *e;
697 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
698 if (e->lapic_prio < ne->lapic_prio) {
699 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
703 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
707 lapic_set_cpuid(int cpu_id, int apic_id)
709 CPUID_TO_APICID(cpu_id) = apic_id;
710 APICID_TO_CPUID(apic_id) = cpu_id;
714 lapic_fixup_noioapic(void)
718 /* Only allowed on BSP */
719 KKASSERT(mycpuid == 0);
720 KKASSERT(!ioapic_enable);
722 temp = lapic->lvt_lint0;
723 temp &= ~APIC_LVT_MASKED;
724 lapic->lvt_lint0 = temp;
726 temp = lapic->lvt_lint1;
727 temp |= APIC_LVT_MASKED;
728 lapic->lvt_lint1 = temp;
732 lapic_sysinit(void *dummy __unused)
737 error = lapic_config();
743 /* Initialize BSP's local APIC */
745 } else if (ioapic_enable) {
747 icu_reinit_noioapic();
750 SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL)