sys/platform/pc32/i386/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.206 2009/11/12 10:59:00 nyan
  40  */
  41 #include "opt_cpu.h"
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/sysctl.h>
  47 #include <sys/lock.h>
  48
  49 #include <machine/asmacros.h>
  50 #include <machine/clock.h>
  51 #include <machine/cputypes.h>
  52 #include <machine/segments.h>
  53 #include <machine/specialreg.h>
  54 #include <machine/md_var.h>
  55 #include <machine/intr_machdep.h>
  56 #include <machine/npx.h>
  57
  58 #define IDENTBLUE_CYRIX486      0
  59 #define IDENTBLUE_IBMCPU        1
  60 #define IDENTBLUE_CYRIXM2       2
  61
  62 /* XXX - should be in header file: */
  63 void printcpuinfo(void);
  64 void finishidentcpu(void);
  65 void earlysetcpuclass(void);
  66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  67 void    enable_K5_wt_alloc(void);
  68 void    enable_K6_wt_alloc(void);
  69 void    enable_K6_2_wt_alloc(void);
  70 #endif
  71 void panicifcpuunsupported(void);
  72
  73 static void init_exthigh(void);
  74 static u_int find_cpu_vendor_id(void);
  75 static void print_AMD_info(void);
  76 static void print_INTEL_info(void);
  77 static void print_INTEL_TLB(u_int data);
  78 static void print_AMD_assoc(int i);
  79 static void print_transmeta_info(void);
  80 static void print_via_padlock_info(void);
  81
  82 int     cpu_class;
  83 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
  84 char machine[] = MACHINE;
  85 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  86     machine, 0, "Machine class");
  87
  88 static char cpu_model[128];
  89 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  90     cpu_model, 0, "Machine model");
  91
  92 static int hw_clockrate;
  93 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
  94     &hw_clockrate, 0, "CPU instruction clock rate");
  95
  96 static char cpu_brand[48];
  97
  98 #define MAX_ADDITIONAL_INFO     16
  99
 100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
 101 static u_int additional_cpu_info_count;
 102
 103 #define MAX_BRAND_INDEX 8
 104
 105 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 106         NULL,                   /* No brand */
 107         "Intel Celeron",
 108         "Intel Pentium III",
 109         "Intel Pentium III Xeon",
 110         NULL,
 111         NULL,
 112         NULL,
 113         NULL,
 114         "Intel Pentium 4"
 115 };
 116
 117 static struct {
 118         char    *cpu_name;
 119         int     cpu_class;
 120 } i386_cpus[] = {
 121         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 122         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 123         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 124         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 125         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 126         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 127         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 128         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 129         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 130         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 131         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 132         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 133 };
 134
 135 static struct {
 136         char    *vendor;
 137         u_int   vendor_id;
 138 } cpu_vendors[] = {
 139         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 140         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 141         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 142         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 143         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 144         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 145         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 146         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 147         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 148 #if 0
 149         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 150         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 151 #endif
 152 };
 153
 154 #ifdef foo
 155 static int cpu_cores;
 156 static int cpu_logical;
 157 #endif
 158
 159 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 160 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
 161 #endif
 162
 163 static void
 164 init_exthigh(void)
 165 {
 166         static int done = 0;
 167         u_int regs[4];
 168
 169         if (done == 0) {
 170                 if (cpu_high > 0 &&
 171                     (cpu_vendor_id == CPU_VENDOR_INTEL ||
 172                     cpu_vendor_id == CPU_VENDOR_AMD ||
 173                     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 174                     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 175                     cpu_vendor_id == CPU_VENDOR_NSC)) {
 176                         do_cpuid(0x80000000, regs);
 177                         if (regs[0] >= 0x80000000)
 178                                 cpu_exthigh = regs[0];
 179                 }
 180
 181                 done = 1;
 182         }
 183 }
 184
 185 void
 186 printcpuinfo(void)
 187 {
 188         u_int regs[4], i;
 189         char *brand;
 190
 191         cpu_class = i386_cpus[cpu].cpu_class;
 192         kprintf("CPU: ");
 193         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
 194
 195         /* Check for extended CPUID information and a processor name. */
 196         init_exthigh();
 197         if (cpu_exthigh >= 0x80000004) {
 198                 brand = cpu_brand;
 199                 for (i = 0x80000002; i < 0x80000005; i++) {
 200                         do_cpuid(i, regs);
 201                         memcpy(brand, regs, sizeof(regs));
 202                         brand += sizeof(regs);
 203                 }
 204         }
 205
 206         if (cpu_vendor_id == CPU_VENDOR_INTEL) {
 207                 if ((cpu_id & 0xf00) > 0x300) {
 208                         u_int brand_index;
 209
 210                         cpu_model[0] = '\0';
 211
 212                         switch (cpu_id & 0x3000) {
 213                         case 0x1000:
 214                                 strcpy(cpu_model, "Overdrive ");
 215                                 break;
 216                         case 0x2000:
 217                                 strcpy(cpu_model, "Dual ");
 218                                 break;
 219                         }
 220
 221                         switch (cpu_id & 0xf00) {
 222                         case 0x400:
 223                                 strcat(cpu_model, "i486 ");
 224                                 /* Check the particular flavor of 486 */
 225                                 switch (cpu_id & 0xf0) {
 226                                 case 0x00:
 227                                 case 0x10:
 228                                         strcat(cpu_model, "DX");
 229                                         break;
 230                                 case 0x20:
 231                                         strcat(cpu_model, "SX");
 232                                         break;
 233                                 case 0x30:
 234                                         strcat(cpu_model, "DX2");
 235                                         break;
 236                                 case 0x40:
 237                                         strcat(cpu_model, "SL");
 238                                         break;
 239                                 case 0x50:
 240                                         strcat(cpu_model, "SX2");
 241                                         break;
 242                                 case 0x70:
 243                                         strcat(cpu_model,
 244                                             "DX2 Write-Back Enhanced");
 245                                         break;
 246                                 case 0x80:
 247                                         strcat(cpu_model, "DX4");
 248                                         break;
 249                                 }
 250                                 break;
 251                         case 0x500:
 252                                 /* Check the particular flavor of 586 */
 253                                 strcat(cpu_model, "Pentium");
 254                                 switch (cpu_id & 0xf0) {
 255                                 case 0x00:
 256                                         strcat(cpu_model, " A-step");
 257                                         break;
 258                                 case 0x10:
 259                                         strcat(cpu_model, "/P5");
 260                                         break;
 261                                 case 0x20:
 262                                         strcat(cpu_model, "/P54C");
 263                                         break;
 264                                 case 0x30:
 265                                         strcat(cpu_model, "/P24T");
 266                                         break;
 267                                 case 0x40:
 268                                         strcat(cpu_model, "/P55C");
 269                                         break;
 270                                 case 0x70:
 271                                         strcat(cpu_model, "/P54C");
 272                                         break;
 273                                 case 0x80:
 274                                         strcat(cpu_model, "/P55C (quarter-micron)");
 275                                         break;
 276                                 default:
 277                                         /* nothing */
 278                                         break;
 279                                 }
 280 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 281                                 /*
 282                                  * XXX - If/when Intel fixes the bug, this
 283                                  * should also check the version of the
 284                                  * CPU, not just that it's a Pentium.
 285                                  */
 286                                 has_f00f_bug = 1;
 287 #endif
 288                                 break;
 289                         case 0x600:
 290                                 /* Check the particular flavor of 686 */
 291                                 switch (cpu_id & 0xf0) {
 292                                 case 0x00:
 293                                         strcat(cpu_model, "Pentium Pro A-step");
 294                                         break;
 295                                 case 0x10:
 296                                         strcat(cpu_model, "Pentium Pro");
 297                                         break;
 298                                 case 0x30:
 299                                 case 0x50:
 300                                 case 0x60:
 301                                         strcat(cpu_model,
 302                                 "Pentium II/Pentium II Xeon/Celeron");
 303                                         cpu = CPU_PII;
 304                                         break;
 305                                 case 0x70:
 306                                 case 0x80:
 307                                 case 0xa0:
 308                                 case 0xb0:
 309                                         strcat(cpu_model,
 310                                         "Pentium III/Pentium III Xeon/Celeron");
 311                                         cpu = CPU_PIII;
 312                                         break;
 313                                 default:
 314                                         strcat(cpu_model, "Unknown 80686");
 315                                         break;
 316                                 }
 317                                 break;
 318                         case 0xf00:
 319                                 strcat(cpu_model, "Pentium 4");
 320                                 cpu = CPU_P4;
 321                                 break;
 322                         default:
 323                                 strcat(cpu_model, "unknown");
 324                                 break;
 325                         }
 326
 327                         /*
 328                          * If we didn't get a brand name from the extended
 329                          * CPUID, try to look it up in the brand table.
 330                          */
 331                         if (cpu_high > 0 && *cpu_brand == '\0') {
 332                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 333                                 if (brand_index <= MAX_BRAND_INDEX &&
 334                                     cpu_brandtable[brand_index] != NULL)
 335                                         strcpy(cpu_brand,
 336                                             cpu_brandtable[brand_index]);
 337                         }
 338                 }
 339         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
 340                 /*
 341                  * Values taken from AMD Processor Recognition
 342                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 343                  * (also describes ``Features'' encodings.
 344                  */
 345                 strcpy(cpu_model, "AMD ");
 346                 switch (cpu_id & 0xFF0) {
 347                 case 0x410:
 348                         strcat(cpu_model, "Standard Am486DX");
 349                         break;
 350                 case 0x430:
 351                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 352                         break;
 353                 case 0x470:
 354                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 355                         break;
 356                 case 0x480:
 357                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 358                         break;
 359                 case 0x490:
 360                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 361                         break;
 362                 case 0x4E0:
 363                         strcat(cpu_model, "Am5x86 Write-Through");
 364                         break;
 365                 case 0x4F0:
 366                         strcat(cpu_model, "Am5x86 Write-Back");
 367                         break;
 368                 case 0x500:
 369                         strcat(cpu_model, "K5 model 0");
 370                         tsc_is_broken = 1;
 371                         break;
 372                 case 0x510:
 373                         strcat(cpu_model, "K5 model 1");
 374                         break;
 375                 case 0x520:
 376                         strcat(cpu_model, "K5 PR166 (model 2)");
 377                         break;
 378                 case 0x530:
 379                         strcat(cpu_model, "K5 PR200 (model 3)");
 380                         break;
 381                 case 0x560:
 382                         strcat(cpu_model, "K6");
 383                         break;
 384                 case 0x570:
 385                         strcat(cpu_model, "K6 266 (model 1)");
 386                         break;
 387                 case 0x580:
 388                         strcat(cpu_model, "K6-2");
 389                         break;
 390                 case 0x590:
 391                         strcat(cpu_model, "K6-III");
 392                         break;
 393                 case 0x5a0:
 394                         strcat(cpu_model, "Geode LX");
 395                         /*
 396                          * Make sure the TSC runs through suspension,
 397                          * otherwise we can't use it as timecounter
 398                          */
 399                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 400                         break;
 401                 default:
 402                         strcat(cpu_model, "Unknown");
 403                         break;
 404                 }
 405 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 406                 if ((cpu_id & 0xf00) == 0x500) {
 407                         if (((cpu_id & 0x0f0) > 0)
 408                             && ((cpu_id & 0x0f0) < 0x60)
 409                             && ((cpu_id & 0x00f) > 3))
 410                                 enable_K5_wt_alloc();
 411                         else if (((cpu_id & 0x0f0) > 0x80)
 412                                  || (((cpu_id & 0x0f0) == 0x80)
 413                                      && (cpu_id & 0x00f) > 0x07))
 414                                 enable_K6_2_wt_alloc();
 415                         else if ((cpu_id & 0x0f0) > 0x50)
 416                                 enable_K6_wt_alloc();
 417                 }
 418 #endif
 419         } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
 420                 strcpy(cpu_model, "Rise ");
 421                 switch (cpu_id & 0xff0) {
 422                 case 0x500:
 423                         strcat(cpu_model, "mP6");
 424                         break;
 425                 default:
 426                         strcat(cpu_model, "Unknown");
 427                 }
 428         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 429                 switch (cpu_id & 0xff0) {
 430                 case 0x540:
 431                         strcpy(cpu_model, "IDT WinChip C6");
 432                         tsc_is_broken = 1;
 433                         break;
 434                 case 0x580:
 435                         strcpy(cpu_model, "IDT WinChip 2");
 436                         break;
 437                 case 0x660:
 438                         strcpy(cpu_model, "VIA C3 Samuel");
 439                         break;
 440                 case 0x670:
 441                         if (cpu_id & 0x8)
 442                                 strcpy(cpu_model, "VIA C3 Ezra");
 443                         else
 444                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 445                         break;
 446                 case 0x680:
 447                         strcpy(cpu_model, "VIA C3 Ezra-T");
 448                         break;
 449                 case 0x690:
 450                         strcpy(cpu_model, "VIA C3 Nehemiah");
 451                         break;
 452                 case 0x6a0:
 453                 case 0x6d0:
 454                         strcpy(cpu_model, "VIA C7 Esther");
 455                         break;
 456                 case 0x6f0:
 457                         strcpy(cpu_model, "VIA Nano");
 458                         break;
 459                 default:
 460                         strcpy(cpu_model, "VIA/IDT Unknown");
 461                 }
 462         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
 463                 strcpy(cpu_model, "Blue Lightning CPU");
 464         } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
 465                 switch (cpu_id & 0xfff) {
 466                 case 0x540:
 467                         strcpy(cpu_model, "Geode SC1100");
 468                         cpu = CPU_GEODE1100;
 469                         tsc_is_broken = 1;
 470                         break;
 471                 default:
 472                         strcpy(cpu_model, "Geode/NSC unknown");
 473                         break;
 474                 }
 475         }
 476
 477         /*
 478          * Replace cpu_model with cpu_brand minus leading spaces if
 479          * we have one.
 480          */
 481         brand = cpu_brand;
 482         while (*brand == ' ')
 483                 ++brand;
 484         if (*brand != '\0')
 485                 strcpy(cpu_model, brand);
 486
 487         kprintf("%s (", cpu_model);
 488         switch(cpu_class) {
 489         case CPUCLASS_286:
 490                 kprintf("286");
 491                 break;
 492         case CPUCLASS_386:
 493                 kprintf("386");
 494                 break;
 495 #if defined(I486_CPU)
 496         case CPUCLASS_486:
 497                 kprintf("486");
 498                 break;
 499 #endif
 500 #if defined(I586_CPU)
 501         case CPUCLASS_586:
 502                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 503                 kprintf("%jd.%02d-MHz ",
 504                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 505                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 506                 kprintf("586");
 507                 break;
 508 #endif
 509 #if defined(I686_CPU)
 510         case CPUCLASS_686:
 511                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 512                 kprintf("%jd.%02d-MHz ",
 513                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 514                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 515                 kprintf("686");
 516                 break;
 517 #endif
 518         default:
 519                 kprintf("Unknown");     /* will panic below... */
 520         }
 521         kprintf("-class CPU)\n");
 522         if(*cpu_vendor)
 523                 kprintf("  Origin = \"%s\"",cpu_vendor);
 524         if(cpu_id)
 525                 kprintf("  Id = 0x%x", cpu_id);
 526
 527         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 528             cpu_vendor_id == CPU_VENDOR_AMD ||
 529             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 530             cpu_vendor_id == CPU_VENDOR_RISE ||
 531             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 532             cpu_vendor_id == CPU_VENDOR_NSC) {
 533                 kprintf("  Stepping = %u", cpu_id & 0xf);
 534                 if (cpu_high > 0) {
 535 #if 0
 536                         u_int cmp = 1, htt = 1;
 537 #endif
 538                         /*
 539                          * Here we should probably set up flags indicating
 540                          * whether or not various features are available.
 541                          * The interesting ones are probably VME, PSE, PAE,
 542                          * and PGE.  The code already assumes without bothering
 543                          * to check that all CPUs >= Pentium have a TSC and
 544                          * MSRs.
 545                          */
 546                         kprintf("\n  Features=0x%b", cpu_feature,
 547                         "\020"
 548                         "\001FPU"       /* Integral FPU */
 549                         "\002VME"       /* Extended VM86 mode support */
 550                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 551                         "\004PSE"       /* 4MByte page tables */
 552                         "\005TSC"       /* Timestamp counter */
 553                         "\006MSR"       /* Machine specific registers */
 554                         "\007PAE"       /* Physical address extension */
 555                         "\010MCE"       /* Machine Check support */
 556                         "\011CX8"       /* CMPEXCH8 instruction */
 557                         "\012APIC"      /* SMP local APIC */
 558                         "\013oldMTRR"   /* Previous implementation of MTRR */
 559                         "\014SEP"       /* Fast System Call */
 560                         "\015MTRR"      /* Memory Type Range Registers */
 561                         "\016PGE"       /* PG_G (global bit) support */
 562                         "\017MCA"       /* Machine Check Architecture */
 563                         "\020CMOV"      /* CMOV instruction */
 564                         "\021PAT"       /* Page attributes table */
 565                         "\022PSE36"     /* 36 bit address space support */
 566                         "\023PN"        /* Processor Serial number */
 567                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 568                         "\025<b20>"
 569                         "\026DTS"       /* Debug Trace Store */
 570                         "\027ACPI"      /* ACPI support */
 571                         "\030MMX"       /* MMX instructions */
 572                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 573                         "\032SSE"       /* Streaming SIMD Extensions */
 574                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 575                         "\034SS"        /* Self snoop */
 576                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 577                         "\036TM"        /* Thermal Monitor clock slowdown */
 578                         "\037IA64"      /* CPU can execute IA64 instructions */
 579                         "\040PBE"       /* Pending Break Enable */
 580                         );
 581
 582                         if (cpu_feature2 != 0) {
 583                                 kprintf("\n  Features2=0x%b", cpu_feature2,
 584                                 "\020"
 585                                 "\001SSE3"      /* SSE3 */
 586                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
 587                                 "\003DTES64"    /* 64-bit Debug Trace */
 588                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 589                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 590                                 "\006VMX"       /* Virtual Machine Extensions */
 591                                 "\007SMX"       /* Safer Mode Extensions */
 592                                 "\010EST"       /* Enhanced SpeedStep */
 593                                 "\011TM2"       /* Thermal Monitor 2 */
 594                                 "\012SSSE3"     /* SSSE3 */
 595                                 "\013CNXT-ID"   /* L1 context ID available */
 596                                 "\014<b11>"
 597                                 "\015FMA"       /* Fused Multiply Add */
 598                                 "\016CX16"      /* CMPXCHG16B Instruction */
 599                                 "\017xTPR"      /* Send Task Priority Messages */
 600                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 601                                 "\021<b16>"
 602                                 "\022PCID"      /* Process-context Identifiers */
 603                                 "\023DCA"       /* Direct Cache Access */
 604                                 "\024SSE4.1"    /* SSE 4.1 */
 605                                 "\025SSE4.2"    /* SSE 4.2 */
 606                                 "\026x2APIC"    /* xAPIC Extensions */
 607                                 "\027MOVBE"     /* MOVBE Instruction */
 608                                 "\030POPCNT"    /* POPCNT Instruction */
 609                                 "\031TSCDLT"    /* TSC-Deadline Timer */
 610                                 "\032AESNI"     /* AES Crypto */
 611                                 "\033XSAVE"     /* XSAVE/XRSTOR States */
 612                                 "\034OSXSAVE"   /* OS-Enabled State Management */
 613                                 "\035AVX"       /* Advanced Vector Extensions */
 614                                 "\036F16C"      /* Half-precision conversions */
 615                                 "\037RDRND"     /* RDRAND RNG function */
 616                                 "\040VMM"       /* Running on a hypervisor */
 617                                 );
 618                         }
 619
 620                         /*
 621                          * AMD64 Architecture Programmer's Manual Volume 3:
 622                          * General-Purpose and System Instructions
 623                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
 624                          *
 625                          * IA-32 Intel Architecture Software Developer's Manual,
 626                          * Volume 2A: Instruction Set Reference, A-M
 627                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
 628                          */
 629                         if (amd_feature != 0) {
 630                                 kprintf("\n  AMD Features=0x%b", amd_feature,
 631                                 "\020"          /* in hex */
 632                                 "\001<s0>"      /* Same */
 633                                 "\002<s1>"      /* Same */
 634                                 "\003<s2>"      /* Same */
 635                                 "\004<s3>"      /* Same */
 636                                 "\005<s4>"      /* Same */
 637                                 "\006<s5>"      /* Same */
 638                                 "\007<s6>"      /* Same */
 639                                 "\010<s7>"      /* Same */
 640                                 "\011<s8>"      /* Same */
 641                                 "\012<s9>"      /* Same */
 642                                 "\013<b10>"     /* Undefined */
 643                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 644                                 "\015<s12>"     /* Same */
 645                                 "\016<s13>"     /* Same */
 646                                 "\017<s14>"     /* Same */
 647                                 "\020<s15>"     /* Same */
 648                                 "\021<s16>"     /* Same */
 649                                 "\022<s17>"     /* Same */
 650                                 "\023<b18>"     /* Reserved, unknown */
 651                                 "\024MP"        /* Multiprocessor Capable */
 652                                 "\025NX"        /* Has EFER.NXE, NX */
 653                                 "\026<b21>"     /* Undefined */
 654                                 "\027MMX+"      /* AMD MMX Extensions */
 655                                 "\030<s23>"     /* Same */
 656                                 "\031<s24>"     /* Same */
 657                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 658                                 "\033Page1GB"   /* 1-GB large page support */
 659                                 "\034RDTSCP"    /* RDTSCP */
 660                                 "\035<b28>"     /* Undefined */
 661                                 "\036LM"        /* 64 bit long mode */
 662                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 663                                 "\0403DNow!"    /* AMD 3DNow! */
 664                                 );
 665                         }
 666
 667                         if (amd_feature2 != 0) {
 668                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
 669                                 "\020"
 670                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 671                                 "\002CMP"       /* CMP legacy */
 672                                 "\003SVM"       /* Secure Virtual Mode */
 673                                 "\004ExtAPIC"   /* Extended APIC register */
 674                                 "\005CR8"       /* CR8 in legacy mode */
 675                                 "\006ABM"       /* LZCNT instruction */
 676                                 "\007SSE4A"     /* SSE4A */
 677                                 "\010MAS"       /* Misaligned SSE mode */
 678                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 679                                 "\012OSVW"      /* OS visible workaround */
 680                                 "\013IBS"       /* Instruction based sampling */
 681                                 "\014XOP"       /* XOP extended instructions */
 682                                 "\015SKINIT"    /* SKINIT/STGI */
 683                                 "\016WDT"       /* Watchdog timer */
 684                                 "\017<b14>"
 685                                 "\020LWP"       /* Lightweight Profiling */
 686                                 "\021FMA4"      /* 4-operand FMA instructions */
 687                                 "\022TCE"       /* Translation Cache Extension */
 688                                 "\023<b18>"
 689                                 "\024NodeId"    /* NodeId MSR support */
 690                                 "\025<b20>"
 691                                 "\026TBM"       /* Trailing Bit Manipulation */
 692                                 "\027Topology"  /* Topology Extensions */
 693                                 "\030PCX_CORE"  /* Core Performance Counter */
 694                                 "\031PCX_NB"    /* NB Performance Counter */
 695                                 "\032SPM"       /* Streaming Perf Monitor */
 696                                 "\033DBE"       /* Data Breakpoint Extension */
 697                                 "\034PTSC"      /* Performance TSC */
 698                                 "\035PCX_L2I"   /* L2I Performance Counter */
 699                                 "\036<b29>"
 700                                 "\037<b30>"
 701                                 "\040<b31>"
 702                                 );
 703                         }
 704
 705                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
 706                                 print_via_padlock_info();
 707
 708                         /*
 709                          * INVALID CPU TOPOLOGY INFORMATION PRINT
 710                          * DEPRECATED - CPU_TOPOLOGY_DETECTION moved to
 711                          * - sys/platform/pc64/x86_64/mp_machdep.c
 712                          * - sys/kern/subr_cpu_topology
 713                          */
 714
 715 #if 0
 716                         if ((cpu_feature & CPUID_HTT) &&
 717                             cpu_vendor_id == CPU_VENDOR_AMD)
 718                                 cpu_feature &= ~CPUID_HTT;
 719 #endif
 720
 721                         /*
 722                          * If this CPU supports HTT or CMP then mention the
 723                          * number of physical/logical cores it contains.
 724                          */
 725 #if 0
 726                         if (cpu_feature & CPUID_HTT)
 727                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
 728                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
 729                             (amd_feature2 & AMDID2_CMP))
 730                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
 731                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
 732                             (cpu_high >= 4)) {
 733                                 cpuid_count(4, 0, regs);
 734                                 if ((regs[0] & 0x1f) != 0)
 735                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
 736                         }
 737 #endif
 738 #ifdef foo
 739                         /*
 740                          * XXX For Intel CPUs, this is max number of cores per
 741                          * package, not the actual cores per package.
 742                          */
 743 #if 0
 744                         cpu_cores = cmp;
 745                         cpu_logical = htt / cmp;
 746
 747                         if (cpu_cores > 1)
 748                                 kprintf("\n  Cores per package: %d", cpu_cores);
 749                         if (cpu_logical > 1) {
 750                                 kprintf("\n  Logical CPUs per core: %d",
 751                                     cpu_logical);
 752                         }
 753 #endif
 754 #endif
 755
 756 #if 0
 757                         /*
 758                          * If this CPU supports P-state invariant TSC then
 759                          * mention the capability.
 760                          */
 761                         switch (cpu_vendor_id) {
 762                         case CPU_VENDOR_AMD:
 763                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
 764                                     CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
 765                                     cpu_id == 0x60fb2)
 766                                         tsc_is_invariant = 1;
 767                                 break;
 768                         case CPU_VENDOR_INTEL:
 769                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
 770                                     (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 771                                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
 772                                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
 773                                     CPUID_TO_MODEL(cpu_id) >= 0x3))
 774                                         tsc_is_invariant = 1;
 775                                 break;
 776                         case CPU_VENDOR_CENTAUR:
 777                                 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 778                                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
 779                                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
 780                                         tsc_is_invariant = 1;
 781                                 break;
 782                         }
 783                         if (tsc_is_invariant)
 784                                 kprintf("\n  TSC: P-state invariant");
 785 #endif
 786
 787                 }
 788         }
 789
 790         /* Avoid ugly blank lines: only print newline when we have to. */
 791         if (*cpu_vendor || cpu_id)
 792                 kprintf("\n");
 793
 794         for (i = 0; i < additional_cpu_info_count; ++i) {
 795                 kprintf("  %s\n", additional_cpu_info_ary[i]);
 796         }
 797
 798         if (!bootverbose)
 799                 return;
 800
 801         if (cpu_vendor_id == CPU_VENDOR_AMD)
 802                 print_AMD_info();
 803         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 804                 print_INTEL_info();
 805         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
 806                 print_transmeta_info();
 807
 808 #ifdef CPU_HAS_SSE2
 809         kprintf("Use SSE2 (lfence, mfence)\n");
 810 #endif
 811         kprintf("npx mask: 0x%8.8x\n", npx_mxcsr_mask);
 812 }
 813
 814 void
 815 panicifcpuunsupported(void)
 816 {
 817
 818 #if !defined(lint)
 819 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 820 #error This kernel is not configured for one of the supported CPUs
 821 #endif
 822 #else /* lint */
 823 #endif /* lint */
 824         /*
 825          * Now that we have told the user what they have,
 826          * let them know if that machine type isn't configured.
 827          */
 828         switch (cpu_class) {
 829         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
 830         case CPUCLASS_386:
 831 #if !defined(I486_CPU)
 832         case CPUCLASS_486:
 833 #endif
 834 #if !defined(I586_CPU)
 835         case CPUCLASS_586:
 836 #endif
 837 #if !defined(I686_CPU)
 838         case CPUCLASS_686:
 839 #endif
 840                 panic("CPU class not configured");
 841         default:
 842                 break;
 843         }
 844 }
 845
 846
 847 static  volatile u_int trap_by_rdmsr;
 848
 849 /*
 850  * Special exception 6 handler.
 851  * The rdmsr instruction generates invalid opcodes fault on 486-class
 852  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
 853  * function identblue() when this handler is called.  Stacked eip should
 854  * be advanced.
 855  */
 856 inthand_t       bluetrap6;
 857
 858 __asm
 859 ("                                                                      \n\
 860         .text                                                           \n\
 861         .p2align 2,0x90                                                 \n\
 862         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
 863 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
 864         ss                                                              \n\
 865         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
 866         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
 867         iret                                                            \n\
 868 ");
 869
 870 /*
 871  * Special exception 13 handler.
 872  * Accessing non-existent MSR generates general protection fault.
 873  */
 874 inthand_t       bluetrap13;
 875
 876 __asm
 877 ("                                                                      \n\
 878         .text                                                           \n\
 879         .p2align 2,0x90                                                 \n\
 880         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
 881 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
 882         ss                                                              \n\
 883         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
 884         popl    %eax            /* discard error code */                \n\
 885         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
 886         iret                                                            \n\
 887 ");
 888
 889 /*
 890  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
 891  * support cpuid instruction.  This function should be called after
 892  * loading interrupt descriptor table register.
 893  *
 894  * I don't like this method that handles fault, but I couldn't get
 895  * information for any other methods.  Does blue giant know?
 896  */
 897 static int
 898 identblue(void)
 899 {
 900
 901         trap_by_rdmsr = 0;
 902
 903         /*
 904          * Cyrix 486-class CPU does not support rdmsr instruction.
 905          * The rdmsr instruction generates invalid opcode fault, and exception
 906          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
 907          * bluetrap6() set the magic number to trap_by_rdmsr.
 908          */
 909         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL,
 910             GSEL(GCODE_SEL, SEL_KPL));
 911
 912         /*
 913          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
 914          * In this case, rdmsr generates general protection fault, and
 915          * exception will be trapped by bluetrap13().
 916          */
 917         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL,
 918             GSEL(GCODE_SEL, SEL_KPL));
 919
 920         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
 921
 922         if (trap_by_rdmsr == 0xa8c1d)
 923                 return IDENTBLUE_CYRIX486;
 924         else if (trap_by_rdmsr == 0xa89c4)
 925                 return IDENTBLUE_CYRIXM2;
 926         return IDENTBLUE_IBMCPU;
 927 }
 928
 929 #if 0
 930 /* Update TSC freq with the value indicated by the caller. */
 931 static void
 932 tsc_frequency_changed(void *arg, const struct cf_level *level, int status)
 933 {
 934         /*
 935          * If there was an error during the transition or
 936          * TSC is P-state invariant, don't do anything.
 937          */
 938         if (status != 0 || tsc_is_invariant)
 939                 return;
 940
 941         /* Total setting for this level gives the new frequency in MHz. */
 942         hw_clockrate = level->total_set.freq;
 943 }
 944 #endif
 945
 946 /*
 947  * Final stage of CPU identification. -- Should I check TI?
 948  */
 949 void
 950 finishidentcpu(void)
 951 {
 952         int     isblue = 0;
 953         u_int   regs[4];
 954
 955         cpu_vendor_id = find_cpu_vendor_id();
 956
 957         /*
 958          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
 959          * function number again if it is set from BIOS.  It is necessary
 960          * for probing correct CPU topology later.
 961          * XXX This is only done on the BSP package.
 962          */
 963         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
 964             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
 965             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
 966                 uint64_t msr;
 967                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
 968                 if ((msr & 0x400000ULL) != 0) {
 969                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
 970                         do_cpuid(0, regs);
 971                         cpu_high = regs[0];
 972                 }
 973         }
 974
 975         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
 976         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 977             cpu_vendor_id == CPU_VENDOR_AMD) {
 978                 init_exthigh();
 979                 if (cpu_exthigh >= 0x80000001) {
 980                         do_cpuid(0x80000001, regs);
 981                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 982                         amd_feature2 = regs[2];
 983                 }
 984 #if 0
 985                 if (cpu_exthigh >= 0x80000007) {
 986                         do_cpuid(0x80000007, regs);
 987                         amd_pminfo = regs[3];
 988                 }
 989 #endif
 990                 if (cpu_exthigh >= 0x80000008) {
 991                         do_cpuid(0x80000008, regs);
 992                         cpu_procinfo2 = regs[2];
 993                 }
 994         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
 995                 /*
 996                  * There are BlueLightning CPUs that do not change
 997                  * undefined flags by dividing 5 by 2.  In this case,
 998                  * the CPU identification routine in locore.s leaves
 999                  * cpu_vendor null string and puts CPU_486 into the
1000                  * cpu.
1001                  */
1002                 isblue = identblue();
1003                 if (isblue == IDENTBLUE_IBMCPU) {
1004                         strcpy(cpu_vendor, "IBM");
1005                         cpu_vendor_id = CPU_VENDOR_IBM;
1006                         cpu = CPU_BLUE;
1007                 }
1008         }
1009
1010         /*
1011          * Set MI flags for MI procedures implemented using machine-specific
1012          * features.
1013          */
1014         if (cpu_feature & CPUID_SSE2)
1015                 cpu_mi_feature |= CPU_MI_BZERONT;
1016
1017         if (cpu_feature2 & CPUID2_MON)
1018                 cpu_mi_feature |= CPU_MI_MONITOR;
1019
1020 #ifdef CPU_HAS_SSE2
1021         if ((cpu_feature & CPUID_SSE2) == 0)
1022                 panic("CPU does not has SSE2, remove options CPU_HAS_SSE2");
1023 #endif
1024 }
1025
1026 static u_int
1027 find_cpu_vendor_id(void)
1028 {
1029         int     i;
1030
1031         for (i = 0; i < NELEM(cpu_vendors); i++)
1032                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1033                         return (cpu_vendors[i].vendor_id);
1034         return (0);
1035 }
1036
1037 static void
1038 print_AMD_assoc(int i)
1039 {
1040         if (i == 255)
1041                 kprintf(", fully associative\n");
1042         else
1043                 kprintf(", %d-way associative\n", i);
1044 }
1045
1046 /*
1047  * #31116 Rev 3.06 section 3.9
1048  * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1049  */
1050 static void
1051 print_AMD_L2L3_assoc(int i)
1052 {
1053         static const char *assoc_str[] = {
1054                 [0x0] = "disabled",
1055                 [0x1] = "direct mapped",
1056                 [0x2] = "2-way associative",
1057                 [0x4] = "4-way associative",
1058                 [0x6] = "8-way associative",
1059                 [0x8] = "16-way associative",
1060                 [0xa] = "32-way associative",
1061                 [0xb] = "48-way associative",
1062                 [0xc] = "64-way associative",
1063                 [0xd] = "96-way associative",
1064                 [0xe] = "128-way associative",
1065                 [0xf] = "fully associative"
1066         };
1067
1068         i &= 0xf;
1069         if (assoc_str[i] == NULL)
1070                 kprintf(", unknown associative\n");
1071         else
1072                 kprintf(", %s\n", assoc_str[i]);
1073 }
1074
1075 static void
1076 print_AMD_info(void)
1077 {
1078         quad_t amd_whcr;
1079
1080         if (cpu_exthigh >= 0x80000005) {
1081                 u_int regs[4];
1082
1083                 do_cpuid(0x80000005, regs);
1084                 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1085                 print_AMD_assoc(regs[1] >> 24);
1086                 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1087                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1088                 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1089                 kprintf(", %d bytes/line", regs[2] & 0xff);
1090                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1091                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1092                 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1093                 kprintf(", %d bytes/line", regs[3] & 0xff);
1094                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1095                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1096                 if (cpu_exthigh >= 0x80000006) {        /* K6-III or later */
1097                         do_cpuid(0x80000006, regs);
1098                         /*
1099                          * Report right L2 cache size on Duron rev. A0.
1100                          */
1101                         if ((cpu_id & 0xFF0) == 0x630)
1102                                 kprintf("L2 internal cache: 64 kbytes");
1103                         else
1104                                 kprintf("L2 internal cache: %d kbytes", regs[2] >> 16);
1105
1106                         kprintf(", %d bytes/line", regs[2] & 0xff);
1107                         kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1108                         print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1109
1110                         /*
1111                          * #31116 Rev 3.06 section 2.16.2:
1112                          * ... If EDX[31:16] is not zero then the processor
1113                          * includes an L3. ...
1114                          */
1115                         if ((regs[3] & 0xffff0000) != 0) {
1116                                 kprintf("L3 shared cache: %d kbytes",
1117                                         (regs[3] >> 18) * 512);
1118                                 kprintf(", %d bytes/line", regs[3] & 0xff);
1119                                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1120                                 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1121                         }
1122                 }
1123         }
1124         if (((cpu_id & 0xf00) == 0x500)
1125             && (((cpu_id & 0x0f0) > 0x80)
1126                 || (((cpu_id & 0x0f0) == 0x80)
1127                     && (cpu_id & 0x00f) > 0x07))) {
1128                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1129                 amd_whcr = rdmsr(0xc0000082);
1130                 if (!(amd_whcr & (0x3ff << 22))) {
1131                         kprintf("Write Allocate Disable\n");
1132                 } else {
1133                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1134                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1135                         kprintf("Write Allocate 15-16M bytes: %s\n",
1136                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1137                 }
1138         } else if (((cpu_id & 0xf00) == 0x500)
1139                    && ((cpu_id & 0x0f0) > 0x50)) {
1140                 /* K6, K6-2(old core) */
1141                 amd_whcr = rdmsr(0xc0000082);
1142                 if (!(amd_whcr & (0x7f << 1))) {
1143                         kprintf("Write Allocate Disable\n");
1144                 } else {
1145                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1146                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1147                         kprintf("Write Allocate 15-16M bytes: %s\n",
1148                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1149                         kprintf("Hardware Write Allocate Control: %s\n",
1150                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1151                 }
1152         }
1153
1154         /*
1155          * Opteron Rev E shows a bug as in very rare occasions a read memory
1156          * barrier is not performed as expected if it is followed by a
1157          * non-atomic read-modify-write instruction.
1158          * As long as that bug pops up very rarely (intensive machine usage
1159          * on other operating systems generally generates one unexplainable
1160          * crash any 2 months) and as long as a model specific fix would be
1161          * impratical at this stage, print out a warning string if the broken
1162          * model and family are identified.
1163          */
1164         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1165             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1166                 kprintf("WARNING: This architecture revision has known SMP "
1167                     "hardware bugs which may cause random instability\n");
1168 }
1169
1170 static void
1171 print_INTEL_info(void)
1172 {
1173         u_int regs[4];
1174         u_int rounds, regnum;
1175         u_int nwaycode, nway;
1176
1177         if (cpu_high >= 2) {
1178                 rounds = 0;
1179                 do {
1180                         do_cpuid(0x2, regs);
1181                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1182                                 break;  /* we have a buggy CPU */
1183
1184                         for (regnum = 0; regnum <= 3; ++regnum) {
1185                                 if (regs[regnum] & (1<<31))
1186                                         continue;
1187                                 if (regnum != 0)
1188                                         print_INTEL_TLB(regs[regnum] & 0xff);
1189                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1190                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1191                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1192                         }
1193                 } while (--rounds > 0);
1194         }
1195
1196         if (cpu_exthigh >= 0x80000006) {
1197                 do_cpuid(0x80000006, regs);
1198                 nwaycode = (regs[2] >> 12) & 0x0f;
1199                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1200                         nway = 1 << (nwaycode / 2);
1201                 else
1202                         nway = 0;
1203                 kprintf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1204                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1205         }
1206
1207         kprintf("\n");
1208 }
1209
1210 static void
1211 print_INTEL_TLB(u_int data)
1212 {
1213         switch (data) {
1214         case 0x0:
1215         case 0x40:
1216         default:
1217                 break;
1218         case 0x1:
1219                 kprintf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1220                 break;
1221         case 0x2:
1222                 kprintf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1223                 break;
1224         case 0x3:
1225                 kprintf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1226                 break;
1227         case 0x4:
1228                 kprintf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1229                 break;
1230         case 0x6:
1231                 kprintf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1232                 break;
1233         case 0x8:
1234                 kprintf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1235                 break;
1236         case 0xa:
1237                 kprintf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1238                 break;
1239         case 0xc:
1240                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1241                 break;
1242         case 0x22:
1243                 kprintf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1244                 break;
1245         case 0x23:
1246                 kprintf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1247                 break;
1248         case 0x25:
1249                 kprintf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1250                 break;
1251         case 0x29:
1252                 kprintf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1253                 break;
1254         case 0x2c:
1255                 kprintf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1256                 break;
1257         case 0x30:
1258                 kprintf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1259                 break;
1260         case 0x39:
1261                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1262                 break;
1263         case 0x3b:
1264                 kprintf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1265                 break;
1266         case 0x3c:
1267                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1268                 break;
1269         case 0x41:
1270                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1271                 break;
1272         case 0x42:
1273                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1274                 break;
1275         case 0x43:
1276                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1277                 break;
1278         case 0x44:
1279                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1280                 break;
1281         case 0x45:
1282                 kprintf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1283                 break;
1284         case 0x46:
1285                 kprintf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1286                 break;
1287         case 0x47:
1288                 kprintf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1289                 break;
1290         case 0x50:
1291                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1292                 break;
1293         case 0x51:
1294                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1295                 break;
1296         case 0x52:
1297                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1298                 break;
1299         case 0x5b:
1300                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1301                 break;
1302         case 0x5c:
1303                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1304                 break;
1305         case 0x5d:
1306                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1307                 break;
1308         case 0x60:
1309                 kprintf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1310                 break;
1311         case 0x66:
1312                 kprintf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1313                 break;
1314         case 0x67:
1315                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1316                 break;
1317         case 0x68:
1318                 kprintf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1319                 break;
1320         case 0x70:
1321                 kprintf("\nTrace cache: 12K-uops, 8-way set associative");
1322                 break;
1323         case 0x71:
1324                 kprintf("\nTrace cache: 16K-uops, 8-way set associative");
1325                 break;
1326         case 0x72:
1327                 kprintf("\nTrace cache: 32K-uops, 8-way set associative");
1328                 break;
1329         case 0x78:
1330                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1331                 break;
1332         case 0x79:
1333                 kprintf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1334                 break;
1335         case 0x7a:
1336                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1337                 break;
1338         case 0x7b:
1339                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1340                 break;
1341         case 0x7c:
1342                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1343                 break;
1344         case 0x7d:
1345                 kprintf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1346                 break;
1347         case 0x7f:
1348                 kprintf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1349                 break;
1350         case 0x82:
1351                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1352                 break;
1353         case 0x83:
1354                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1355                 break;
1356         case 0x84:
1357                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1358                 break;
1359         case 0x85:
1360                 kprintf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1361                 break;
1362         case 0x86:
1363                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1364                 break;
1365         case 0x87:
1366                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1367                 break;
1368         case 0xb0:
1369                 kprintf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1370                 break;
1371         case 0xb3:
1372                 kprintf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1373                 break;
1374         }
1375 }
1376
1377 static void
1378 print_transmeta_info(void)
1379 {
1380         u_int regs[4], nreg = 0;
1381
1382         do_cpuid(0x80860000, regs);
1383         nreg = regs[0];
1384         if (nreg >= 0x80860001) {
1385                 do_cpuid(0x80860001, regs);
1386                 kprintf("  Processor revision %u.%u.%u.%u\n",
1387                        (regs[1] >> 24) & 0xff,
1388                        (regs[1] >> 16) & 0xff,
1389                        (regs[1] >> 8) & 0xff,
1390                        regs[1] & 0xff);
1391         }
1392         if (nreg >= 0x80860002) {
1393                 do_cpuid(0x80860002, regs);
1394                 kprintf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1395                        (regs[1] >> 24) & 0xff,
1396                        (regs[1] >> 16) & 0xff,
1397                        (regs[1] >> 8) & 0xff,
1398                        regs[1] & 0xff,
1399                        regs[2]);
1400         }
1401         if (nreg >= 0x80860006) {
1402                 char info[65];
1403                 do_cpuid(0x80860003, (u_int*) &info[0]);
1404                 do_cpuid(0x80860004, (u_int*) &info[16]);
1405                 do_cpuid(0x80860005, (u_int*) &info[32]);
1406                 do_cpuid(0x80860006, (u_int*) &info[48]);
1407                 info[64] = 0;
1408                 kprintf("  %s\n", info);
1409         }
1410 }
1411
1412 static void
1413 print_via_padlock_info(void)
1414 {
1415         u_int regs[4];
1416
1417         /* Check for supported models. */
1418         switch (cpu_id & 0xff0) {
1419         case 0x690:
1420                 if ((cpu_id & 0xf) < 3)
1421                         return;
1422         case 0x6a0:
1423         case 0x6d0:
1424         case 0x6f0:
1425                 break;
1426         default:
1427                 return;
1428         }
1429
1430         do_cpuid(0xc0000000, regs);
1431         if (regs[0] >= 0xc0000001)
1432                 do_cpuid(0xc0000001, regs);
1433         else
1434                 return;
1435
1436         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
1437         "\020"
1438         "\003RNG"               /* RNG */
1439         "\007AES"               /* ACE */
1440         "\011AES-CTR"           /* ACE2 */
1441         "\013SHA1,SHA256"       /* PHE */
1442         "\015RSA"               /* PMM */
1443         );
1444 }
1445
1446 void
1447 additional_cpu_info(const char *line)
1448 {
1449         int i;
1450
1451         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1452                 additional_cpu_info_ary[i] = line;
1453                 ++additional_cpu_info_count;
1454         }
1455 }