2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
41 * Routines to handle clock hardware.
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
52 #include "opt_clock.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/eventhandler.h>
58 #include <sys/kernel.h>
63 #include <sys/sysctl.h>
65 #include <sys/systimer.h>
66 #include <sys/globaldata.h>
67 #include <sys/thread2.h>
68 #include <sys/systimer.h>
69 #include <sys/machintr.h>
71 #include <machine/clock.h>
72 #ifdef CLK_CALIBRATION_LOOP
74 #include <machine/cputypes.h>
75 #include <machine/frame.h>
76 #include <machine/ipl.h>
77 #include <machine/limits.h>
78 #include <machine/md_var.h>
79 #include <machine/psl.h>
80 #include <machine/segments.h>
81 #include <machine/smp.h>
82 #include <machine/specialreg.h>
84 #include <machine_base/icu/icu.h>
85 #include <bus/isa/isa.h>
86 #include <bus/isa/rtc.h>
87 #include <machine_base/isa/timerreg.h>
89 #include <machine_base/isa/intr_machdep.h>
91 #ifdef SMP /* APIC-IO */
92 /* The interrupt triggered by the 8254 (timer) chip */
94 static void setup_8254_mixed_mode (void);
96 static void i8254_restore(void);
97 static void resettodr_on_shutdown(void *arg __unused);
100 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
101 * can use a simple formula for leap years.
103 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
104 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
107 #define TIMER_FREQ 1193182
110 static uint8_t i8254_walltimer_sel;
111 static uint16_t i8254_walltimer_cntr;
113 int adjkerntz; /* local offset from GMT in seconds */
114 int disable_rtc_set; /* disable resettodr() if != 0 */
116 int64_t tsc_frequency;
118 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
120 enum tstate { RELEASED, ACQUIRED };
121 enum tstate timer0_state;
122 enum tstate timer1_state;
123 enum tstate timer2_state;
125 static int beeping = 0;
126 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
127 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
128 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
129 static int rtc_loaded;
131 static int i8254_cputimer_div;
133 static int i8254_nointr;
134 static int i8254_intr_disable = 0;
135 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
137 static struct callout sysbeepstop_ch;
139 static sysclock_t i8254_cputimer_count(void);
140 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
141 static void i8254_cputimer_destruct(struct cputimer *cputimer);
143 static struct cputimer i8254_cputimer = {
144 SLIST_ENTRY_INITIALIZER,
148 i8254_cputimer_count,
149 cputimer_default_fromhz,
150 cputimer_default_fromus,
151 i8254_cputimer_construct,
152 i8254_cputimer_destruct,
157 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
158 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
159 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
161 static struct cputimer_intr i8254_cputimer_intr = {
163 .reload = i8254_intr_reload,
164 .enable = cputimer_intr_default_enable,
165 .config = i8254_intr_config,
166 .restart = cputimer_intr_default_restart,
167 .pmfixup = cputimer_intr_default_pmfixup,
168 .initclock = i8254_intr_initclock,
169 .next = SLIST_ENTRY_INITIALIZER,
171 .type = CPUTIMER_INTR_8254,
172 .prio = CPUTIMER_INTR_PRIO_8254,
173 .caps = CPUTIMER_INTR_CAP_PS
177 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
178 * counting as of this interrupt. We use timer1 in free-running mode (not
179 * generating any interrupts) as our main counter. Each cpu has timeouts
182 * This code is INTR_MPSAFE and may be called without the BGL held.
185 clkintr(void *dummy, void *frame_arg)
187 static sysclock_t sysclock_count; /* NOTE! Must be static */
188 struct globaldata *gd = mycpu;
190 struct globaldata *gscan;
195 * SWSTROBE mode is a one-shot, the timer is no longer running
200 * XXX the dispatcher needs work. right now we call systimer_intr()
201 * directly or via IPI for any cpu with systimers queued, which is
202 * usually *ALL* of them. We need to use the LAPIC timer for this.
204 sysclock_count = sys_cputimer->count();
206 for (n = 0; n < ncpus; ++n) {
207 gscan = globaldata_find(n);
208 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
211 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
214 systimer_intr(&sysclock_count, 0, frame_arg);
218 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
219 systimer_intr(&sysclock_count, 0, frame_arg);
228 acquire_timer2(int mode)
230 if (timer2_state != RELEASED)
232 timer2_state = ACQUIRED;
235 * This access to the timer registers is as atomic as possible
236 * because it is a single instruction. We could do better if we
239 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
246 if (timer2_state != ACQUIRED)
248 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
249 timer2_state = RELEASED;
257 DB_SHOW_COMMAND(rtc, rtc)
259 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
260 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
261 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
262 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
267 * Return the current cpu timer count as a 32 bit integer.
271 i8254_cputimer_count(void)
273 static __uint16_t cputimer_last;
278 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
279 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
280 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
281 count = -count; /* -> countup */
282 if (count < cputimer_last) /* rollover */
283 i8254_cputimer.base += 0x00010000;
284 ret = i8254_cputimer.base | count;
285 cputimer_last = count;
291 * This function is called whenever the system timebase changes, allowing
292 * us to calculate what is needed to convert a system timebase tick
293 * into an 8254 tick for the interrupt timer. If we can convert to a
294 * simple shift, multiplication, or division, we do so. Otherwise 64
295 * bit arithmatic is required every time the interrupt timer is reloaded.
298 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
304 * Will a simple divide do the trick?
306 div = (timer->freq + (cti->freq / 2)) / cti->freq;
307 freq = cti->freq * div;
309 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
310 i8254_cputimer_div = div;
312 i8254_cputimer_div = 0;
316 * Reload for the next timeout. It is possible for the reload value
317 * to be 0 or negative, indicating that an immediate timer interrupt
318 * is desired. For now make the minimum 2 ticks.
320 * We may have to convert from the system timebase to the 8254 timebase.
323 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
327 if (i8254_cputimer_div)
328 reload /= i8254_cputimer_div;
330 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
336 if (timer0_running) {
337 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
338 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
339 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
340 if (reload < count) {
341 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
342 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
343 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
348 reload = 0; /* full count */
349 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
350 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
351 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
357 * DELAY(usec) - Spin for the specified number of microseconds.
358 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
359 * but do a thread switch in the loop
361 * Relies on timer 1 counting down from (cputimer_freq / hz)
362 * Note: timer had better have been programmed before this is first used!
365 DODELAY(int n, int doswitch)
367 int delta, prev_tick, tick, ticks_left;
372 static int state = 0;
376 for (n1 = 1; n1 <= 10000000; n1 *= 10)
381 kprintf("DELAY(%d)...", n);
384 * Guard against the timer being uninitialized if we are called
385 * early for console i/o.
387 if (timer0_state == RELEASED)
391 * Read the counter first, so that the rest of the setup overhead is
392 * counted. Then calculate the number of hardware timer ticks
393 * required, rounding up to be sure we delay at least the requested
394 * number of microseconds.
396 prev_tick = sys_cputimer->count();
397 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
403 while (ticks_left > 0) {
404 tick = sys_cputimer->count();
408 delta = tick - prev_tick;
413 if (doswitch && ticks_left > 0)
419 kprintf(" %d calls to getit() at %d usec each\n",
420 getit_calls, (n + 5) / getit_calls);
425 * DELAY() never switches
434 CHECKTIMEOUT(TOTALDELAY *tdd)
439 if (tdd->started == 0) {
440 if (timer0_state == RELEASED)
442 tdd->last_clock = sys_cputimer->count();
446 delta = sys_cputimer->count() - tdd->last_clock;
447 us = (u_int64_t)delta * (u_int64_t)1000000 /
448 (u_int64_t)sys_cputimer->freq;
449 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
452 return (tdd->us < 0);
456 * DRIVERSLEEP() does not switch if called with a spinlock held or
457 * from a hard interrupt.
460 DRIVERSLEEP(int usec)
462 globaldata_t gd = mycpu;
464 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
472 sysbeepstop(void *chan)
474 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
480 sysbeep(int pitch, int period)
482 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
484 if (sysbeep_enable == 0)
487 * Nobody else is using timer2, we do not need the clock lock
489 outb(TIMER_CNTR2, pitch);
490 outb(TIMER_CNTR2, (pitch>>8));
492 /* enable counter2 output to speaker */
493 outb(IO_PPI, inb(IO_PPI) | 3);
495 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
501 * RTC support routines
512 val = inb(IO_RTC + 1);
519 writertc(u_char reg, u_char val)
525 outb(IO_RTC + 1, val);
526 inb(0x84); /* XXX work around wrong order in rtcin() */
533 return(bcd2bin(rtcin(port)));
537 calibrate_clocks(void)
540 u_int count, prev_count, tot_count;
541 int sec, start_sec, timeout;
544 kprintf("Calibrating clock(s) ... ");
545 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
549 /* Read the mc146818A seconds counter. */
551 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
552 sec = rtcin(RTC_SEC);
559 /* Wait for the mC146818A seconds counter to change. */
562 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
563 sec = rtcin(RTC_SEC);
564 if (sec != start_sec)
571 /* Start keeping track of the i8254 counter. */
572 prev_count = sys_cputimer->count();
578 old_tsc = 0; /* shut up gcc */
581 * Wait for the mc146818A seconds counter to change. Read the i8254
582 * counter for each iteration since this is convenient and only
583 * costs a few usec of inaccuracy. The timing of the final reads
584 * of the counters almost matches the timing of the initial reads,
585 * so the main cause of inaccuracy is the varying latency from
586 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
587 * rtcin(RTC_SEC) that returns a changed seconds count. The
588 * maximum inaccuracy from this cause is < 10 usec on 486's.
592 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
593 sec = rtcin(RTC_SEC);
594 count = sys_cputimer->count();
595 tot_count += (int)(count - prev_count);
597 if (sec != start_sec)
604 * Read the cpu cycle counter. The timing considerations are
605 * similar to those for the i8254 clock.
608 tsc_frequency = rdtsc() - old_tsc;
612 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
613 kprintf("i8254 clock: %u Hz\n", tot_count);
617 kprintf("failed, using default i8254 clock of %u Hz\n",
618 i8254_cputimer.freq);
619 return (i8254_cputimer.freq);
625 timer0_state = ACQUIRED;
630 * Timer0 is our fine-grained variable clock interrupt
632 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
633 outb(TIMER_CNTR0, 2); /* lsb */
634 outb(TIMER_CNTR0, 0); /* msb */
638 cputimer_intr_register(&i8254_cputimer_intr);
639 cputimer_intr_select(&i8254_cputimer_intr, 0);
643 * Timer1 or timer2 is our free-running clock, but only if another
644 * has not been selected.
646 cputimer_register(&i8254_cputimer);
647 cputimer_select(&i8254_cputimer, 0);
651 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
656 * Should we use timer 1 or timer 2 ?
659 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
660 if (which != 1 && which != 2)
665 timer->name = "i8254_timer1";
666 timer->type = CPUTIMER_8254_SEL1;
667 i8254_walltimer_sel = TIMER_SEL1;
668 i8254_walltimer_cntr = TIMER_CNTR1;
669 timer1_state = ACQUIRED;
672 timer->name = "i8254_timer2";
673 timer->type = CPUTIMER_8254_SEL2;
674 i8254_walltimer_sel = TIMER_SEL2;
675 i8254_walltimer_cntr = TIMER_CNTR2;
676 timer2_state = ACQUIRED;
680 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
683 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
684 outb(i8254_walltimer_cntr, 0); /* lsb */
685 outb(i8254_walltimer_cntr, 0); /* msb */
686 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
691 i8254_cputimer_destruct(struct cputimer *timer)
693 switch(timer->type) {
694 case CPUTIMER_8254_SEL1:
695 timer1_state = RELEASED;
697 case CPUTIMER_8254_SEL2:
698 timer2_state = RELEASED;
709 /* Restore all of the RTC's "status" (actually, control) registers. */
710 writertc(RTC_STATUSB, RTCSB_24HR);
711 writertc(RTC_STATUSA, rtc_statusa);
712 writertc(RTC_STATUSB, rtc_statusb);
716 * Restore all the timers.
718 * This function is called to resynchronize our core timekeeping after a
719 * long halt, e.g. from apm_default_resume() and friends. It is also
720 * called if after a BIOS call we have detected munging of the 8254.
721 * It is necessary because cputimer_count() counter's delta may have grown
722 * too large for nanouptime() and friends to handle, or (in the case of 8254
723 * munging) might cause the SYSTIMER code to prematurely trigger.
729 i8254_restore(); /* restore timer_freq and hz */
730 rtc_restore(); /* reenable RTC interrupts */
735 * Initialize 8254 timer 0 early so that it can be used in DELAY().
743 * Can we use the TSC?
745 if (cpu_feature & CPUID_TSC)
751 * Initial RTC state, don't do anything unexpected
753 writertc(RTC_STATUSA, rtc_statusa);
754 writertc(RTC_STATUSB, RTCSB_24HR);
757 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
758 * generate an interrupt, which we will ignore for now.
760 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
761 * (so it counts a full 2^16 and repeats). We will use this timer
765 freq = calibrate_clocks();
766 #ifdef CLK_CALIBRATION_LOOP
769 "Press a key on the console to abort clock calibration\n");
770 while (cncheckc() == -1)
776 * Use the calibrated i8254 frequency if it seems reasonable.
777 * Otherwise use the default, and don't use the calibrated i586
780 delta = freq > i8254_cputimer.freq ?
781 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
782 if (delta < i8254_cputimer.freq / 100) {
783 #ifndef CLK_USE_I8254_CALIBRATION
786 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
787 freq = i8254_cputimer.freq;
791 * Interrupt timer's freq must be adjusted
792 * before we change the cuptimer's frequency.
794 i8254_cputimer_intr.freq = freq;
795 cputimer_set_frequency(&i8254_cputimer, freq);
799 "%d Hz differs from default of %d Hz by more than 1%%\n",
800 freq, i8254_cputimer.freq);
804 #ifndef CLK_USE_TSC_CALIBRATION
805 if (tsc_frequency != 0) {
808 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
812 if (tsc_present && tsc_frequency == 0) {
814 * Calibration of the i586 clock relative to the mc146818A
815 * clock failed. Do a less accurate calibration relative
816 * to the i8254 clock.
818 u_int64_t old_tsc = rdtsc();
821 tsc_frequency = rdtsc() - old_tsc;
822 #ifdef CLK_USE_TSC_CALIBRATION
824 kprintf("TSC clock: %llu Hz (Method B)\n",
830 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
834 * We can not use the TSC in SMP mode, until we figure out a
835 * cheap (impossible), reliable and precise (yeah right!) way
836 * to synchronize the TSCs of all the CPUs.
837 * Curse Intel for leaving the counter out of the I/O APIC.
842 * We can not use the TSC if we support APM. Precise timekeeping
843 * on an APM'ed machine is at best a fools pursuit, since
844 * any and all of the time spent in various SMM code can't
845 * be reliably accounted for. Reading the RTC is your only
846 * source of reliable time info. The i8254 looses too of course
847 * but we need to have some kind of time...
848 * We don't know at this point whether APM is going to be used
849 * or not, nor when it might be activated. Play it safe.
852 #endif /* NAPM > 0 */
854 #endif /* !defined(SMP) */
858 * Sync the time of day back to the RTC on shutdown, but only if
859 * we have already loaded it and have not crashed.
862 resettodr_on_shutdown(void *arg __unused)
864 if (rtc_loaded && panicstr == NULL) {
870 * Initialize the time of day register, based on the time base which is, e.g.
874 inittodr(time_t base)
876 unsigned long sec, days;
887 /* Look if we have a RTC present and the time is valid */
888 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
891 /* wait for time update to complete */
892 /* If RTCSA_TUP is zero, we have at least 244us before next update */
894 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
900 #ifdef USE_RTC_CENTURY
901 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
903 year = readrtc(RTC_YEAR) + 1900;
911 month = readrtc(RTC_MONTH);
912 for (m = 1; m < month; m++)
913 days += daysinmonth[m-1];
914 if ((month > 2) && LEAPYEAR(year))
916 days += readrtc(RTC_DAY) - 1;
917 for (y = 1970; y < year; y++)
918 days += DAYSPERYEAR + LEAPYEAR(y);
919 sec = ((( days * 24 +
920 readrtc(RTC_HRS)) * 60 +
921 readrtc(RTC_MIN)) * 60 +
923 /* sec now contains the number of seconds, since Jan 1 1970,
924 in the local time zone */
926 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
928 y = time_second - sec;
929 if (y <= -2 || y >= 2) {
930 /* badly off, adjust it */
940 kprintf("Invalid time in real time clock.\n");
941 kprintf("Check and reset the date immediately!\n");
945 * Write system time back to RTC
962 /* Disable RTC updates and interrupts. */
963 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
965 /* Calculate local time to put in RTC */
967 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
969 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
970 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
971 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
973 /* We have now the days since 01-01-1970 in tm */
974 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
975 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
977 y++, m = DAYSPERYEAR + LEAPYEAR(y))
980 /* Now we have the years in y and the day-of-the-year in tm */
981 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
982 #ifdef USE_RTC_CENTURY
983 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
989 if (m == 1 && LEAPYEAR(y))
996 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
997 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
999 /* Reenable RTC updates and interrupts. */
1000 writertc(RTC_STATUSB, rtc_statusb);
1006 * Start both clocks running. DragonFly note: the stat clock is no longer
1007 * used. Instead, 8254 based systimers are used for all major clock
1011 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1013 #ifdef SMP /* APIC-IO */
1014 int apic_8254_trial = 0;
1015 void *clkdesc = NULL;
1018 callout_init(&sysbeepstop_ch);
1020 if (!selected && i8254_intr_disable) {
1021 i8254_nointr = 1; /* don't try to register again */
1022 cputimer_intr_deregister(cti);
1027 * The stat interrupt mask is different without the
1028 * statistics clock. Also, don't set the interrupt
1029 * flag which would normally cause the RTC to generate
1032 rtc_statusb = RTCSB_24HR;
1034 /* Finish initializing 8253 timer 0. */
1035 #ifdef SMP /* APIC-IO */
1036 if (apic_io_enable) {
1037 apic_8254_intr = isa_apic_irq(0);
1038 if (apic_8254_intr >= 0 ) {
1039 if (apic_int_type(0, 0) == 3)
1040 apic_8254_trial = 1;
1042 /* look for ExtInt on pin 0 */
1043 if (apic_int_type(0, 0) == 3) {
1044 apic_8254_intr = apic_irq(0, 0);
1045 setup_8254_mixed_mode();
1047 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1050 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1052 INTR_EXCL | INTR_CLOCK |
1053 INTR_NOPOLL | INTR_MPSAFE |
1055 machintr_intren(apic_8254_intr);
1058 register_int(0, clkintr, NULL, "clk", NULL,
1059 INTR_EXCL | INTR_CLOCK |
1060 INTR_NOPOLL | INTR_MPSAFE |
1062 machintr_intren(ICU_IRQ0);
1063 #ifdef SMP /* APIC-IO */
1067 /* Initialize RTC. */
1068 writertc(RTC_STATUSA, rtc_statusa);
1069 writertc(RTC_STATUSB, RTCSB_24HR);
1071 #ifdef SMP /* APIC-IO */
1072 if (apic_io_enable) {
1073 if (apic_8254_trial) {
1078 * Following code assumes the 8254 is the cpu timer,
1079 * so make sure it is.
1081 KKASSERT(sys_cputimer == &i8254_cputimer);
1082 KKASSERT(cti == &i8254_cputimer_intr);
1084 lastcnt = get_interrupt_counter(apic_8254_intr);
1087 * Force an 8254 Timer0 interrupt and wait 1/100s for
1088 * it to happen, then see if we got it.
1090 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1091 i8254_intr_reload(cti, 2);
1092 base = sys_cputimer->count();
1093 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1095 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1097 * The MP table is broken.
1098 * The 8254 was not connected to the specified pin
1100 * Workaround: Limited variant of mixed mode.
1102 machintr_intrdis(apic_8254_intr);
1103 unregister_int(clkdesc);
1104 kprintf("APIC_IO: Broken MP table detected: "
1105 "8254 is not connected to "
1106 "IOAPIC #%d intpin %d\n",
1107 int_to_apicintpin[apic_8254_intr].ioapic,
1108 int_to_apicintpin[apic_8254_intr].int_pin);
1110 * Revoke current ISA IRQ 0 assignment and
1111 * configure a fallback interrupt routing from
1112 * the 8254 Timer via the 8259 PIC to the
1113 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1114 * We reuse the low level interrupt handler number.
1116 if (apic_irq(0, 0) < 0) {
1117 revoke_apic_irq(apic_8254_intr);
1118 assign_apic_irq(0, 0, apic_8254_intr);
1120 apic_8254_intr = apic_irq(0, 0);
1121 setup_8254_mixed_mode();
1122 register_int(apic_8254_intr, clkintr, NULL, "clk",
1124 INTR_EXCL | INTR_CLOCK |
1125 INTR_NOPOLL | INTR_MPSAFE |
1127 machintr_intren(apic_8254_intr);
1130 if (apic_int_type(0, 0) != 3 ||
1131 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1132 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1133 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1134 int_to_apicintpin[apic_8254_intr].ioapic,
1135 int_to_apicintpin[apic_8254_intr].int_pin);
1138 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1144 #ifdef SMP /* APIC-IO */
1147 setup_8254_mixed_mode(void)
1150 * Allow 8254 timer to INTerrupt 8259:
1151 * re-initialize master 8259:
1152 * reset; prog 4 bytes, single ICU, edge triggered
1154 outb(IO_ICU1, 0x13);
1155 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1156 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1157 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1158 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1160 /* program IO APIC for type 3 INT on INT0 */
1161 if (ext_int_setup(0, 0) < 0)
1162 panic("8254 redirect via APIC pin0 impossible!");
1167 setstatclockrate(int newhz)
1169 if (newhz == RTC_PROFRATE)
1170 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1172 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1173 writertc(RTC_STATUSA, rtc_statusa);
1178 tsc_get_timecount(struct timecounter *tc)
1184 #ifdef KERN_TIMESTAMP
1185 #define KERN_TIMESTAMP_SIZE 16384
1186 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1187 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1188 sizeof(tsc), "LU", "Kernel timestamps");
1194 tsc[i] = (u_int32_t)rdtsc();
1197 if (i >= KERN_TIMESTAMP_SIZE)
1199 tsc[i] = 0; /* mark last entry */
1201 #endif /* KERN_TIMESTAMP */
1208 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1215 if (sys_cputimer == &i8254_cputimer)
1216 count = sys_cputimer->count();
1224 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1225 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1228 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1229 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1231 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1232 0, 0, hw_i8254_timestamp, "A", "");
1234 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1235 &tsc_present, 0, "TSC Available");
1236 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1237 &tsc_frequency, 0, "TSC Frequency");