1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
4 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
6 * This code is derived from software contributed to The DragonFly Project
7 * by Sepherosa Ziehau <sepherosa@gmail.com> and
8 * Matthew Dillon <dillon@apollo.backplane.com>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in
18 * the documentation and/or other materials provided with the
20 * 3. Neither the name of The DragonFly Project nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific, prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
40 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
42 * Permission to use, copy, modify, and distribute this software for any
43 * purpose with or without fee is hereby granted, provided that the above
44 * copyright notice and this permission notice appear in all copies.
46 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
47 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
48 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
49 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
50 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
51 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
52 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
55 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
57 #include "opt_polling.h"
59 #include <sys/param.h>
60 #include <sys/endian.h>
61 #include <sys/kernel.h>
63 #include <sys/interrupt.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
71 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/ifq_var.h>
78 #include <net/if_types.h>
79 #include <net/if_var.h>
80 #include <net/vlan/if_vlan_var.h>
81 #include <net/vlan/if_vlan_ether.h>
83 #include <bus/pci/pcireg.h>
84 #include <bus/pci/pcivar.h>
85 #include <bus/pci/pcidevs.h>
87 #include <dev/netif/mii_layer/mii.h>
88 #include <dev/netif/mii_layer/miivar.h>
90 #include "miibus_if.h"
92 #include <dev/netif/nfe/if_nfereg.h>
93 #include <dev/netif/nfe/if_nfevar.h>
96 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
98 static int nfe_probe(device_t);
99 static int nfe_attach(device_t);
100 static int nfe_detach(device_t);
101 static void nfe_shutdown(device_t);
102 static int nfe_resume(device_t);
103 static int nfe_suspend(device_t);
105 static int nfe_miibus_readreg(device_t, int, int);
106 static void nfe_miibus_writereg(device_t, int, int, int);
107 static void nfe_miibus_statchg(device_t);
109 #ifdef DEVICE_POLLING
110 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
111 static void nfe_disable_intrs(struct nfe_softc *);
113 static void nfe_intr(void *);
114 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
115 static int nfe_rxeof(struct nfe_softc *);
116 static int nfe_txeof(struct nfe_softc *, int);
117 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 static void nfe_start(struct ifnet *);
120 static void nfe_watchdog(struct ifnet *);
121 static void nfe_init(void *);
122 static void nfe_stop(struct nfe_softc *);
123 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
124 static void nfe_jfree(void *);
125 static void nfe_jref(void *);
126 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
127 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
128 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
129 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
133 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static int nfe_ifmedia_upd(struct ifnet *);
137 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
138 static void nfe_setmulti(struct nfe_softc *);
139 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
140 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
141 static void nfe_powerup(device_t);
142 static void nfe_mac_reset(struct nfe_softc *);
143 static void nfe_tick(void *);
144 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
146 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
148 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
150 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
152 static void nfe_enable_intrs(struct nfe_softc *);
154 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
159 static int nfe_debug = 0;
160 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
161 static int nfe_tx_ring_count = NFE_TX_RING_DEF_COUNT;
163 * hw timer simulated interrupt moderation @4000Hz. Negative values
164 * disable the timer when the discrete interrupt rate falls below
165 * the moderation rate.
167 * XXX 8000Hz might be better but if the interrupt is shared it can
170 static int nfe_imtime = -250; /* uS */
172 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
173 TUNABLE_INT("hw.nfe.tx_ring_count", &nfe_tx_ring_count);
174 TUNABLE_INT("hw.nfe.imtimer", &nfe_imtime);
175 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
177 #define DPRINTF(sc, fmt, ...) do { \
178 if ((sc)->sc_debug) { \
179 if_printf(&(sc)->arpcom.ac_if, \
184 #define DPRINTFN(sc, lv, fmt, ...) do { \
185 if ((sc)->sc_debug >= (lv)) { \
186 if_printf(&(sc)->arpcom.ac_if, \
191 #else /* !NFE_DEBUG */
193 #define DPRINTF(sc, fmt, ...)
194 #define DPRINTFN(sc, lv, fmt, ...)
196 #endif /* NFE_DEBUG */
198 static const struct nfe_dev {
203 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
204 "NVIDIA nForce Fast Ethernet" },
206 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
207 "NVIDIA nForce2 Fast Ethernet" },
209 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
210 "NVIDIA nForce3 Gigabit Ethernet" },
212 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
213 chipset, and possibly also the 400R; it might be both nForce2- and
214 nForce3-based boards can use the same MCPs (= southbridges) */
215 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
216 "NVIDIA nForce3 Gigabit Ethernet" },
218 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
219 "NVIDIA nForce3 Gigabit Ethernet" },
221 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
222 "NVIDIA nForce3 Gigabit Ethernet" },
224 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
225 "NVIDIA nForce3 Gigabit Ethernet" },
227 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
228 "NVIDIA CK804 Gigabit Ethernet" },
230 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
231 "NVIDIA CK804 Gigabit Ethernet" },
233 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
234 "NVIDIA MCP04 Gigabit Ethernet" },
236 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
237 "NVIDIA MCP04 Gigabit Ethernet" },
239 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
240 "NVIDIA MCP51 Gigabit Ethernet" },
242 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
243 "NVIDIA MCP51 Gigabit Ethernet" },
245 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
246 "NVIDIA MCP55 Gigabit Ethernet" },
248 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
249 "NVIDIA MCP55 Gigabit Ethernet" },
251 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
252 "NVIDIA MCP61 Gigabit Ethernet" },
254 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
255 "NVIDIA MCP61 Gigabit Ethernet" },
257 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
258 "NVIDIA MCP61 Gigabit Ethernet" },
260 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
261 "NVIDIA MCP61 Gigabit Ethernet" },
263 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
264 "NVIDIA MCP65 Gigabit Ethernet" },
266 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
267 "NVIDIA MCP65 Gigabit Ethernet" },
269 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
270 "NVIDIA MCP65 Gigabit Ethernet" },
272 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
273 "NVIDIA MCP65 Gigabit Ethernet" },
275 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
276 "NVIDIA MCP67 Gigabit Ethernet" },
278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
279 "NVIDIA MCP67 Gigabit Ethernet" },
281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
282 "NVIDIA MCP67 Gigabit Ethernet" },
284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
285 "NVIDIA MCP67 Gigabit Ethernet" },
287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
288 "NVIDIA MCP73 Gigabit Ethernet" },
290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
291 "NVIDIA MCP73 Gigabit Ethernet" },
293 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
294 "NVIDIA MCP73 Gigabit Ethernet" },
296 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
297 "NVIDIA MCP73 Gigabit Ethernet" },
299 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
300 "NVIDIA MCP77 Gigabit Ethernet" },
302 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
303 "NVIDIA MCP77 Gigabit Ethernet" },
305 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
306 "NVIDIA MCP77 Gigabit Ethernet" },
308 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
309 "NVIDIA MCP77 Gigabit Ethernet" },
311 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
312 "NVIDIA MCP79 Gigabit Ethernet" },
314 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
315 "NVIDIA MCP79 Gigabit Ethernet" },
317 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
318 "NVIDIA MCP79 Gigabit Ethernet" },
320 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
321 "NVIDIA MCP79 Gigabit Ethernet" },
326 static device_method_t nfe_methods[] = {
327 /* Device interface */
328 DEVMETHOD(device_probe, nfe_probe),
329 DEVMETHOD(device_attach, nfe_attach),
330 DEVMETHOD(device_detach, nfe_detach),
331 DEVMETHOD(device_suspend, nfe_suspend),
332 DEVMETHOD(device_resume, nfe_resume),
333 DEVMETHOD(device_shutdown, nfe_shutdown),
336 DEVMETHOD(bus_print_child, bus_generic_print_child),
337 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
340 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
341 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
342 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
347 static driver_t nfe_driver = {
350 sizeof(struct nfe_softc)
353 static devclass_t nfe_devclass;
355 DECLARE_DUMMY_MODULE(if_nfe);
356 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
357 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, NULL, NULL);
358 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, NULL, NULL);
361 * NOTE: NFE_WORDALIGN support is guesswork right now.
364 nfe_probe(device_t dev)
366 const struct nfe_dev *n;
369 vid = pci_get_vendor(dev);
370 did = pci_get_device(dev);
371 for (n = nfe_devices; n->desc != NULL; ++n) {
372 if (vid == n->vid && did == n->did) {
373 struct nfe_softc *sc = device_get_softc(dev);
376 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
377 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
378 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
379 sc->sc_caps = NFE_NO_PWRCTL |
382 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
383 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
384 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
385 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
386 sc->sc_caps = NFE_JUMBO_SUP |
391 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
392 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
393 sc->sc_caps = NFE_FIX_EADDR;
395 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
396 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
397 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
398 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
399 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
400 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
401 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
402 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
403 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
404 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
405 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
406 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
407 sc->sc_caps |= NFE_40BIT_ADDR;
409 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
410 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
411 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
412 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
413 sc->sc_caps = NFE_JUMBO_SUP |
419 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
420 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
421 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
422 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
423 sc->sc_caps = NFE_JUMBO_SUP |
426 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
427 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
428 sc->sc_caps = NFE_JUMBO_SUP |
434 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
435 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
436 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
437 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
438 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
439 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
440 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
441 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
442 sc->sc_caps = NFE_40BIT_ADDR |
448 device_set_desc(dev, n->desc);
449 device_set_async_attach(dev, TRUE);
457 nfe_attach(device_t dev)
459 struct nfe_softc *sc = device_get_softc(dev);
460 struct ifnet *ifp = &sc->arpcom.ac_if;
461 uint8_t eaddr[ETHER_ADDR_LEN];
465 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
466 lwkt_serialize_init(&sc->sc_jbuf_serializer);
469 * Initialize sysctl variables
471 sc->sc_rx_ring_count = nfe_rx_ring_count;
472 sc->sc_tx_ring_count = nfe_tx_ring_count;
473 sc->sc_debug = nfe_debug;
474 if (nfe_imtime < 0) {
475 sc->sc_flags |= NFE_F_DYN_IM;
476 sc->sc_imtime = -nfe_imtime;
478 sc->sc_imtime = nfe_imtime;
480 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
482 sc->sc_mem_rid = PCIR_BAR(0);
484 if (sc->sc_caps & NFE_40BIT_ADDR)
485 sc->rxtxctl_desc = NFE_RXTX_DESC_V3;
486 else if (sc->sc_caps & NFE_JUMBO_SUP)
487 sc->rxtxctl_desc = NFE_RXTX_DESC_V2;
490 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
493 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
494 irq = pci_read_config(dev, PCIR_INTLINE, 4);
496 device_printf(dev, "chip is in D%d power mode "
497 "-- setting to D0\n", pci_get_powerstate(dev));
499 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
501 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
502 pci_write_config(dev, PCIR_INTLINE, irq, 4);
504 #endif /* !BURN_BRIDGE */
506 /* Enable bus mastering */
507 pci_enable_busmaster(dev);
509 /* Allocate IO memory */
510 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
511 &sc->sc_mem_rid, RF_ACTIVE);
512 if (sc->sc_mem_res == NULL) {
513 device_printf(dev, "could not allocate io memory\n");
516 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
517 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
521 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
523 RF_SHAREABLE | RF_ACTIVE);
524 if (sc->sc_irq_res == NULL) {
525 device_printf(dev, "could not allocate irq\n");
531 NFE_WRITE(sc, NFE_WOL_CTL, 0);
533 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
536 nfe_get_macaddr(sc, eaddr);
539 * Allocate top level DMA tag
541 if (sc->sc_caps & NFE_40BIT_ADDR)
542 lowaddr = NFE_BUS_SPACE_MAXADDR;
544 lowaddr = BUS_SPACE_MAXADDR_32BIT;
545 error = bus_dma_tag_create(NULL, /* parent */
546 1, 0, /* alignment, boundary */
547 lowaddr, /* lowaddr */
548 BUS_SPACE_MAXADDR, /* highaddr */
549 NULL, NULL, /* filter, filterarg */
550 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
552 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
556 device_printf(dev, "could not allocate parent dma tag\n");
561 * Allocate Tx and Rx rings.
563 error = nfe_alloc_tx_ring(sc, &sc->txq);
565 device_printf(dev, "could not allocate Tx ring\n");
569 error = nfe_alloc_rx_ring(sc, &sc->rxq);
571 device_printf(dev, "could not allocate Rx ring\n");
578 sysctl_ctx_init(&sc->sc_sysctl_ctx);
579 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
580 SYSCTL_STATIC_CHILDREN(_hw),
582 device_get_nameunit(dev),
584 if (sc->sc_sysctl_tree == NULL) {
585 device_printf(dev, "can't add sysctl node\n");
589 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
590 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
591 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
592 sc, 0, nfe_sysctl_imtime, "I",
593 "Interrupt moderation time (usec). "
594 "0 to disable interrupt moderation.");
595 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
596 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
597 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
599 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
600 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
601 "tx_ring_count", CTLFLAG_RD, &sc->sc_tx_ring_count,
603 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
604 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
605 "debug", CTLFLAG_RW, &sc->sc_debug,
606 0, "control debugging printfs");
608 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
611 device_printf(dev, "MII without any phy\n");
616 ifp->if_mtu = ETHERMTU;
617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
618 ifp->if_ioctl = nfe_ioctl;
619 ifp->if_start = nfe_start;
620 #ifdef DEVICE_POLLING
621 ifp->if_poll = nfe_poll;
623 ifp->if_watchdog = nfe_watchdog;
624 ifp->if_init = nfe_init;
625 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_count);
626 ifq_set_ready(&ifp->if_snd);
628 ifp->if_capabilities = IFCAP_VLAN_MTU;
630 if (sc->sc_caps & NFE_HW_VLAN)
631 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
634 if (sc->sc_caps & NFE_HW_CSUM) {
635 ifp->if_capabilities |= IFCAP_HWCSUM;
636 ifp->if_hwassist = NFE_CSUM_FEATURES;
639 sc->sc_caps &= ~NFE_HW_CSUM;
641 ifp->if_capenable = ifp->if_capabilities;
643 callout_init(&sc->sc_tick_ch);
645 ether_ifattach(ifp, eaddr, NULL);
647 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
648 &sc->sc_ih, ifp->if_serializer);
650 device_printf(dev, "could not setup intr\n");
655 ifp->if_cpuid = rman_get_cpuid(sc->sc_irq_res);
656 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
665 nfe_detach(device_t dev)
667 struct nfe_softc *sc = device_get_softc(dev);
669 if (device_is_attached(dev)) {
670 struct ifnet *ifp = &sc->arpcom.ac_if;
672 lwkt_serialize_enter(ifp->if_serializer);
674 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
675 lwkt_serialize_exit(ifp->if_serializer);
680 if (sc->sc_miibus != NULL)
681 device_delete_child(dev, sc->sc_miibus);
682 bus_generic_detach(dev);
684 if (sc->sc_sysctl_tree != NULL)
685 sysctl_ctx_free(&sc->sc_sysctl_ctx);
687 if (sc->sc_irq_res != NULL) {
688 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
692 if (sc->sc_mem_res != NULL) {
693 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
697 nfe_free_tx_ring(sc, &sc->txq);
698 nfe_free_rx_ring(sc, &sc->rxq);
699 if (sc->sc_dtag != NULL)
700 bus_dma_tag_destroy(sc->sc_dtag);
706 nfe_shutdown(device_t dev)
708 struct nfe_softc *sc = device_get_softc(dev);
709 struct ifnet *ifp = &sc->arpcom.ac_if;
711 lwkt_serialize_enter(ifp->if_serializer);
713 lwkt_serialize_exit(ifp->if_serializer);
717 nfe_suspend(device_t dev)
719 struct nfe_softc *sc = device_get_softc(dev);
720 struct ifnet *ifp = &sc->arpcom.ac_if;
722 lwkt_serialize_enter(ifp->if_serializer);
724 lwkt_serialize_exit(ifp->if_serializer);
730 nfe_resume(device_t dev)
732 struct nfe_softc *sc = device_get_softc(dev);
733 struct ifnet *ifp = &sc->arpcom.ac_if;
735 lwkt_serialize_enter(ifp->if_serializer);
736 if (ifp->if_flags & IFF_UP)
738 lwkt_serialize_exit(ifp->if_serializer);
744 nfe_miibus_statchg(device_t dev)
746 struct nfe_softc *sc = device_get_softc(dev);
747 struct mii_data *mii = device_get_softc(sc->sc_miibus);
748 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
750 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
752 phy = NFE_READ(sc, NFE_PHY_IFACE);
753 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
755 seed = NFE_READ(sc, NFE_RNDSEED);
756 seed &= ~NFE_SEED_MASK;
758 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
759 phy |= NFE_PHY_HDX; /* half-duplex */
760 misc |= NFE_MISC1_HDX;
763 switch (IFM_SUBTYPE(mii->mii_media_active)) {
764 case IFM_1000_T: /* full-duplex only */
765 link |= NFE_MEDIA_1000T;
766 seed |= NFE_SEED_1000T;
767 phy |= NFE_PHY_1000T;
770 link |= NFE_MEDIA_100TX;
771 seed |= NFE_SEED_100TX;
772 phy |= NFE_PHY_100TX;
775 link |= NFE_MEDIA_10T;
776 seed |= NFE_SEED_10T;
780 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
782 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
783 NFE_WRITE(sc, NFE_MISC1, misc);
784 NFE_WRITE(sc, NFE_LINKSPEED, link);
788 nfe_miibus_readreg(device_t dev, int phy, int reg)
790 struct nfe_softc *sc = device_get_softc(dev);
794 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
796 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
797 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
801 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
803 for (ntries = 0; ntries < 1000; ntries++) {
805 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
808 if (ntries == 1000) {
809 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
813 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
814 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
818 val = NFE_READ(sc, NFE_PHY_DATA);
819 if (val != 0xffffffff && val != 0)
820 sc->mii_phyaddr = phy;
822 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
828 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
830 struct nfe_softc *sc = device_get_softc(dev);
834 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
836 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
837 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
841 NFE_WRITE(sc, NFE_PHY_DATA, val);
842 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
843 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
845 for (ntries = 0; ntries < 1000; ntries++) {
847 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
853 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
857 #ifdef DEVICE_POLLING
860 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
862 struct nfe_softc *sc = ifp->if_softc;
864 ASSERT_SERIALIZED(ifp->if_serializer);
868 nfe_disable_intrs(sc);
871 case POLL_DEREGISTER:
872 nfe_enable_intrs(sc);
875 case POLL_AND_CHECK_STATUS:
878 if (ifp->if_flags & IFF_RUNNING) {
891 struct nfe_softc *sc = arg;
892 struct ifnet *ifp = &sc->arpcom.ac_if;
895 r = NFE_READ(sc, NFE_IRQ_STATUS);
897 return; /* not for us */
898 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
900 if (sc->sc_rate_second != time_second) {
902 * Calculate sc_rate_avg - interrupts per second.
904 sc->sc_rate_second = time_second;
905 if (sc->sc_rate_avg < sc->sc_rate_acc)
906 sc->sc_rate_avg = sc->sc_rate_acc;
908 sc->sc_rate_avg = (sc->sc_rate_avg * 3 +
909 sc->sc_rate_acc) / 4;
911 } else if (sc->sc_rate_avg < sc->sc_rate_acc) {
913 * Don't wait for a tick to roll over if we are taking
914 * a lot of interrupts.
916 sc->sc_rate_avg = sc->sc_rate_acc;
919 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
921 if (r & NFE_IRQ_LINK) {
922 NFE_READ(sc, NFE_PHY_STATUS);
923 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
924 DPRINTF(sc, "link state changed %s\n", "");
927 if (ifp->if_flags & IFF_RUNNING) {
935 ret |= nfe_txeof(sc, 1);
937 /* update the rate accumulator */
941 if (sc->sc_flags & NFE_F_DYN_IM) {
942 rate = 1000000 / sc->sc_imtime;
943 if ((sc->sc_flags & NFE_F_IRQ_TIMER) == 0 &&
944 sc->sc_rate_avg > rate) {
946 * Use the hardware timer to reduce the
947 * interrupt rate if the discrete interrupt
948 * rate has exceeded our threshold.
950 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_IMTIMER);
951 sc->sc_flags |= NFE_F_IRQ_TIMER;
952 } else if ((sc->sc_flags & NFE_F_IRQ_TIMER) &&
953 sc->sc_rate_avg <= rate) {
955 * Use discrete TX/RX interrupts if the rate
956 * has fallen below our threshold.
958 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_NOIMTIMER);
959 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
962 * Recollect, mainly to avoid the possible race
963 * introduced by changing interrupt masks.
973 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
975 struct nfe_softc *sc = ifp->if_softc;
976 struct ifreq *ifr = (struct ifreq *)data;
977 struct mii_data *mii;
978 int error = 0, mask, jumbo_cap;
980 ASSERT_SERIALIZED(ifp->if_serializer);
984 if ((sc->sc_caps & NFE_JUMBO_SUP) && sc->rxq.jbuf != NULL)
989 if ((jumbo_cap && ifr->ifr_mtu > NFE_JUMBO_MTU) ||
990 (!jumbo_cap && ifr->ifr_mtu > ETHERMTU)) {
992 } else if (ifp->if_mtu != ifr->ifr_mtu) {
993 ifp->if_mtu = ifr->ifr_mtu;
994 if (ifp->if_flags & IFF_RUNNING)
999 if (ifp->if_flags & IFF_UP) {
1001 * If only the PROMISC or ALLMULTI flag changes, then
1002 * don't do a full re-init of the chip, just update
1005 if ((ifp->if_flags & IFF_RUNNING) &&
1006 ((ifp->if_flags ^ sc->sc_if_flags) &
1007 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
1010 if (!(ifp->if_flags & IFF_RUNNING))
1014 if (ifp->if_flags & IFF_RUNNING)
1017 sc->sc_if_flags = ifp->if_flags;
1021 if (ifp->if_flags & IFF_RUNNING)
1026 mii = device_get_softc(sc->sc_miibus);
1027 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1030 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
1031 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
1032 ifp->if_capenable ^= mask;
1033 if (IFCAP_TXCSUM & ifp->if_capenable)
1034 ifp->if_hwassist = NFE_CSUM_FEATURES;
1036 ifp->if_hwassist = 0;
1038 if (ifp->if_flags & IFF_RUNNING)
1043 error = ether_ioctl(ifp, cmd, data);
1050 nfe_rxeof(struct nfe_softc *sc)
1052 struct ifnet *ifp = &sc->arpcom.ac_if;
1053 struct nfe_rx_ring *ring = &sc->rxq;
1058 struct nfe_rx_data *data = &ring->data[ring->cur];
1063 if (sc->sc_caps & NFE_40BIT_ADDR) {
1064 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
1066 flags = le16toh(desc64->flags);
1067 len = le16toh(desc64->length) & 0x3fff;
1069 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
1071 flags = le16toh(desc32->flags);
1072 len = le16toh(desc32->length) & 0x3fff;
1075 if (flags & NFE_RX_READY)
1080 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1081 if (!(flags & NFE_RX_VALID_V1))
1084 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
1085 flags &= ~NFE_RX_ERROR;
1086 len--; /* fix buffer length */
1089 if (!(flags & NFE_RX_VALID_V2))
1092 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
1093 flags &= ~NFE_RX_ERROR;
1094 len--; /* fix buffer length */
1098 if (flags & NFE_RX_ERROR) {
1105 if (sc->sc_flags & NFE_F_USE_JUMBO)
1106 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
1108 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
1115 m->m_pkthdr.len = m->m_len = len;
1116 m->m_pkthdr.rcvif = ifp;
1118 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1119 (flags & NFE_RX_CSUMOK)) {
1120 if (flags & NFE_RX_IP_CSUMOK_V2) {
1121 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1126 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1127 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1129 CSUM_FRAG_NOT_CHECKED;
1130 m->m_pkthdr.csum_data = 0xffff;
1135 ifp->if_input(ifp, m);
1137 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1138 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1144 nfe_txeof(struct nfe_softc *sc, int start)
1146 struct ifnet *ifp = &sc->arpcom.ac_if;
1147 struct nfe_tx_ring *ring = &sc->txq;
1148 struct nfe_tx_data *data = NULL;
1150 while (ring->next != ring->cur) {
1153 if (sc->sc_caps & NFE_40BIT_ADDR)
1154 flags = le16toh(ring->desc64[ring->next].flags);
1156 flags = le16toh(ring->desc32[ring->next].flags);
1158 if (flags & NFE_TX_VALID)
1161 data = &ring->data[ring->next];
1163 if ((sc->sc_caps & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1164 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1167 if ((flags & NFE_TX_ERROR_V1) != 0) {
1168 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1175 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1178 if ((flags & NFE_TX_ERROR_V2) != 0) {
1179 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1187 if (data->m == NULL) { /* should not get there */
1189 "last fragment bit w/o associated mbuf!\n");
1193 /* last fragment of the mbuf chain transmitted */
1194 bus_dmamap_unload(ring->data_tag, data->map);
1199 KKASSERT(ring->queued >= 0);
1200 ring->next = (ring->next + 1) % sc->sc_tx_ring_count;
1203 if (sc->sc_tx_ring_count - ring->queued >=
1204 sc->sc_tx_spare + NFE_NSEG_RSVD)
1205 ifp->if_flags &= ~IFF_OACTIVE;
1207 if (ring->queued == 0)
1210 if (start && !ifq_is_empty(&ifp->if_snd))
1220 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1222 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1223 struct nfe_tx_data *data, *data_map;
1225 struct nfe_desc64 *desc64 = NULL;
1226 struct nfe_desc32 *desc32 = NULL;
1229 int error, i, j, maxsegs, nsegs;
1231 data = &ring->data[ring->cur];
1233 data_map = data; /* Remember who owns the DMA map */
1235 maxsegs = (sc->sc_tx_ring_count - ring->queued) - NFE_NSEG_RSVD;
1236 if (maxsegs > NFE_MAX_SCATTER)
1237 maxsegs = NFE_MAX_SCATTER;
1238 KASSERT(maxsegs >= sc->sc_tx_spare,
1239 ("not enough segments %d,%d", maxsegs, sc->sc_tx_spare));
1241 error = bus_dmamap_load_mbuf_defrag(ring->data_tag, map, &m0,
1242 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1245 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1249 /* setup h/w VLAN tagging */
1250 if (m0->m_flags & M_VLANTAG)
1251 vtag = m0->m_pkthdr.ether_vlantag;
1253 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1254 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1255 flags |= NFE_TX_IP_CSUM;
1256 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1257 flags |= NFE_TX_TCP_CSUM;
1261 * XXX urm. somebody is unaware of how hardware works. You
1262 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1263 * the ring until the entire chain is actually *VALID*. Otherwise
1264 * the hardware may encounter a partially initialized chain that
1265 * is marked as being ready to go when it in fact is not ready to
1269 for (i = 0; i < nsegs; i++) {
1270 j = (ring->cur + i) % sc->sc_tx_ring_count;
1271 data = &ring->data[j];
1273 if (sc->sc_caps & NFE_40BIT_ADDR) {
1274 desc64 = &ring->desc64[j];
1275 desc64->physaddr[0] =
1276 htole32(NFE_ADDR_HI(segs[i].ds_addr));
1277 desc64->physaddr[1] =
1278 htole32(NFE_ADDR_LO(segs[i].ds_addr));
1279 desc64->length = htole16(segs[i].ds_len - 1);
1280 desc64->vtag = htole32(vtag);
1281 desc64->flags = htole16(flags);
1283 desc32 = &ring->desc32[j];
1284 desc32->physaddr = htole32(segs[i].ds_addr);
1285 desc32->length = htole16(segs[i].ds_len - 1);
1286 desc32->flags = htole16(flags);
1289 /* csum flags and vtag belong to the first fragment only */
1290 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1294 KKASSERT(ring->queued <= sc->sc_tx_ring_count);
1297 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1298 if (sc->sc_caps & NFE_40BIT_ADDR) {
1299 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1301 if (sc->sc_caps & NFE_JUMBO_SUP)
1302 flags = NFE_TX_LASTFRAG_V2;
1304 flags = NFE_TX_LASTFRAG_V1;
1305 desc32->flags |= htole16(flags);
1309 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1310 * whole mess until the first descriptor in the map is flagged.
1312 for (i = nsegs - 1; i >= 0; --i) {
1313 j = (ring->cur + i) % sc->sc_tx_ring_count;
1314 if (sc->sc_caps & NFE_40BIT_ADDR) {
1315 desc64 = &ring->desc64[j];
1316 desc64->flags |= htole16(NFE_TX_VALID);
1318 desc32 = &ring->desc32[j];
1319 desc32->flags |= htole16(NFE_TX_VALID);
1322 ring->cur = (ring->cur + nsegs) % sc->sc_tx_ring_count;
1324 /* Exchange DMA map */
1325 data_map->map = data->map;
1335 nfe_start(struct ifnet *ifp)
1337 struct nfe_softc *sc = ifp->if_softc;
1338 struct nfe_tx_ring *ring = &sc->txq;
1339 int count = 0, oactive = 0;
1342 ASSERT_SERIALIZED(ifp->if_serializer);
1344 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1350 if (sc->sc_tx_ring_count - ring->queued <
1351 sc->sc_tx_spare + NFE_NSEG_RSVD) {
1353 ifp->if_flags |= IFF_OACTIVE;
1362 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1366 ETHER_BPF_MTAP(ifp, m0);
1368 error = nfe_encap(sc, ring, m0);
1371 if (error == EFBIG) {
1373 ifp->if_flags |= IFF_OACTIVE;
1387 * `m0' may be freed in nfe_encap(), so
1388 * it should not be touched any more.
1392 if (count == 0) /* nothing sent */
1396 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1399 * Set a timeout in case the chip goes out to lunch.
1405 nfe_watchdog(struct ifnet *ifp)
1407 struct nfe_softc *sc = ifp->if_softc;
1409 ASSERT_SERIALIZED(ifp->if_serializer);
1411 if (ifp->if_flags & IFF_RUNNING) {
1412 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1417 if_printf(ifp, "watchdog timeout\n");
1419 nfe_init(ifp->if_softc);
1427 struct nfe_softc *sc = xsc;
1428 struct ifnet *ifp = &sc->arpcom.ac_if;
1432 ASSERT_SERIALIZED(ifp->if_serializer);
1436 if ((sc->sc_caps & NFE_NO_PWRCTL) == 0)
1441 * Switching between jumbo frames and normal frames should
1442 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1444 if (ifp->if_mtu > ETHERMTU) {
1445 sc->sc_flags |= NFE_F_USE_JUMBO;
1446 sc->rxq.bufsz = NFE_JBYTES;
1447 sc->sc_tx_spare = NFE_NSEG_SPARE_JUMBO;
1449 if_printf(ifp, "use jumbo frames\n");
1451 sc->sc_flags &= ~NFE_F_USE_JUMBO;
1452 sc->rxq.bufsz = MCLBYTES;
1453 sc->sc_tx_spare = NFE_NSEG_SPARE;
1455 if_printf(ifp, "use non-jumbo frames\n");
1458 error = nfe_init_tx_ring(sc, &sc->txq);
1464 error = nfe_init_rx_ring(sc, &sc->rxq);
1470 NFE_WRITE(sc, NFE_TX_POLL, 0);
1471 NFE_WRITE(sc, NFE_STATUS, 0);
1473 sc->rxtxctl = NFE_RXTX_BIT2 | sc->rxtxctl_desc;
1475 if (ifp->if_capenable & IFCAP_RXCSUM)
1476 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1479 * Although the adapter is capable of stripping VLAN tags from received
1480 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1481 * purpose. This will be done in software by our network stack.
1483 if (sc->sc_caps & NFE_HW_VLAN)
1484 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1486 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1488 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1490 if (sc->sc_caps & NFE_HW_VLAN)
1491 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1493 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1495 /* set MAC address */
1496 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1498 /* tell MAC where rings are in memory */
1499 if (sc->sc_caps & NFE_40BIT_ADDR) {
1500 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
1501 NFE_ADDR_HI(sc->rxq.physaddr));
1503 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, NFE_ADDR_LO(sc->rxq.physaddr));
1505 if (sc->sc_caps & NFE_40BIT_ADDR) {
1506 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI,
1507 NFE_ADDR_HI(sc->txq.physaddr));
1509 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
1511 NFE_WRITE(sc, NFE_RING_SIZE,
1512 (sc->sc_rx_ring_count - 1) << 16 |
1513 (sc->sc_tx_ring_count - 1));
1515 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1517 /* force MAC to wakeup */
1518 tmp = NFE_READ(sc, NFE_PWR_STATE);
1519 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1521 tmp = NFE_READ(sc, NFE_PWR_STATE);
1522 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1524 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1525 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1526 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1528 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1529 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1531 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1533 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1534 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1536 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1541 nfe_ifmedia_upd(ifp);
1544 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1547 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1549 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1551 #ifdef DEVICE_POLLING
1552 if ((ifp->if_flags & IFF_POLLING))
1553 nfe_disable_intrs(sc);
1556 nfe_enable_intrs(sc);
1558 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1560 ifp->if_flags |= IFF_RUNNING;
1561 ifp->if_flags &= ~IFF_OACTIVE;
1564 * If we had stuff in the tx ring before its all cleaned out now
1565 * so we are not going to get an interrupt, jump-start any pending
1568 if (!ifq_is_empty(&ifp->if_snd))
1573 nfe_stop(struct nfe_softc *sc)
1575 struct ifnet *ifp = &sc->arpcom.ac_if;
1576 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
1579 ASSERT_SERIALIZED(ifp->if_serializer);
1581 callout_stop(&sc->sc_tick_ch);
1584 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1585 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
1587 #define WAITMAX 50000
1592 NFE_WRITE(sc, NFE_TX_CTL, 0);
1593 for (i = 0; i < WAITMAX; ++i) {
1595 if ((NFE_READ(sc, NFE_TX_STATUS) & NFE_TX_STATUS_BUSY) == 0)
1599 if_printf(ifp, "can't stop TX\n");
1605 NFE_WRITE(sc, NFE_RX_CTL, 0);
1606 for (i = 0; i < WAITMAX; ++i) {
1608 if ((NFE_READ(sc, NFE_RX_STATUS) & NFE_RX_STATUS_BUSY) == 0)
1612 if_printf(ifp, "can't stop RX\n");
1617 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
1619 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
1621 /* Disable interrupts */
1622 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1624 /* Reset Tx and Rx rings */
1625 nfe_reset_tx_ring(sc, &sc->txq);
1626 nfe_reset_rx_ring(sc, &sc->rxq);
1630 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1632 int i, j, error, descsize;
1636 if (sc->sc_caps & NFE_40BIT_ADDR) {
1637 desc = (void *)&ring->desc64;
1638 descsize = sizeof(struct nfe_desc64);
1640 desc = (void *)&ring->desc32;
1641 descsize = sizeof(struct nfe_desc32);
1644 ring->bufsz = MCLBYTES;
1645 ring->cur = ring->next = 0;
1647 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1648 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1649 sc->sc_rx_ring_count * descsize,
1650 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1652 if_printf(&sc->arpcom.ac_if,
1653 "could not create RX desc ring\n");
1656 ring->tag = dmem.dmem_tag;
1657 ring->map = dmem.dmem_map;
1658 *desc = dmem.dmem_addr;
1659 ring->physaddr = dmem.dmem_busaddr;
1661 if (sc->sc_caps & NFE_JUMBO_SUP) {
1663 kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT(sc),
1664 M_DEVBUF, M_WAITOK | M_ZERO);
1666 error = nfe_jpool_alloc(sc, ring);
1668 if_printf(&sc->arpcom.ac_if,
1669 "could not allocate jumbo frames\n");
1670 kfree(ring->jbuf, M_DEVBUF);
1672 /* Allow jumbo frame allocation to fail */
1676 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1677 M_DEVBUF, M_WAITOK | M_ZERO);
1679 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
1680 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1682 MCLBYTES, 1, MCLBYTES,
1683 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
1686 if_printf(&sc->arpcom.ac_if,
1687 "could not create RX mbuf DMA tag\n");
1691 /* Create a spare RX mbuf DMA map */
1692 error = bus_dmamap_create(ring->data_tag, BUS_DMA_WAITOK,
1693 &ring->data_tmpmap);
1695 if_printf(&sc->arpcom.ac_if,
1696 "could not create spare RX mbuf DMA map\n");
1697 bus_dma_tag_destroy(ring->data_tag);
1698 ring->data_tag = NULL;
1702 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1703 error = bus_dmamap_create(ring->data_tag, BUS_DMA_WAITOK,
1704 &ring->data[i].map);
1706 if_printf(&sc->arpcom.ac_if,
1707 "could not create %dth RX mbuf DMA mapn", i);
1713 for (j = 0; j < i; ++j)
1714 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1715 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1716 bus_dma_tag_destroy(ring->data_tag);
1717 ring->data_tag = NULL;
1722 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1726 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1727 struct nfe_rx_data *data = &ring->data[i];
1729 if (data->m != NULL) {
1730 if ((sc->sc_flags & NFE_F_USE_JUMBO) == 0)
1731 bus_dmamap_unload(ring->data_tag, data->map);
1737 ring->cur = ring->next = 0;
1741 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1745 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1748 /* XXX should use a function pointer */
1749 if (sc->sc_flags & NFE_F_USE_JUMBO)
1750 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1752 error = nfe_newbuf_std(sc, ring, i, 1);
1754 if_printf(&sc->arpcom.ac_if,
1755 "could not allocate RX buffer\n");
1758 nfe_set_ready_rxdesc(sc, ring, i);
1764 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1766 if (ring->data_tag != NULL) {
1767 struct nfe_rx_data *data;
1770 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1771 data = &ring->data[i];
1773 if (data->m != NULL) {
1774 bus_dmamap_unload(ring->data_tag, data->map);
1777 bus_dmamap_destroy(ring->data_tag, data->map);
1779 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1780 bus_dma_tag_destroy(ring->data_tag);
1783 nfe_jpool_free(sc, ring);
1785 if (ring->jbuf != NULL)
1786 kfree(ring->jbuf, M_DEVBUF);
1787 if (ring->data != NULL)
1788 kfree(ring->data, M_DEVBUF);
1790 if (ring->tag != NULL) {
1793 if (sc->sc_caps & NFE_40BIT_ADDR)
1794 desc = ring->desc64;
1796 desc = ring->desc32;
1798 bus_dmamap_unload(ring->tag, ring->map);
1799 bus_dmamem_free(ring->tag, desc, ring->map);
1800 bus_dma_tag_destroy(ring->tag);
1804 static struct nfe_jbuf *
1805 nfe_jalloc(struct nfe_softc *sc)
1807 struct ifnet *ifp = &sc->arpcom.ac_if;
1808 struct nfe_jbuf *jbuf;
1810 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1812 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1814 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1817 if_printf(ifp, "no free jumbo buffer\n");
1820 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1826 nfe_jfree(void *arg)
1828 struct nfe_jbuf *jbuf = arg;
1829 struct nfe_softc *sc = jbuf->sc;
1830 struct nfe_rx_ring *ring = jbuf->ring;
1832 if (&ring->jbuf[jbuf->slot] != jbuf)
1833 panic("%s: free wrong jumbo buffer", __func__);
1834 else if (jbuf->inuse == 0)
1835 panic("%s: jumbo buffer already freed", __func__);
1837 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1838 atomic_subtract_int(&jbuf->inuse, 1);
1839 if (jbuf->inuse == 0)
1840 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1841 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1847 struct nfe_jbuf *jbuf = arg;
1848 struct nfe_rx_ring *ring = jbuf->ring;
1850 if (&ring->jbuf[jbuf->slot] != jbuf)
1851 panic("%s: ref wrong jumbo buffer", __func__);
1852 else if (jbuf->inuse == 0)
1853 panic("%s: jumbo buffer already freed", __func__);
1855 atomic_add_int(&jbuf->inuse, 1);
1859 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1861 struct nfe_jbuf *jbuf;
1863 bus_addr_t physaddr;
1868 * Allocate a big chunk of DMA'able memory.
1870 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1871 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1873 BUS_DMA_WAITOK, &dmem);
1875 if_printf(&sc->arpcom.ac_if,
1876 "could not create jumbo buffer\n");
1879 ring->jtag = dmem.dmem_tag;
1880 ring->jmap = dmem.dmem_map;
1881 ring->jpool = dmem.dmem_addr;
1882 physaddr = dmem.dmem_busaddr;
1884 /* ..and split it into 9KB chunks */
1885 SLIST_INIT(&ring->jfreelist);
1888 for (i = 0; i < NFE_JPOOL_COUNT(sc); i++) {
1889 jbuf = &ring->jbuf[i];
1896 jbuf->physaddr = physaddr;
1898 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1901 physaddr += NFE_JBYTES;
1908 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1910 if (ring->jtag != NULL) {
1911 bus_dmamap_unload(ring->jtag, ring->jmap);
1912 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1913 bus_dma_tag_destroy(ring->jtag);
1918 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1920 int i, j, error, descsize;
1924 if (sc->sc_caps & NFE_40BIT_ADDR) {
1925 desc = (void *)&ring->desc64;
1926 descsize = sizeof(struct nfe_desc64);
1928 desc = (void *)&ring->desc32;
1929 descsize = sizeof(struct nfe_desc32);
1933 ring->cur = ring->next = 0;
1935 error = bus_dmamem_coherent(sc->sc_dtag, PAGE_SIZE, 0,
1936 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1937 sc->sc_tx_ring_count * descsize,
1938 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1940 if_printf(&sc->arpcom.ac_if,
1941 "could not create TX desc ring\n");
1944 ring->tag = dmem.dmem_tag;
1945 ring->map = dmem.dmem_map;
1946 *desc = dmem.dmem_addr;
1947 ring->physaddr = dmem.dmem_busaddr;
1949 ring->data = kmalloc(sizeof(struct nfe_tx_data) * sc->sc_tx_ring_count,
1950 M_DEVBUF, M_WAITOK | M_ZERO);
1952 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
1953 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1955 NFE_JBYTES, NFE_MAX_SCATTER, MCLBYTES,
1956 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1959 if_printf(&sc->arpcom.ac_if,
1960 "could not create TX buf DMA tag\n");
1964 for (i = 0; i < sc->sc_tx_ring_count; i++) {
1965 error = bus_dmamap_create(ring->data_tag,
1966 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1967 &ring->data[i].map);
1969 if_printf(&sc->arpcom.ac_if,
1970 "could not create %dth TX buf DMA map\n", i);
1977 for (j = 0; j < i; ++j)
1978 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1979 bus_dma_tag_destroy(ring->data_tag);
1980 ring->data_tag = NULL;
1985 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1989 for (i = 0; i < sc->sc_tx_ring_count; i++) {
1990 struct nfe_tx_data *data = &ring->data[i];
1992 if (sc->sc_caps & NFE_40BIT_ADDR)
1993 ring->desc64[i].flags = 0;
1995 ring->desc32[i].flags = 0;
1997 if (data->m != NULL) {
1998 bus_dmamap_unload(ring->data_tag, data->map);
2005 ring->cur = ring->next = 0;
2009 nfe_init_tx_ring(struct nfe_softc *sc __unused,
2010 struct nfe_tx_ring *ring __unused)
2016 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
2018 if (ring->data_tag != NULL) {
2019 struct nfe_tx_data *data;
2022 for (i = 0; i < sc->sc_tx_ring_count; ++i) {
2023 data = &ring->data[i];
2025 if (data->m != NULL) {
2026 bus_dmamap_unload(ring->data_tag, data->map);
2029 bus_dmamap_destroy(ring->data_tag, data->map);
2032 bus_dma_tag_destroy(ring->data_tag);
2035 if (ring->data != NULL)
2036 kfree(ring->data, M_DEVBUF);
2038 if (ring->tag != NULL) {
2041 if (sc->sc_caps & NFE_40BIT_ADDR)
2042 desc = ring->desc64;
2044 desc = ring->desc32;
2046 bus_dmamap_unload(ring->tag, ring->map);
2047 bus_dmamem_free(ring->tag, desc, ring->map);
2048 bus_dma_tag_destroy(ring->tag);
2053 nfe_ifmedia_upd(struct ifnet *ifp)
2055 struct nfe_softc *sc = ifp->if_softc;
2056 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2058 ASSERT_SERIALIZED(ifp->if_serializer);
2060 if (mii->mii_instance != 0) {
2061 struct mii_softc *miisc;
2063 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2064 mii_phy_reset(miisc);
2072 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2074 struct nfe_softc *sc = ifp->if_softc;
2075 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2077 ASSERT_SERIALIZED(ifp->if_serializer);
2080 ifmr->ifm_status = mii->mii_media_status;
2081 ifmr->ifm_active = mii->mii_media_active;
2085 nfe_setmulti(struct nfe_softc *sc)
2087 struct ifnet *ifp = &sc->arpcom.ac_if;
2088 struct ifmultiaddr *ifma;
2089 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2090 uint32_t filter = NFE_RXFILTER_MAGIC;
2093 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2094 bzero(addr, ETHER_ADDR_LEN);
2095 bzero(mask, ETHER_ADDR_LEN);
2099 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2100 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2102 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2105 if (ifma->ifma_addr->sa_family != AF_LINK)
2108 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2109 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2110 addr[i] &= maddr[i];
2111 mask[i] &= ~maddr[i];
2115 for (i = 0; i < ETHER_ADDR_LEN; i++)
2119 addr[0] |= 0x01; /* make sure multicast bit is set */
2121 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2122 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2123 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2124 addr[5] << 8 | addr[4]);
2125 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2126 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2127 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2128 mask[5] << 8 | mask[4]);
2130 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2131 NFE_WRITE(sc, NFE_RXFILTER, filter);
2135 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2139 lo = NFE_READ(sc, NFE_MACADDR_LO);
2140 hi = NFE_READ(sc, NFE_MACADDR_HI);
2141 if (sc->sc_caps & NFE_FIX_EADDR) {
2142 addr[0] = (lo >> 8) & 0xff;
2143 addr[1] = (lo & 0xff);
2145 addr[2] = (hi >> 24) & 0xff;
2146 addr[3] = (hi >> 16) & 0xff;
2147 addr[4] = (hi >> 8) & 0xff;
2148 addr[5] = (hi & 0xff);
2150 addr[0] = (hi & 0xff);
2151 addr[1] = (hi >> 8) & 0xff;
2152 addr[2] = (hi >> 16) & 0xff;
2153 addr[3] = (hi >> 24) & 0xff;
2155 addr[4] = (lo & 0xff);
2156 addr[5] = (lo >> 8) & 0xff;
2161 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2163 NFE_WRITE(sc, NFE_MACADDR_LO,
2164 addr[5] << 8 | addr[4]);
2165 NFE_WRITE(sc, NFE_MACADDR_HI,
2166 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2172 struct nfe_softc *sc = arg;
2173 struct ifnet *ifp = &sc->arpcom.ac_if;
2174 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2176 lwkt_serialize_enter(ifp->if_serializer);
2179 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2181 lwkt_serialize_exit(ifp->if_serializer);
2185 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2188 struct nfe_rx_data *data = &ring->data[idx];
2189 bus_dma_segment_t seg;
2194 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2197 m->m_len = m->m_pkthdr.len = MCLBYTES;
2200 * Aligning the payload improves access times.
2202 if (sc->sc_caps & NFE_WORDALIGN)
2203 m_adj(m, ETHER_ALIGN);
2205 error = bus_dmamap_load_mbuf_segment(ring->data_tag, ring->data_tmpmap,
2206 m, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
2210 if_printf(&sc->arpcom.ac_if,
2211 "could map RX mbuf %d\n", error);
2216 if (data->m != NULL) {
2217 /* Sync and unload originally mapped mbuf */
2218 bus_dmamap_sync(ring->data_tag, data->map,
2219 BUS_DMASYNC_POSTREAD);
2220 bus_dmamap_unload(ring->data_tag, data->map);
2223 /* Swap this DMA map with tmp DMA map */
2225 data->map = ring->data_tmpmap;
2226 ring->data_tmpmap = map;
2228 /* Caller is assumed to have collected the old mbuf */
2231 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2236 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2239 struct nfe_rx_data *data = &ring->data[idx];
2240 struct nfe_jbuf *jbuf;
2243 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2247 jbuf = nfe_jalloc(sc);
2250 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2251 "-- packet dropped!\n");
2255 m->m_ext.ext_arg = jbuf;
2256 m->m_ext.ext_buf = jbuf->buf;
2257 m->m_ext.ext_free = nfe_jfree;
2258 m->m_ext.ext_ref = nfe_jref;
2259 m->m_ext.ext_size = NFE_JBYTES;
2261 m->m_data = m->m_ext.ext_buf;
2262 m->m_flags |= M_EXT;
2263 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2266 * Aligning the payload improves access times.
2268 if (sc->sc_caps & NFE_WORDALIGN)
2269 m_adj(m, ETHER_ALIGN);
2271 /* Caller is assumed to have collected the old mbuf */
2274 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2279 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2280 bus_addr_t physaddr)
2282 if (sc->sc_caps & NFE_40BIT_ADDR) {
2283 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2285 desc64->physaddr[0] = htole32(NFE_ADDR_HI(physaddr));
2286 desc64->physaddr[1] = htole32(NFE_ADDR_LO(physaddr));
2288 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2290 desc32->physaddr = htole32(physaddr);
2295 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2297 if (sc->sc_caps & NFE_40BIT_ADDR) {
2298 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2300 desc64->length = htole16(ring->bufsz);
2301 desc64->flags = htole16(NFE_RX_READY);
2303 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2305 desc32->length = htole16(ring->bufsz);
2306 desc32->flags = htole16(NFE_RX_READY);
2311 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2313 struct nfe_softc *sc = arg1;
2314 struct ifnet *ifp = &sc->arpcom.ac_if;
2318 lwkt_serialize_enter(ifp->if_serializer);
2320 flags = sc->sc_flags & ~NFE_F_DYN_IM;
2322 if (sc->sc_flags & NFE_F_DYN_IM)
2325 error = sysctl_handle_int(oidp, &v, 0, req);
2326 if (error || req->newptr == NULL)
2330 flags |= NFE_F_DYN_IM;
2334 if (v != sc->sc_imtime || (flags ^ sc->sc_flags)) {
2335 if (NFE_IMTIME(v) == 0)
2338 sc->sc_flags = flags;
2339 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2341 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2343 nfe_enable_intrs(sc);
2347 lwkt_serialize_exit(ifp->if_serializer);
2352 nfe_powerup(device_t dev)
2354 struct nfe_softc *sc = device_get_softc(dev);
2359 * Bring MAC and PHY out of low power state
2362 pwr_state = NFE_READ(sc, NFE_PWR_STATE2) & ~NFE_PWRUP_MASK;
2364 did = pci_get_device(dev);
2365 if ((did == PCI_PRODUCT_NVIDIA_MCP51_LAN1 ||
2366 did == PCI_PRODUCT_NVIDIA_MCP51_LAN2) &&
2367 pci_get_revid(dev) >= 0xa3)
2368 pwr_state |= NFE_PWRUP_REV_A3;
2370 NFE_WRITE(sc, NFE_PWR_STATE2, pwr_state);
2374 nfe_mac_reset(struct nfe_softc *sc)
2376 uint32_t rxtxctl = sc->rxtxctl_desc | NFE_RXTX_BIT2;
2377 uint32_t macaddr_hi, macaddr_lo, tx_poll;
2379 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | rxtxctl);
2381 /* Save several registers for later restoration */
2382 macaddr_hi = NFE_READ(sc, NFE_MACADDR_HI);
2383 macaddr_lo = NFE_READ(sc, NFE_MACADDR_LO);
2384 tx_poll = NFE_READ(sc, NFE_TX_POLL);
2386 NFE_WRITE(sc, NFE_MAC_RESET, NFE_RESET_ASSERT);
2389 NFE_WRITE(sc, NFE_MAC_RESET, 0);
2392 /* Restore saved registers */
2393 NFE_WRITE(sc, NFE_MACADDR_HI, macaddr_hi);
2394 NFE_WRITE(sc, NFE_MACADDR_LO, macaddr_lo);
2395 NFE_WRITE(sc, NFE_TX_POLL, tx_poll);
2397 NFE_WRITE(sc, NFE_RXTX_CTL, rxtxctl);
2401 nfe_enable_intrs(struct nfe_softc *sc)
2404 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
2405 * It is unclear how wide the timer is. Base programming does
2406 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
2407 * we don't get any interrupt moderation. TX moderation is
2408 * possible by using the timer interrupt instead of TX_DONE.
2410 * It is unclear whether there are other bits that can be
2411 * set to make the NFE device actually do interrupt moderation
2414 * For now set a 128uS interval as a placemark, but don't use
2417 if (sc->sc_imtime == 0)
2418 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
2420 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
2422 /* Enable interrupts */
2423 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
2425 if (sc->sc_irq_enable & NFE_IRQ_TIMER)
2426 sc->sc_flags |= NFE_F_IRQ_TIMER;
2428 sc->sc_flags &= ~NFE_F_IRQ_TIMER;
2431 #ifdef DEVICE_POLLING
2433 nfe_disable_intrs(struct nfe_softc *sc)
2435 /* Disable interrupts */
2436 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
2437 sc->sc_flags &= ~NFE_F_IRQ_TIMER;