sys/dev/netif/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 1.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  35  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.12 2004/03/14 15:36:52 joerg Exp $
  36  *
  37  * $FreeBSD: src/sys/pci/if_sk.c,v 1.19.2.9 2003/03/05 18:42:34 njl Exp $
  38  */
  39
  40 /*
  41  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  42  *
  43  * Permission to use, copy, modify, and distribute this software for any
  44  * purpose with or without fee is hereby granted, provided that the above
  45  * copyright notice and this permission notice appear in all copies.
  46  *
  47  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  48  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  49  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  50  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  51  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  52  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  53  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  54  */
  55
  56 /*
  57  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  58  * the SK-984x series adapters, both single port and dual port.
  59  * References:
  60  *      The XaQti XMAC II datasheet,
  61  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  62  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  63  *
  64  * Note: XaQti has been aquired by Vitesse, and Vitesse does not have the
  65  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  66  * convenience to others until Vitesse corrects this problem:
  67  *
  68  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  69  *
  70  * Written by Bill Paul <wpaul@ee.columbia.edu>
  71  * Department of Electrical Engineering
  72  * Columbia University, New York City
  73  */
  74
  75 /*
  76  * The SysKonnect gigabit ethernet adapters consist of two main
  77  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  78  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  79  * components and a PHY while the GEnesis controller provides a PCI
  80  * interface with DMA support. Each card may have between 512K and
  81  * 2MB of SRAM on board depending on the configuration.
  82  *
  83  * The SysKonnect GEnesis controller can have either one or two XMAC
  84  * chips connected to it, allowing single or dual port NIC configurations.
  85  * SysKonnect has the distinction of being the only vendor on the market
  86  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  87  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  88  * XMAC registers. This driver takes advantage of these features to allow
  89  * both XMACs to operate as independent interfaces.
  90  */
  91
  92 #include <sys/param.h>
  93 #include <sys/systm.h>
  94 #include <sys/sockio.h>
  95 #include <sys/mbuf.h>
  96 #include <sys/malloc.h>
  97 #include <sys/kernel.h>
  98 #include <sys/socket.h>
  99 #include <sys/queue.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106
 107 #include <net/bpf.h>
 108
 109 #include <vm/vm.h>              /* for vtophys */
 110 #include <vm/pmap.h>            /* for vtophys */
 111 #include <machine/clock.h>      /* for DELAY */
 112 #include <machine/bus_pio.h>
 113 #include <machine/bus_memio.h>
 114 #include <machine/bus.h>
 115 #include <machine/resource.h>
 116 #include <sys/bus.h>
 117 #include <sys/rman.h>
 118
 119 #include "../mii_layer/mii.h"
 120 #include "../mii_layer/miivar.h"
 121 #include "../mii_layer/brgphyreg.h"
 122
 123 #include <bus/pci/pcireg.h>
 124 #include <bus/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include "if_skreg.h"
 131 #include "xmaciireg.h"
 132 #include "yukonreg.h"
 133
 134 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 135 #include "miibus_if.h"
 136
 137 static struct sk_type sk_devs[] = {
 138         {
 139                 VENDORID_SK,
 140                 DEVICEID_SK_V1,
 141                 "SysKonnect Gigabit Ethernet (V1.0)"
 142         },
 143         {
 144                 VENDORID_SK,
 145                 DEVICEID_SK_V2,
 146                 "SysKonnect Gigabit Ethernet (V2.0)"
 147         },
 148         {
 149                 VENDORID_MARVELL,
 150                 DEVICEID_SK_V2,
 151                 "Marvell Gigabit Ethernet"
 152         },
 153         {
 154                 VENDORID_3COM,
 155                 DEVICEID_3COM_3C940,
 156                 "3Com 3C940 Gigabit Ethernet"
 157         },
 158         { 0, 0, NULL }
 159 };
 160
 161 static int skc_probe            (device_t);
 162 static int skc_attach           (device_t);
 163 static int skc_detach           (device_t);
 164 static void skc_shutdown        (device_t);
 165 static int sk_probe             (device_t);
 166 static int sk_attach            (device_t);
 167 static int sk_detach            (device_t);
 168 static void sk_tick             (void *);
 169 static void sk_intr             (void *);
 170 static void sk_intr_bcom        (struct sk_if_softc *);
 171 static void sk_intr_xmac        (struct sk_if_softc *);
 172 static void sk_intr_yukon       (struct sk_if_softc *);
 173 static void sk_rxeof            (struct sk_if_softc *);
 174 static void sk_txeof            (struct sk_if_softc *);
 175 static int sk_encap             (struct sk_if_softc *, struct mbuf *,
 176                                         u_int32_t *);
 177 static void sk_start            (struct ifnet *);
 178 static int sk_ioctl             (struct ifnet *, u_long, caddr_t);
 179 static void sk_init             (void *);
 180 static void sk_init_xmac        (struct sk_if_softc *);
 181 static void sk_init_yukon       (struct sk_if_softc *);
 182 static void sk_stop             (struct sk_if_softc *);
 183 static void sk_watchdog         (struct ifnet *);
 184 static int sk_ifmedia_upd       (struct ifnet *);
 185 static void sk_ifmedia_sts      (struct ifnet *, struct ifmediareq *);
 186 static void sk_reset            (struct sk_softc *);
 187 static int sk_newbuf            (struct sk_if_softc *,
 188                                         struct sk_chain *, struct mbuf *);
 189 static int sk_alloc_jumbo_mem   (struct sk_if_softc *);
 190 static void *sk_jalloc          (struct sk_if_softc *);
 191 static void sk_jfree            (caddr_t, u_int);
 192 static void sk_jref             (caddr_t, u_int);
 193 static int sk_init_rx_ring      (struct sk_if_softc *);
 194 static void sk_init_tx_ring     (struct sk_if_softc *);
 195 static u_int32_t sk_win_read_4  (struct sk_softc *, int);
 196 static u_int16_t sk_win_read_2  (struct sk_softc *, int);
 197 static u_int8_t sk_win_read_1   (struct sk_softc *, int);
 198 static void sk_win_write_4      (struct sk_softc *, int, u_int32_t);
 199 static void sk_win_write_2      (struct sk_softc *, int, u_int32_t);
 200 static void sk_win_write_1      (struct sk_softc *, int, u_int32_t);
 201 static u_int8_t sk_vpd_readbyte (struct sk_softc *, int);
 202 static void sk_vpd_read_res     (struct sk_softc *,
 203                                         struct vpd_res *, int);
 204 static void sk_vpd_read         (struct sk_softc *);
 205
 206 static int sk_miibus_readreg    (device_t, int, int);
 207 static int sk_miibus_writereg   (device_t, int, int, int);
 208 static void sk_miibus_statchg   (device_t);
 209
 210 static int sk_xmac_miibus_readreg     (struct sk_if_softc *, int, int);
 211 static int sk_xmac_miibus_writereg    (struct sk_if_softc *, int, int, int);
 212 static void sk_xmac_miibus_statchg    (struct sk_if_softc *);
 213
 214 static int sk_marv_miibus_readreg     (struct sk_if_softc *, int, int);
 215 static int sk_marv_miibus_writereg    (struct sk_if_softc *, int, int, int);
 216 static void sk_marv_miibus_statchg    (struct sk_if_softc *);
 217
 218 static u_int32_t xmac_calchash  (caddr_t);
 219 static u_int32_t gmac_calchash  (caddr_t);
 220 static void sk_setfilt          (struct sk_if_softc *, caddr_t, int);
 221 static void sk_setmulti         (struct sk_if_softc *);
 222 static void sk_setpromisc       (struct sk_if_softc *);
 223
 224 #ifdef SK_USEIOSPACE
 225 #define SK_RES          SYS_RES_IOPORT
 226 #define SK_RID          SK_PCI_LOIO
 227 #else
 228 #define SK_RES          SYS_RES_MEMORY
 229 #define SK_RID          SK_PCI_LOMEM
 230 #endif
 231
 232 /*
 233  * Note that we have newbus methods for both the GEnesis controller
 234  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 235  * the miibus code is a child of the XMACs. We need to do it this way
 236  * so that the miibus drivers can access the PHY registers on the
 237  * right PHY. It's not quite what I had in mind, but it's the only
 238  * design that achieves the desired effect.
 239  */
 240 static device_method_t skc_methods[] = {
 241         /* Device interface */
 242         DEVMETHOD(device_probe,         skc_probe),
 243         DEVMETHOD(device_attach,        skc_attach),
 244         DEVMETHOD(device_detach,        skc_detach),
 245         DEVMETHOD(device_shutdown,      skc_shutdown),
 246
 247         /* bus interface */
 248         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 249         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 250
 251         { 0, 0 }
 252 };
 253
 254 static driver_t skc_driver = {
 255         "skc",
 256         skc_methods,
 257         sizeof(struct sk_softc)
 258 };
 259
 260 static devclass_t skc_devclass;
 261
 262 static device_method_t sk_methods[] = {
 263         /* Device interface */
 264         DEVMETHOD(device_probe,         sk_probe),
 265         DEVMETHOD(device_attach,        sk_attach),
 266         DEVMETHOD(device_detach,        sk_detach),
 267         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 268
 269         /* bus interface */
 270         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 271         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 272
 273         /* MII interface */
 274         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 275         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 276         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 277
 278         { 0, 0 }
 279 };
 280
 281 static driver_t sk_driver = {
 282         "sk",
 283         sk_methods,
 284         sizeof(struct sk_if_softc)
 285 };
 286
 287 static devclass_t sk_devclass;
 288
 289 DECLARE_DUMMY_MODULE(if_sk);
 290 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 291 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 292 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 293
 294 #define SK_SETBIT(sc, reg, x)           \
 295         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 296
 297 #define SK_CLRBIT(sc, reg, x)           \
 298         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 299
 300 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 301         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 302
 303 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 304         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 305
 306 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 307         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 308
 309 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 310         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 311
 312 static u_int32_t sk_win_read_4(sc, reg)
 313         struct sk_softc         *sc;
 314         int                     reg;
 315 {
 316 #ifdef SK_USEIOSPACE
 317         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 318         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 319 #else
 320         return(CSR_READ_4(sc, reg));
 321 #endif
 322 }
 323
 324 static u_int16_t sk_win_read_2(sc, reg)
 325         struct sk_softc         *sc;
 326         int                     reg;
 327 {
 328 #ifdef SK_USEIOSPACE
 329         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 330         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 331 #else
 332         return(CSR_READ_2(sc, reg));
 333 #endif
 334 }
 335
 336 static u_int8_t sk_win_read_1(sc, reg)
 337         struct sk_softc         *sc;
 338         int                     reg;
 339 {
 340 #ifdef SK_USEIOSPACE
 341         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 342         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 343 #else
 344         return(CSR_READ_1(sc, reg));
 345 #endif
 346 }
 347
 348 static void sk_win_write_4(sc, reg, val)
 349         struct sk_softc         *sc;
 350         int                     reg;
 351         u_int32_t               val;
 352 {
 353 #ifdef SK_USEIOSPACE
 354         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 355         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 356 #else
 357         CSR_WRITE_4(sc, reg, val);
 358 #endif
 359         return;
 360 }
 361
 362 static void sk_win_write_2(sc, reg, val)
 363         struct sk_softc         *sc;
 364         int                     reg;
 365         u_int32_t               val;
 366 {
 367 #ifdef SK_USEIOSPACE
 368         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 369         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 370 #else
 371         CSR_WRITE_2(sc, reg, val);
 372 #endif
 373         return;
 374 }
 375
 376 static void sk_win_write_1(sc, reg, val)
 377         struct sk_softc         *sc;
 378         int                     reg;
 379         u_int32_t               val;
 380 {
 381 #ifdef SK_USEIOSPACE
 382         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 383         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 384 #else
 385         CSR_WRITE_1(sc, reg, val);
 386 #endif
 387         return;
 388 }
 389
 390 /*
 391  * The VPD EEPROM contains Vital Product Data, as suggested in
 392  * the PCI 2.1 specification. The VPD data is separared into areas
 393  * denoted by resource IDs. The SysKonnect VPD contains an ID string
 394  * resource (the name of the adapter), a read-only area resource
 395  * containing various key/data fields and a read/write area which
 396  * can be used to store asset management information or log messages.
 397  * We read the ID string and read-only into buffers attached to
 398  * the controller softc structure for later use. At the moment,
 399  * we only use the ID string during sk_attach().
 400  */
 401 static u_int8_t sk_vpd_readbyte(sc, addr)
 402         struct sk_softc         *sc;
 403         int                     addr;
 404 {
 405         int                     i;
 406
 407         sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
 408         for (i = 0; i < SK_TIMEOUT; i++) {
 409                 DELAY(1);
 410                 if (sk_win_read_2(sc,
 411                     SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
 412                         break;
 413         }
 414
 415         if (i == SK_TIMEOUT)
 416                 return(0);
 417
 418         return(sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA)));
 419 }
 420
 421 static void sk_vpd_read_res(sc, res, addr)
 422         struct sk_softc         *sc;
 423         struct vpd_res          *res;
 424         int                     addr;
 425 {
 426         int                     i;
 427         u_int8_t                *ptr;
 428
 429         ptr = (u_int8_t *)res;
 430         for (i = 0; i < sizeof(struct vpd_res); i++)
 431                 ptr[i] = sk_vpd_readbyte(sc, i + addr);
 432
 433         return;
 434 }
 435
 436 static void sk_vpd_read(sc)
 437         struct sk_softc         *sc;
 438 {
 439         int                     pos = 0, i;
 440         struct vpd_res          res;
 441
 442         if (sc->sk_vpd_prodname != NULL)
 443                 free(sc->sk_vpd_prodname, M_DEVBUF);
 444         if (sc->sk_vpd_readonly != NULL)
 445                 free(sc->sk_vpd_readonly, M_DEVBUF);
 446         sc->sk_vpd_prodname = NULL;
 447         sc->sk_vpd_readonly = NULL;
 448
 449         sk_vpd_read_res(sc, &res, pos);
 450
 451         if (res.vr_id != VPD_RES_ID) {
 452                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 453                     sc->sk_unit, VPD_RES_ID, res.vr_id);
 454                 return;
 455         }
 456
 457         pos += sizeof(res);
 458         sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT);
 459         for (i = 0; i < res.vr_len; i++)
 460                 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
 461         sc->sk_vpd_prodname[i] = '\0';
 462         pos += i;
 463
 464         sk_vpd_read_res(sc, &res, pos);
 465
 466         if (res.vr_id != VPD_RES_READ) {
 467                 printf("skc%d: bad VPD resource id: expected %x got %x\n",
 468                     sc->sk_unit, VPD_RES_READ, res.vr_id);
 469                 return;
 470         }
 471
 472         pos += sizeof(res);
 473         sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT);
 474         for (i = 0; i < res.vr_len + 1; i++)
 475                 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
 476
 477         return;
 478 }
 479
 480 static int sk_miibus_readreg(dev, phy, reg)
 481         device_t                dev;
 482         int                     phy, reg;
 483 {
 484         struct sk_if_softc      *sc_if;
 485
 486         sc_if = device_get_softc(dev);
 487
 488         switch(sc_if->sk_softc->sk_type) {
 489         case SK_GENESIS:
 490                 return(sk_xmac_miibus_readreg(sc_if, phy, reg));
 491         case SK_YUKON:
 492                 return(sk_marv_miibus_readreg(sc_if, phy, reg));
 493         }
 494
 495         return(0);
 496 }
 497
 498 static int sk_miibus_writereg(dev, phy, reg, val)
 499         device_t                dev;
 500         int                     phy, reg, val;
 501 {
 502         struct sk_if_softc      *sc_if;
 503
 504         sc_if = device_get_softc(dev);
 505
 506         switch(sc_if->sk_softc->sk_type) {
 507         case SK_GENESIS:
 508                 return(sk_xmac_miibus_writereg(sc_if, phy, reg, val));
 509         case SK_YUKON:
 510                 return(sk_marv_miibus_writereg(sc_if, phy, reg, val));
 511         }
 512
 513         return(0);
 514 }
 515
 516 static void sk_miibus_statchg(dev)
 517         device_t                dev;
 518 {
 519         struct sk_if_softc      *sc_if;
 520
 521         sc_if = device_get_softc(dev);
 522
 523         switch(sc_if->sk_softc->sk_type) {
 524         case SK_GENESIS:
 525                 sk_xmac_miibus_statchg(sc_if);
 526                 break;
 527         case SK_YUKON:
 528                 sk_marv_miibus_statchg(sc_if);
 529                 break;
 530         }
 531
 532         return;
 533 }
 534
 535 static int sk_xmac_miibus_readreg(sc_if, phy, reg)
 536         struct sk_if_softc      *sc_if;
 537         int                     phy, reg;
 538 {
 539         int                     i;
 540
 541         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 542                 return(0);
 543
 544         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 545         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 546         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 547                 for (i = 0; i < SK_TIMEOUT; i++) {
 548                         DELAY(1);
 549                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 550                             XM_MMUCMD_PHYDATARDY)
 551                                 break;
 552                 }
 553
 554                 if (i == SK_TIMEOUT) {
 555                         printf("sk%d: phy failed to come ready\n",
 556                             sc_if->sk_unit);
 557                         return(0);
 558                 }
 559         }
 560         DELAY(1);
 561         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 562 }
 563
 564 static int sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 565         struct sk_if_softc      *sc_if;
 566         int                     phy, reg, val;
 567 {
 568         int                     i;
 569
 570         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 571         for (i = 0; i < SK_TIMEOUT; i++) {
 572                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 573                         break;
 574         }
 575
 576         if (i == SK_TIMEOUT) {
 577                 printf("sk%d: phy failed to come ready\n", sc_if->sk_unit);
 578                 return(ETIMEDOUT);
 579         }
 580
 581         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 582         for (i = 0; i < SK_TIMEOUT; i++) {
 583                 DELAY(1);
 584                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 585                         break;
 586         }
 587
 588         if (i == SK_TIMEOUT)
 589                 printf("sk%d: phy write timed out\n", sc_if->sk_unit);
 590
 591         return(0);
 592 }
 593
 594 static void sk_xmac_miibus_statchg(sc_if)
 595         struct sk_if_softc      *sc_if;
 596 {
 597         struct mii_data         *mii;
 598
 599         mii = device_get_softc(sc_if->sk_miibus);
 600
 601         /*
 602          * If this is a GMII PHY, manually set the XMAC's
 603          * duplex mode accordingly.
 604          */
 605         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 606                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 607                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 608                 } else {
 609                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 610                 }
 611         }
 612
 613         return;
 614 }
 615
 616 static int sk_marv_miibus_readreg(sc_if, phy, reg)
 617         struct sk_if_softc      *sc_if;
 618         int                     phy, reg;
 619 {
 620         u_int16_t               val;
 621         int                     i;
 622
 623         if (phy != 0 ||
 624             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 625              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 626                 return(0);
 627         }
 628
 629         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 630                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 631
 632         for (i = 0; i < SK_TIMEOUT; i++) {
 633                 DELAY(1);
 634                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 635                 if (val & YU_SMICR_READ_VALID)
 636                         break;
 637         }
 638
 639         if (i == SK_TIMEOUT) {
 640                 printf("sk%d: phy failed to come ready\n",
 641                     sc_if->sk_unit);
 642                 return(0);
 643         }
 644
 645         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 646
 647         return(val);
 648 }
 649
 650 static int sk_marv_miibus_writereg(sc_if, phy, reg, val)
 651         struct sk_if_softc      *sc_if;
 652         int                     phy, reg, val;
 653 {
 654         int                     i;
 655
 656         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 657         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 658                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 659
 660         for (i = 0; i < SK_TIMEOUT; i++) {
 661                 DELAY(1);
 662                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 663                         break;
 664         }
 665
 666         return(0);
 667 }
 668
 669 static void sk_marv_miibus_statchg(sc_if)
 670         struct sk_if_softc      *sc_if;
 671 {
 672         return;
 673 }
 674
 675 #define XMAC_POLY               0xEDB88320
 676 #define GMAC_POLY               0x04C11DB7L
 677 #define HASH_BITS               6
 678
 679 static u_int32_t xmac_calchash(addr)
 680         caddr_t                 addr;
 681 {
 682         u_int32_t               idx, bit, data, crc;
 683
 684         /* Compute CRC for the address value. */
 685         crc = 0xFFFFFFFF; /* initial value */
 686
 687         for (idx = 0; idx < 6; idx++) {
 688                 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
 689                         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? XMAC_POLY : 0);
 690         }
 691
 692         return (~crc & ((1 << HASH_BITS) - 1));
 693 }
 694
 695 static u_int32_t gmac_calchash(addr)
 696     caddr_t                     addr;
 697 {
 698     u_int32_t               idx, bit, crc, tmpData, data;
 699
 700     /* Compute CRC for the address value. */
 701     crc = 0xFFFFFFFF; /* initial value */
 702
 703     for (idx = 0; idx < 6; idx++) {
 704         data = *addr++;
 705
 706         /* Change bit order in byte. */
 707         tmpData = data;
 708         for (bit = 0; bit < 8; bit++) {
 709             if (tmpData & 1) {
 710                 data |=  1 << (7 - bit);
 711             }
 712             else {
 713                 data &= ~(1 << (7 - bit));
 714             }
 715
 716             tmpData >>= 1;
 717         }
 718
 719         crc ^= (data << 24);
 720         for (bit = 0; bit < 8; bit++) {
 721             if (crc & 0x80000000) {
 722                 crc = (crc << 1) ^ GMAC_POLY;
 723             } else {
 724                 crc <<= 1;
 725             }
 726         }
 727     }
 728
 729     return (crc & ((1 << HASH_BITS) - 1));
 730 }
 731
 732 static void sk_setfilt(sc_if, addr, slot)
 733         struct sk_if_softc      *sc_if;
 734         caddr_t                 addr;
 735         int                     slot;
 736 {
 737         int                     base;
 738
 739         base = XM_RXFILT_ENTRY(slot);
 740
 741         SK_XM_WRITE_2(sc_if, base, *(u_int16_t *)(&addr[0]));
 742         SK_XM_WRITE_2(sc_if, base + 2, *(u_int16_t *)(&addr[2]));
 743         SK_XM_WRITE_2(sc_if, base + 4, *(u_int16_t *)(&addr[4]));
 744
 745         return;
 746 }
 747
 748 static void sk_setmulti(sc_if)
 749         struct sk_if_softc      *sc_if;
 750 {
 751         struct sk_softc         *sc = sc_if->sk_softc;
 752         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 753         u_int32_t               hashes[2] = { 0, 0 };
 754         int                     h, i;
 755         struct ifmultiaddr      *ifma;
 756         u_int8_t                dummy[] = { 0, 0, 0, 0, 0 ,0 };
 757
 758
 759         /* First, zot all the existing filters. */
 760         switch(sc->sk_type) {
 761         case SK_GENESIS:
 762                 for (i = 1; i < XM_RXFILT_MAX; i++)
 763                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 764
 765                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 766                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 767                 break;
 768         case SK_YUKON:
 769                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 770                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 771                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 772                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 773                 break;
 774         }
 775
 776         /* Now program new ones. */
 777         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 778                 hashes[0] = 0xFFFFFFFF;
 779                 hashes[1] = 0xFFFFFFFF;
 780         } else {
 781                 i = 1;
 782                 /* First find the tail of the list. */
 783                 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
 784                                         ifma = ifma->ifma_link.le_next) {
 785                         if (ifma->ifma_link.le_next == NULL)
 786                                 break;
 787                 }
 788                 /* Now traverse the list backwards. */
 789                 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
 790                         ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
 791                         if (ifma->ifma_addr->sa_family != AF_LINK)
 792                                 continue;
 793                         /*
 794                          * Program the first XM_RXFILT_MAX multicast groups
 795                          * into the perfect filter. For all others,
 796                          * use the hash table.
 797                          */
 798                         if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
 799                                 sk_setfilt(sc_if,
 800                         LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
 801                                 i++;
 802                                 continue;
 803                         }
 804
 805                         switch(sc->sk_type) {
 806                         case SK_GENESIS:
 807                             h = xmac_calchash(
 808                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 809                             if (h < 32)
 810                                 hashes[0] |= (1 << h);
 811                             else
 812                                 hashes[1] |= (1 << (h - 32));
 813                             break;
 814
 815                         case SK_YUKON:
 816                             h = gmac_calchash(
 817                                 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
 818                             if (h < 32)
 819                                 hashes[0] |= (1 << h);
 820                             else
 821                                 hashes[1] |= (1 << (h - 32));
 822                             break;
 823                         }
 824                 }
 825         }
 826
 827         switch(sc->sk_type) {
 828         case SK_GENESIS:
 829                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 830                                XM_MODE_RX_USE_PERFECT);
 831                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 832                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 833                 break;
 834         case SK_YUKON:
 835                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 836                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 837                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 838                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 839                 break;
 840         }
 841
 842         return;
 843 }
 844
 845 static void sk_setpromisc(sc_if)
 846         struct sk_if_softc      *sc_if;
 847 {
 848         struct sk_softc         *sc = sc_if->sk_softc;
 849         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 850
 851         switch(sc->sk_type) {
 852         case SK_GENESIS:
 853                 if (ifp->if_flags & IFF_PROMISC) {
 854                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 855                 } else {
 856                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 857                 }
 858                 break;
 859         case SK_YUKON:
 860                 if (ifp->if_flags & IFF_PROMISC) {
 861                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 862                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 863                 } else {
 864                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 865                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 866                 }
 867                 break;
 868         }
 869
 870         return;
 871 }
 872
 873 static int sk_init_rx_ring(sc_if)
 874         struct sk_if_softc      *sc_if;
 875 {
 876         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 877         struct sk_ring_data     *rd = sc_if->sk_rdata;
 878         int                     i;
 879
 880         bzero((char *)rd->sk_rx_ring,
 881             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 882
 883         for (i = 0; i < SK_RX_RING_CNT; i++) {
 884                 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
 885                 if (sk_newbuf(sc_if, &cd->sk_rx_chain[i], NULL) == ENOBUFS)
 886                         return(ENOBUFS);
 887                 if (i == (SK_RX_RING_CNT - 1)) {
 888                         cd->sk_rx_chain[i].sk_next =
 889                             &cd->sk_rx_chain[0];
 890                         rd->sk_rx_ring[i].sk_next =
 891                             vtophys(&rd->sk_rx_ring[0]);
 892                 } else {
 893                         cd->sk_rx_chain[i].sk_next =
 894                             &cd->sk_rx_chain[i + 1];
 895                         rd->sk_rx_ring[i].sk_next =
 896                             vtophys(&rd->sk_rx_ring[i + 1]);
 897                 }
 898         }
 899
 900         sc_if->sk_cdata.sk_rx_prod = 0;
 901         sc_if->sk_cdata.sk_rx_cons = 0;
 902
 903         return(0);
 904 }
 905
 906 static void sk_init_tx_ring(sc_if)
 907         struct sk_if_softc      *sc_if;
 908 {
 909         struct sk_chain_data    *cd = &sc_if->sk_cdata;
 910         struct sk_ring_data     *rd = sc_if->sk_rdata;
 911         int                     i;
 912
 913         bzero((char *)sc_if->sk_rdata->sk_tx_ring,
 914             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 915
 916         for (i = 0; i < SK_TX_RING_CNT; i++) {
 917                 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
 918                 if (i == (SK_TX_RING_CNT - 1)) {
 919                         cd->sk_tx_chain[i].sk_next =
 920                             &cd->sk_tx_chain[0];
 921                         rd->sk_tx_ring[i].sk_next =
 922                             vtophys(&rd->sk_tx_ring[0]);
 923                 } else {
 924                         cd->sk_tx_chain[i].sk_next =
 925                             &cd->sk_tx_chain[i + 1];
 926                         rd->sk_tx_ring[i].sk_next =
 927                             vtophys(&rd->sk_tx_ring[i + 1]);
 928                 }
 929         }
 930
 931         sc_if->sk_cdata.sk_tx_prod = 0;
 932         sc_if->sk_cdata.sk_tx_cons = 0;
 933         sc_if->sk_cdata.sk_tx_cnt = 0;
 934
 935         return;
 936 }
 937
 938 static int sk_newbuf(sc_if, c, m)
 939         struct sk_if_softc      *sc_if;
 940         struct sk_chain         *c;
 941         struct mbuf             *m;
 942 {
 943         struct mbuf             *m_new = NULL;
 944         struct sk_rx_desc       *r;
 945
 946         if (m == NULL) {
 947                 caddr_t                 *buf = NULL;
 948
 949                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 950                 if (m_new == NULL)
 951                         return(ENOBUFS);
 952
 953                 /* Allocate the jumbo buffer */
 954                 buf = sk_jalloc(sc_if);
 955                 if (buf == NULL) {
 956                         m_freem(m_new);
 957 #ifdef SK_VERBOSE
 958                         printf("sk%d: jumbo allocation failed "
 959                             "-- packet dropped!\n", sc_if->sk_unit);
 960 #endif
 961                         return(ENOBUFS);
 962                 }
 963
 964                 /* Attach the buffer to the mbuf */
 965                 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
 966                 m_new->m_flags |= M_EXT;
 967                 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
 968                     m_new->m_len = SK_MCLBYTES;
 969                 m_new->m_ext.ext_free = sk_jfree;
 970                 m_new->m_ext.ext_ref = sk_jref;
 971         } else {
 972                 /*
 973                  * We're re-using a previously allocated mbuf;
 974                  * be sure to re-init pointers and lengths to
 975                  * default values.
 976                  */
 977                 m_new = m;
 978                 m_new->m_len = m_new->m_pkthdr.len = SK_MCLBYTES;
 979                 m_new->m_data = m_new->m_ext.ext_buf;
 980         }
 981
 982         /*
 983          * Adjust alignment so packet payload begins on a
 984          * longword boundary. Mandatory for Alpha, useful on
 985          * x86 too.
 986          */
 987         m_adj(m_new, ETHER_ALIGN);
 988
 989         r = c->sk_desc;
 990         c->sk_mbuf = m_new;
 991         r->sk_data_lo = vtophys(mtod(m_new, caddr_t));
 992         r->sk_ctl = m_new->m_len | SK_RXSTAT;
 993
 994         return(0);
 995 }
 996
 997 /*
 998  * Allocate jumbo buffer storage. The SysKonnect adapters support
 999  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1000  * use them in their drivers. In order for us to use them, we need
1001  * large 9K receive buffers, however standard mbuf clusters are only
1002  * 2048 bytes in size. Consequently, we need to allocate and manage
1003  * our own jumbo buffer pool. Fortunately, this does not require an
1004  * excessive amount of additional code.
1005  */
1006 static int sk_alloc_jumbo_mem(sc_if)
1007         struct sk_if_softc      *sc_if;
1008 {
1009         caddr_t                 ptr;
1010         int             i;
1011         struct sk_jpool_entry   *entry;
1012
1013         /* Grab a big chunk o' storage. */
1014         sc_if->sk_cdata.sk_jumbo_buf = contigmalloc(SK_JMEM, M_DEVBUF,
1015             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1016
1017         if (sc_if->sk_cdata.sk_jumbo_buf == NULL) {
1018                 printf("sk%d: no memory for jumbo buffers!\n", sc_if->sk_unit);
1019                 return(ENOBUFS);
1020         }
1021
1022         SLIST_INIT(&sc_if->sk_jfree_listhead);
1023         SLIST_INIT(&sc_if->sk_jinuse_listhead);
1024
1025         /*
1026          * Now divide it up into 9K pieces and save the addresses
1027          * in an array. Note that we play an evil trick here by using
1028          * the first few bytes in the buffer to hold the the address
1029          * of the softc structure for this interface. This is because
1030          * sk_jfree() needs it, but it is called by the mbuf management
1031          * code which will not pass it to us explicitly.
1032          */
1033         ptr = sc_if->sk_cdata.sk_jumbo_buf;
1034         for (i = 0; i < SK_JSLOTS; i++) {
1035                 u_int64_t               **aptr;
1036                 aptr = (u_int64_t **)ptr;
1037                 aptr[0] = (u_int64_t *)sc_if;
1038                 ptr += sizeof(u_int64_t);
1039                 sc_if->sk_cdata.sk_jslots[i].sk_buf = ptr;
1040                 sc_if->sk_cdata.sk_jslots[i].sk_inuse = 0;
1041                 ptr += SK_MCLBYTES;
1042                 entry = malloc(sizeof(struct sk_jpool_entry),
1043                     M_DEVBUF, M_NOWAIT);
1044                 if (entry == NULL) {
1045                         free(sc_if->sk_cdata.sk_jumbo_buf, M_DEVBUF);
1046                         sc_if->sk_cdata.sk_jumbo_buf = NULL;
1047                         printf("sk%d: no memory for jumbo "
1048                             "buffer queue!\n", sc_if->sk_unit);
1049                         return(ENOBUFS);
1050                 }
1051                 entry->slot = i;
1052                 SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1053                     entry, jpool_entries);
1054         }
1055
1056         return(0);
1057 }
1058
1059 /*
1060  * Allocate a jumbo buffer.
1061  */
1062 static void *sk_jalloc(sc_if)
1063         struct sk_if_softc      *sc_if;
1064 {
1065         struct sk_jpool_entry   *entry;
1066
1067         entry = SLIST_FIRST(&sc_if->sk_jfree_listhead);
1068
1069         if (entry == NULL) {
1070 #ifdef SK_VERBOSE
1071                 printf("sk%d: no free jumbo buffers\n", sc_if->sk_unit);
1072 #endif
1073                 return(NULL);
1074         }
1075
1076         SLIST_REMOVE_HEAD(&sc_if->sk_jfree_listhead, jpool_entries);
1077         SLIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
1078         sc_if->sk_cdata.sk_jslots[entry->slot].sk_inuse = 1;
1079         return(sc_if->sk_cdata.sk_jslots[entry->slot].sk_buf);
1080 }
1081
1082 /*
1083  * Adjust usage count on a jumbo buffer. In general this doesn't
1084  * get used much because our jumbo buffers don't get passed around
1085  * a lot, but it's implemented for correctness.
1086  */
1087 static void sk_jref(buf, size)
1088         caddr_t                 buf;
1089         u_int                   size;
1090 {
1091         struct sk_if_softc      *sc_if;
1092         u_int64_t               **aptr;
1093         int             i;
1094
1095         /* Extract the softc struct pointer. */
1096         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1097         sc_if = (struct sk_if_softc *)(aptr[0]);
1098
1099         if (sc_if == NULL)
1100                 panic("sk_jref: can't find softc pointer!");
1101
1102         if (size != SK_MCLBYTES)
1103                 panic("sk_jref: adjusting refcount of buf of wrong size!");
1104
1105         /* calculate the slot this buffer belongs to */
1106
1107         i = ((vm_offset_t)aptr
1108              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1109
1110         if ((i < 0) || (i >= SK_JSLOTS))
1111                 panic("sk_jref: asked to reference buffer "
1112                     "that we don't manage!");
1113         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1114                 panic("sk_jref: buffer already free!");
1115         else
1116                 sc_if->sk_cdata.sk_jslots[i].sk_inuse++;
1117
1118         return;
1119 }
1120
1121 /*
1122  * Release a jumbo buffer.
1123  */
1124 static void sk_jfree(buf, size)
1125         caddr_t                 buf;
1126         u_int                   size;
1127 {
1128         struct sk_if_softc      *sc_if;
1129         u_int64_t               **aptr;
1130         int                     i;
1131         struct sk_jpool_entry   *entry;
1132
1133         /* Extract the softc struct pointer. */
1134         aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
1135         sc_if = (struct sk_if_softc *)(aptr[0]);
1136
1137         if (sc_if == NULL)
1138                 panic("sk_jfree: can't find softc pointer!");
1139
1140         if (size != SK_MCLBYTES)
1141                 panic("sk_jfree: freeing buffer of wrong size!");
1142
1143         /* calculate the slot this buffer belongs to */
1144
1145         i = ((vm_offset_t)aptr
1146              - (vm_offset_t)sc_if->sk_cdata.sk_jumbo_buf) / SK_JLEN;
1147
1148         if ((i < 0) || (i >= SK_JSLOTS))
1149                 panic("sk_jfree: asked to free buffer that we don't manage!");
1150         else if (sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0)
1151                 panic("sk_jfree: buffer already free!");
1152         else {
1153                 sc_if->sk_cdata.sk_jslots[i].sk_inuse--;
1154                 if(sc_if->sk_cdata.sk_jslots[i].sk_inuse == 0) {
1155                         entry = SLIST_FIRST(&sc_if->sk_jinuse_listhead);
1156                         if (entry == NULL)
1157                                 panic("sk_jfree: buffer not in use!");
1158                         entry->slot = i;
1159                         SLIST_REMOVE_HEAD(&sc_if->sk_jinuse_listhead,
1160                                           jpool_entries);
1161                         SLIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
1162                                           entry, jpool_entries);
1163                 }
1164         }
1165
1166         return;
1167 }
1168
1169 /*
1170  * Set media options.
1171  */
1172 static int sk_ifmedia_upd(ifp)
1173         struct ifnet            *ifp;
1174 {
1175         struct sk_if_softc      *sc_if = ifp->if_softc;
1176         struct mii_data         *mii;
1177
1178         mii = device_get_softc(sc_if->sk_miibus);
1179         sk_init(sc_if);
1180         mii_mediachg(mii);
1181
1182         return(0);
1183 }
1184
1185 /*
1186  * Report current media status.
1187  */
1188 static void sk_ifmedia_sts(ifp, ifmr)
1189         struct ifnet            *ifp;
1190         struct ifmediareq       *ifmr;
1191 {
1192         struct sk_if_softc      *sc_if;
1193         struct mii_data         *mii;
1194
1195         sc_if = ifp->if_softc;
1196         mii = device_get_softc(sc_if->sk_miibus);
1197
1198         mii_pollstat(mii);
1199         ifmr->ifm_active = mii->mii_media_active;
1200         ifmr->ifm_status = mii->mii_media_status;
1201
1202         return;
1203 }
1204
1205 static int sk_ioctl(ifp, command, data)
1206         struct ifnet            *ifp;
1207         u_long                  command;
1208         caddr_t                 data;
1209 {
1210         struct sk_if_softc      *sc_if = ifp->if_softc;
1211         struct ifreq            *ifr = (struct ifreq *) data;
1212         int                     s, error = 0;
1213         struct mii_data         *mii;
1214
1215         s = splimp();
1216
1217         switch(command) {
1218         case SIOCSIFADDR:
1219         case SIOCGIFADDR:
1220                 error = ether_ioctl(ifp, command, data);
1221                 break;
1222         case SIOCSIFMTU:
1223                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
1224                         error = EINVAL;
1225                 else {
1226                         ifp->if_mtu = ifr->ifr_mtu;
1227                         sk_init(sc_if);
1228                 }
1229                 break;
1230         case SIOCSIFFLAGS:
1231                 if (ifp->if_flags & IFF_UP) {
1232                         if (ifp->if_flags & IFF_RUNNING) {
1233                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1234                                     & IFF_PROMISC) {
1235                                         sk_setpromisc(sc_if);
1236                                         sk_setmulti(sc_if);
1237                                 }
1238                         } else
1239                                 sk_init(sc_if);
1240                 } else {
1241                         if (ifp->if_flags & IFF_RUNNING)
1242                                 sk_stop(sc_if);
1243                 }
1244                 sc_if->sk_if_flags = ifp->if_flags;
1245                 error = 0;
1246                 break;
1247         case SIOCADDMULTI:
1248         case SIOCDELMULTI:
1249                 sk_setmulti(sc_if);
1250                 error = 0;
1251                 break;
1252         case SIOCGIFMEDIA:
1253         case SIOCSIFMEDIA:
1254                 mii = device_get_softc(sc_if->sk_miibus);
1255                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1256                 break;
1257         default:
1258                 error = EINVAL;
1259                 break;
1260         }
1261
1262         (void)splx(s);
1263
1264         return(error);
1265 }
1266
1267 /*
1268  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1269  * IDs against our list and return a device name if we find a match.
1270  */
1271 static int skc_probe(dev)
1272         device_t                dev;
1273 {
1274         struct sk_softc         *sc;
1275         struct sk_type          *t = sk_devs;
1276
1277         sc = device_get_softc(dev);
1278
1279         while(t->sk_name != NULL) {
1280                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1281                     (pci_get_device(dev) == t->sk_did)) {
1282                         device_set_desc(dev, t->sk_name);
1283                         return(0);
1284                 }
1285                 t++;
1286         }
1287
1288         return(ENXIO);
1289 }
1290
1291 /*
1292  * Force the GEnesis into reset, then bring it out of reset.
1293  */
1294 static void sk_reset(sc)
1295         struct sk_softc         *sc;
1296 {
1297         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1298         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1299         if (sc->sk_type == SK_YUKON)
1300                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1301
1302         DELAY(1000);
1303         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1304         DELAY(2);
1305         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1306         if (sc->sk_type == SK_YUKON)
1307                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1308
1309         if (sc->sk_type == SK_GENESIS) {
1310                 /* Configure packet arbiter */
1311                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1312                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1313                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1314                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1315                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1316         }
1317
1318         /* Enable RAM interface */
1319         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1320
1321         /*
1322          * Configure interrupt moderation. The moderation timer
1323          * defers interrupts specified in the interrupt moderation
1324          * timer mask based on the timeout specified in the interrupt
1325          * moderation timer init register. Each bit in the timer
1326          * register represents 18.825ns, so to specify a timeout in
1327          * microseconds, we have to multiply by 54.
1328          */
1329         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(200));
1330         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1331             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1332         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1333
1334         return;
1335 }
1336
1337 static int sk_probe(dev)
1338         device_t                dev;
1339 {
1340         struct sk_softc         *sc;
1341
1342         sc = device_get_softc(device_get_parent(dev));
1343
1344         /*
1345          * Not much to do here. We always know there will be
1346          * at least one XMAC present, and if there are two,
1347          * skc_attach() will create a second device instance
1348          * for us.
1349          */
1350         switch (sc->sk_type) {
1351         case SK_GENESIS:
1352                 device_set_desc(dev, "XaQti Corp. XMAC II");
1353                 break;
1354         case SK_YUKON:
1355                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1356                 break;
1357         }
1358
1359         return(0);
1360 }
1361
1362 /*
1363  * Each XMAC chip is attached as a separate logical IP interface.
1364  * Single port cards will have only one logical interface of course.
1365  */
1366 static int sk_attach(dev)
1367         device_t                dev;
1368 {
1369         struct sk_softc         *sc;
1370         struct sk_if_softc      *sc_if;
1371         struct ifnet            *ifp;
1372         int                     i, port;
1373
1374         if (dev == NULL)
1375                 return(EINVAL);
1376
1377         sc_if = device_get_softc(dev);
1378         sc = device_get_softc(device_get_parent(dev));
1379         port = *(int *)device_get_ivars(dev);
1380         free(device_get_ivars(dev), M_DEVBUF);
1381         device_set_ivars(dev, NULL);
1382         sc_if->sk_dev = dev;
1383
1384         bzero((char *)sc_if, sizeof(struct sk_if_softc));
1385
1386         sc_if->sk_dev = dev;
1387         sc_if->sk_unit = device_get_unit(dev);
1388         sc_if->sk_port = port;
1389         sc_if->sk_softc = sc;
1390         sc->sk_if[port] = sc_if;
1391         if (port == SK_PORT_A)
1392                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1393         if (port == SK_PORT_B)
1394                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1395
1396         /*
1397          * Get station address for this interface. Note that
1398          * dual port cards actually come with three station
1399          * addresses: one for each port, plus an extra. The
1400          * extra one is used by the SysKonnect driver software
1401          * as a 'virtual' station address for when both ports
1402          * are operating in failover mode. Currently we don't
1403          * use this extra address.
1404          */
1405         for (i = 0; i < ETHER_ADDR_LEN; i++)
1406                 sc_if->arpcom.ac_enaddr[i] =
1407                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1408
1409         printf("sk%d: Ethernet address: %6D\n",
1410             sc_if->sk_unit, sc_if->arpcom.ac_enaddr, ":");
1411
1412         /*
1413          * Set up RAM buffer addresses. The NIC will have a certain
1414          * amount of SRAM on it, somewhere between 512K and 2MB. We
1415          * need to divide this up a) between the transmitter and
1416          * receiver and b) between the two XMACs, if this is a
1417          * dual port NIC. Our algotithm is to divide up the memory
1418          * evenly so that everyone gets a fair share.
1419          */
1420         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1421                 u_int32_t               chunk, val;
1422
1423                 chunk = sc->sk_ramsize / 2;
1424                 val = sc->sk_rboff / sizeof(u_int64_t);
1425                 sc_if->sk_rx_ramstart = val;
1426                 val += (chunk / sizeof(u_int64_t));
1427                 sc_if->sk_rx_ramend = val - 1;
1428                 sc_if->sk_tx_ramstart = val;
1429                 val += (chunk / sizeof(u_int64_t));
1430                 sc_if->sk_tx_ramend = val - 1;
1431         } else {
1432                 u_int32_t               chunk, val;
1433
1434                 chunk = sc->sk_ramsize / 4;
1435                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1436                     sizeof(u_int64_t);
1437                 sc_if->sk_rx_ramstart = val;
1438                 val += (chunk / sizeof(u_int64_t));
1439                 sc_if->sk_rx_ramend = val - 1;
1440                 sc_if->sk_tx_ramstart = val;
1441                 val += (chunk / sizeof(u_int64_t));
1442                 sc_if->sk_tx_ramend = val - 1;
1443         }
1444
1445         /* Read and save PHY type and set PHY address */
1446         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1447         switch(sc_if->sk_phytype) {
1448         case SK_PHYTYPE_XMAC:
1449                 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1450                 break;
1451         case SK_PHYTYPE_BCOM:
1452                 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1453                 break;
1454         case SK_PHYTYPE_MARV_COPPER:
1455                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1456                 break;
1457         default:
1458                 printf("skc%d: unsupported PHY type: %d\n",
1459                     sc->sk_unit, sc_if->sk_phytype);
1460                 return(ENODEV);
1461         }
1462
1463         /* Allocate the descriptor queues. */
1464         sc_if->sk_rdata = contigmalloc(sizeof(struct sk_ring_data), M_DEVBUF,
1465             M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1466
1467         if (sc_if->sk_rdata == NULL) {
1468                 printf("sk%d: no memory for list buffers!\n", sc_if->sk_unit);
1469                 sc->sk_if[port] = NULL;
1470                 return(ENOMEM);
1471         }
1472
1473         bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
1474
1475         /* Try to allocate memory for jumbo buffers. */
1476         if (sk_alloc_jumbo_mem(sc_if)) {
1477                 printf("sk%d: jumbo buffer allocation failed\n",
1478                     sc_if->sk_unit);
1479                 contigfree(sc_if->sk_rdata,
1480                     sizeof(struct sk_ring_data), M_DEVBUF);
1481                 sc->sk_if[port] = NULL;
1482                 return(ENOMEM);
1483         }
1484
1485         ifp = &sc_if->arpcom.ac_if;
1486         ifp->if_softc = sc_if;
1487         if_initname(ifp, "sk", sc_if->sk_unit);
1488         ifp->if_mtu = ETHERMTU;
1489         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1490         ifp->if_ioctl = sk_ioctl;
1491         ifp->if_output = ether_output;
1492         ifp->if_start = sk_start;
1493         ifp->if_watchdog = sk_watchdog;
1494         ifp->if_init = sk_init;
1495         ifp->if_baudrate = 1000000000;
1496         ifp->if_snd.ifq_maxlen = SK_TX_RING_CNT - 1;
1497
1498         /*
1499          * Do miibus setup.
1500          */
1501         switch (sc->sk_type) {
1502         case SK_GENESIS:
1503                 sk_init_xmac(sc_if);
1504                 break;
1505         case SK_YUKON:
1506                 sk_init_yukon(sc_if);
1507                 break;
1508         }
1509
1510         if (mii_phy_probe(dev, &sc_if->sk_miibus,
1511             sk_ifmedia_upd, sk_ifmedia_sts)) {
1512                 printf("skc%d: no PHY found!\n", sc_if->sk_unit);
1513                 contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM,
1514                     M_DEVBUF);
1515                 contigfree(sc_if->sk_rdata,
1516                     sizeof(struct sk_ring_data), M_DEVBUF);
1517                 return(ENXIO);
1518         }
1519
1520         /*
1521          * Call MI attach routine.
1522          */
1523         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr);
1524         callout_handle_init(&sc_if->sk_tick_ch);
1525
1526         return(0);
1527 }
1528
1529 /*
1530  * Attach the interface. Allocate softc structures, do ifmedia
1531  * setup and ethernet/BPF attach.
1532  */
1533 static int skc_attach(dev)
1534         device_t                dev;
1535 {
1536         int                     s;
1537         u_int32_t               command;
1538         struct sk_softc         *sc;
1539         int                     unit, error = 0, rid, *port;
1540
1541         s = splimp();
1542
1543         sc = device_get_softc(dev);
1544         unit = device_get_unit(dev);
1545         bzero(sc, sizeof(struct sk_softc));
1546         switch (pci_get_device(dev)) {
1547         case DEVICEID_SK_V1:
1548                 sc->sk_type = SK_GENESIS;
1549                 break;
1550         case DEVICEID_SK_V2:
1551         case DEVICEID_3COM_3C940:
1552                 sc->sk_type = SK_YUKON;
1553                 break;
1554         }
1555
1556         /*
1557          * Handle power management nonsense.
1558          */
1559         command = pci_read_config(dev, SK_PCI_CAPID, 4) & 0x000000FF;
1560         if (command == 0x01) {
1561                 command = pci_read_config(dev, SK_PCI_PWRMGMTCTRL, 4);
1562                 if (command & SK_PSTATE_MASK) {
1563                         u_int32_t               iobase, membase, irq;
1564
1565                         /* Save important PCI config data. */
1566                         iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1567                         membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1568                         irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1569
1570                         /* Reset the power state. */
1571                         printf("skc%d: chip is in D%d power mode "
1572                         "-- setting to D0\n", unit, command & SK_PSTATE_MASK);
1573                         command &= 0xFFFFFFFC;
1574                         pci_write_config(dev, SK_PCI_PWRMGMTCTRL, command, 4);
1575
1576                         /* Restore PCI config data. */
1577                         pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1578                         pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1579                         pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1580                 }
1581         }
1582
1583         /*
1584          * Map control/status registers.
1585          */
1586         command = pci_read_config(dev, PCIR_COMMAND, 4);
1587         command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1588         pci_write_config(dev, PCIR_COMMAND, command, 4);
1589         command = pci_read_config(dev, PCIR_COMMAND, 4);
1590
1591 #ifdef SK_USEIOSPACE
1592         if (!(command & PCIM_CMD_PORTEN)) {
1593                 printf("skc%d: failed to enable I/O ports!\n", unit);
1594                 error = ENXIO;
1595                 goto fail;
1596         }
1597 #else
1598         if (!(command & PCIM_CMD_MEMEN)) {
1599                 printf("skc%d: failed to enable memory mapping!\n", unit);
1600                 error = ENXIO;
1601                 goto fail;
1602         }
1603 #endif
1604
1605         rid = SK_RID;
1606         sc->sk_res = bus_alloc_resource(dev, SK_RES, &rid,
1607             0, ~0, 1, RF_ACTIVE);
1608
1609         if (sc->sk_res == NULL) {
1610                 printf("sk%d: couldn't map ports/memory\n", unit);
1611                 error = ENXIO;
1612                 goto fail;
1613         }
1614
1615         sc->sk_btag = rman_get_bustag(sc->sk_res);
1616         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1617
1618         /* Allocate interrupt */
1619         rid = 0;
1620         sc->sk_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1621             RF_SHAREABLE | RF_ACTIVE);
1622
1623         if (sc->sk_irq == NULL) {
1624                 printf("skc%d: couldn't map interrupt\n", unit);
1625                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1626                 error = ENXIO;
1627                 goto fail;
1628         }
1629
1630         error = bus_setup_intr(dev, sc->sk_irq, INTR_TYPE_NET,
1631             sk_intr, sc, &sc->sk_intrhand);
1632
1633         if (error) {
1634                 printf("skc%d: couldn't set up irq\n", unit);
1635                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1636                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1637                 goto fail;
1638         }
1639
1640         /* Reset the adapter. */
1641         sk_reset(sc);
1642
1643         sc->sk_unit = unit;
1644
1645         /* Read and save vital product data from EEPROM. */
1646         sk_vpd_read(sc);
1647
1648         if (sc->sk_type == SK_GENESIS) {
1649                 /* Read and save RAM size and RAMbuffer offset */
1650                 switch(sk_win_read_1(sc, SK_EPROM0)) {
1651                 case SK_RAMSIZE_512K_64:
1652                         sc->sk_ramsize = 0x80000;
1653                         sc->sk_rboff = SK_RBOFF_0;
1654                         break;
1655                 case SK_RAMSIZE_1024K_64:
1656                         sc->sk_ramsize = 0x100000;
1657                         sc->sk_rboff = SK_RBOFF_80000;
1658                         break;
1659                 case SK_RAMSIZE_1024K_128:
1660                         sc->sk_ramsize = 0x100000;
1661                         sc->sk_rboff = SK_RBOFF_0;
1662                         break;
1663                 case SK_RAMSIZE_2048K_128:
1664                         sc->sk_ramsize = 0x200000;
1665                         sc->sk_rboff = SK_RBOFF_0;
1666                         break;
1667                 default:
1668                         printf("skc%d: unknown ram size: %d\n",
1669                             sc->sk_unit, sk_win_read_1(sc, SK_EPROM0));
1670                         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1671                         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1672                         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1673                         error = ENXIO;
1674                         goto fail;
1675                         break;
1676                 }
1677         } else {
1678                 sc->sk_ramsize = 0x20000;
1679                 sc->sk_rboff = SK_RBOFF_0;
1680         }
1681
1682         /* Read and save physical media type */
1683         switch(sk_win_read_1(sc, SK_PMDTYPE)) {
1684         case SK_PMD_1000BASESX:
1685                 sc->sk_pmd = IFM_1000_SX;
1686                 break;
1687         case SK_PMD_1000BASELX:
1688                 sc->sk_pmd = IFM_1000_LX;
1689                 break;
1690         case SK_PMD_1000BASECX:
1691                 sc->sk_pmd = IFM_1000_CX;
1692                 break;
1693         case SK_PMD_1000BASETX:
1694                 sc->sk_pmd = IFM_1000_TX;
1695                 break;
1696         default:
1697                 printf("skc%d: unknown media type: 0x%x\n",
1698                     sc->sk_unit, sk_win_read_1(sc, SK_PMDTYPE));
1699                 bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1700                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1701                 bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1702                 error = ENXIO;
1703                 goto fail;
1704         }
1705
1706         /* Announce the product name. */
1707         printf("skc%d: %s\n", sc->sk_unit, sc->sk_vpd_prodname);
1708         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1709         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1710         *port = SK_PORT_A;
1711         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1712
1713         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1714                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1715                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1716                 *port = SK_PORT_B;
1717                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1718         }
1719
1720         /* Turn on the 'driver is loaded' LED. */
1721         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1722
1723         bus_generic_attach(dev);
1724
1725 fail:
1726         splx(s);
1727         return(error);
1728 }
1729
1730 static int sk_detach(dev)
1731         device_t                dev;
1732 {
1733         struct sk_softc         *sc;
1734         struct sk_if_softc      *sc_if;
1735         struct ifnet            *ifp;
1736         int                     s;
1737
1738         s = splimp();
1739
1740         sc = device_get_softc(device_get_parent(dev));
1741         sc_if = device_get_softc(dev);
1742         ifp = &sc_if->arpcom.ac_if;
1743         sk_stop(sc_if);
1744         ether_ifdetach(ifp);
1745         bus_generic_detach(dev);
1746         if (sc_if->sk_miibus != NULL)
1747                 device_delete_child(dev, sc_if->sk_miibus);
1748         contigfree(sc_if->sk_cdata.sk_jumbo_buf, SK_JMEM, M_DEVBUF);
1749         contigfree(sc_if->sk_rdata, sizeof(struct sk_ring_data), M_DEVBUF);
1750
1751         return(0);
1752 }
1753
1754 static int skc_detach(dev)
1755         device_t                dev;
1756 {
1757         struct sk_softc         *sc;
1758         int                     s;
1759
1760         s = splimp();
1761
1762         sc = device_get_softc(dev);
1763
1764         bus_generic_detach(dev);
1765         if (sc->sk_devs[SK_PORT_A] != NULL)
1766                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1767         if (sc->sk_devs[SK_PORT_B] != NULL)
1768                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1769
1770         bus_teardown_intr(dev, sc->sk_irq, sc->sk_intrhand);
1771         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sk_irq);
1772         bus_release_resource(dev, SK_RES, SK_RID, sc->sk_res);
1773
1774         splx(s);
1775
1776         return(0);
1777 }
1778
1779 static int sk_encap(sc_if, m_head, txidx)
1780         struct sk_if_softc      *sc_if;
1781         struct mbuf             *m_head;
1782         u_int32_t               *txidx;
1783 {
1784         struct sk_tx_desc       *f = NULL;
1785         struct mbuf             *m;
1786         u_int32_t               frag, cur, cnt = 0;
1787
1788         m = m_head;
1789         cur = frag = *txidx;
1790
1791         /*
1792          * Start packing the mbufs in this chain into
1793          * the fragment pointers. Stop when we run out
1794          * of fragments or hit the end of the mbuf chain.
1795          */
1796         for (m = m_head; m != NULL; m = m->m_next) {
1797                 if (m->m_len != 0) {
1798                         if ((SK_TX_RING_CNT -
1799                             (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2)
1800                                 return(ENOBUFS);
1801                         f = &sc_if->sk_rdata->sk_tx_ring[frag];
1802                         f->sk_data_lo = vtophys(mtod(m, vm_offset_t));
1803                         f->sk_ctl = m->m_len | SK_OPCODE_DEFAULT;
1804                         if (cnt == 0)
1805                                 f->sk_ctl |= SK_TXCTL_FIRSTFRAG;
1806                         else
1807                                 f->sk_ctl |= SK_TXCTL_OWN;
1808                         cur = frag;
1809                         SK_INC(frag, SK_TX_RING_CNT);
1810                         cnt++;
1811                 }
1812         }
1813
1814         if (m != NULL)
1815                 return(ENOBUFS);
1816
1817         sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1818                 SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR;
1819         sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1820         sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |= SK_TXCTL_OWN;
1821         sc_if->sk_cdata.sk_tx_cnt += cnt;
1822
1823         *txidx = frag;
1824
1825         return(0);
1826 }
1827
1828 static void sk_start(ifp)
1829         struct ifnet            *ifp;
1830 {
1831         struct sk_softc         *sc;
1832         struct sk_if_softc      *sc_if;
1833         struct mbuf             *m_head = NULL;
1834         u_int32_t               idx;
1835
1836         sc_if = ifp->if_softc;
1837         sc = sc_if->sk_softc;
1838
1839         idx = sc_if->sk_cdata.sk_tx_prod;
1840
1841         while(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1842                 IF_DEQUEUE(&ifp->if_snd, m_head);
1843                 if (m_head == NULL)
1844                         break;
1845
1846                 /*
1847                  * Pack the data into the transmit ring. If we
1848                  * don't have room, set the OACTIVE flag and wait
1849                  * for the NIC to drain the ring.
1850                  */
1851                 if (sk_encap(sc_if, m_head, &idx)) {
1852                         IF_PREPEND(&ifp->if_snd, m_head);
1853                         ifp->if_flags |= IFF_OACTIVE;
1854                         break;
1855                 }
1856
1857                 /*
1858                  * If there's a BPF listener, bounce a copy of this frame
1859                  * to him.
1860                  */
1861                 if (ifp->if_bpf)
1862                         bpf_mtap(ifp, m_head);
1863         }
1864
1865         /* Transmit */
1866         sc_if->sk_cdata.sk_tx_prod = idx;
1867         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1868
1869         /* Set a timeout in case the chip goes out to lunch. */
1870         ifp->if_timer = 5;
1871
1872         return;
1873 }
1874
1875
1876 static void sk_watchdog(ifp)
1877         struct ifnet            *ifp;
1878 {
1879         struct sk_if_softc      *sc_if;
1880
1881         sc_if = ifp->if_softc;
1882
1883         printf("sk%d: watchdog timeout\n", sc_if->sk_unit);
1884         sk_init(sc_if);
1885
1886         return;
1887 }
1888
1889 static void skc_shutdown(dev)
1890         device_t                dev;
1891 {
1892         struct sk_softc         *sc;
1893
1894         sc = device_get_softc(dev);
1895
1896         /* Turn off the 'driver is loaded' LED. */
1897         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1898
1899         /*
1900          * Reset the GEnesis controller. Doing this should also
1901          * assert the resets on the attached XMAC(s).
1902          */
1903         sk_reset(sc);
1904
1905         return;
1906 }
1907
1908 static void sk_rxeof(sc_if)
1909         struct sk_if_softc      *sc_if;
1910 {
1911         struct ether_header     *eh;
1912         struct mbuf             *m;
1913         struct ifnet            *ifp;
1914         struct sk_chain         *cur_rx;
1915         int                     total_len = 0;
1916         int                     i;
1917         u_int32_t               rxstat;
1918
1919         ifp = &sc_if->arpcom.ac_if;
1920         i = sc_if->sk_cdata.sk_rx_prod;
1921         cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1922
1923         while(!(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl & SK_RXCTL_OWN)) {
1924
1925                 cur_rx = &sc_if->sk_cdata.sk_rx_chain[i];
1926                 rxstat = sc_if->sk_rdata->sk_rx_ring[i].sk_xmac_rxstat;
1927                 m = cur_rx->sk_mbuf;
1928                 cur_rx->sk_mbuf = NULL;
1929                 total_len = SK_RXBYTES(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
1930                 SK_INC(i, SK_RX_RING_CNT);
1931
1932                 if (rxstat & XM_RXSTAT_ERRFRAME) {
1933                         ifp->if_ierrors++;
1934                         sk_newbuf(sc_if, cur_rx, m);
1935                         continue;
1936                 }
1937
1938                 /*
1939                  * Try to allocate a new jumbo buffer. If that
1940                  * fails, copy the packet to mbufs and put the
1941                  * jumbo buffer back in the ring so it can be
1942                  * re-used. If allocating mbufs fails, then we
1943                  * have to drop the packet.
1944                  */
1945                 if (sk_newbuf(sc_if, cur_rx, NULL) == ENOBUFS) {
1946                         struct mbuf             *m0;
1947                         m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1948                             total_len + ETHER_ALIGN, 0, ifp, NULL);
1949                         sk_newbuf(sc_if, cur_rx, m);
1950                         if (m0 == NULL) {
1951                                 printf("sk%d: no receive buffers "
1952                                     "available -- packet dropped!\n",
1953                                     sc_if->sk_unit);
1954                                 ifp->if_ierrors++;
1955                                 continue;
1956                         }
1957                         m_adj(m0, ETHER_ALIGN);
1958                         m = m0;
1959                 } else {
1960                         m->m_pkthdr.rcvif = ifp;
1961                         m->m_pkthdr.len = m->m_len = total_len;
1962                 }
1963
1964                 ifp->if_ipackets++;
1965                 eh = mtod(m, struct ether_header *);
1966
1967                 /* Remove header from mbuf and pass it on. */
1968                 m_adj(m, sizeof(struct ether_header));
1969                 ether_input(ifp, eh, m);
1970         }
1971
1972         sc_if->sk_cdata.sk_rx_prod = i;
1973
1974         return;
1975 }
1976
1977 static void sk_txeof(sc_if)
1978         struct sk_if_softc      *sc_if;
1979 {
1980         struct sk_tx_desc       *cur_tx = NULL;
1981         struct ifnet            *ifp;
1982         u_int32_t               idx;
1983
1984         ifp = &sc_if->arpcom.ac_if;
1985
1986         /*
1987          * Go through our tx ring and free mbufs for those
1988          * frames that have been sent.
1989          */
1990         idx = sc_if->sk_cdata.sk_tx_cons;
1991         while(idx != sc_if->sk_cdata.sk_tx_prod) {
1992                 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1993                 if (cur_tx->sk_ctl & SK_TXCTL_OWN)
1994                         break;
1995                 if (cur_tx->sk_ctl & SK_TXCTL_LASTFRAG)
1996                         ifp->if_opackets++;
1997                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1998                         m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1999                         sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2000                 }
2001                 sc_if->sk_cdata.sk_tx_cnt--;
2002                 SK_INC(idx, SK_TX_RING_CNT);
2003                 ifp->if_timer = 0;
2004         }
2005
2006         sc_if->sk_cdata.sk_tx_cons = idx;
2007
2008         if (cur_tx != NULL)
2009                 ifp->if_flags &= ~IFF_OACTIVE;
2010
2011         return;
2012 }
2013
2014 static void sk_tick(xsc_if)
2015         void                    *xsc_if;
2016 {
2017         struct sk_if_softc      *sc_if;
2018         struct mii_data         *mii;
2019         struct ifnet            *ifp;
2020         int                     i;
2021
2022         sc_if = xsc_if;
2023         ifp = &sc_if->arpcom.ac_if;
2024         mii = device_get_softc(sc_if->sk_miibus);
2025
2026         if (!(ifp->if_flags & IFF_UP))
2027                 return;
2028
2029         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2030                 sk_intr_bcom(sc_if);
2031                 return;
2032         }
2033
2034         /*
2035          * According to SysKonnect, the correct way to verify that
2036          * the link has come back up is to poll bit 0 of the GPIO
2037          * register three times. This pin has the signal from the
2038          * link_sync pin connected to it; if we read the same link
2039          * state 3 times in a row, we know the link is up.
2040          */
2041         for (i = 0; i < 3; i++) {
2042                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2043                         break;
2044         }
2045
2046         if (i != 3) {
2047                 sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2048                 return;
2049         }
2050
2051         /* Turn the GP0 interrupt back on. */
2052         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2053         SK_XM_READ_2(sc_if, XM_ISR);
2054         mii_tick(mii);
2055         mii_pollstat(mii);
2056         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2057
2058         return;
2059 }
2060
2061 static void sk_intr_bcom(sc_if)
2062         struct sk_if_softc      *sc_if;
2063 {
2064         struct sk_softc         *sc;
2065         struct mii_data         *mii;
2066         struct ifnet            *ifp;
2067         int                     status;
2068
2069         sc = sc_if->sk_softc;
2070         mii = device_get_softc(sc_if->sk_miibus);
2071         ifp = &sc_if->arpcom.ac_if;
2072
2073         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2074
2075         /*
2076          * Read the PHY interrupt register to make sure
2077          * we clear any pending interrupts.
2078          */
2079         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2080
2081         if (!(ifp->if_flags & IFF_RUNNING)) {
2082                 sk_init_xmac(sc_if);
2083                 return;
2084         }
2085
2086         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2087                 int                     lstat;
2088                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2089                     BRGPHY_MII_AUXSTS);
2090
2091                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2092                         mii_mediachg(mii);
2093                         /* Turn off the link LED. */
2094                         SK_IF_WRITE_1(sc_if, 0,
2095                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2096                         sc_if->sk_link = 0;
2097                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2098                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2099                             BRGPHY_MII_IMR, 0xFF00);
2100                         mii_tick(mii);
2101                         sc_if->sk_link = 1;
2102                         /* Turn on the link LED. */
2103                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2104                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2105                             SK_LINKLED_BLINK_OFF);
2106                         mii_pollstat(mii);
2107                 } else {
2108                         mii_tick(mii);
2109                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2110                 }
2111         }
2112
2113         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2114
2115         return;
2116 }
2117
2118 static void sk_intr_xmac(sc_if)
2119         struct sk_if_softc      *sc_if;
2120 {
2121         struct sk_softc         *sc;
2122         u_int16_t               status;
2123         struct mii_data         *mii;
2124
2125         sc = sc_if->sk_softc;
2126         mii = device_get_softc(sc_if->sk_miibus);
2127         status = SK_XM_READ_2(sc_if, XM_ISR);
2128
2129         /*
2130          * Link has gone down. Start MII tick timeout to
2131          * watch for link resync.
2132          */
2133         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2134                 if (status & XM_ISR_GP0_SET) {
2135                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2136                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2137                 }
2138
2139                 if (status & XM_ISR_AUTONEG_DONE) {
2140                         sc_if->sk_tick_ch = timeout(sk_tick, sc_if, hz);
2141                 }
2142         }
2143
2144         if (status & XM_IMR_TX_UNDERRUN)
2145                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2146
2147         if (status & XM_IMR_RX_OVERRUN)
2148                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2149
2150         status = SK_XM_READ_2(sc_if, XM_ISR);
2151
2152         return;
2153 }
2154
2155 static void sk_intr_yukon(sc_if)
2156         struct sk_if_softc      *sc_if;
2157 {
2158         int status;
2159
2160         status = SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2161
2162         return;
2163 }
2164
2165 static void sk_intr(xsc)
2166         void                    *xsc;
2167 {
2168         struct sk_softc         *sc = xsc;
2169         struct sk_if_softc      *sc_if0 = NULL, *sc_if1 = NULL;
2170         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2171         u_int32_t               status;
2172
2173         sc_if0 = sc->sk_if[SK_PORT_A];
2174         sc_if1 = sc->sk_if[SK_PORT_B];
2175
2176         if (sc_if0 != NULL)
2177                 ifp0 = &sc_if0->arpcom.ac_if;
2178         if (sc_if1 != NULL)
2179                 ifp1 = &sc_if1->arpcom.ac_if;
2180
2181         for (;;) {
2182                 status = CSR_READ_4(sc, SK_ISSR);
2183                 if (!(status & sc->sk_intrmask))
2184                         break;
2185
2186                 /* Handle receive interrupts first. */
2187                 if (status & SK_ISR_RX1_EOF) {
2188                         sk_rxeof(sc_if0);
2189                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2190                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2191                 }
2192                 if (status & SK_ISR_RX2_EOF) {
2193                         sk_rxeof(sc_if1);
2194                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2195                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2196                 }
2197
2198                 /* Then transmit interrupts. */
2199                 if (status & SK_ISR_TX1_S_EOF) {
2200                         sk_txeof(sc_if0);
2201                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2202                             SK_TXBMU_CLR_IRQ_EOF);
2203                 }
2204                 if (status & SK_ISR_TX2_S_EOF) {
2205                         sk_txeof(sc_if1);
2206                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2207                             SK_TXBMU_CLR_IRQ_EOF);
2208                 }
2209
2210                 /* Then MAC interrupts. */
2211                 if (status & SK_ISR_MAC1 && ifp0->if_flags & IFF_RUNNING) {
2212                         if (sc->sk_type == SK_GENESIS)
2213                                 sk_intr_xmac(sc_if0);
2214                         else
2215                                 sk_intr_yukon(sc_if0);
2216                 }
2217
2218                 if (status & SK_ISR_MAC2 && ifp1->if_flags & IFF_RUNNING) {
2219                         if (sc->sk_type == SK_GENESIS)
2220                                 sk_intr_xmac(sc_if1);
2221                         else
2222                                 sk_intr_yukon(sc_if0);
2223                 }
2224
2225                 if (status & SK_ISR_EXTERNAL_REG) {
2226                         if (ifp0 != NULL &&
2227                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2228                                 sk_intr_bcom(sc_if0);
2229                         if (ifp1 != NULL &&
2230                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2231                                 sk_intr_bcom(sc_if1);
2232                 }
2233         }
2234
2235         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2236
2237         if (ifp0 != NULL && ifp0->if_snd.ifq_head != NULL)
2238                 sk_start(ifp0);
2239         if (ifp1 != NULL && ifp1->if_snd.ifq_head != NULL)
2240                 sk_start(ifp1);
2241
2242         return;
2243 }
2244
2245 static void sk_init_xmac(sc_if)
2246         struct sk_if_softc      *sc_if;
2247 {
2248         struct sk_softc         *sc;
2249         struct ifnet            *ifp;
2250         struct sk_bcom_hack     bhack[] = {
2251         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2252         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2253         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2254         { 0, 0 } };
2255
2256         sc = sc_if->sk_softc;
2257         ifp = &sc_if->arpcom.ac_if;
2258
2259         /* Unreset the XMAC. */
2260         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2261         DELAY(1000);
2262
2263         /* Reset the XMAC's internal state. */
2264         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2265
2266         /* Save the XMAC II revision */
2267         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2268
2269         /*
2270          * Perform additional initialization for external PHYs,
2271          * namely for the 1000baseTX cards that use the XMAC's
2272          * GMII mode.
2273          */
2274         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2275                 int                     i = 0;
2276                 u_int32_t               val;
2277
2278                 /* Take PHY out of reset. */
2279                 val = sk_win_read_4(sc, SK_GPIO);
2280                 if (sc_if->sk_port == SK_PORT_A)
2281                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2282                 else
2283                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2284                 sk_win_write_4(sc, SK_GPIO, val);
2285
2286                 /* Enable GMII mode on the XMAC. */
2287                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2288
2289                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2290                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2291                 DELAY(10000);
2292                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2293                     BRGPHY_MII_IMR, 0xFFF0);
2294
2295                 /*
2296                  * Early versions of the BCM5400 apparently have
2297                  * a bug that requires them to have their reserved
2298                  * registers initialized to some magic values. I don't
2299                  * know what the numbers do, I'm just the messenger.
2300                  */
2301                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2302                     == 0x6041) {
2303                         while(bhack[i].reg) {
2304                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2305                                     bhack[i].reg, bhack[i].val);
2306                                 i++;
2307                         }
2308                 }
2309         }
2310
2311         /* Set station address */
2312         SK_XM_WRITE_2(sc_if, XM_PAR0,
2313             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2314         SK_XM_WRITE_2(sc_if, XM_PAR1,
2315             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2316         SK_XM_WRITE_2(sc_if, XM_PAR2,
2317             *(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2318         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2319
2320         if (ifp->if_flags & IFF_BROADCAST) {
2321                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2322         } else {
2323                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2324         }
2325
2326         /* We don't need the FCS appended to the packet. */
2327         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2328
2329         /* We want short frames padded to 60 bytes. */
2330         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2331
2332         /*
2333          * Enable the reception of all error frames. This is is
2334          * a necessary evil due to the design of the XMAC. The
2335          * XMAC's receive FIFO is only 8K in size, however jumbo
2336          * frames can be up to 9000 bytes in length. When bad
2337          * frame filtering is enabled, the XMAC's RX FIFO operates
2338          * in 'store and forward' mode. For this to work, the
2339          * entire frame has to fit into the FIFO, but that means
2340          * that jumbo frames larger than 8192 bytes will be
2341          * truncated. Disabling all bad frame filtering causes
2342          * the RX FIFO to operate in streaming mode, in which
2343          * case the XMAC will start transfering frames out of the
2344          * RX FIFO as soon as the FIFO threshold is reached.
2345          */
2346         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2347             XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2348             XM_MODE_RX_INRANGELEN);
2349
2350         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2351                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2352         else
2353                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2354
2355         /*
2356          * Bump up the transmit threshold. This helps hold off transmit
2357          * underruns when we're blasting traffic from both ports at once.
2358          */
2359         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2360
2361         /* Set promiscuous mode */
2362         sk_setpromisc(sc_if);
2363
2364         /* Set multicast filter */
2365         sk_setmulti(sc_if);
2366
2367         /* Clear and enable interrupts */
2368         SK_XM_READ_2(sc_if, XM_ISR);
2369         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2370                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2371         else
2372                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2373
2374         /* Configure MAC arbiter */
2375         switch(sc_if->sk_xmac_rev) {
2376         case XM_XMAC_REV_B2:
2377                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2378                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2379                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2380                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2381                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2382                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2383                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2384                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2385                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2386                 break;
2387         case XM_XMAC_REV_C1:
2388                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2389                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2390                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2391                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2392                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2393                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2394                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2395                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2396                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2397                 break;
2398         default:
2399                 break;
2400         }
2401         sk_win_write_2(sc, SK_MACARB_CTL,
2402             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2403
2404         sc_if->sk_link = 1;
2405
2406         return;
2407 }
2408
2409 static void sk_init_yukon(sc_if)
2410         struct sk_if_softc      *sc_if;
2411 {
2412         u_int32_t               phy;
2413         u_int16_t               reg;
2414         int                     i;
2415
2416         /* GMAC and GPHY Reset */
2417         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2418         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2419         DELAY(1000);
2420         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2421         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2422         DELAY(1000);
2423
2424         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2425                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2426
2427         switch(sc_if->sk_softc->sk_pmd) {
2428         case IFM_1000_SX:
2429         case IFM_1000_LX:
2430                 phy |= SK_GPHY_FIBER;
2431                 break;
2432
2433         case IFM_1000_CX:
2434         case IFM_1000_TX:
2435                 phy |= SK_GPHY_COPPER;
2436                 break;
2437         }
2438
2439         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2440         DELAY(1000);
2441         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2442         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2443                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2444
2445         /* unused read of the interrupt source register */
2446         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2447
2448         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2449
2450         /* MIB Counter Clear Mode set */
2451         reg |= YU_PAR_MIB_CLR;
2452         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2453
2454         /* MIB Counter Clear Mode clear */
2455         reg &= ~YU_PAR_MIB_CLR;
2456         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2457
2458         /* receive control reg */
2459         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2460
2461         /* transmit parameter register */
2462         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2463                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2464
2465         /* serial mode register */
2466         SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2467                       YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e));
2468
2469         /* Setup Yukon's address */
2470         for (i = 0; i < 3; i++) {
2471                 /* Write Source Address 1 (unicast filter) */
2472                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2473                               sc_if->arpcom.ac_enaddr[i * 2] |
2474                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2475         }
2476
2477         for (i = 0; i < 3; i++) {
2478                 reg = sk_win_read_2(sc_if->sk_softc,
2479                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2480                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2481         }
2482
2483         /* Set promiscuous mode */
2484         sk_setpromisc(sc_if);
2485
2486         /* Set multicast filter */
2487         sk_setmulti(sc_if);
2488
2489         /* enable interrupt mask for counter overflows */
2490         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2491         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2492         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2493
2494         /* Configure RX MAC FIFO */
2495         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2496         SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2497
2498         /* Configure TX MAC FIFO */
2499         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2500         SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2501 }
2502
2503 /*
2504  * Note that to properly initialize any part of the GEnesis chip,
2505  * you first have to take it out of reset mode.
2506  */
2507 static void sk_init(xsc)
2508         void                    *xsc;
2509 {
2510         struct sk_if_softc      *sc_if = xsc;
2511         struct sk_softc         *sc;
2512         struct ifnet            *ifp;
2513         struct mii_data         *mii;
2514         int                     s;
2515         u_int16_t               reg;
2516
2517         s = splimp();
2518
2519         ifp = &sc_if->arpcom.ac_if;
2520         sc = sc_if->sk_softc;
2521         mii = device_get_softc(sc_if->sk_miibus);
2522
2523         /* Cancel pending I/O and free all RX/TX buffers. */
2524         sk_stop(sc_if);
2525
2526         if (sc->sk_type == SK_GENESIS) {
2527                 /* Configure LINK_SYNC LED */
2528                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2529                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2530                         SK_LINKLED_LINKSYNC_ON);
2531
2532                 /* Configure RX LED */
2533                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2534                         SK_RXLEDCTL_COUNTER_START);
2535
2536                 /* Configure TX LED */
2537                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2538                         SK_TXLEDCTL_COUNTER_START);
2539         }
2540
2541         /* Configure I2C registers */
2542
2543         /* Configure XMAC(s) */
2544         switch (sc->sk_type) {
2545         case SK_GENESIS:
2546                 sk_init_xmac(sc_if);
2547                 break;
2548         case SK_YUKON:
2549                 sk_init_yukon(sc_if);
2550                 break;
2551         }
2552         mii_mediachg(mii);
2553
2554         if (sc->sk_type == SK_GENESIS) {
2555                 /* Configure MAC FIFOs */
2556                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2557                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2558                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2559
2560                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2561                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2562                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2563         }
2564
2565         /* Configure transmit arbiter(s) */
2566         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2567             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2568
2569         /* Configure RAMbuffers */
2570         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2571         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2572         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2573         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2574         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2575         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2576
2577         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2578         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2579         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2580         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2581         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2582         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2583         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2584
2585         /* Configure BMUs */
2586         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2587         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2588             vtophys(&sc_if->sk_rdata->sk_rx_ring[0]));
2589         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2590
2591         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2592         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2593             vtophys(&sc_if->sk_rdata->sk_tx_ring[0]));
2594         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2595
2596         /* Init descriptors */
2597         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2598                 printf("sk%d: initialization failed: no "
2599                     "memory for rx buffers\n", sc_if->sk_unit);
2600                 sk_stop(sc_if);
2601                 (void)splx(s);
2602                 return;
2603         }
2604         sk_init_tx_ring(sc_if);
2605
2606         /* Configure interrupt handling */
2607         CSR_READ_4(sc, SK_ISSR);
2608         if (sc_if->sk_port == SK_PORT_A)
2609                 sc->sk_intrmask |= SK_INTRS1;
2610         else
2611                 sc->sk_intrmask |= SK_INTRS2;
2612
2613         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2614
2615         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2616
2617         /* Start BMUs. */
2618         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2619
2620         switch(sc->sk_type) {
2621         case SK_GENESIS:
2622                 /* Enable XMACs TX and RX state machines */
2623                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2624                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2625                 break;
2626         case SK_YUKON:
2627                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2628                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2629                 reg &= ~(YU_GPCR_SPEED_EN | YU_GPCR_DPLX_EN);
2630                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2631         }
2632
2633         ifp->if_flags |= IFF_RUNNING;
2634         ifp->if_flags &= ~IFF_OACTIVE;
2635
2636         splx(s);
2637
2638         return;
2639 }
2640
2641 static void sk_stop(sc_if)
2642         struct sk_if_softc      *sc_if;
2643 {
2644         int                     i;
2645         struct sk_softc         *sc;
2646         struct ifnet            *ifp;
2647
2648         sc = sc_if->sk_softc;
2649         ifp = &sc_if->arpcom.ac_if;
2650
2651         untimeout(sk_tick, sc_if, sc_if->sk_tick_ch);
2652
2653         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2654                 u_int32_t               val;
2655
2656                 /* Put PHY back into reset. */
2657                 val = sk_win_read_4(sc, SK_GPIO);
2658                 if (sc_if->sk_port == SK_PORT_A) {
2659                         val |= SK_GPIO_DIR0;
2660                         val &= ~SK_GPIO_DAT0;
2661                 } else {
2662                         val |= SK_GPIO_DIR2;
2663                         val &= ~SK_GPIO_DAT2;
2664                 }
2665                 sk_win_write_4(sc, SK_GPIO, val);
2666         }
2667
2668         /* Turn off various components of this interface. */
2669         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2670         switch (sc->sk_type) {
2671         case SK_GENESIS:
2672                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2673                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2674                 break;
2675         case SK_YUKON:
2676                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2677                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2678                 break;
2679         }
2680         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2681         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2682         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2683         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2684         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2685         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2686         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2687         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2688         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2689
2690         /* Disable interrupts */
2691         if (sc_if->sk_port == SK_PORT_A)
2692                 sc->sk_intrmask &= ~SK_INTRS1;
2693         else
2694                 sc->sk_intrmask &= ~SK_INTRS2;
2695         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2696
2697         SK_XM_READ_2(sc_if, XM_ISR);
2698         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2699
2700         /* Free RX and TX mbufs still in the queues. */
2701         for (i = 0; i < SK_RX_RING_CNT; i++) {
2702                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2703                         m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2704                         sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2705                 }
2706         }
2707
2708         for (i = 0; i < SK_TX_RING_CNT; i++) {
2709                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2710                         m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2711                         sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2712                 }
2713         }
2714
2715         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2716
2717         return;
2718 }