2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.24 2005/12/31 14:07:59 sephe Exp $
31 * Myson fast ethernet PCI NIC driver
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
44 #include <sys/module.h>
45 #include <sys/serialize.h>
47 #include <sys/thread2.h>
50 #include <net/ifq_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_media.h>
54 #include <net/if_dl.h>
57 #include <vm/vm.h> /* for vtophys */
58 #include <vm/pmap.h> /* for vtophys */
59 #include <machine/clock.h> /* for DELAY */
60 #include <machine/bus_memio.h>
61 #include <machine/bus_pio.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
70 #include "../mii_layer/mii.h"
71 #include "../mii_layer/miivar.h"
73 #include "miibus_if.h"
76 * #define MY_USEIOSPACE
79 static int MY_USEIOSPACE = 1;
82 #define MY_RES SYS_RES_IOPORT
83 #define MY_RID MY_PCI_LOIO
85 #define MY_RES SYS_RES_MEMORY
86 #define MY_RID MY_PCI_LOMEM
93 * Various supported device vendors/types and their names.
95 static struct my_type my_devs[] = {
96 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
97 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
98 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
103 * Various supported PHY vendors/types and their names. Note that this driver
104 * will work with pretty much any MII-compliant PHY, so failure to positively
105 * identify the chip is not a fatal error.
107 static struct my_type my_phys[] = {
108 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
109 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
110 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
111 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
112 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
113 {0, 0, "<MII-compliant physical interface>"}
116 static int my_probe(device_t);
117 static int my_attach(device_t);
118 static int my_detach(device_t);
119 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
120 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
121 static void my_rxeof(struct my_softc *);
122 static void my_txeof(struct my_softc *);
123 static void my_txeoc(struct my_softc *);
124 static void my_intr(void *);
125 static void my_start(struct ifnet *);
126 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
127 static void my_init(void *);
128 static void my_stop(struct my_softc *);
129 static void my_watchdog(struct ifnet *);
130 static void my_shutdown(device_t);
131 static int my_ifmedia_upd(struct ifnet *);
132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static u_int16_t my_phy_readreg(struct my_softc *, int);
134 static void my_phy_writereg(struct my_softc *, int, int);
135 static void my_autoneg_xmit(struct my_softc *);
136 static void my_autoneg_mii(struct my_softc *, int, int);
137 static void my_setmode_mii(struct my_softc *, int);
138 static void my_getmode_mii(struct my_softc *);
139 static void my_setcfg(struct my_softc *, int);
140 static u_int8_t my_calchash(caddr_t);
141 static void my_setmulti(struct my_softc *);
142 static void my_reset(struct my_softc *);
143 static int my_list_rx_init(struct my_softc *);
144 static int my_list_tx_init(struct my_softc *);
145 static long my_send_cmd_to_phy(struct my_softc *, int, int);
147 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
148 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
150 static device_method_t my_methods[] = {
151 /* Device interface */
152 DEVMETHOD(device_probe, my_probe),
153 DEVMETHOD(device_attach, my_attach),
154 DEVMETHOD(device_detach, my_detach),
155 DEVMETHOD(device_shutdown, my_shutdown),
160 static driver_t my_driver = {
163 sizeof(struct my_softc)
166 static devclass_t my_devclass;
168 DECLARE_DUMMY_MODULE(if_my);
169 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
172 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
178 /* enable MII output */
179 miir = CSR_READ_4(sc, MY_MANAGEMENT);
182 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
184 /* send 32 1's preamble */
185 for (i = 0; i < 32; i++) {
186 /* low MDC; MDO is already high (miir) */
187 miir &= ~MY_MASK_MIIR_MII_MDC;
188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
191 miir |= MY_MASK_MIIR_MII_MDC;
192 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
195 /* calculate ST+OP+PHYAD+REGAD+TA */
196 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
201 /* low MDC, prepare MDO */
202 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
204 miir |= MY_MASK_MIIR_MII_MDO;
206 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
208 miir |= MY_MASK_MIIR_MII_MDC;
209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
214 if (mask == 0x2 && opcode == MY_OP_READ)
215 miir &= ~MY_MASK_MIIR_MII_WRITE;
223 my_phy_readreg(struct my_softc * sc, int reg)
228 if (sc->my_info->my_did == MTD803ID)
229 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
231 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
238 miir &= ~MY_MASK_MIIR_MII_MDC;
239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
242 miir = CSR_READ_4(sc, MY_MANAGEMENT);
243 if (miir & MY_MASK_MIIR_MII_MDI)
246 /* high MDC, and wait */
247 miir |= MY_MASK_MIIR_MII_MDC;
248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
256 miir &= ~MY_MASK_MIIR_MII_MDC;
257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
260 return (u_int16_t) data;
265 my_phy_writereg(struct my_softc * sc, int reg, int data)
270 if (sc->my_info->my_did == MTD803ID)
271 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
273 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
278 /* low MDC, prepare MDO */
279 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
281 miir |= MY_MASK_MIIR_MII_MDO;
282 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
286 miir |= MY_MASK_MIIR_MII_MDC;
287 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
295 miir &= ~MY_MASK_MIIR_MII_MDC;
296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
301 my_calchash(caddr_t addr)
303 u_int32_t crc, carry;
307 /* Compute CRC for the address value. */
308 crc = 0xFFFFFFFF; /* initial value */
310 for (i = 0; i < 6; i++) {
312 for (j = 0; j < 8; j++) {
313 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
317 crc = (crc ^ 0x04c11db6) | carry;
322 * return the filter bit position Note: I arrived at the following
323 * nonsense through experimentation. It's not the usual way to
324 * generate the bit position but it's the only thing I could come up
327 return (~(crc >> 26) & 0x0000003F);
332 * Program the 64-bit multicast hash filter.
335 my_setmulti(struct my_softc * sc)
337 struct ifnet *ifp = &sc->arpcom.ac_if;
339 u_int32_t hashes[2] = {0, 0};
340 struct ifmultiaddr *ifma;
344 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
346 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
348 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
349 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
350 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
354 /* first, zot all the existing hash bits */
355 CSR_WRITE_4(sc, MY_MAR0, 0);
356 CSR_WRITE_4(sc, MY_MAR1, 0);
358 /* now program new ones */
359 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
360 if (ifma->ifma_addr->sa_family != AF_LINK)
362 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
364 hashes[0] |= (1 << h);
366 hashes[1] |= (1 << (h - 32));
374 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
375 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
376 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
380 * Initiate an autonegotiation session.
383 my_autoneg_xmit(struct my_softc * sc)
385 u_int16_t phy_sts = 0;
387 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
389 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
391 phy_sts = my_phy_readreg(sc, PHY_BMCR);
392 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
393 my_phy_writereg(sc, PHY_BMCR, phy_sts);
398 * Invoke autonegotiation on a PHY.
401 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
403 u_int16_t phy_sts = 0, media, advert, ability;
404 u_int16_t ability2 = 0;
405 struct ifnet *ifp = &sc->arpcom.ac_if;
406 struct ifmedia *ifm = &sc->ifmedia;
408 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
410 #ifndef FORCE_AUTONEG_TFOUR
412 * First, see if autoneg is supported. If not, there's no point in
415 phy_sts = my_phy_readreg(sc, PHY_BMSR);
416 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
418 printf("my%d: autonegotiation not supported\n",
420 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
425 case MY_FLAG_FORCEDELAY:
427 * XXX Never use this option anywhere but in the probe
428 * routine: making the kernel stop dead in its tracks for
429 * three whole seconds after we've gone multi-user is really
435 case MY_FLAG_SCHEDDELAY:
437 * Wait for the transmitter to go idle before starting an
438 * autoneg session, otherwise my_start() may clobber our
439 * timeout, and we don't want to allow transmission during an
440 * autoneg session since that can screw it up.
442 if (sc->my_cdata.my_tx_head != NULL) {
443 sc->my_want_auto = 1;
449 sc->my_want_auto = 0;
451 case MY_FLAG_DELAYTIMEO:
456 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
460 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
462 printf("my%d: autoneg complete, ", sc->my_unit);
463 phy_sts = my_phy_readreg(sc, PHY_BMSR);
466 printf("my%d: autoneg not complete, ", sc->my_unit);
469 media = my_phy_readreg(sc, PHY_BMCR);
471 /* Link is good. Report modes and set duplex mode. */
472 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
474 printf("my%d: link status good. ", sc->my_unit);
475 advert = my_phy_readreg(sc, PHY_ANAR);
476 ability = my_phy_readreg(sc, PHY_LPAR);
477 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
478 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
479 ability2 = my_phy_readreg(sc, PHY_1000SR);
480 if (ability2 & PHY_1000SR_1000BTXFULL) {
484 * this version did not support 1000M,
486 * IFM_ETHER | IFM_1000_T | IFM_FDX;
489 IFM_ETHER | IFM_100_TX | IFM_FDX;
490 media &= ~PHY_BMCR_SPEEDSEL;
491 media |= PHY_BMCR_1000;
492 media |= PHY_BMCR_DUPLEX;
493 printf("(full-duplex, 1000Mbps)\n");
494 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
498 * this version did not support 1000M,
499 * ifm->ifm_media = IFM_ETHER | IFM_1000_T;
501 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
502 media &= ~PHY_BMCR_SPEEDSEL;
503 media &= ~PHY_BMCR_DUPLEX;
504 media |= PHY_BMCR_1000;
505 printf("(half-duplex, 1000Mbps)\n");
508 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
509 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
510 media |= PHY_BMCR_SPEEDSEL;
511 media &= ~PHY_BMCR_DUPLEX;
512 printf("(100baseT4)\n");
513 } else if (advert & PHY_ANAR_100BTXFULL &&
514 ability & PHY_ANAR_100BTXFULL) {
515 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
516 media |= PHY_BMCR_SPEEDSEL;
517 media |= PHY_BMCR_DUPLEX;
518 printf("(full-duplex, 100Mbps)\n");
519 } else if (advert & PHY_ANAR_100BTXHALF &&
520 ability & PHY_ANAR_100BTXHALF) {
521 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
522 media |= PHY_BMCR_SPEEDSEL;
523 media &= ~PHY_BMCR_DUPLEX;
524 printf("(half-duplex, 100Mbps)\n");
525 } else if (advert & PHY_ANAR_10BTFULL &&
526 ability & PHY_ANAR_10BTFULL) {
527 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
528 media &= ~PHY_BMCR_SPEEDSEL;
529 media |= PHY_BMCR_DUPLEX;
530 printf("(full-duplex, 10Mbps)\n");
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media &= ~PHY_BMCR_DUPLEX;
535 printf("(half-duplex, 10Mbps)\n");
537 media &= ~PHY_BMCR_AUTONEGENBL;
539 /* Set ASIC's duplex mode to match the PHY. */
540 my_phy_writereg(sc, PHY_BMCR, media);
541 my_setcfg(sc, media);
544 printf("my%d: no carrier\n", sc->my_unit);
548 if (sc->my_tx_pend) {
556 * To get PHY ability.
559 my_getmode_mii(struct my_softc * sc)
561 struct ifnet *ifp = &sc->arpcom.ac_if;
564 bmsr = my_phy_readreg(sc, PHY_BMSR);
566 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
569 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
571 if (bmsr & PHY_BMSR_10BTHALF) {
573 printf("my%d: 10Mbps half-duplex mode supported\n",
575 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
577 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
579 if (bmsr & PHY_BMSR_10BTFULL) {
581 printf("my%d: 10Mbps full-duplex mode supported\n",
584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
586 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
588 if (bmsr & PHY_BMSR_100BTXHALF) {
590 printf("my%d: 100Mbps half-duplex mode supported\n",
592 ifp->if_baudrate = 100000000;
593 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
598 if (bmsr & PHY_BMSR_100BTXFULL) {
600 printf("my%d: 100Mbps full-duplex mode supported\n",
602 ifp->if_baudrate = 100000000;
603 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
605 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
607 /* Some also support 100BaseT4. */
608 if (bmsr & PHY_BMSR_100BT4) {
610 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
611 ifp->if_baudrate = 100000000;
612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
613 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
614 #ifdef FORCE_AUTONEG_TFOUR
616 printf("my%d: forcing on autoneg support for BT4\n",
618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
619 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
622 #if 0 /* this version did not support 1000M, */
623 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
625 printf("my%d: 1000Mbps half-duplex mode supported\n",
628 ifp->if_baudrate = 1000000000;
629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
633 printf("my%d: 1000Mbps full-duplex mode supported\n",
635 ifp->if_baudrate = 1000000000;
636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
638 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
641 if (bmsr & PHY_BMSR_CANAUTONEG) {
643 printf("my%d: autoneg supported\n", sc->my_unit);
644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
645 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
650 * Set speed and duplex mode.
653 my_setmode_mii(struct my_softc * sc, int media)
655 struct ifnet *ifp = &sc->arpcom.ac_if;
659 * If an autoneg session is in progress, stop it.
661 if (sc->my_autoneg) {
662 printf("my%d: canceling autoneg session\n", sc->my_unit);
663 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
664 bmcr = my_phy_readreg(sc, PHY_BMCR);
665 bmcr &= ~PHY_BMCR_AUTONEGENBL;
666 my_phy_writereg(sc, PHY_BMCR, bmcr);
668 printf("my%d: selecting MII, ", sc->my_unit);
669 bmcr = my_phy_readreg(sc, PHY_BMCR);
670 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
671 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
673 #if 0 /* this version did not support 1000M, */
674 if (IFM_SUBTYPE(media) == IFM_1000_T) {
675 printf("1000Mbps/T4, half-duplex\n");
676 bmcr &= ~PHY_BMCR_SPEEDSEL;
677 bmcr &= ~PHY_BMCR_DUPLEX;
678 bmcr |= PHY_BMCR_1000;
681 if (IFM_SUBTYPE(media) == IFM_100_T4) {
682 printf("100Mbps/T4, half-duplex\n");
683 bmcr |= PHY_BMCR_SPEEDSEL;
684 bmcr &= ~PHY_BMCR_DUPLEX;
686 if (IFM_SUBTYPE(media) == IFM_100_TX) {
688 bmcr |= PHY_BMCR_SPEEDSEL;
690 if (IFM_SUBTYPE(media) == IFM_10_T) {
692 bmcr &= ~PHY_BMCR_SPEEDSEL;
694 if ((media & IFM_GMASK) == IFM_FDX) {
695 printf("full duplex\n");
696 bmcr |= PHY_BMCR_DUPLEX;
698 printf("half duplex\n");
699 bmcr &= ~PHY_BMCR_DUPLEX;
701 my_phy_writereg(sc, PHY_BMCR, bmcr);
706 * The Myson manual states that in order to fiddle with the 'full-duplex' and
707 * '100Mbps' bits in the netconfig register, we first have to put the
708 * transmit and/or receive logic in the idle state.
711 my_setcfg(struct my_softc * sc, int bmcr)
715 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
717 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
718 for (i = 0; i < MY_TIMEOUT; i++) {
720 if (!(CSR_READ_4(sc, MY_TCRRCR) &
721 (MY_TXRUN | MY_RXRUN)))
725 printf("my%d: failed to force tx and rx to idle \n",
728 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
729 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
730 if (bmcr & PHY_BMCR_1000)
731 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
732 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
733 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
734 if (bmcr & PHY_BMCR_DUPLEX)
735 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
737 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
739 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
743 my_reset(struct my_softc * sc)
747 MY_SETBIT(sc, MY_BCR, MY_SWR);
748 for (i = 0; i < MY_TIMEOUT; i++) {
750 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
754 printf("m0x%d: reset never completed!\n", sc->my_unit);
756 /* Wait a little while for the chip to get its brains in order. */
761 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
762 * list and return a device name if we find a match.
765 my_probe(device_t dev)
768 uint16_t vendor, product;
770 vendor = pci_get_vendor(dev);
771 product = pci_get_device(dev);
773 for (t = my_devs; t->my_name != NULL; t++) {
774 if (vendor == t->my_vid && product == t->my_did) {
775 device_set_desc(dev, t->my_name);
784 * Attach the interface. Allocate softc structures, do ifmedia setup and
785 * ethernet/BPF attach.
788 my_attach(device_t dev)
791 u_char eaddr[ETHER_ADDR_LEN];
792 u_int32_t command, iobase;
795 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
799 u_int16_t phy_vid, phy_did, phy_sts = 0;
800 int rid, unit, error = 0;
802 uint16_t vendor, product;
804 vendor = pci_get_vendor(dev);
805 product = pci_get_device(dev);
807 for (t = my_devs; t->my_name != NULL; t++) {
808 if (vendor == t->my_vid && product == t->my_did)
812 if (t->my_name == NULL)
815 sc = device_get_softc(dev);
816 unit = device_get_unit(dev);
819 * Map control/status registers.
821 command = pci_read_config(dev, PCIR_COMMAND, 4);
822 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
823 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
824 command = pci_read_config(dev, PCIR_COMMAND, 4);
826 if (t->my_did == MTD800ID) {
827 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
832 if (!(command & PCIM_CMD_PORTEN)) {
833 printf("my%d: failed to enable I/O ports!\n", unit);
838 if (!(command & PCIM_CMD_MEMEN)) {
839 printf("my%d: failed to enable memory mapping!\n",
847 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
849 if (sc->my_res == NULL) {
850 printf("my%d: couldn't map ports/memory\n", unit);
854 sc->my_btag = rman_get_bustag(sc->my_res);
855 sc->my_bhandle = rman_get_bushandle(sc->my_res);
858 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
859 RF_SHAREABLE | RF_ACTIVE);
861 if (sc->my_irq == NULL) {
862 printf("my%d: couldn't map interrupt\n", unit);
869 /* Reset the adapter. */
873 * Get station address
875 for (i = 0; i < ETHER_ADDR_LEN; ++i)
876 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
880 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
882 if (sc->my_ldata_ptr == NULL) {
883 printf("my%d: no memory for list buffers!\n", unit);
887 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
888 round = (unsigned int)sc->my_ldata_ptr & 0xF;
889 roundptr = sc->my_ldata_ptr;
890 for (i = 0; i < 8; i++) {
897 sc->my_ldata = (struct my_list_data *) roundptr;
898 bzero(sc->my_ldata, sizeof(struct my_list_data));
900 ifp = &sc->arpcom.ac_if;
902 if_initname(ifp, "my", unit);
903 ifp->if_mtu = ETHERMTU;
904 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
905 ifp->if_ioctl = my_ioctl;
906 ifp->if_start = my_start;
907 ifp->if_watchdog = my_watchdog;
908 ifp->if_init = my_init;
909 ifp->if_baudrate = 10000000;
910 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
911 ifq_set_ready(&ifp->if_snd);
913 if (sc->my_info->my_did == MTD803ID)
914 sc->my_pinfo = my_phys;
917 printf("my%d: probing for a PHY\n", sc->my_unit);
918 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
920 printf("my%d: checking address: %d\n",
923 phy_sts = my_phy_readreg(sc, PHY_BMSR);
924 if ((phy_sts != 0) && (phy_sts != 0xffff))
930 phy_vid = my_phy_readreg(sc, PHY_VENID);
931 phy_did = my_phy_readreg(sc, PHY_DEVID);
933 printf("my%d: found PHY at address %d, ",
934 sc->my_unit, sc->my_phy_addr);
935 printf("vendor id: %x device id: %x\n",
940 if (phy_vid == p->my_vid) {
946 if (sc->my_pinfo == NULL)
947 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
949 printf("my%d: PHY type: %s\n",
950 sc->my_unit, sc->my_pinfo->my_name);
952 printf("my%d: MII without any phy!\n", sc->my_unit);
958 /* Do ifmedia setup. */
959 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
961 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
962 media = sc->ifmedia.ifm_media;
964 ifmedia_set(&sc->ifmedia, media);
966 ether_ifattach(ifp, eaddr, NULL);
968 error = bus_setup_intr(dev, sc->my_irq, INTR_NETSAFE,
969 my_intr, sc, &sc->my_intrhand,
973 printf("my%d: couldn't set up irq\n", unit);
985 my_detach(device_t dev)
987 struct my_softc *sc = device_get_softc(dev);
988 struct ifnet *ifp = &sc->arpcom.ac_if;
990 if (device_is_attached(dev)) {
991 lwkt_serialize_enter(ifp->if_serializer);
993 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
994 lwkt_serialize_exit(ifp->if_serializer);
1000 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1002 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1009 * Initialize the transmit descriptors.
1012 my_list_tx_init(struct my_softc * sc)
1014 struct my_chain_data *cd;
1015 struct my_list_data *ld;
1020 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1021 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1022 if (i == (MY_TX_LIST_CNT - 1))
1023 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1025 cd->my_tx_chain[i].my_nextdesc =
1026 &cd->my_tx_chain[i + 1];
1028 cd->my_tx_free = &cd->my_tx_chain[0];
1029 cd->my_tx_tail = cd->my_tx_head = NULL;
1034 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1035 * arrange the descriptors in a closed ring, so that the last descriptor
1036 * points back to the first.
1039 my_list_rx_init(struct my_softc * sc)
1041 struct my_chain_data *cd;
1042 struct my_list_data *ld;
1047 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1048 cd->my_rx_chain[i].my_ptr =
1049 (struct my_desc *) & ld->my_rx_list[i];
1050 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1052 if (i == (MY_RX_LIST_CNT - 1)) {
1053 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1054 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1056 cd->my_rx_chain[i].my_nextdesc =
1057 &cd->my_rx_chain[i + 1];
1058 ld->my_rx_list[i].my_next =
1059 vtophys(&ld->my_rx_list[i + 1]);
1062 cd->my_rx_head = &cd->my_rx_chain[0];
1067 * Initialize an RX descriptor and attach an MBUF cluster.
1070 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1072 struct mbuf *m_new = NULL;
1074 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1075 if (m_new == NULL) {
1076 printf("my%d: no memory for rx list -- packet dropped!\n",
1080 MCLGET(m_new, MB_DONTWAIT);
1081 if (!(m_new->m_flags & M_EXT)) {
1082 printf("my%d: no memory for rx list -- packet dropped!\n",
1088 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1089 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1090 c->my_ptr->my_status = MY_OWNByNIC;
1095 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1099 my_rxeof(struct my_softc * sc)
1102 struct ifnet *ifp = &sc->arpcom.ac_if;
1103 struct my_chain_onefrag *cur_rx;
1107 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1109 cur_rx = sc->my_cdata.my_rx_head;
1110 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1112 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1114 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1117 /* No errors; receive the packet. */
1118 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1119 total_len -= ETHER_CRC_LEN;
1121 if (total_len < MINCLSIZE) {
1122 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1123 total_len, 0, ifp, NULL);
1124 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1130 m = cur_rx->my_mbuf;
1132 * Try to conjure up a new mbuf cluster. If that
1133 * fails, it means we have an out of memory condition
1134 * and should leave the buffer in place and continue.
1135 * This will result in a lost packet, but there's
1136 * little else we can do in this situation.
1138 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1140 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1143 m->m_pkthdr.rcvif = ifp;
1144 m->m_pkthdr.len = m->m_len = total_len;
1147 ifp->if_input(ifp, m);
1153 * A frame was downloaded to the chip. It's safe for us to clean up the list
1157 my_txeof(struct my_softc * sc)
1159 struct ifnet *ifp = &sc->arpcom.ac_if;
1160 struct my_chain *cur_tx;
1162 /* Clear the timeout timer. */
1164 if (sc->my_cdata.my_tx_head == NULL)
1167 * Go through our tx list and free mbufs for those frames that have
1170 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1173 cur_tx = sc->my_cdata.my_tx_head;
1174 txstat = MY_TXSTATUS(cur_tx);
1175 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1177 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1178 if (txstat & MY_TXERR) {
1180 if (txstat & MY_EC) /* excessive collision */
1181 ifp->if_collisions++;
1182 if (txstat & MY_LC) /* late collision */
1183 ifp->if_collisions++;
1185 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1189 m_freem(cur_tx->my_mbuf);
1190 cur_tx->my_mbuf = NULL;
1191 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1192 sc->my_cdata.my_tx_head = NULL;
1193 sc->my_cdata.my_tx_tail = NULL;
1196 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1198 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1199 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1204 * TX 'end of channel' interrupt handler.
1207 my_txeoc(struct my_softc * sc)
1209 struct ifnet *ifp = &sc->arpcom.ac_if;
1212 if (sc->my_cdata.my_tx_head == NULL) {
1213 ifp->if_flags &= ~IFF_OACTIVE;
1214 sc->my_cdata.my_tx_tail = NULL;
1215 if (sc->my_want_auto)
1216 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1218 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1219 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1221 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1229 struct my_softc *sc = arg;
1230 struct ifnet *ifp = &sc->arpcom.ac_if;
1233 if (!(ifp->if_flags & IFF_UP))
1236 /* Disable interrupts. */
1237 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1240 status = CSR_READ_4(sc, MY_ISR);
1243 CSR_WRITE_4(sc, MY_ISR, status);
1247 if (status & MY_RI) /* receive interrupt */
1250 if ((status & MY_RBU) || (status & MY_RxErr)) {
1251 /* rx buffer unavailable or rx error */
1259 if (status & MY_TI) /* tx interrupt */
1261 if (status & MY_ETI) /* tx early interrupt */
1263 if (status & MY_TBU) /* tx buffer unavailable */
1266 #if 0 /* 90/1/18 delete */
1267 if (status & MY_FBE) {
1275 /* Re-enable interrupts. */
1276 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1277 if (!ifq_is_empty(&ifp->if_snd))
1282 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1283 * pointers to the fragment pointers.
1286 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1288 struct my_desc *f = NULL;
1290 struct mbuf *m, *m_new = NULL;
1292 /* calculate the total tx pkt length */
1294 for (m = m_head; m != NULL; m = m->m_next)
1295 total_len += m->m_len;
1297 * Start packing the mbufs in this chain into the fragment pointers.
1298 * Stop when we run out of fragments or hit the end of the mbuf
1302 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1303 if (m_new == NULL) {
1304 printf("my%d: no memory for tx list", sc->my_unit);
1307 if (m_head->m_pkthdr.len > MHLEN) {
1308 MCLGET(m_new, MB_DONTWAIT);
1309 if (!(m_new->m_flags & M_EXT)) {
1311 printf("my%d: no memory for tx list", sc->my_unit);
1315 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1316 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1319 f = &c->my_ptr->my_frag[0];
1321 f->my_data = vtophys(mtod(m_new, caddr_t));
1322 total_len = m_new->m_len;
1323 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1324 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1325 f->my_ctl |= total_len; /* buffer size */
1326 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1327 if (sc->my_info->my_did == MTD891ID)
1328 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1329 c->my_mbuf = m_head;
1331 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1336 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1337 * to the mbuf data regions directly in the transmit lists. We also save a
1338 * copy of the pointers since the transmit list fragment pointers are
1339 * physical addresses.
1342 my_start(struct ifnet * ifp)
1344 struct my_softc *sc = ifp->if_softc;
1345 struct mbuf *m_head = NULL;
1346 struct my_chain *cur_tx = NULL, *start_tx;
1350 if (sc->my_autoneg) {
1356 * Check for an available queue slot. If there are none, punt.
1358 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1359 ifp->if_flags |= IFF_OACTIVE;
1364 start_tx = sc->my_cdata.my_tx_free;
1365 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1366 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1370 /* Pick a descriptor off the free list. */
1371 cur_tx = sc->my_cdata.my_tx_free;
1372 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1374 /* Pack the data into the descriptor. */
1375 my_encap(sc, cur_tx, m_head);
1377 if (cur_tx != start_tx)
1378 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1379 BPF_MTAP(ifp, cur_tx->my_mbuf);
1382 * If there are no packets queued, bail.
1384 if (cur_tx == NULL) {
1389 * Place the request for the upload interrupt in the last descriptor
1390 * in the chain. This way, if we're chaining several packets at once,
1391 * we'll only get an interupt once for the whole chain rather than
1392 * once for each packet.
1394 MY_TXCTL(cur_tx) |= MY_TXIC;
1395 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1396 sc->my_cdata.my_tx_tail = cur_tx;
1397 if (sc->my_cdata.my_tx_head == NULL)
1398 sc->my_cdata.my_tx_head = start_tx;
1399 MY_TXOWN(start_tx) = MY_OWNByNIC;
1400 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1403 * Set a timeout in case the chip goes out to lunch.
1413 struct my_softc *sc = xsc;
1414 struct ifnet *ifp = &sc->arpcom.ac_if;
1415 u_int16_t phy_bmcr = 0;
1418 if (sc->my_autoneg) {
1422 if (sc->my_pinfo != NULL)
1423 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1425 * Cancel pending I/O and free all RX/TX buffers.
1431 * Set cache alignment and burst length.
1433 #if 0 /* 89/9/1 modify, */
1434 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1435 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1437 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1438 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1440 * 89/12/29 add, for mtd891,
1442 if (sc->my_info->my_did == MTD891ID) {
1443 MY_SETBIT(sc, MY_BCR, MY_PROG);
1444 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1446 my_setcfg(sc, phy_bmcr);
1447 /* Init circular RX list. */
1448 if (my_list_rx_init(sc) == ENOBUFS) {
1449 printf("my%d: init failed: no memory for rx buffers\n",
1455 /* Init TX descriptors. */
1456 my_list_tx_init(sc);
1458 /* If we want promiscuous mode, set the allframes bit. */
1459 if (ifp->if_flags & IFF_PROMISC)
1460 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1462 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1465 * Set capture broadcast bit to capture broadcast frames.
1467 if (ifp->if_flags & IFF_BROADCAST)
1468 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1470 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1473 * Program the multicast filter, if necessary.
1478 * Load the address of the RX list.
1480 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1481 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1484 * Enable interrupts.
1486 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1487 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1489 /* Enable receiver and transmitter. */
1490 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1491 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1492 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1493 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1495 /* Restore state of BMCR */
1496 if (sc->my_pinfo != NULL)
1497 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1498 ifp->if_flags |= IFF_RUNNING;
1499 ifp->if_flags &= ~IFF_OACTIVE;
1504 * Set media options.
1508 my_ifmedia_upd(struct ifnet * ifp)
1510 struct my_softc *sc = ifp->if_softc;
1511 struct ifmedia *ifm = &sc->ifmedia;
1513 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1518 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1519 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1521 my_setmode_mii(sc, ifm->ifm_media);
1529 * Report current media status.
1533 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1535 struct my_softc *sc = ifp->if_softc;
1536 u_int16_t advert = 0, ability = 0;
1540 ifmr->ifm_active = IFM_ETHER;
1541 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1542 #if 0 /* this version did not support 1000M, */
1543 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1544 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1546 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1547 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1549 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1550 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1551 ifmr->ifm_active |= IFM_FDX;
1553 ifmr->ifm_active |= IFM_HDX;
1559 ability = my_phy_readreg(sc, PHY_LPAR);
1560 advert = my_phy_readreg(sc, PHY_ANAR);
1562 #if 0 /* this version did not support 1000M, */
1563 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1564 ability2 = my_phy_readreg(sc, PHY_1000SR);
1565 if (ability2 & PHY_1000SR_1000BTXFULL) {
1568 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX;
1569 } else if (ability & PHY_1000SR_1000BTXHALF) {
1572 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX;
1576 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1577 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1578 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1579 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1580 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1581 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1582 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1583 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1584 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1585 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1591 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr)
1593 struct my_softc *sc = ifp->if_softc;
1594 struct ifreq *ifr = (struct ifreq *) data;
1600 if (ifp->if_flags & IFF_UP)
1602 else if (ifp->if_flags & IFF_RUNNING)
1613 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1616 error = ether_ioctl(ifp, command, data);
1625 my_watchdog(struct ifnet * ifp)
1627 struct my_softc *sc = ifp->if_softc;
1631 if (sc->my_autoneg) {
1632 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1637 printf("my%d: watchdog timeout\n", sc->my_unit);
1638 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1639 printf("my%d: no carrier - transceiver cable problem?\n",
1644 if (!ifq_is_empty(&ifp->if_snd))
1651 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1654 my_stop(struct my_softc * sc)
1656 struct ifnet *ifp = &sc->arpcom.ac_if;
1661 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1662 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1663 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1664 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1667 * Free data in the RX lists.
1669 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1670 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1671 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1672 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1675 bzero((char *)&sc->my_ldata->my_rx_list,
1676 sizeof(sc->my_ldata->my_rx_list));
1678 * Free the TX list buffers.
1680 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1681 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1682 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1683 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1686 bzero((char *)&sc->my_ldata->my_tx_list,
1687 sizeof(sc->my_ldata->my_tx_list));
1688 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1692 * Stop all chip I/O so that the kernel's probe routines don't get confused
1693 * by errant DMAs when rebooting.
1696 my_shutdown(device_t dev)
1698 struct my_softc *sc;
1700 sc = device_get_softc(dev);