2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine_base/apic/mpapic.h>
36 #include <machine/segments.h>
37 #include <sys/thread2.h>
39 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
41 /* EISA Edge/Level trigger control registers */
42 #define ELCR0 0x4d0 /* eisa irq 0-7 */
43 #define ELCR1 0x4d1 /* eisa irq 8-15 */
45 static void lapic_timer_calibrate(void);
46 static void lapic_timer_set_divisor(int);
47 static void lapic_timer_intr_reload(sysclock_t);
48 static void lapic_timer_fixup_handler(void *);
49 static void lapic_timer_restart_handler(void *);
51 void lapic_timer_fixup(void);
52 void lapic_timer_process(void);
53 void lapic_timer_process_frame(struct intrframe *);
54 void lapic_timer_intr_test(void);
55 void lapic_timer_oneshot_intr_enable(void);
56 void lapic_timer_restart(void);
59 int lapic_timer_enable;
61 TUNABLE_INT("hw.lapic_timer_test", &lapic_timer_test);
62 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
65 * pointers to pmapped apic hardware.
68 volatile ioapic_t **ioapic;
70 static sysclock_t lapic_timer_freq;
71 static int lapic_timer_divisor_idx = -1;
72 static const uint32_t lapic_timer_divisors[] = {
73 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
74 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
76 #define APIC_TIMER_NDIVISORS \
77 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
81 * Enable APIC, configure interrupts.
84 apic_initialize(boolean_t bsp)
90 * setup LVT1 as ExtINT on the BSP. This is theoretically an
91 * aggregate interrupt input from the 8259. The INTA cycle
92 * will be routed to the external controller (the 8259) which
93 * is expected to supply the vector.
95 * Must be setup edge triggered, active high.
97 * Disable LVT1 on the APs. It doesn't matter what delivery
98 * mode we use because we leave it masked.
100 temp = lapic.lvt_lint0;
101 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
102 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
103 if (mycpu->gd_cpuid == 0)
104 temp |= APIC_LVT_DM_EXTINT;
106 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
107 lapic.lvt_lint0 = temp;
110 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
112 temp = lapic.lvt_lint1;
113 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
114 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
115 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
116 lapic.lvt_lint1 = temp;
119 * Mask the apic error interrupt, apic performance counter
122 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
123 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
125 /* Set apic timer vector and mask the apic timer interrupt. */
126 timer = lapic.lvt_timer;
127 timer &= ~APIC_LVTT_VECTOR;
128 timer |= XTIMER_OFFSET;
129 timer |= APIC_LVTT_MASKED;
130 lapic.lvt_timer = timer;
133 * Set the Task Priority Register as needed. At the moment allow
134 * interrupts on all cpus (the APs will remain CLId until they are
135 * ready to deal). We could disable all but IPIs by setting
136 * temp |= TPR_IPI_ONLY for cpu != 0.
139 temp &= ~APIC_TPR_PRIO; /* clear priority field */
142 * If we are NOT running the IO APICs, the LAPIC will only be used
143 * for IPIs. Set the TPR to prevent any unintentional interrupts.
145 temp |= TPR_IPI_ONLY;
151 * enable the local APIC
154 temp |= APIC_SVR_ENABLE; /* enable the APIC */
155 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
158 * Set the spurious interrupt vector. The low 4 bits of the vector
161 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
162 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
163 temp &= ~APIC_SVR_VECTOR;
164 temp |= XSPURIOUSINT_OFFSET;
169 * Pump out a few EOIs to clean out interrupts that got through
170 * before we were able to set the TPR.
177 lapic_timer_calibrate();
178 if (lapic_timer_enable)
179 cputimer_intr_reload = lapic_timer_intr_reload;
181 lapic_timer_set_divisor(lapic_timer_divisor_idx);
185 apic_dump("apic_initialize()");
190 lapic_timer_set_divisor(int divisor_idx)
192 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
193 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
197 lapic_timer_oneshot(u_int count)
201 value = lapic.lvt_timer;
202 value &= ~APIC_LVTT_PERIODIC;
203 lapic.lvt_timer = value;
204 lapic.icr_timer = count;
208 lapic_timer_oneshot_quick(u_int count)
210 lapic.icr_timer = count;
214 lapic_timer_calibrate(void)
218 /* Try to calibrate the local APIC timer. */
219 for (lapic_timer_divisor_idx = 0;
220 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
221 lapic_timer_divisor_idx++) {
222 lapic_timer_set_divisor(lapic_timer_divisor_idx);
223 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
225 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
226 if (value != APIC_TIMER_MAX_COUNT)
229 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
230 panic("lapic: no proper timer divisor?!\n");
231 lapic_timer_freq = value / 2;
233 kprintf("lapic: divisor index %d, frequency %u Hz\n",
234 lapic_timer_divisor_idx, lapic_timer_freq);
238 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
242 gd->gd_timer_running = 0;
244 count = sys_cputimer->count();
245 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
246 systimer_intr(&count, 0, frame);
250 lapic_timer_process(void)
252 struct globaldata *gd = mycpu;
254 if (__predict_false(lapic_timer_test)) {
255 gd->gd_timer_running = 0;
256 kprintf("%d proc\n", gd->gd_cpuid);
258 lapic_timer_process_oncpu(gd, NULL);
263 lapic_timer_process_frame(struct intrframe *frame)
265 struct globaldata *gd = mycpu;
267 if (__predict_false(lapic_timer_test)) {
268 gd->gd_timer_running = 0;
269 kprintf("%d proc frame\n", gd->gd_cpuid);
271 lapic_timer_process_oncpu(gd, frame);
276 lapic_timer_intr_test(void)
278 struct globaldata *gd = mycpu;
280 if (!gd->gd_timer_running) {
281 gd->gd_timer_running = 1;
282 KKASSERT(lapic_timer_freq != 0);
283 lapic_timer_oneshot_quick(lapic_timer_freq);
288 lapic_timer_intr_reload(sysclock_t reload)
290 struct globaldata *gd = mycpu;
292 reload = (int64_t)reload * lapic_timer_freq / sys_cputimer->freq;
296 if (gd->gd_timer_running) {
297 if (reload < lapic.ccr_timer)
298 lapic_timer_oneshot_quick(reload);
300 gd->gd_timer_running = 1;
301 lapic_timer_oneshot_quick(reload);
306 lapic_timer_oneshot_intr_enable(void)
310 timer = lapic.lvt_timer;
311 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
312 lapic.lvt_timer = timer;
314 lapic_timer_fixup_handler(NULL);
318 lapic_timer_fixup_handler(void *arg)
325 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
327 * Detect the presence of C1E capability mostly on latest
328 * dual-cores (or future) k8 family. This feature renders
329 * the local APIC timer dead, so we disable it by reading
330 * the Interrupt Pending Message register and clearing both
331 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
334 * "BIOS and Kernel Developer's Guide for AMD NPT
335 * Family 0Fh Processors"
336 * #32559 revision 3.00
338 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
339 (cpu_id & 0x0fff0000) >= 0x00040000) {
342 msr = rdmsr(0xc0010055);
343 if (msr & 0x18000000) {
344 struct globaldata *gd = mycpu;
346 kprintf("cpu%d: AMD C1E detected\n",
348 wrmsr(0xc0010055, msr & ~0x18000000ULL);
351 * We are kinda stalled;
354 gd->gd_timer_running = 1;
355 lapic_timer_oneshot_quick(2);
365 lapic_timer_restart_handler(void *dummy __unused)
369 lapic_timer_fixup_handler(&started);
371 struct globaldata *gd = mycpu;
373 gd->gd_timer_running = 1;
374 lapic_timer_oneshot_quick(2);
379 * This function is called only by ACPI-CA code currently:
380 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
381 * module controls PM. So once ACPI-CA is attached, we try
382 * to apply the fixup to prevent LAPIC timer from hanging.
385 lapic_timer_fixup(void)
387 if (lapic_timer_test || lapic_timer_enable) {
388 lwkt_send_ipiq_mask(smp_active_mask,
389 lapic_timer_fixup_handler, NULL);
394 lapic_timer_restart(void)
396 KKASSERT(lapic_timer_enable);
397 cputimer_intr_reload = lapic_timer_intr_reload;
398 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
403 * dump contents of local APIC registers
408 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
409 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
410 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
420 #define IOAPIC_ISA_INTS 16
421 #define REDIRCNT_IOAPIC(A) \
422 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
424 static int trigger (int apic, int pin, u_int32_t * flags);
425 static void polarity (int apic, int pin, u_int32_t * flags, int level);
427 #define DEFAULT_FLAGS \
433 #define DEFAULT_ISA_FLAGS \
442 io_apic_set_id(int apic, int id)
446 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
447 if (((ux & APIC_ID_MASK) >> 24) != id) {
448 kprintf("Changing APIC ID for IO APIC #%d"
449 " from %d to %d on chip\n",
450 apic, ((ux & APIC_ID_MASK) >> 24), id);
451 ux &= ~APIC_ID_MASK; /* clear the ID field */
453 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
454 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
455 if (((ux & APIC_ID_MASK) >> 24) != id)
456 panic("can't control IO APIC #%d ID, reg: 0x%08x",
463 io_apic_get_id(int apic)
465 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
474 extern int apic_pin_trigger; /* 'opaque' */
477 io_apic_setup_intpin(int apic, int pin)
479 int bus, bustype, irq;
480 u_char select; /* the select register is 8 bits */
481 u_int32_t flags; /* the window register is 32 bits */
482 u_int32_t target; /* the window register is 32 bits */
483 u_int32_t vector; /* the window register is 32 bits */
486 select = pin * 2 + IOAPIC_REDTBL0; /* register */
489 * Always clear an IO APIC pin before [re]programming it. This is
490 * particularly important if the pin is set up for a level interrupt
491 * as the IOART_REM_IRR bit might be set. When we reprogram the
492 * vector any EOI from pending ints on this pin could be lost and
493 * IRR might never get reset.
495 * To fix this problem, clear the vector and make sure it is
496 * programmed as an edge interrupt. This should theoretically
497 * clear IRR so we can later, safely program it as a level
502 flags = io_apic_read(apic, select) & IOART_RESV;
503 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
504 flags |= IOART_DESTPHY | IOART_DELFIXED;
506 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
507 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
511 io_apic_write(apic, select, flags | vector);
512 io_apic_write(apic, select + 1, target);
517 * We only deal with vectored interrupts here. ? documentation is
518 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
521 * This test also catches unconfigured pins.
523 if (apic_int_type(apic, pin) != 0)
527 * Leave the pin unprogrammed if it does not correspond to
530 irq = apic_irq(apic, pin);
534 /* determine the bus type for this pin */
535 bus = apic_src_bus_id(apic, pin);
538 bustype = apic_bus_type(bus);
540 if ((bustype == ISA) &&
541 (pin < IOAPIC_ISA_INTS) &&
543 (apic_polarity(apic, pin) == 0x1) &&
544 (apic_trigger(apic, pin) == 0x3)) {
546 * A broken BIOS might describe some ISA
547 * interrupts as active-high level-triggered.
548 * Use default ISA flags for those interrupts.
550 flags = DEFAULT_ISA_FLAGS;
553 * Program polarity and trigger mode according to
556 flags = DEFAULT_FLAGS;
557 level = trigger(apic, pin, &flags);
559 apic_pin_trigger |= (1 << irq);
560 polarity(apic, pin, &flags, level);
564 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
569 * Program the appropriate registers. This routing may be
570 * overridden when an interrupt handler for a device is
571 * actually added (see register_int(), which calls through
572 * the MACHINTR ABI to set up an interrupt handler/vector).
574 * The order in which we must program the two registers for
575 * safety is unclear! XXX
579 vector = IDT_OFFSET + irq; /* IDT vec */
580 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
581 target |= IOART_HI_DEST_BROADCAST;
582 flags |= io_apic_read(apic, select) & IOART_RESV;
583 io_apic_write(apic, select, flags | vector);
584 io_apic_write(apic, select + 1, target);
590 io_apic_setup(int apic)
596 apic_pin_trigger = 0; /* default to edge-triggered */
598 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
599 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
601 for (pin = 0; pin < maxpin; ++pin) {
602 io_apic_setup_intpin(apic, pin);
605 if (apic_int_type(apic, pin) >= 0) {
606 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
607 " cannot program!\n", apic, pin);
612 /* return GOOD status */
615 #undef DEFAULT_ISA_FLAGS
619 #define DEFAULT_EXTINT_FLAGS \
628 * Setup the source of External INTerrupts.
631 ext_int_setup(int apic, int intr)
633 u_char select; /* the select register is 8 bits */
634 u_int32_t flags; /* the window register is 32 bits */
635 u_int32_t target; /* the window register is 32 bits */
636 u_int32_t vector; /* the window register is 32 bits */
638 if (apic_int_type(apic, intr) != 3)
641 target = IOART_HI_DEST_BROADCAST;
642 select = IOAPIC_REDTBL0 + (2 * intr);
643 vector = IDT_OFFSET + intr;
644 flags = DEFAULT_EXTINT_FLAGS;
646 io_apic_write(apic, select, flags | vector);
647 io_apic_write(apic, select + 1, target);
651 #undef DEFAULT_EXTINT_FLAGS
655 * Set the trigger level for an IO APIC pin.
658 trigger(int apic, int pin, u_int32_t * flags)
663 static int intcontrol = -1;
665 switch (apic_trigger(apic, pin)) {
671 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
675 *flags |= IOART_TRGRLVL;
683 if ((id = apic_src_bus_id(apic, pin)) == -1)
686 switch (apic_bus_type(id)) {
688 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
692 eirq = apic_src_bus_irq(apic, pin);
694 if (eirq < 0 || eirq > 15) {
695 kprintf("EISA IRQ %d?!?!\n", eirq);
699 if (intcontrol == -1) {
700 intcontrol = inb(ELCR1) << 8;
701 intcontrol |= inb(ELCR0);
702 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
705 /* Use ELCR settings to determine level or edge mode */
706 level = (intcontrol >> eirq) & 1;
709 * Note that on older Neptune chipset based systems, any
710 * pci interrupts often show up here and in the ELCR as well
711 * as level sensitive interrupts attributed to the EISA bus.
715 *flags |= IOART_TRGRLVL;
717 *flags &= ~IOART_TRGRLVL;
722 *flags |= IOART_TRGRLVL;
731 panic("bad APIC IO INT flags");
736 * Set the polarity value for an IO APIC pin.
739 polarity(int apic, int pin, u_int32_t * flags, int level)
743 switch (apic_polarity(apic, pin)) {
749 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
753 *flags |= IOART_INTALO;
761 if ((id = apic_src_bus_id(apic, pin)) == -1)
764 switch (apic_bus_type(id)) {
766 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
770 /* polarity converter always gives active high */
771 *flags &= ~IOART_INTALO;
775 *flags |= IOART_INTALO;
784 panic("bad APIC IO INT flags");
789 * Print contents of apic_imen.
791 extern u_int apic_imen; /* keep apic_imen 'opaque' */
797 kprintf("SMP: enabled INTs: ");
798 for (x = 0; x < 24; ++x)
799 if ((apic_imen & (1 << x)) == 0)
801 kprintf("apic_imen: 0x%08x\n", apic_imen);
806 * Inter Processor Interrupt functions.
812 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
814 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
815 * vector is any valid SYSTEM INT vector
816 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
818 * A backlog of requests can create a deadlock between cpus. To avoid this
819 * we have to be able to accept IPIs at the same time we are trying to send
820 * them. The critical section prevents us from attempting to send additional
821 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
822 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
823 * to occur but fortunately it does not happen too often.
826 apic_ipi(int dest_type, int vector, int delivery_mode)
831 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
832 unsigned int eflags = read_eflags();
834 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
837 write_eflags(eflags);
840 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
841 delivery_mode | vector;
842 lapic.icr_lo = icr_lo;
848 single_apic_ipi(int cpu, int vector, int delivery_mode)
854 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
855 unsigned int eflags = read_eflags();
857 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
860 write_eflags(eflags);
862 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
863 icr_hi |= (CPU_TO_ID(cpu) << 24);
864 lapic.icr_hi = icr_hi;
867 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
868 | APIC_DEST_DESTFLD | delivery_mode | vector;
871 lapic.icr_lo = icr_lo;
878 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
880 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
881 * to the target, and the scheduler does not 'poll' for IPI messages.
884 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
890 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
894 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
895 icr_hi |= (CPU_TO_ID(cpu) << 24);
896 lapic.icr_hi = icr_hi;
899 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
900 | APIC_DEST_DESTFLD | delivery_mode | vector;
903 lapic.icr_lo = icr_lo;
911 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
913 * target is a bitmask of destination cpus. Vector is any
914 * valid system INT vector. Delivery mode may be either
915 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
918 selected_apic_ipi(u_int target, int vector, int delivery_mode)
922 int n = bsfl(target);
924 single_apic_ipi(n, vector, delivery_mode);
930 * Timer code, in development...
931 * - suggested by rgrimes@gndrsh.aac.dev.com
935 * Load a 'downcount time' in uSeconds.
938 set_apic_timer(int us)
943 * When we reach here, lapic timer's frequency
944 * must have been calculated as well as the
945 * divisor (lapic.dcr_timer is setup during the
946 * divisor calculation).
948 KKASSERT(lapic_timer_freq != 0 &&
949 lapic_timer_divisor_idx >= 0);
951 count = ((us * (int64_t)lapic_timer_freq) + 999999) / 1000000;
952 lapic_timer_oneshot(count);
957 * Read remaining time in timer.
960 read_apic_timer(void)
963 /** XXX FIXME: we need to return the actual remaining time,
964 * for now we just return the remaining count.
967 return lapic.ccr_timer;
973 * Spin-style delay, set delay time in uS, spin till it drains.
978 set_apic_timer(count);
979 while (read_apic_timer())