2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.55 2008/08/02 01:14:43 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/eventhandler.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
70 #include <sys/machintr.h>
72 #include <machine/clock.h>
73 #ifdef CLK_CALIBRATION_LOOP
75 #include <machine/cputypes.h>
76 #include <machine/frame.h>
77 #include <machine/ipl.h>
78 #include <machine/limits.h>
79 #include <machine/md_var.h>
80 #include <machine/psl.h>
81 #include <machine/segments.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 #include <machine_base/isa/intr_machdep.h>
93 /* The interrupt triggered by the 8254 (timer) chip */
95 static void setup_8254_mixed_mode (void);
97 static void i8254_restore(void);
98 static void resettodr_on_shutdown(void *arg __unused);
101 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
102 * can use a simple formula for leap years.
104 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
105 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
108 #define TIMER_FREQ 1193182
111 static uint8_t i8254_walltimer_sel;
112 static uint16_t i8254_walltimer_cntr;
114 int adjkerntz; /* local offset from GMT in seconds */
115 int disable_rtc_set; /* disable resettodr() if != 0 */
116 int statclock_disable = 1; /* we don't use the statclock right now */
118 int64_t tsc_frequency;
120 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
122 enum tstate { RELEASED, ACQUIRED };
123 enum tstate timer0_state;
124 enum tstate timer1_state;
125 enum tstate timer2_state;
127 static void i8254_intr_reload(sysclock_t);
128 void (*cputimer_intr_reload)(sysclock_t) = i8254_intr_reload;
130 static int beeping = 0;
131 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
132 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
133 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
134 static int rtc_loaded;
136 static int i8254_cputimer_div;
138 static int i8254_intr_disable = 0;
139 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
141 static struct callout sysbeepstop_ch;
143 static sysclock_t i8254_cputimer_count(void);
144 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
145 static void i8254_cputimer_destruct(struct cputimer *cputimer);
147 static struct cputimer i8254_cputimer = {
148 SLIST_ENTRY_INITIALIZER,
152 i8254_cputimer_count,
153 cputimer_default_fromhz,
154 cputimer_default_fromus,
155 i8254_cputimer_construct,
156 i8254_cputimer_destruct,
162 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
163 * counting as of this interrupt. We use timer1 in free-running mode (not
164 * generating any interrupts) as our main counter. Each cpu has timeouts
167 * This code is INTR_MPSAFE and may be called without the BGL held.
170 clkintr(void *dummy, void *frame_arg)
172 static sysclock_t sysclock_count; /* NOTE! Must be static */
173 struct globaldata *gd = mycpu;
175 struct globaldata *gscan;
180 * SWSTROBE mode is a one-shot, the timer is no longer running
185 * XXX the dispatcher needs work. right now we call systimer_intr()
186 * directly or via IPI for any cpu with systimers queued, which is
187 * usually *ALL* of them. We need to use the LAPIC timer for this.
189 sysclock_count = sys_cputimer->count();
191 for (n = 0; n < ncpus; ++n) {
192 gscan = globaldata_find(n);
193 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
196 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
199 systimer_intr(&sysclock_count, 0, frame_arg);
203 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
204 systimer_intr(&sysclock_count, 0, frame_arg);
213 acquire_timer2(int mode)
215 if (timer2_state != RELEASED)
217 timer2_state = ACQUIRED;
220 * This access to the timer registers is as atomic as possible
221 * because it is a single instruction. We could do better if we
224 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
231 if (timer2_state != ACQUIRED)
233 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
234 timer2_state = RELEASED;
239 * This routine receives statistical clock interrupts from the RTC.
240 * As explained above, these occur at 128 interrupts per second.
241 * When profiling, we receive interrupts at a rate of 1024 Hz.
243 * This does not actually add as much overhead as it sounds, because
244 * when the statistical clock is active, the hardclock driver no longer
245 * needs to keep (inaccurate) statistics on its own. This decouples
246 * statistics gathering from scheduling interrupts.
248 * The RTC chip requires that we read status register C (RTC_INTR)
249 * to acknowledge an interrupt, before it will generate the next one.
250 * Under high interrupt load, rtcintr() can be indefinitely delayed and
251 * the clock can tick immediately after the read from RTC_INTR. In this
252 * case, the mc146818A interrupt signal will not drop for long enough
253 * to register with the 8259 PIC. If an interrupt is missed, the stat
254 * clock will halt, considerably degrading system performance. This is
255 * why we use 'while' rather than a more straightforward 'if' below.
256 * Stat clock ticks can still be lost, causing minor loss of accuracy
257 * in the statistics, but the stat clock will no longer stop.
260 rtcintr(void *dummy, void *frame)
262 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
264 /* statclock(frame); no longer used */
271 DB_SHOW_COMMAND(rtc, rtc)
273 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
274 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
275 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
276 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
281 * Return the current cpu timer count as a 32 bit integer.
285 i8254_cputimer_count(void)
287 static __uint16_t cputimer_last;
292 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
293 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
294 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
295 count = -count; /* -> countup */
296 if (count < cputimer_last) /* rollover */
297 i8254_cputimer.base += 0x00010000;
298 ret = i8254_cputimer.base | count;
299 cputimer_last = count;
305 * This function is called whenever the system timebase changes, allowing
306 * us to calculate what is needed to convert a system timebase tick
307 * into an 8254 tick for the interrupt timer. If we can convert to a
308 * simple shift, multiplication, or division, we do so. Otherwise 64
309 * bit arithmatic is required every time the interrupt timer is reloaded.
312 cputimer_intr_config(struct cputimer *timer)
318 * Will a simple divide do the trick?
320 div = (timer->freq + (i8254_cputimer.freq / 2)) / i8254_cputimer.freq;
321 freq = i8254_cputimer.freq * div;
323 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
324 i8254_cputimer_div = div;
326 i8254_cputimer_div = 0;
330 * Reload for the next timeout. It is possible for the reload value
331 * to be 0 or negative, indicating that an immediate timer interrupt
332 * is desired. For now make the minimum 2 ticks.
334 * We may have to convert from the system timebase to the 8254 timebase.
337 i8254_intr_reload(sysclock_t reload)
341 if (i8254_cputimer_div)
342 reload /= i8254_cputimer_div;
344 reload = (int64_t)reload * i8254_cputimer.freq / sys_cputimer->freq;
350 if (timer0_running) {
351 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
352 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
353 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
354 if (reload < count) {
355 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
356 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
357 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
362 reload = 0; /* full count */
363 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
364 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
365 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
372 extern int lapic_timer_test;
373 extern int lapic_timer_enable;
374 extern void lapic_timer_oneshot_intr_enable(void);
375 extern void lapic_timer_intr_test(void);
376 extern void lapic_timer_restart(void);
378 /* Piggyback lapic_timer test */
380 i8254_intr_reload_test(sysclock_t reload)
382 i8254_intr_reload(reload);
383 if (__predict_false(lapic_timer_test))
384 lapic_timer_intr_test();
390 cputimer_intr_enable(void)
393 if (lapic_timer_test || lapic_timer_enable) {
394 lapic_timer_oneshot_intr_enable();
395 if (lapic_timer_test) /* XXX */
396 cputimer_intr_reload = i8254_intr_reload_test;
402 cputimer_intr_switch(enum cputimer_intr_type type)
405 if (!i8254_intr_disable &&
406 (lapic_timer_enable || lapic_timer_test)) {
408 case CPUTIMER_INTRT_C3:
409 cputimer_intr_reload = i8254_intr_reload;
410 /* Force a quick reload */
411 i8254_intr_reload(0);
414 case CPUTIMER_INTRT_FAST:
415 if (lapic_timer_test) /* XXX */
416 cputimer_intr_reload = i8254_intr_reload_test;
417 else if (lapic_timer_enable)
418 lapic_timer_restart();
426 sysctl_cputimer_intr_switch(SYSCTL_HANDLER_ARGS)
428 enum cputimer_intr_type type = CPUTIMER_INTRT_FAST;
431 error = sysctl_handle_int(oidp, &type, 0, req);
432 if (error || req->newptr == NULL)
435 case CPUTIMER_INTRT_C3:
436 case CPUTIMER_INTRT_FAST:
441 cputimer_intr_switch(type);
444 SYSCTL_PROC(_hw, OID_AUTO, cputimer_intr_type, CTLTYPE_INT | CTLFLAG_RW,
445 0, 0, sysctl_cputimer_intr_switch, "I",
446 "cputimer_intr switch [0|1]");
449 * DELAY(usec) - Spin for the specified number of microseconds.
450 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
451 * but do a thread switch in the loop
453 * Relies on timer 1 counting down from (cputimer_freq / hz)
454 * Note: timer had better have been programmed before this is first used!
457 DODELAY(int n, int doswitch)
459 int delta, prev_tick, tick, ticks_left;
464 static int state = 0;
468 for (n1 = 1; n1 <= 10000000; n1 *= 10)
473 kprintf("DELAY(%d)...", n);
476 * Guard against the timer being uninitialized if we are called
477 * early for console i/o.
479 if (timer0_state == RELEASED)
483 * Read the counter first, so that the rest of the setup overhead is
484 * counted. Then calculate the number of hardware timer ticks
485 * required, rounding up to be sure we delay at least the requested
486 * number of microseconds.
488 prev_tick = sys_cputimer->count();
489 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
495 while (ticks_left > 0) {
496 tick = sys_cputimer->count();
500 delta = tick - prev_tick;
505 if (doswitch && ticks_left > 0)
510 kprintf(" %d calls to getit() at %d usec each\n",
511 getit_calls, (n + 5) / getit_calls);
522 DRIVERSLEEP(int usec)
524 globaldata_t gd = mycpu;
526 if (gd->gd_intr_nesting_level ||
527 gd->gd_spinlock_rd ||
528 gd->gd_spinlocks_wr) {
536 sysbeepstop(void *chan)
538 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
544 sysbeep(int pitch, int period)
546 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
549 * Nobody else is using timer2, we do not need the clock lock
551 outb(TIMER_CNTR2, pitch);
552 outb(TIMER_CNTR2, (pitch>>8));
554 /* enable counter2 output to speaker */
555 outb(IO_PPI, inb(IO_PPI) | 3);
557 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
563 * RTC support routines
574 val = inb(IO_RTC + 1);
581 writertc(u_char reg, u_char val)
587 outb(IO_RTC + 1, val);
588 inb(0x84); /* XXX work around wrong order in rtcin() */
595 return(bcd2bin(rtcin(port)));
599 calibrate_clocks(void)
602 u_int count, prev_count, tot_count;
603 int sec, start_sec, timeout;
606 kprintf("Calibrating clock(s) ... ");
607 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
611 /* Read the mc146818A seconds counter. */
613 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
614 sec = rtcin(RTC_SEC);
621 /* Wait for the mC146818A seconds counter to change. */
624 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
625 sec = rtcin(RTC_SEC);
626 if (sec != start_sec)
633 /* Start keeping track of the i8254 counter. */
634 prev_count = sys_cputimer->count();
640 old_tsc = 0; /* shut up gcc */
643 * Wait for the mc146818A seconds counter to change. Read the i8254
644 * counter for each iteration since this is convenient and only
645 * costs a few usec of inaccuracy. The timing of the final reads
646 * of the counters almost matches the timing of the initial reads,
647 * so the main cause of inaccuracy is the varying latency from
648 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
649 * rtcin(RTC_SEC) that returns a changed seconds count. The
650 * maximum inaccuracy from this cause is < 10 usec on 486's.
654 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
655 sec = rtcin(RTC_SEC);
656 count = sys_cputimer->count();
657 tot_count += (int)(count - prev_count);
659 if (sec != start_sec)
666 * Read the cpu cycle counter. The timing considerations are
667 * similar to those for the i8254 clock.
670 tsc_frequency = rdtsc() - old_tsc;
674 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
675 kprintf("i8254 clock: %u Hz\n", tot_count);
679 kprintf("failed, using default i8254 clock of %u Hz\n",
680 i8254_cputimer.freq);
681 return (i8254_cputimer.freq);
687 timer0_state = ACQUIRED;
692 * Timer0 is our fine-grained variable clock interrupt
694 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
695 outb(TIMER_CNTR0, 2); /* lsb */
696 outb(TIMER_CNTR0, 0); /* msb */
700 * Timer1 or timer2 is our free-running clock, but only if another
701 * has not been selected.
703 cputimer_register(&i8254_cputimer);
704 cputimer_select(&i8254_cputimer, 0);
708 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
713 * Should we use timer 1 or timer 2 ?
716 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
717 if (which != 1 && which != 2)
722 timer->name = "i8254_timer1";
723 timer->type = CPUTIMER_8254_SEL1;
724 i8254_walltimer_sel = TIMER_SEL1;
725 i8254_walltimer_cntr = TIMER_CNTR1;
726 timer1_state = ACQUIRED;
729 timer->name = "i8254_timer2";
730 timer->type = CPUTIMER_8254_SEL2;
731 i8254_walltimer_sel = TIMER_SEL2;
732 i8254_walltimer_cntr = TIMER_CNTR2;
733 timer2_state = ACQUIRED;
737 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
740 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
741 outb(i8254_walltimer_cntr, 0); /* lsb */
742 outb(i8254_walltimer_cntr, 0); /* msb */
743 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
748 i8254_cputimer_destruct(struct cputimer *timer)
750 switch(timer->type) {
751 case CPUTIMER_8254_SEL1:
752 timer1_state = RELEASED;
754 case CPUTIMER_8254_SEL2:
755 timer2_state = RELEASED;
766 /* Restore all of the RTC's "status" (actually, control) registers. */
767 writertc(RTC_STATUSB, RTCSB_24HR);
768 writertc(RTC_STATUSA, rtc_statusa);
769 writertc(RTC_STATUSB, rtc_statusb);
773 * Restore all the timers.
775 * This function is called to resynchronize our core timekeeping after a
776 * long halt, e.g. from apm_default_resume() and friends. It is also
777 * called if after a BIOS call we have detected munging of the 8254.
778 * It is necessary because cputimer_count() counter's delta may have grown
779 * too large for nanouptime() and friends to handle, or (in the case of 8254
780 * munging) might cause the SYSTIMER code to prematurely trigger.
786 i8254_restore(); /* restore timer_freq and hz */
787 rtc_restore(); /* reenable RTC interrupts */
792 * Initialize 8254 timer 0 early so that it can be used in DELAY().
800 * Can we use the TSC?
802 if (cpu_feature & CPUID_TSC)
808 * Initial RTC state, don't do anything unexpected
810 writertc(RTC_STATUSA, rtc_statusa);
811 writertc(RTC_STATUSB, RTCSB_24HR);
814 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
815 * generate an interrupt, which we will ignore for now.
817 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
818 * (so it counts a full 2^16 and repeats). We will use this timer
822 freq = calibrate_clocks();
823 #ifdef CLK_CALIBRATION_LOOP
826 "Press a key on the console to abort clock calibration\n");
827 while (cncheckc() == -1)
833 * Use the calibrated i8254 frequency if it seems reasonable.
834 * Otherwise use the default, and don't use the calibrated i586
837 delta = freq > i8254_cputimer.freq ?
838 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
839 if (delta < i8254_cputimer.freq / 100) {
840 #ifndef CLK_USE_I8254_CALIBRATION
843 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
844 freq = i8254_cputimer.freq;
846 cputimer_set_frequency(&i8254_cputimer, freq);
850 "%d Hz differs from default of %d Hz by more than 1%%\n",
851 freq, i8254_cputimer.freq);
855 #ifndef CLK_USE_TSC_CALIBRATION
856 if (tsc_frequency != 0) {
859 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
863 if (tsc_present && tsc_frequency == 0) {
865 * Calibration of the i586 clock relative to the mc146818A
866 * clock failed. Do a less accurate calibration relative
867 * to the i8254 clock.
869 u_int64_t old_tsc = rdtsc();
872 tsc_frequency = rdtsc() - old_tsc;
873 #ifdef CLK_USE_TSC_CALIBRATION
875 kprintf("TSC clock: %llu Hz (Method B)\n",
881 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
885 * We can not use the TSC in SMP mode, until we figure out a
886 * cheap (impossible), reliable and precise (yeah right!) way
887 * to synchronize the TSCs of all the CPUs.
888 * Curse Intel for leaving the counter out of the I/O APIC.
893 * We can not use the TSC if we support APM. Precise timekeeping
894 * on an APM'ed machine is at best a fools pursuit, since
895 * any and all of the time spent in various SMM code can't
896 * be reliably accounted for. Reading the RTC is your only
897 * source of reliable time info. The i8254 looses too of course
898 * but we need to have some kind of time...
899 * We don't know at this point whether APM is going to be used
900 * or not, nor when it might be activated. Play it safe.
903 #endif /* NAPM > 0 */
905 #endif /* !defined(SMP) */
909 * Sync the time of day back to the RTC on shutdown, but only if
910 * we have already loaded it and have not crashed.
913 resettodr_on_shutdown(void *arg __unused)
915 if (rtc_loaded && panicstr == NULL) {
921 * Initialize the time of day register, based on the time base which is, e.g.
925 inittodr(time_t base)
927 unsigned long sec, days;
939 /* Look if we have a RTC present and the time is valid */
940 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
943 /* wait for time update to complete */
944 /* If RTCSA_TUP is zero, we have at least 244us before next update */
946 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
952 #ifdef USE_RTC_CENTURY
953 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
955 year = readrtc(RTC_YEAR) + 1900;
963 month = readrtc(RTC_MONTH);
964 for (m = 1; m < month; m++)
965 days += daysinmonth[m-1];
966 if ((month > 2) && LEAPYEAR(year))
968 days += readrtc(RTC_DAY) - 1;
970 for (y = 1970; y < year; y++)
971 days += DAYSPERYEAR + LEAPYEAR(y);
972 sec = ((( days * 24 +
973 readrtc(RTC_HRS)) * 60 +
974 readrtc(RTC_MIN)) * 60 +
976 /* sec now contains the number of seconds, since Jan 1 1970,
977 in the local time zone */
979 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
981 y = time_second - sec;
982 if (y <= -2 || y >= 2) {
983 /* badly off, adjust it */
993 kprintf("Invalid time in real time clock.\n");
994 kprintf("Check and reset the date immediately!\n");
998 * Write system time back to RTC
1008 if (disable_rtc_set)
1015 /* Disable RTC updates and interrupts. */
1016 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
1018 /* Calculate local time to put in RTC */
1020 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
1022 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
1023 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
1024 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
1026 /* We have now the days since 01-01-1970 in tm */
1027 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
1028 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
1030 y++, m = DAYSPERYEAR + LEAPYEAR(y))
1033 /* Now we have the years in y and the day-of-the-year in tm */
1034 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
1035 #ifdef USE_RTC_CENTURY
1036 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
1038 for (m = 0; ; m++) {
1041 ml = daysinmonth[m];
1042 if (m == 1 && LEAPYEAR(y))
1049 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
1050 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
1052 /* Reenable RTC updates and interrupts. */
1053 writertc(RTC_STATUSB, rtc_statusb);
1059 * Start both clocks running. DragonFly note: the stat clock is no longer
1060 * used. Instead, 8254 based systimers are used for all major clock
1061 * interrupts. statclock_disable is set by default.
1064 cpu_initclocks(void *arg __unused)
1068 int apic_8254_trial;
1070 #endif /* APIC_IO */
1072 callout_init(&sysbeepstop_ch);
1075 if (lapic_timer_enable && i8254_intr_disable)
1079 if (statclock_disable) {
1081 * The stat interrupt mask is different without the
1082 * statistics clock. Also, don't set the interrupt
1083 * flag which would normally cause the RTC to generate
1086 rtc_statusb = RTCSB_24HR;
1088 /* Setting stathz to nonzero early helps avoid races. */
1089 stathz = RTC_NOPROFRATE;
1090 profhz = RTC_PROFRATE;
1093 /* Finish initializing 8253 timer 0. */
1096 apic_8254_intr = isa_apic_irq(0);
1097 apic_8254_trial = 0;
1098 if (apic_8254_intr >= 0 ) {
1099 if (apic_int_type(0, 0) == 3)
1100 apic_8254_trial = 1;
1102 /* look for ExtInt on pin 0 */
1103 if (apic_int_type(0, 0) == 3) {
1104 apic_8254_intr = apic_irq(0, 0);
1105 setup_8254_mixed_mode();
1107 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1110 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1112 INTR_EXCL | INTR_FAST |
1113 INTR_NOPOLL | INTR_MPSAFE |
1115 machintr_intren(apic_8254_intr);
1119 register_int(0, clkintr, NULL, "clk", NULL,
1120 INTR_EXCL | INTR_FAST |
1121 INTR_NOPOLL | INTR_MPSAFE |
1123 machintr_intren(ICU_IRQ0);
1125 #endif /* APIC_IO */
1127 /* Initialize RTC. */
1128 writertc(RTC_STATUSA, rtc_statusa);
1129 writertc(RTC_STATUSB, RTCSB_24HR);
1131 if (statclock_disable == 0) {
1132 diag = rtcin(RTC_DIAG);
1134 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1137 if (isa_apic_irq(8) != 8)
1138 panic("APIC RTC != 8");
1139 #endif /* APIC_IO */
1141 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1142 INTR_EXCL | INTR_FAST | INTR_NOPOLL |
1146 writertc(RTC_STATUSB, rtc_statusb);
1150 if (apic_8254_trial) {
1155 * Following code assumes the 8254 is the cpu timer,
1156 * so make sure it is.
1158 KKASSERT(sys_cputimer == &i8254_cputimer);
1160 lastcnt = get_interrupt_counter(apic_8254_intr);
1163 * Force an 8254 Timer0 interrupt and wait 1/100s for
1164 * it to happen, then see if we got it.
1166 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1167 i8254_intr_reload(2);
1168 base = sys_cputimer->count();
1169 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1171 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1173 * The MP table is broken.
1174 * The 8254 was not connected to the specified pin
1176 * Workaround: Limited variant of mixed mode.
1178 machintr_intrdis(apic_8254_intr);
1179 unregister_int(clkdesc);
1180 kprintf("APIC_IO: Broken MP table detected: "
1181 "8254 is not connected to "
1182 "IOAPIC #%d intpin %d\n",
1183 int_to_apicintpin[apic_8254_intr].ioapic,
1184 int_to_apicintpin[apic_8254_intr].int_pin);
1186 * Revoke current ISA IRQ 0 assignment and
1187 * configure a fallback interrupt routing from
1188 * the 8254 Timer via the 8259 PIC to the
1189 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1190 * We reuse the low level interrupt handler number.
1192 if (apic_irq(0, 0) < 0) {
1193 revoke_apic_irq(apic_8254_intr);
1194 assign_apic_irq(0, 0, apic_8254_intr);
1196 apic_8254_intr = apic_irq(0, 0);
1197 setup_8254_mixed_mode();
1198 register_int(apic_8254_intr, clkintr, NULL, "clk",
1200 INTR_EXCL | INTR_FAST |
1201 INTR_NOPOLL | INTR_MPSAFE |
1203 machintr_intren(apic_8254_intr);
1207 if (apic_int_type(0, 0) != 3 ||
1208 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1209 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1210 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1211 int_to_apicintpin[apic_8254_intr].ioapic,
1212 int_to_apicintpin[apic_8254_intr].int_pin);
1215 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1219 SYSINIT(clocks8254, SI_BOOT2_CLOCKREG, SI_ORDER_FIRST, cpu_initclocks, NULL)
1224 setup_8254_mixed_mode(void)
1227 * Allow 8254 timer to INTerrupt 8259:
1228 * re-initialize master 8259:
1229 * reset; prog 4 bytes, single ICU, edge triggered
1231 outb(IO_ICU1, 0x13);
1232 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1233 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1234 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1235 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1237 /* program IO APIC for type 3 INT on INT0 */
1238 if (ext_int_setup(0, 0) < 0)
1239 panic("8254 redirect via APIC pin0 impossible!");
1244 setstatclockrate(int newhz)
1246 if (newhz == RTC_PROFRATE)
1247 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1249 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1250 writertc(RTC_STATUSA, rtc_statusa);
1255 tsc_get_timecount(struct timecounter *tc)
1261 #ifdef KERN_TIMESTAMP
1262 #define KERN_TIMESTAMP_SIZE 16384
1263 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1264 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1265 sizeof(tsc), "LU", "Kernel timestamps");
1271 tsc[i] = (u_int32_t)rdtsc();
1274 if (i >= KERN_TIMESTAMP_SIZE)
1276 tsc[i] = 0; /* mark last entry */
1278 #endif /* KERN_TIMESTAMP */
1285 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1292 if (sys_cputimer == &i8254_cputimer)
1293 count = sys_cputimer->count();
1301 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1302 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1305 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1306 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1308 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1309 0, 0, hw_i8254_timestamp, "A", "");
1311 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1312 &tsc_present, 0, "TSC Available");
1313 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1314 &tsc_frequency, 0, "TSC Frequency");