2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/an/if_an_pci.c,v 1.2.2.8 2003/02/11 03:32:48 ambrisko Exp $
33 * $DragonFly: src/sys/dev/netif/an/if_an_pci.c,v 1.12 2005/06/15 11:35:22 joerg Exp $
37 * This is a PCI shim for the Aironet PC4500/4800 wireless network
38 * driver. Aironet makes PCMCIA, ISA and PCI versions of these devices,
39 * which all have basically the same interface. The ISA and PCI cards
40 * are actually bridge adapters with PCMCIA cards inserted into them,
41 * however they appear as normal PCI or ISA devices to the host.
43 * All we do here is handle the PCI probe and attach and set up an
44 * interrupt handler entry point. The PCI version of the card uses
45 * a PLX 9050 PCI to "dumb bus" bridge chip, which provides us with
46 * multiple PCI address space mappings. The primary mapping at PCI
47 * register 0x14 is for the PLX chip itself, *NOT* the Aironet card.
48 * The I/O address of the Aironet is actually at register 0x18, which
49 * is the local bus mapping register for bus space 0. There are also
50 * registers for additional register spaces at registers 0x1C and
51 * 0x20, but these are unused in the Aironet devices. To find out
52 * more, you need a datasheet for the 9050 from PLX, but you have
53 * to go through their sales office to get it. Bleh.
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/sockio.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/socket.h>
70 #include <sys/module.h>
72 #include <machine/bus.h>
74 #include <machine/resource.h>
77 #include <net/if_arp.h>
78 #include <net/ethernet.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
82 #include <bus/pci/pcireg.h>
83 #include <bus/pci/pcivar.h>
85 #include "if_aironet_ieee.h"
94 #define AIRONET_VENDORID 0x14B9
95 #define AIRONET_DEVICEID_35x 0x0350
96 #define AIRONET_DEVICEID_4500 0x4500
97 #define AIRONET_DEVICEID_4800 0x4800
98 #define AIRONET_DEVICEID_4xxx 0x0001
99 #define AIRONET_DEVICEID_MPI350 0xA504
100 #define AN_PCI_PLX_LOIO 0x14 /* PLX chip iobase */
101 #define AN_PCI_LOIO 0x18 /* Aironet iobase */
103 static struct an_type an_devs[] = {
104 { AIRONET_VENDORID, AIRONET_DEVICEID_35x, "Cisco Aironet 350 Series" },
105 { AIRONET_VENDORID, AIRONET_DEVICEID_4500, "Aironet PCI4500" },
106 { AIRONET_VENDORID, AIRONET_DEVICEID_4800, "Aironet PCI4800" },
107 { AIRONET_VENDORID, AIRONET_DEVICEID_4xxx, "Aironet PCI4500/PCI4800" },
108 { AIRONET_VENDORID, AIRONET_DEVICEID_MPI350, "Cisco Aironet MPI350" },
112 static int an_probe_pci (device_t);
113 static int an_attach_pci (device_t);
114 static int an_detach_pci (device_t);
115 static int an_suspend_pci (device_t);
116 static int an_resume_pci (device_t);
119 an_probe_pci(device_t dev)
125 while (t->an_name != NULL) {
126 if (pci_get_vendor(dev) == t->an_vid &&
127 pci_get_device(dev) == t->an_did) {
128 device_set_desc(dev, t->an_name);
142 int flags, error = 0;
144 sc = device_get_softc(dev);
145 flags = device_get_flags(dev);
147 if (pci_get_vendor(dev) == AIRONET_VENDORID &&
148 pci_get_device(dev) == AIRONET_DEVICEID_MPI350) {
150 sc->port_rid = PCIR_MAPS;
153 * Map control/status registers.
155 command = pci_read_config(dev, PCIR_COMMAND, 4);
156 command |= PCIM_CMD_PORTEN;
157 pci_write_config(dev, PCIR_COMMAND, command, 4);
158 command = pci_read_config(dev, PCIR_COMMAND, 4);
160 if (!(command & PCIM_CMD_PORTEN)) {
161 device_printf(dev, "failed to enable I/O ports!\n");
165 sc->port_rid = AN_PCI_LOIO;
167 error = an_alloc_port(dev, sc->port_rid, 1);
170 device_printf(dev, "couldn't map ports\n");
174 sc->an_btag = rman_get_bustag(sc->port_res);
175 sc->an_bhandle = rman_get_bushandle(sc->port_res);
177 /* Allocate memory for MPI350 */
179 /* Allocate memory */
180 sc->mem_rid = PCIR_MAPS + 4;
181 error = an_alloc_memory(dev, sc->mem_rid, 1);
183 device_printf(dev, "couldn't map memory\n");
186 sc->an_mem_btag = rman_get_bustag(sc->mem_res);
187 sc->an_mem_bhandle = rman_get_bushandle(sc->mem_res);
189 /* Allocate aux. memory */
190 sc->mem_aux_rid = PCIR_MAPS + 8;
191 error = an_alloc_aux_memory(dev, sc->mem_aux_rid,
194 device_printf(dev, "couldn't map aux memory\n");
197 sc->an_mem_aux_btag = rman_get_bustag(sc->mem_aux_res);
198 sc->an_mem_aux_bhandle = rman_get_bushandle(sc->mem_aux_res);
200 /* Allocate DMA region */
201 error = bus_dma_tag_create(NULL, /* parent */
202 1, 0, /* alignment, bounds */
203 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
204 BUS_SPACE_MAXADDR, /* highaddr */
205 NULL, NULL, /* filter, filterarg */
206 0x3ffff, /* maxsize XXX */
208 0xffff, /* maxsegsize XXX */
209 BUS_DMA_ALLOCNOW, /* flags */
212 device_printf(dev, "couldn't get DMA region\n");
217 /* Allocate interrupt */
218 error = an_alloc_irq(dev, 0, RF_SHAREABLE);
222 error = an_attach(sc, dev, flags);
226 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET,
227 an_intr, sc, &sc->irq_handle, NULL);
229 ifmedia_removeall(&sc->an_ifmedia);
230 ether_ifdetach(&sc->arpcom.ac_if);
237 an_release_resources(dev);
242 an_detach_pci(device_t dev)
244 struct an_softc *sc = device_get_softc(dev);
245 struct ifnet *ifp = &sc->arpcom.ac_if;
248 ifmedia_removeall(&sc->an_ifmedia);
250 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
251 an_release_resources(dev);
257 an_suspend_pci(device_t dev)
265 an_resume_pci(device_t dev)
272 static device_method_t an_pci_methods[] = {
273 /* Device interface */
274 DEVMETHOD(device_probe, an_probe_pci),
275 DEVMETHOD(device_attach, an_attach_pci),
276 DEVMETHOD(device_detach, an_detach_pci),
277 DEVMETHOD(device_shutdown, an_shutdown),
278 DEVMETHOD(device_suspend, an_suspend_pci),
279 DEVMETHOD(device_resume, an_resume_pci),
283 static driver_t an_pci_driver = {
286 sizeof(struct an_softc),
289 static devclass_t an_devclass;
291 DRIVER_MODULE(if_an, pci, an_pci_driver, an_devclass, 0, 0);