2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/syslog.h>
49 #include <sys/module.h>
52 #include <sys/thread2.h>
53 #include <sys/machintr.h>
55 #include <net/ethernet.h>
57 #include <net/ifq_var.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_mib.h>
61 #include <net/if_media.h>
64 #include <dev/netif/mii_layer/mii.h>
65 #include <dev/netif/mii_layer/miivar.h>
70 #include <machine/md_var.h>
75 devclass_t ed_devclass;
77 static void ed_init (void *);
78 static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
79 static void ed_start (struct ifnet *);
80 static void ed_reset (struct ifnet *);
81 static void ed_watchdog (struct ifnet *);
83 static void ed_tick (void *);
86 static void ds_getmcaf (struct ed_softc *, u_int32_t *);
88 static void ed_get_packet (struct ed_softc *, char *, u_short);
90 static __inline void ed_rint (struct ed_softc *);
91 static __inline void ed_xmit (struct ed_softc *);
92 static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
94 static void ed_hpp_set_physical_link (struct ed_softc *);
95 static void ed_hpp_readmem (struct ed_softc *, u_short, u_char *, u_short);
96 static void ed_hpp_writemem (struct ed_softc *, u_char *, u_short, u_short);
97 static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *, int);
99 static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *, int);
101 static void ed_setrcr (struct ed_softc *);
103 static uint32_t ds_mchash (const uint8_t *);
105 DECLARE_DUMMY_MODULE(if_ed);
108 * Interrupt conversion table for WD/SMC ASIC/83C584
110 static u_short ed_intr_val[] = {
122 * Interrupt conversion table for 83C790
124 static u_short ed_790_intr_val[] = {
136 * Interrupt conversion table for the HP PC LAN+
139 static u_short ed_hpp_intr_val[] = {
159 * Generic probe routine for testing for the existance of a DS8390.
160 * Must be called after the NIC has just been reset. This routine
161 * works by looking at certain register values that are guaranteed
162 * to be initialized a certain way after power-up or reset. Seems
163 * not to currently work on the 83C690.
167 * Register reset bits set bits
168 * Command Register (CR) TXP, STA RD2, STP
169 * Interrupt Status (ISR) RST
170 * Interrupt Mask (IMR) All bits
171 * Data Control (DCR) LAS
172 * Transmit Config. (TCR) LB1, LB0
174 * We only look at the CR and ISR registers, however, because looking at
175 * the others would require changing register pages (which would be
176 * intrusive if this isn't an 8390).
178 * Return 1 if 8390 was found, 0 if not.
182 ed_probe_generic8390(struct ed_softc *sc)
184 if ((ed_nic_inb(sc, ED_P0_CR) &
185 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
186 (ED_CR_RD2 | ED_CR_STP))
188 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
195 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
198 ed_probe_WD80x3_generic(device_t dev, int flags, u_short *intr_vals[])
200 struct ed_softc *sc = device_get_softc(dev);
203 u_int memsize, maddr;
204 u_char iptr, isa16bit, sum, totalsum;
205 u_long conf_maddr, conf_msize, irq, junk;
207 sc->chip_type = ED_CHIP_TYPE_DP8390;
209 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
210 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
211 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
215 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
218 * Attempt to do a checksum over the station address PROM. If it
219 * fails, it's probably not a SMC/WD board. There is a problem with
220 * this, though: some clone WD boards don't pass the checksum test.
221 * Danpex boards for one.
223 for (sum = 0, i = 0; i < 8; ++i)
224 sum += ed_asic_inb(sc, ED_WD_PROM + i);
226 if (sum != totalsum) {
229 * Checksum is invalid. This often happens with cheap WD8003E
230 * clones. In this case, the checksum byte (the eighth byte)
231 * seems to always be zero.
233 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
234 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
237 /* reset card to force it into a known state. */
238 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
239 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
241 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
244 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
245 /* wait in the case this card is reading its EEROM */
248 sc->vendor = ED_VENDOR_WD_SMC;
249 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
252 * Set initial values for width/size.
257 case ED_TYPE_WD8003S:
258 sc->type_str = "WD8003S";
260 case ED_TYPE_WD8003E:
261 sc->type_str = "WD8003E";
263 case ED_TYPE_WD8003EB:
264 sc->type_str = "WD8003EB";
266 case ED_TYPE_WD8003W:
267 sc->type_str = "WD8003W";
269 case ED_TYPE_WD8013EBT:
270 sc->type_str = "WD8013EBT";
274 case ED_TYPE_WD8013W:
275 sc->type_str = "WD8013W";
279 case ED_TYPE_WD8013EP: /* also WD8003EP */
280 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
283 sc->type_str = "WD8013EP";
285 sc->type_str = "WD8003EP";
288 case ED_TYPE_WD8013WC:
289 sc->type_str = "WD8013WC";
293 case ED_TYPE_WD8013EBP:
294 sc->type_str = "WD8013EBP";
298 case ED_TYPE_WD8013EPC:
299 sc->type_str = "WD8013EPC";
303 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
304 case ED_TYPE_SMC8216T:
305 if (sc->type == ED_TYPE_SMC8216C) {
306 sc->type_str = "SMC8216/SMC8216C";
308 sc->type_str = "SMC8216T";
311 ed_asic_outb(sc, ED_WD790_HWR,
312 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
313 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
314 case ED_WD790_RAR_SZ64:
317 case ED_WD790_RAR_SZ32:
320 case ED_WD790_RAR_SZ16:
323 case ED_WD790_RAR_SZ8:
324 /* 8216 has 16K shared mem -- 8416 has 8K */
325 if (sc->type == ED_TYPE_SMC8216C) {
326 sc->type_str = "SMC8416C/SMC8416BT";
328 sc->type_str = "SMC8416T";
333 ed_asic_outb(sc, ED_WD790_HWR,
334 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
337 sc->chip_type = ED_CHIP_TYPE_WD790;
339 case ED_TYPE_TOSHIBA1:
340 sc->type_str = "Toshiba1";
344 case ED_TYPE_TOSHIBA4:
345 sc->type_str = "Toshiba4";
355 * Make some adjustments to initial values depending on what is found
358 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
359 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
360 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
365 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
366 &conf_maddr, &conf_msize);
371 kprintf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
372 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
373 for (i = 0; i < 8; i++)
374 kprintf("%x -> %x\n", i, ed_asic_inb(sc, i));
378 * Allow the user to override the autoconfiguration
381 memsize = conf_msize;
384 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
385 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
386 maddr, maddr + memsize);
391 * (note that if the user specifies both of the following flags that
392 * '8bit' mode intentionally has precedence)
394 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
396 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
400 * If possible, get the assigned interrupt number from the card and
403 if ((sc->type & ED_WD_SOFTCONFIG) &&
404 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
407 * Assemble together the encoded interrupt number.
409 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
410 ((ed_asic_inb(sc, ED_WD_IRR) &
411 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
414 * If no interrupt specified (or "?"), use what the board tells us.
416 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
418 if (error && intr_vals[0] != NULL) {
419 int intr_val = intr_vals[0][iptr];
421 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
422 intr_val, 1, machintr_intr_cpuid(intr_val));
428 * Enable the interrupt.
430 ed_asic_outb(sc, ED_WD_IRR,
431 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
433 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
434 ed_asic_outb(sc, ED_WD790_HWR,
435 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
436 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
437 (ed_asic_inb(sc, ED_WD790_GCR) &
438 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
439 ed_asic_outb(sc, ED_WD790_HWR,
440 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
443 * If no interrupt specified (or "?"), use what the board tells us.
445 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
447 if (error && intr_vals[1] != NULL) {
448 int intr_val = intr_vals[1][iptr];
450 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
451 intr_val, 1, machintr_intr_cpuid(intr_val));
459 ed_asic_outb(sc, ED_WD790_ICR,
460 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
462 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
465 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
469 sc->isa16bit = isa16bit;
472 error = ed_alloc_memory(dev, 0, memsize);
474 kprintf("*** ed_alloc_memory() failed! (%d)\n", error);
477 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
480 * allocate one xmit buffer if < 16k, two buffers otherwise
482 if ((memsize < 16384) ||
483 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
488 sc->tx_page_start = ED_WD_PAGE_OFFSET;
489 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
490 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
491 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
492 sc->mem_size = memsize;
493 sc->mem_end = sc->mem_start + memsize;
496 * Get station address from on-board ROM
498 for (i = 0; i < ETHER_ADDR_LEN; ++i)
499 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
502 * Set upper address bits and 8/16 bit access to shared memory.
505 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
506 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
508 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
509 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
512 * Enable 16bit access
514 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
517 if (((sc->type & ED_WD_SOFTCONFIG) ||
518 (sc->type == ED_TYPE_TOSHIBA1) ||
519 (sc->type == ED_TYPE_TOSHIBA4) ||
520 (sc->type == ED_TYPE_WD8013EBT)) &&
521 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
522 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
524 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
529 * Set address and enable interface shared memory.
531 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
532 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
533 ed_asic_outb(sc, ED_WD_MSR + 1,
534 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
535 ed_asic_outb(sc, ED_WD_MSR + 2,
536 ((kvtop(sc->mem_start) >> 16) & 0x0f));
537 ed_asic_outb(sc, ED_WD_MSR,
538 ED_WD_MSR_MENB | ED_WD_MSR_POW);
540 ed_asic_outb(sc, ED_WD_MSR,
541 ((kvtop(sc->mem_start) >> 13) &
542 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
544 sc->cr_proto = ED_CR_RD2;
546 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
547 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
548 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
549 ((kvtop(sc->mem_start) >> 11) & 0x40) |
550 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
551 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
556 kprintf("starting memory performance test at 0x%x, size %d...\n",
557 sc->mem_start, memsize*16384);
558 for (i = 0; i < 16384; i++)
559 bzero(sc->mem_start, memsize);
560 kprintf("***DONE***\n");
564 * Now zero memory and verify that it is clear
566 bzero(sc->mem_start, memsize);
568 for (i = 0; i < memsize; ++i) {
569 if (sc->mem_start[i]) {
570 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
571 (long long)kvtop(sc->mem_start + i));
574 * Disable 16 bit access to shared memory
577 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
578 ed_asic_outb(sc, ED_WD_MSR, 0x00);
580 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
588 * Disable 16bit access to shared memory - we leave it
589 * disabled so that 1) machines reboot properly when the board
590 * is set 16 bit mode and there are conflicting 8bit
591 * devices/ROMS in the same 128k address space as this boards
592 * shared memory. and 2) so that other 8 bit devices with
593 * shared memory can be used in this 128k region, too.
596 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
597 ed_asic_outb(sc, ED_WD_MSR, 0x00);
599 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
606 ed_probe_WD80x3(device_t dev, int port_rid, int flags)
608 struct ed_softc *sc = device_get_softc(dev);
610 static u_short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
612 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
616 sc->asic_offset = ED_WD_ASIC_OFFSET;
617 sc->nic_offset = ED_WD_NIC_OFFSET;
619 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
623 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
626 ed_probe_3Com(device_t dev, int port_rid, int flags)
628 struct ed_softc *sc = device_get_softc(dev);
633 u_long conf_maddr, conf_msize, irq, junk;
635 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
639 sc->asic_offset = ED_3COM_ASIC_OFFSET;
640 sc->nic_offset = ED_3COM_NIC_OFFSET;
643 * Verify that the kernel configured I/O address matches the board
646 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
647 case ED_3COM_BCFR_300:
648 if (rman_get_start(sc->port_res) != 0x300)
651 case ED_3COM_BCFR_310:
652 if (rman_get_start(sc->port_res) != 0x310)
655 case ED_3COM_BCFR_330:
656 if (rman_get_start(sc->port_res) != 0x330)
659 case ED_3COM_BCFR_350:
660 if (rman_get_start(sc->port_res) != 0x350)
663 case ED_3COM_BCFR_250:
664 if (rman_get_start(sc->port_res) != 0x250)
667 case ED_3COM_BCFR_280:
668 if (rman_get_start(sc->port_res) != 0x280)
671 case ED_3COM_BCFR_2A0:
672 if (rman_get_start(sc->port_res) != 0x2a0)
675 case ED_3COM_BCFR_2E0:
676 if (rman_get_start(sc->port_res) != 0x2e0)
683 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
684 &conf_maddr, &conf_msize);
689 * Verify that the kernel shared memory address matches the board
690 * configured address.
692 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
693 case ED_3COM_PCFR_DC000:
694 if (conf_maddr != 0xdc000)
697 case ED_3COM_PCFR_D8000:
698 if (conf_maddr != 0xd8000)
701 case ED_3COM_PCFR_CC000:
702 if (conf_maddr != 0xcc000)
705 case ED_3COM_PCFR_C8000:
706 if (conf_maddr != 0xc8000)
715 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
716 * sequence because it'll lock up if the cable isn't connected if we
719 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
722 * Wait for a while, then un-reset it
727 * The 3Com ASIC defaults to rather strange settings for the CR after
728 * a reset - it's important to set it again after the following outb
729 * (this is done when we map the PROM below).
731 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
734 * Wait a bit for the NIC to recover from the reset
738 sc->vendor = ED_VENDOR_3COM;
739 sc->type_str = "3c503";
741 sc->cr_proto = ED_CR_RD2;
744 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
750 * Get station address from on-board ROM
754 * First, map ethernet address PROM over the top of where the NIC
755 * registers normally appear.
757 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
759 for (i = 0; i < ETHER_ADDR_LEN; ++i)
760 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
763 * Unmap PROM - select NIC registers. The proper setting of the
764 * tranceiver is set in ed_init so that the attach code is given a
765 * chance to set the default based on a compile-time config option
767 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
770 * Determine if this is an 8bit or 16bit board
774 * select page 0 registers
776 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
779 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
782 ed_nic_outb(sc, ED_P0_DCR, 0);
785 * select page 2 registers
787 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
790 * The 3c503 forces the WTS bit to a one if this is a 16bit board
792 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
798 * select page 0 registers
800 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
802 error = ed_alloc_memory(dev, 0, memsize);
806 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
807 sc->mem_size = memsize;
808 sc->mem_end = sc->mem_start + memsize;
811 * We have an entire 8k window to put the transmit buffers on the
812 * 16bit boards. But since the 16bit 3c503's shared memory is only
813 * fast enough to overlap the loading of one full-size packet, trying
814 * to load more than 2 buffers can actually leave the transmitter idle
815 * during the load. So 2 seems the best value. (Although a mix of
816 * variable-sized packets might change this assumption. Nonetheless,
817 * we optimize for linear transfers of same-size packets.)
820 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
825 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
826 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
827 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
828 ED_3COM_RX_PAGE_OFFSET_16BIT;
829 sc->mem_ring = sc->mem_start;
832 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
833 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
834 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
835 ED_3COM_TX_PAGE_OFFSET_8BIT;
836 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
839 sc->isa16bit = isa16bit;
842 * Initialize GA page start/stop registers. Probably only needed if
843 * doing DMA, but what the hell.
845 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
846 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
849 * Set IRQ. 3c503 only allows a choice of irq 2-5.
851 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
858 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
861 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
864 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
867 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
870 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
876 * Initialize GA configuration register. Set bank and enable shared
879 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
883 * Initialize "Vector Pointer" registers. These gawd-awful things are
884 * compared to 20 bits of the address on ISA, and if they match, the
885 * shared memory is disabled. We set them to 0xffff0...allegedly the
888 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
889 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
890 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
893 * Zero memory and verify that it is clear
895 bzero(sc->mem_start, memsize);
897 for (i = 0; i < memsize; ++i)
898 if (sc->mem_start[i]) {
899 device_printf(dev, "failed to clear shared memory "
900 "at %llx - check configuration\n",
901 (unsigned long long)kvtop(sc->mem_start + i));
908 * Probe and vendor-specific initialization routine for SIC boards
911 ed_probe_SIC(device_t dev, int port_rid, int flags)
913 struct ed_softc *sc = device_get_softc(dev);
917 u_long conf_maddr, conf_msize;
920 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
924 sc->asic_offset = ED_SIC_ASIC_OFFSET;
925 sc->nic_offset = ED_SIC_NIC_OFFSET;
927 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
928 &conf_maddr, &conf_msize);
934 memsize = conf_msize;
936 error = ed_alloc_memory(dev, 0, memsize);
940 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
941 sc->mem_size = memsize;
943 /* Reset card to force it into a known state. */
944 ed_asic_outb(sc, 0, 0x00);
948 * Here we check the card ROM, if the checksum passes, and the
949 * type code and ethernet address check out, then we know we have
952 ed_asic_outb(sc, 0, 0x81);
955 sum = sc->mem_start[6];
956 for (i = 0; i < ETHER_ADDR_LEN; i++) {
957 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
960 device_printf(dev, "ed_probe_sic: got address %6D\n",
961 sc->arpcom.ac_enaddr, ":");
966 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
967 sc->arpcom.ac_enaddr[2]) == 0) {
971 sc->vendor = ED_VENDOR_SIC;
972 sc->type_str = "SIC";
977 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
979 ed_asic_outb(sc, 0, 0x80);
983 * Now zero memory and verify that it is clear
985 bzero(sc->mem_start, sc->mem_size);
987 for (i = 0; i < sc->mem_size; i++) {
988 if (sc->mem_start[i]) {
989 device_printf(dev, "failed to clear shared memory "
990 "at %llx - check configuration\n",
991 (long long)kvtop(sc->mem_start + i));
998 sc->mem_end = sc->mem_start + sc->mem_size;
1001 * allocate one xmit buffer if < 16k, two buffers otherwise
1003 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1008 sc->tx_page_start = 0;
1010 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1011 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1013 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1019 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1022 ed_probe_Novell_generic(device_t dev, int flags)
1024 struct ed_softc *sc = device_get_softc(dev);
1026 u_char romdata[16], tmp;
1027 static char test_pattern[32] = "THIS is A memory TEST pattern";
1028 char test_buffer[32];
1030 /* XXX - do Novell-specific probe here */
1032 /* Reset the board */
1033 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1034 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1037 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1040 * I don't know if this is necessary; probably cruft leftover from
1041 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1042 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1043 * non-invasive...but some boards don't seem to reset and I don't have
1044 * complete documentation on what the 'right' thing to do is...so we
1045 * do the invasive thing for now. Yuck.]
1047 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1051 * This is needed because some NE clones apparently don't reset the
1052 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1053 * - this makes the probe invasive! ...Done against my better
1056 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1060 /* Make sure that we really have an 8390 based board */
1061 if (!ed_probe_generic8390(sc))
1064 sc->vendor = ED_VENDOR_NOVELL;
1066 sc->cr_proto = ED_CR_RD2;
1069 * Test the ability to read and write to the NIC memory. This has the
1070 * side affect of determining if this is an NE1000 or an NE2000.
1074 * This prevents packets from being stored in the NIC memory when the
1075 * readmem routine turns on the start bit in the CR.
1077 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1079 /* Temporarily initialize DCR for byte operations */
1080 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1082 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1083 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1088 * Write a test pattern in byte mode. If this fails, then there
1089 * probably isn't any memory at 8k - which likely means that the board
1092 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1093 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1095 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1096 sc->type = ED_TYPE_NE1000;
1097 sc->type_str = "NE1000";
1100 /* neither an NE1000 nor a Linksys - try NE2000 */
1101 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1102 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1103 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1108 * Write a test pattern in word mode. If this also fails, then
1109 * we don't know what this board is.
1111 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1112 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1113 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1114 sc->type = ED_TYPE_NE2000;
1115 sc->type_str = "NE2000";
1122 /* 8k of memory plus an additional 8k if 16bit */
1123 memsize = 8192 + sc->isa16bit * 8192;
1125 #if 0 /* probably not useful - NE boards only come two ways */
1126 /* allow kernel config file overrides */
1127 if (isa_dev->id_msize)
1128 memsize = isa_dev->id_msize;
1131 sc->mem_size = memsize;
1133 /* NIC memory doesn't start at zero on an NE board */
1134 /* The start address is tied to the bus width */
1135 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1136 sc->mem_end = sc->mem_start + memsize;
1137 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1139 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1140 int x, i, mstart = 0, msize = 0;
1141 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1143 for (i = 0; i < ED_PAGE_SIZE; i++)
1146 /* Clear all the memory. */
1147 for (x = 1; x < 256; x++)
1148 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1150 /* Search for the start of RAM. */
1151 for (x = 1; x < 256; x++) {
1152 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1153 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1154 for (i = 0; i < ED_PAGE_SIZE; i++)
1156 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1157 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1158 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1159 mstart = x * ED_PAGE_SIZE;
1160 msize = ED_PAGE_SIZE;
1167 device_printf(dev, "Cannot find start of RAM.\n");
1170 /* Search for the start of RAM. */
1171 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1172 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1173 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1174 for (i = 0; i < ED_PAGE_SIZE; i++)
1176 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1177 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1178 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1179 msize += ED_PAGE_SIZE;
1189 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1192 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1194 sc->mem_size = msize;
1195 sc->mem_start = (caddr_t) mstart;
1196 sc->mem_end = (caddr_t) (msize + mstart);
1197 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1201 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1204 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1209 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1210 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1212 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1214 ed_pio_readmem(sc, 0, romdata, 16);
1215 for (n = 0; n < ETHER_ADDR_LEN; n++)
1216 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1218 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1219 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1220 sc->type_str = "Gateway AT";
1223 /* clear any pending interrupts that might have occurred above */
1224 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1230 ed_probe_Novell(device_t dev, int port_rid, int flags)
1232 struct ed_softc *sc = device_get_softc(dev);
1235 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1239 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1240 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1242 return ed_probe_Novell_generic(dev, flags);
1245 #define ED_HPP_TEST_SIZE 16
1248 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1249 * (HP Part nos: 27247B and 27252A).
1251 * The card has an asic wrapper around a DS8390 core. The asic handles
1252 * host accesses and offers both standard register IO and memory mapped
1253 * IO. Memory mapped I/O allows better performance at the expense of greater
1254 * chance of an incompatibility with existing ISA cards.
1256 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1257 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1258 * don't allow 32 bit accesses; these are indicated by a bit in the software
1259 * ID register (see if_edreg.h).
1261 * Other caveats are: we should read the MAC address only when the card
1264 * For more information; please consult the CRYNWR packet driver.
1266 * The AUI port is turned on using the "link2" option on the ifconfig
1270 ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
1272 struct ed_softc *sc = device_get_softc(dev);
1274 int n; /* temp var */
1275 int memsize; /* mem on board */
1276 u_char checksum; /* checksum of board address */
1277 u_char irq; /* board configured IRQ */
1278 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1279 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1280 u_long conf_maddr, conf_msize, conf_irq, junk;
1282 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1286 /* Fill in basic information */
1287 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1288 sc->nic_offset = ED_HPP_NIC_OFFSET;
1290 sc->chip_type = ED_CHIP_TYPE_DP8390;
1291 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1294 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1297 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1298 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1299 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1300 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1304 * Read the MAC address and verify checksum on the address.
1307 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1308 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1309 checksum += (sc->arpcom.ac_enaddr[n] =
1310 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1312 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1314 if (checksum != 0xFF)
1318 * Verify that the software model number is 0.
1321 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1322 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1323 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1327 * Read in and save the current options configured on card.
1330 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1332 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1333 ED_HPP_OPTION_CHIP_RESET |
1334 ED_HPP_OPTION_ENABLE_IRQ);
1337 * Reset the chip. This requires writing to the option register
1338 * so take care to preserve the other bits.
1341 ed_asic_outw(sc, ED_HPP_OPTION,
1342 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1343 ED_HPP_OPTION_CHIP_RESET)));
1345 DELAY(5000); /* wait for chip reset to complete */
1347 ed_asic_outw(sc, ED_HPP_OPTION,
1348 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1349 ED_HPP_OPTION_CHIP_RESET |
1350 ED_HPP_OPTION_ENABLE_IRQ)));
1354 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1355 return ENXIO; /* reset did not complete */
1358 * Read out configuration information.
1361 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1363 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1366 * Check for impossible IRQ.
1369 if (irq >= NELEM(ed_hpp_intr_val))
1373 * If the kernel IRQ was specified with a '?' use the cards idea
1374 * of the IRQ. If the kernel IRQ was explicitly specified, it
1375 * should match that of the hardware.
1377 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1380 int intr_val = ed_hpp_intr_val[irq];
1382 bus_set_resource(dev, SYS_RES_IRQ, 0, intr_val, 1,
1383 machintr_intr_cpuid(intr_val));
1385 if (conf_irq != ed_hpp_intr_val[irq])
1390 * Fill in softconfig info.
1393 sc->vendor = ED_VENDOR_HP;
1394 sc->type = ED_TYPE_HP_PCLANPLUS;
1395 sc->type_str = "HP-PCLAN+";
1397 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1398 sc->mem_start = 0; /* we use offsets inside the card RAM */
1400 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1403 * The board has 32KB of memory. Is there a way to determine
1404 * this programmatically?
1410 * Check if memory mapping of the I/O registers possible.
1413 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1418 * determine the memory address from the board.
1421 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1422 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1425 * Check that the kernel specified start of memory and
1426 * hardware's idea of it match.
1428 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1429 &conf_maddr, &conf_msize);
1433 if (mem_addr != conf_maddr)
1436 error = ed_alloc_memory(dev, 0, memsize);
1440 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1444 * Fill in the rest of the soft config structure.
1448 * The transmit page index.
1451 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1453 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1459 * Memory description
1462 sc->mem_size = memsize;
1463 sc->mem_ring = sc->mem_start +
1464 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1465 sc->mem_end = sc->mem_start + sc->mem_size;
1468 * Receive area starts after the transmit area and
1469 * continues till the end of memory.
1472 sc->rec_page_start = sc->tx_page_start +
1473 (sc->txb_cnt * ED_TXBUF_SIZE);
1474 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1477 sc->cr_proto = 0; /* value works */
1480 * Set the wrap registers for string I/O reads.
1483 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1484 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1485 ((sc->rec_page_start / ED_PAGE_SIZE) |
1486 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1489 * Reset the register page to normal operation.
1492 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1495 * Verify that we can read/write from adapter memory.
1496 * Create test pattern.
1499 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1501 test_pattern[n] = (n*n) ^ ~n;
1504 #undef ED_HPP_TEST_SIZE
1507 * Check that the memory is accessible thru the I/O ports.
1508 * Write out the contents of "test_pattern", read back
1509 * into "test_buffer" and compare the two for any
1513 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1515 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1516 sizeof(test_pattern));
1517 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1518 test_buffer, sizeof(test_pattern));
1520 if (bcmp(test_pattern, test_buffer,
1521 sizeof(test_pattern)))
1530 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1534 ed_hpp_set_physical_link(struct ed_softc *sc)
1536 struct ifnet *ifp = &sc->arpcom.ac_if;
1539 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1540 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1542 if (ifp->if_flags & IFF_ALTPHYS) {
1548 lan_page |= ED_HPP_LAN_AUI;
1550 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1551 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1557 * Use the ThinLan interface
1560 lan_page &= ~ED_HPP_LAN_AUI;
1562 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1563 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1568 * Wait for the lan card to re-initialize itself
1571 DELAY(150000); /* wait 150 ms */
1574 * Restore normal pages.
1577 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1582 * Allocate a port resource with the given resource id.
1585 ed_alloc_port(device_t dev, int rid, int size)
1587 struct ed_softc *sc = device_get_softc(dev);
1588 struct resource *res;
1590 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1591 0ul, ~0ul, size, RF_ACTIVE);
1595 sc->port_used = size;
1603 * Allocate a memory resource with the given resource id.
1606 ed_alloc_memory(device_t dev, int rid, int size)
1608 struct ed_softc *sc = device_get_softc(dev);
1609 struct resource *res;
1611 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1612 0ul, ~0ul, size, RF_ACTIVE);
1616 sc->mem_used = size;
1624 * Allocate an irq resource with the given resource id.
1627 ed_alloc_irq(device_t dev, int rid, int flags)
1629 struct ed_softc *sc = device_get_softc(dev);
1630 struct resource *res;
1632 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1633 (RF_ACTIVE | flags));
1644 * Release all resources
1647 ed_release_resources(device_t dev)
1649 struct ed_softc *sc = device_get_softc(dev);
1652 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1653 sc->port_rid, sc->port_res);
1654 bus_release_resource(dev, SYS_RES_IOPORT,
1655 sc->port_rid, sc->port_res);
1659 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1660 sc->mem_rid, sc->mem_res);
1661 bus_release_resource(dev, SYS_RES_MEMORY,
1662 sc->mem_rid, sc->mem_res);
1666 bus_deactivate_resource(dev, SYS_RES_IRQ,
1667 sc->irq_rid, sc->irq_res);
1668 bus_release_resource(dev, SYS_RES_IRQ,
1669 sc->irq_rid, sc->irq_res);
1675 * Install interface into kernel networking data structures
1678 ed_attach(device_t dev)
1680 struct ed_softc *sc = device_get_softc(dev);
1681 struct ifnet *ifp = &sc->arpcom.ac_if;
1683 callout_init(&sc->ed_timer);
1685 * Set interface to stopped condition (reset)
1690 * Initialize ifnet structure
1693 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1694 ifp->if_mtu = ETHERMTU;
1695 ifp->if_start = ed_start;
1696 ifp->if_ioctl = ed_ioctl;
1697 ifp->if_watchdog = ed_watchdog;
1698 ifp->if_init = ed_init;
1699 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
1700 ifq_set_ready(&ifp->if_snd);
1701 ifp->if_linkmib = &sc->mibdata;
1702 ifp->if_linkmiblen = sizeof sc->mibdata;
1703 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1705 * XXX - should do a better job.
1707 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1708 sc->mibdata.dot3StatsEtherChipSet =
1709 DOT3CHIPSET(dot3VendorWesternDigital,
1710 dot3ChipSetWesternDigital83C790);
1712 sc->mibdata.dot3StatsEtherChipSet =
1713 DOT3CHIPSET(dot3VendorNational,
1714 dot3ChipSetNational8390);
1715 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1718 * Set default state for ALTPHYS flag (used to disable the
1719 * tranceiver for AUI operation), based on compile-time
1722 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1723 ifp->if_flags |= IFF_ALTPHYS;
1726 * Attach the interface
1728 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
1730 /* device attach does transition from UNCONFIGURED to IDLE state */
1732 if (sc->type_str && (*sc->type_str != 0))
1733 kprintf("type %s ", sc->type_str);
1735 kprintf("type unknown (0x%x) ", sc->type);
1737 if (sc->vendor == ED_VENDOR_HP)
1738 kprintf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1739 "16-bit" : "32-bit",
1740 sc->hpp_mem_start ? "memory mapped" : "regular");
1742 kprintf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1744 kprintf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1745 (sc->vendor == ED_VENDOR_HP)) &&
1746 (ifp->if_flags & IFF_ALTPHYS)) ? " transceiver disabled" : "");
1755 ed_reset(struct ifnet *ifp)
1757 struct ed_softc *sc = ifp->if_softc;
1767 * Stop interface and re-initialize.
1776 * Take interface offline.
1779 ed_stop(struct ed_softc *sc)
1783 #ifndef ED_NO_MIIBUS
1784 callout_stop(&sc->ed_timer);
1789 * Stop everything on the interface, and select page 0 registers.
1791 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1794 * Wait for interface to enter stopped state, but limit # of checks to
1795 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1796 * just in case it's an old one.
1798 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1799 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1803 * Device timeout/watchdog routine. Entered if the device neglects to
1804 * generate an interrupt after a transmit has been started on it.
1807 ed_watchdog(struct ifnet *ifp)
1809 struct ed_softc *sc = ifp->if_softc;
1813 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1819 #ifndef ED_NO_MIIBUS
1823 struct ed_softc *sc = arg;
1824 struct mii_data *mii;
1827 ifp = &sc->arpcom.ac_if;
1828 lwkt_serialize_enter(ifp->if_serializer);
1835 if (sc->miibus != NULL) {
1836 mii = device_get_softc(sc->miibus);
1840 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1841 lwkt_serialize_exit(ifp->if_serializer);
1846 * Initialize device.
1851 struct ed_softc *sc = xsc;
1852 struct ifnet *ifp = &sc->arpcom.ac_if;
1863 * Initialize the NIC in the exact order outlined in the NS manual.
1864 * This init procedure is "mandatory"...don't change what or when
1868 /* reset transmitter flags */
1874 sc->txb_next_tx = 0;
1876 /* This variable is used below - don't move this assignment */
1877 sc->next_packet = sc->rec_page_start + 1;
1880 * Set interface for page 0, Remote DMA complete, Stopped
1882 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1887 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1888 * order=80x86, word-wide DMA xfers,
1890 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1894 * Same as above, but byte-wide DMA xfers
1896 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1900 * Clear Remote Byte Count Registers
1902 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1903 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1906 * For the moment, don't store incoming packets in memory.
1908 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1911 * Place NIC in internal loopback mode
1913 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1916 * Initialize transmit/receive (ring-buffer) Page Start
1918 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1919 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1920 /* Set lower bits of byte addressable framing to 0 */
1921 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1922 ed_nic_outb(sc, 0x09, 0);
1925 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1927 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1928 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1931 * Clear all interrupts. A '1' in each bit position clears the
1932 * corresponding flag.
1934 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1937 * Enable the following interrupts: receive/transmit complete,
1938 * receive/transmit error, and Receiver OverWrite.
1940 * Counter overflow and Remote DMA complete are *not* enabled.
1942 ed_nic_outb(sc, ED_P0_IMR,
1943 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1946 * Program Command Register for page 1
1948 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1951 * Copy out our station address
1953 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1954 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1957 * Set Current Page pointer to next_packet (initialized above)
1959 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1962 * Program Receiver Configuration Register and multicast filter. CR is
1963 * set to page 0 on return.
1968 * Take interface out of loopback
1970 ed_nic_outb(sc, ED_P0_TCR, 0);
1973 * If this is a 3Com board, the tranceiver must be software enabled
1974 * (there is no settable hardware default).
1976 if (sc->vendor == ED_VENDOR_3COM) {
1977 if (ifp->if_flags & IFF_ALTPHYS) {
1978 ed_asic_outb(sc, ED_3COM_CR, 0);
1980 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1984 #ifndef ED_NO_MIIBUS
1985 if (sc->miibus != NULL) {
1986 struct mii_data *mii;
1987 mii = device_get_softc(sc->miibus);
1992 * Set 'running' flag, and clear output active flag.
1994 ifp->if_flags |= IFF_RUNNING;
1995 ifp->if_flags &= ~IFF_OACTIVE;
1998 * ...and attempt to start output
2002 #ifndef ED_NO_MIIBUS
2003 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
2010 * This routine actually starts the transmission on the interface
2012 static __inline void
2013 ed_xmit(struct ed_softc *sc)
2015 struct ifnet *ifp = (struct ifnet *)sc;
2020 len = sc->txb_len[sc->txb_next_tx];
2023 * Set NIC for page 0 register access
2025 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2028 * Set TX buffer start page
2030 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2031 sc->txb_next_tx * ED_TXBUF_SIZE);
2036 ed_nic_outb(sc, ED_P0_TBCR0, len);
2037 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2040 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2042 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2046 * Point to next transmit buffer slot and wrap if necessary.
2049 if (sc->txb_next_tx == sc->txb_cnt)
2050 sc->txb_next_tx = 0;
2053 * Set a timer just in case we never hear from the board again
2059 * Start output on interface.
2060 * We make two assumptions here:
2061 * 1) that the current priority is set to splimp _before_ this code
2062 * is called *and* is returned to the appropriate priority after
2064 * 2) that the IFF_OACTIVE flag is checked before this code is called
2065 * (i.e. that the output part of the interface is idle)
2068 ed_start(struct ifnet *ifp)
2070 struct ed_softc *sc = ifp->if_softc;
2071 struct mbuf *m0, *m;
2076 kprintf("ed_start(%p) GONE\n",ifp);
2077 ifq_purge(&ifp->if_snd);
2083 * First, see if there are buffered packets and an idle transmitter -
2084 * should never happen at this point.
2086 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2087 kprintf("ed: packets buffered, but transmitter idle\n");
2092 * See if there is room to put another packet in the buffer.
2094 if (sc->txb_inuse == sc->txb_cnt) {
2097 * No room. Indicate this to the outside world and exit.
2099 ifp->if_flags |= IFF_OACTIVE;
2102 m = ifq_dequeue(&ifp->if_snd, NULL);
2106 * We are using the !OACTIVE flag to indicate to the outside
2107 * world that we can accept an additional packet rather than
2108 * that the transmitter is _actually_ active. Indeed, the
2109 * transmitter may be active, but if we haven't filled all the
2110 * buffers with data then we still want to accept more.
2112 ifp->if_flags &= ~IFF_OACTIVE;
2117 * Copy the mbuf chain into the transmit buffer
2122 /* txb_new points to next open buffer slot */
2123 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2125 if (sc->mem_shared) {
2128 * Special case setup for 16 bit boards...
2131 switch (sc->vendor) {
2134 * For 16bit 3Com boards (which have 16k of
2135 * memory), we have the xmit buffers in a
2136 * different page of memory ('page 0') - so
2139 case ED_VENDOR_3COM:
2140 ed_asic_outb(sc, ED_3COM_GACFR,
2141 ED_3COM_GACFR_RSEL);
2145 * Enable 16bit access to shared memory on
2148 case ED_VENDOR_WD_SMC:
2149 ed_asic_outb(sc, ED_WD_LAAR,
2150 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2151 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2152 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2157 for (len = 0; m != 0; m = m->m_next) {
2158 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2164 * Restore previous shared memory access
2167 switch (sc->vendor) {
2168 case ED_VENDOR_3COM:
2169 ed_asic_outb(sc, ED_3COM_GACFR,
2170 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2172 case ED_VENDOR_WD_SMC:
2173 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2174 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2176 ed_asic_outb(sc, ED_WD_LAAR,
2177 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2182 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2189 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2194 * Point to next buffer slot and wrap if necessary.
2197 if (sc->txb_new == sc->txb_cnt)
2200 if (sc->xmit_busy == 0)
2208 * Loop back to the top to possibly buffer more packets
2214 * Ethernet interface receiver interrupt.
2216 static __inline void
2217 ed_rint(struct ed_softc *sc)
2219 struct ifnet *ifp = &sc->arpcom.ac_if;
2222 struct ed_ring packet_hdr;
2229 * Set NIC to page 1 registers to get 'current' pointer
2231 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2234 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2235 * i.e. it points to where new data has been buffered. The 'CURR'
2236 * (current) register points to the logical end of the ring-buffer -
2237 * i.e. it points to where additional new data will be added. We loop
2238 * here until the logical beginning equals the logical end (or in
2239 * other words, until the ring-buffer is empty).
2241 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2243 /* get pointer to this buffer's header structure */
2244 packet_ptr = sc->mem_ring +
2245 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2248 * The byte count includes a 4 byte header that was added by
2252 packet_hdr = *(struct ed_ring *) packet_ptr;
2254 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2255 sizeof(packet_hdr));
2256 len = packet_hdr.count;
2257 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2258 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2260 * Length is a wild value. There's a good chance that
2261 * this was caused by the NIC being old and buggy.
2262 * The bug is that the length low byte is duplicated in
2263 * the high byte. Try to recalculate the length based on
2264 * the pointer to the next packet.
2267 * NOTE: sc->next_packet is pointing at the current packet.
2269 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2270 if (packet_hdr.next_packet >= sc->next_packet) {
2271 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2273 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2274 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2277 * because buffers are aligned on 256-byte boundary,
2278 * the length computed above is off by 256 in almost
2279 * all cases. Fix it...
2283 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2284 + sizeof(struct ed_ring)))
2285 sc->mibdata.dot3StatsFrameTooLongs++;
2288 * Be fairly liberal about what we allow as a "reasonable" length
2289 * so that a [crufty] packet will make it to BPF (and can thus
2290 * be analyzed). Note that all that is really important is that
2291 * we have a length that will fit into one mbuf cluster or less;
2292 * the upper layer protocols can then figure out the length from
2293 * their own length field(s).
2294 * But make sure that we have at least a full ethernet header
2295 * or we would be unable to call ether_input() later.
2297 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2298 (len <= MCLBYTES) &&
2299 (packet_hdr.next_packet >= sc->rec_page_start) &&
2300 (packet_hdr.next_packet < sc->rec_page_stop)) {
2304 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2305 len - sizeof(struct ed_ring));
2309 * Really BAD. The ring pointers are corrupted.
2312 "%s: NIC memory corrupt - invalid packet length %d\n",
2313 ifp->if_xname, len);
2320 * Update next packet pointer
2322 sc->next_packet = packet_hdr.next_packet;
2325 * Update NIC boundry pointer - being careful to keep it one
2326 * buffer behind. (as recommended by NS databook)
2328 boundry = sc->next_packet - 1;
2329 if (boundry < sc->rec_page_start)
2330 boundry = sc->rec_page_stop - 1;
2333 * Set NIC to page 0 registers to update boundry register
2335 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2337 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2340 * Set NIC to page 1 registers before looping to top (prepare
2341 * to get 'CURR' current pointer)
2343 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2348 * Ethernet interface interrupt processor
2353 struct ed_softc *sc = (struct ed_softc*) arg;
2354 struct ifnet *ifp = (struct ifnet *)sc;
2361 * Set NIC to page 0 registers
2363 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2366 * loop until there are no more new interrupts. When the card
2367 * goes away, the hardware will read back 0xff. Looking at
2368 * the interrupts, it would appear that 0xff is impossible,
2369 * or at least extremely unlikely.
2371 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2374 * reset all the bits that we are 'acknowledging' by writing a
2375 * '1' to each bit position that was set (writing a '1'
2378 ed_nic_outb(sc, ED_P0_ISR, isr);
2381 * XXX workaround for AX88190
2382 * We limit this to 5000 iterations. At 1us per inb/outb,
2383 * this translates to about 15ms, which should be plenty
2384 * of time, and also gives protection in the card eject
2387 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2388 count = 5000; /* 15ms */
2389 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2390 ed_nic_outb(sc, ED_P0_ISR,0);
2391 ed_nic_outb(sc, ED_P0_ISR,isr);
2398 * Handle transmitter interrupts. Handle these first because
2399 * the receiver will reset the board under some conditions.
2401 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2402 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2405 * Check for transmit error. If a TX completed with an
2406 * error, we end up throwing the packet away. Really
2407 * the only error that is possible is excessive
2408 * collisions, and in this case it is best to allow
2409 * the automatic mechanisms of TCP to backoff the
2410 * flow. Of course, with UDP we're screwed, but this
2411 * is expected when a network is heavily loaded.
2413 ed_nic_inb(sc, ED_P0_TSR);
2414 if (isr & ED_ISR_TXE) {
2418 * Excessive collisions (16)
2420 tsr = ed_nic_inb(sc, ED_P0_TSR);
2421 if ((tsr & ED_TSR_ABT)
2422 && (collisions == 0)) {
2425 * When collisions total 16, the
2426 * P0_NCR will indicate 0, and the
2430 sc->mibdata.dot3StatsExcessiveCollisions++;
2431 sc->mibdata.dot3StatsCollFrequencies[15]++;
2433 if (tsr & ED_TSR_OWC)
2434 sc->mibdata.dot3StatsLateCollisions++;
2435 if (tsr & ED_TSR_CDH)
2436 sc->mibdata.dot3StatsSQETestErrors++;
2437 if (tsr & ED_TSR_CRS)
2438 sc->mibdata.dot3StatsCarrierSenseErrors++;
2439 if (tsr & ED_TSR_FU)
2440 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2443 * update output errors counter
2449 * Update total number of successfully
2450 * transmitted packets.
2456 * reset tx busy and output active flags
2459 ifp->if_flags &= ~IFF_OACTIVE;
2462 * clear watchdog timer
2467 * Add in total number of collisions on last
2470 ifp->if_collisions += collisions;
2471 switch(collisions) {
2476 sc->mibdata.dot3StatsSingleCollisionFrames++;
2477 sc->mibdata.dot3StatsCollFrequencies[0]++;
2480 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2482 dot3StatsCollFrequencies[collisions-1]
2488 * Decrement buffer in-use count if not zero (can only
2489 * be zero if a transmitter interrupt occured while
2490 * not actually transmitting). If data is ready to
2491 * transmit, start it transmitting, otherwise defer
2492 * until after handling receiver
2494 if (sc->txb_inuse && --sc->txb_inuse)
2499 * Handle receiver interrupts
2501 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2504 * Overwrite warning. In order to make sure that a
2505 * lockup of the local DMA hasn't occurred, we reset
2506 * and re-init the NIC. The NSC manual suggests only a
2507 * partial reset/re-init is necessary - but some chips
2508 * seem to want more. The DMA lockup has been seen
2509 * only with early rev chips - Methinks this bug was
2510 * fixed in later revs. -DG
2512 if (isr & ED_ISR_OVW) {
2516 "%s: warning - receiver ring buffer overrun\n",
2521 * Stop/reset/re-init NIC
2527 * Receiver Error. One or more of: CRC error,
2528 * frame alignment error FIFO overrun, or
2531 if (isr & ED_ISR_RXE) {
2533 rsr = ed_nic_inb(sc, ED_P0_RSR);
2534 if (rsr & ED_RSR_CRC)
2535 sc->mibdata.dot3StatsFCSErrors++;
2536 if (rsr & ED_RSR_FAE)
2537 sc->mibdata.dot3StatsAlignmentErrors++;
2538 if (rsr & ED_RSR_FO)
2539 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2542 if_printf("receive error %x\n",
2543 ed_nic_inb(sc, ED_P0_RSR));
2548 * Go get the packet(s) XXX - Doing this on an
2549 * error is dubious because there shouldn't be
2550 * any data to get (we've configured the
2551 * interface to not accept packets with
2556 * Enable 16bit access to shared memory first
2560 (sc->vendor == ED_VENDOR_WD_SMC)) {
2562 ed_asic_outb(sc, ED_WD_LAAR,
2563 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2564 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2565 ed_asic_outb(sc, ED_WD_MSR,
2571 /* disable 16bit access */
2573 (sc->vendor == ED_VENDOR_WD_SMC)) {
2575 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2576 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2578 ed_asic_outb(sc, ED_WD_LAAR,
2579 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2585 * If it looks like the transmitter can take more data,
2586 * attempt to start output on the interface. This is done
2587 * after handling the receiver to give the receiver priority.
2589 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2593 * return NIC CR to standard state: page 0, remote DMA
2594 * complete, start (toggling the TXP bit off, even if was just
2595 * set in the transmit routine, is *okay* - it is 'edge'
2596 * triggered from low to high)
2598 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2601 * If the Network Talley Counters overflow, read them to reset
2602 * them. It appears that old 8390's won't clear the ISR flag
2603 * otherwise - resulting in an infinite loop.
2605 if (isr & ED_ISR_CNT) {
2606 ed_nic_inb(sc, ED_P0_CNTR0);
2607 ed_nic_inb(sc, ED_P0_CNTR1);
2608 ed_nic_inb(sc, ED_P0_CNTR2);
2614 * Process an ioctl request. This code needs some work - it looks
2618 ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2620 struct ed_softc *sc = ifp->if_softc;
2621 #ifndef ED_NO_MIIBUS
2622 struct ifreq *ifr = (struct ifreq *)data;
2623 struct mii_data *mii;
2629 if (sc == NULL || sc->gone) {
2630 ifp->if_flags &= ~IFF_RUNNING;
2639 * If the interface is marked up and stopped, then start it.
2640 * If it is marked down and running, then stop it.
2642 if (ifp->if_flags & IFF_UP) {
2643 if ((ifp->if_flags & IFF_RUNNING) == 0)
2646 if (ifp->if_flags & IFF_RUNNING) {
2648 ifp->if_flags &= ~IFF_RUNNING;
2653 * Promiscuous flag may have changed, so reprogram the RCR.
2658 * An unfortunate hack to provide the (required) software
2659 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2660 * disables the tranceiver if set.
2662 if (sc->vendor == ED_VENDOR_3COM) {
2663 if (ifp->if_flags & IFF_ALTPHYS) {
2664 ed_asic_outb(sc, ED_3COM_CR, 0);
2666 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2668 } else if (sc->vendor == ED_VENDOR_HP)
2669 ed_hpp_set_physical_link(sc);
2675 * Multicast list has changed; set the hardware filter
2682 #ifndef ED_NO_MIIBUS
2685 if (sc->miibus == NULL) {
2689 mii = device_get_softc(sc->miibus);
2690 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2695 error = ether_ioctl(ifp, command, data);
2705 * Given a source and destination address, copy 'amount' of a packet from
2706 * the ring buffer into a linear destination buffer. Takes into account
2709 static __inline char *
2710 ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount)
2714 /* does copy wrap to lower addr in ring buffer? */
2715 if (src + amount > sc->mem_end) {
2716 tmp_amount = sc->mem_end - src;
2718 /* copy amount up to end of NIC memory */
2720 bcopy(src, dst, tmp_amount);
2722 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2724 amount -= tmp_amount;
2729 bcopy(src, dst, amount);
2731 ed_pio_readmem(sc, (int)src, dst, amount);
2733 return (src + amount);
2737 * Retreive packet from shared memory and send to the next level up via
2741 ed_get_packet(struct ed_softc *sc, char *buf, u_short len)
2743 struct ifnet *ifp = &sc->arpcom.ac_if;
2744 struct ether_header *eh;
2748 * Allocate a header mbuf.
2749 * We always put the received packet in a single buffer -
2750 * either with just an mbuf header or in a cluster attached
2751 * to the header. The +2 is to compensate for the alignment
2754 m = m_getl(len + 2, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
2757 m->m_pkthdr.rcvif = ifp;
2758 m->m_pkthdr.len = m->m_len = len;
2761 * The +2 is to longword align the start of the real packet.
2762 * This is important for NFS.
2765 eh = mtod(m, struct ether_header *);
2768 * Get packet, including link layer address, from interface.
2770 ed_ring_copy(sc, buf, (char *)eh, len);
2772 m->m_pkthdr.len = m->m_len = len;
2774 ifp->if_input(ifp, m);
2778 * Supporting routines
2782 * Given a NIC memory source address and a host memory destination
2783 * address, copy 'amount' from NIC to host using Programmed I/O.
2784 * The 'amount' is rounded up to a word - okay as long as mbufs
2786 * This routine is currently Novell-specific.
2789 ed_pio_readmem(struct ed_softc *sc, int src, u_char *dst, u_short amount)
2791 /* HP PC Lan+ cards need special handling */
2792 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2793 ed_hpp_readmem(sc, src, dst, amount);
2797 /* Regular Novell cards */
2798 /* select page 0 registers */
2799 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2801 /* round up to a word */
2805 /* set up DMA byte count */
2806 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2807 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2809 /* set up source address in NIC mem */
2810 ed_nic_outb(sc, ED_P0_RSAR0, src);
2811 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2813 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2816 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2818 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2823 * Stripped down routine for writing a linear buffer to NIC memory.
2824 * Only used in the probe routine to test the memory. 'len' must
2828 ed_pio_writemem(struct ed_softc *sc, char *src, u_short dst, u_short len)
2830 int maxwait = 200; /* about 240us */
2832 /* select page 0 registers */
2833 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2835 /* reset remote DMA complete flag */
2836 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2838 /* set up DMA byte count */
2839 ed_nic_outb(sc, ED_P0_RBCR0, len);
2840 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2842 /* set up destination address in NIC mem */
2843 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2844 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2846 /* set remote DMA write */
2847 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2850 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2852 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2856 * Wait for remote DMA complete. This is necessary because on the
2857 * transmit side, data is handled internally by the NIC in bursts and
2858 * we can't start another remote DMA until this one completes. Not
2859 * waiting causes really bad things to happen - like the NIC
2860 * irrecoverably jamming the ISA bus.
2862 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2866 * Write an mbuf chain to the destination NIC memory address using
2870 ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
2872 struct ifnet *ifp = (struct ifnet *)sc;
2873 u_short total_len, dma_len;
2875 int maxwait = 200; /* about 240us */
2877 /* HP PC Lan+ cards need special handling */
2878 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2879 return ed_hpp_write_mbufs(sc, m, dst);
2882 /* Regular Novell cards */
2883 /* First, count up the total number of bytes to copy */
2884 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2885 total_len += mp->m_len;
2887 dma_len = total_len;
2888 if (sc->isa16bit && (dma_len & 1))
2891 /* select page 0 registers */
2892 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2894 /* reset remote DMA complete flag */
2895 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2897 /* set up DMA byte count */
2898 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2899 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2901 /* set up destination address in NIC mem */
2902 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2903 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2905 /* set remote DMA write */
2906 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2909 * Transfer the mbuf chain to the NIC memory.
2910 * 16-bit cards require that data be transferred as words, and only words.
2911 * So that case requires some extra code to patch over odd-length mbufs.
2914 if (!sc->isa16bit) {
2915 /* NE1000s are easy */
2918 ed_asic_outsb(sc, ED_NOVELL_DATA,
2919 m->m_data, m->m_len);
2924 /* NE2000s are a pain */
2934 data = mtod(m, caddr_t);
2935 /* finish the last word */
2937 savebyte[1] = *data;
2938 ed_asic_outw(sc, ED_NOVELL_DATA,
2939 *(u_short *)savebyte);
2944 /* output contiguous words */
2946 ed_asic_outsw(sc, ED_NOVELL_DATA,
2951 /* save last byte, if necessary */
2953 savebyte[0] = *data;
2959 /* spit last byte */
2961 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2966 * Wait for remote DMA complete. This is necessary because on the
2967 * transmit side, data is handled internally by the NIC in bursts and
2968 * we can't start another remote DMA until this one completes. Not
2969 * waiting causes really bad things to happen - like the NIC
2970 * irrecoverably jamming the ISA bus.
2972 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2975 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
2984 * Support routines to handle the HP PC Lan+ card.
2988 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2993 ed_hpp_readmem(struct ed_softc *sc, u_short src, u_char *dst, u_short amount)
2996 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2999 /* Program the source address in RAM */
3000 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3003 * The HP PC Lan+ card supports word reads as well as
3004 * a memory mapped i/o port that is aliased to every
3005 * even address on the board.
3008 if (sc->hpp_mem_start) {
3010 /* Enable memory mapped access. */
3011 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3012 ~(ED_HPP_OPTION_MEM_DISABLE |
3013 ED_HPP_OPTION_BOOT_ROM_ENB));
3015 if (use_32bit_access && (amount > 3)) {
3016 u_int32_t *dl = (u_int32_t *) dst;
3017 volatile u_int32_t *const sl =
3018 (u_int32_t *) sc->hpp_mem_start;
3019 u_int32_t *const fence = dl + (amount >> 2);
3021 /* Copy out NIC data. We could probably write this
3022 as a `movsl'. The currently generated code is lousy.
3028 dst += (amount & ~3);
3033 /* Finish off any words left, as a series of short reads */
3035 u_short *d = (u_short *) dst;
3036 volatile u_short *const s =
3037 (u_short *) sc->hpp_mem_start;
3038 u_short *const fence = d + (amount >> 1);
3040 /* Copy out NIC data. */
3045 dst += (amount & ~1);
3050 * read in a byte; however we need to always read 16 bits
3051 * at a time or the hardware gets into a funny state
3055 /* need to read in a short and copy LSB */
3056 volatile u_short *const s =
3057 (volatile u_short *) sc->hpp_mem_start;
3062 /* Restore Boot ROM access. */
3064 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3068 /* Read in data using the I/O port */
3069 if (use_32bit_access && (amount > 3)) {
3070 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3071 dst += (amount & ~3);
3075 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3076 dst += (amount & ~1);
3079 if (amount == 1) { /* read in a short and keep the LSB */
3080 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3086 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3088 * Only used in the probe routine to test the memory. 'len' must
3092 ed_hpp_writemem(struct ed_softc *sc, u_char *src, u_short dst, u_short len)
3094 /* reset remote DMA complete flag */
3095 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3097 /* program the write address in RAM */
3098 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3100 if (sc->hpp_mem_start) {
3101 u_short *s = (u_short *) src;
3102 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3103 u_short *const fence = s + (len >> 1);
3106 * Enable memory mapped access.
3109 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3110 ~(ED_HPP_OPTION_MEM_DISABLE |
3111 ED_HPP_OPTION_BOOT_ROM_ENB));
3114 * Copy to NIC memory.
3121 * Restore Boot ROM access.
3124 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3127 /* write data using I/O writes */
3128 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3133 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3134 * outsw() or via the memory mapped interface to the same register.
3135 * Writes have to be in word units; byte accesses won't work and may cause
3136 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3141 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3146 volatile u_short * const d =
3147 (volatile u_short *) sc->hpp_mem_start;
3148 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3150 /* select page 0 registers */
3151 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3153 /* reset remote DMA complete flag */
3154 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3156 /* program the write address in RAM */
3157 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3159 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3160 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3161 ~(ED_HPP_OPTION_MEM_DISABLE |
3162 ED_HPP_OPTION_BOOT_ROM_ENB));
3167 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3169 total_len += (len = m->m_len);
3171 caddr_t data = mtod(m, caddr_t);
3172 /* finish the last word of the previous mbuf */
3174 savebyte[1] = *data;
3175 *d = *((u_short *) savebyte);
3176 data++; len--; wantbyte = 0;
3178 /* output contiguous words */
3179 if ((len > 3) && (use_32bit_accesses)) {
3180 volatile u_int32_t *const dl =
3181 (volatile u_int32_t *) d;
3182 u_int32_t *sl = (u_int32_t *) data;
3183 u_int32_t *fence = sl + (len >> 2);
3191 /* finish off remain 16 bit writes */
3193 u_short *s = (u_short *) data;
3194 u_short *fence = s + (len >> 1);
3202 /* save last byte if needed */
3203 if ((wantbyte = (len == 1)) != 0)
3204 savebyte[0] = *data;
3206 m = m->m_next; /* to next mbuf */
3208 if (wantbyte) /* write last byte */
3209 *d = *((u_short *) savebyte);
3211 /* use programmed I/O */
3213 total_len += (len = m->m_len);
3215 caddr_t data = mtod(m, caddr_t);
3216 /* finish the last word of the previous mbuf */
3218 savebyte[1] = *data;
3219 ed_asic_outw(sc, ED_HPP_PAGE_4,
3220 *((u_short *)savebyte));
3225 /* output contiguous words */
3226 if ((len > 3) && use_32bit_accesses) {
3227 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3232 /* finish off remaining 16 bit accesses */
3234 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3239 if ((wantbyte = (len == 1)) != 0)
3240 savebyte[0] = *data;
3245 if (wantbyte) /* spit last byte */
3246 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3250 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3251 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3256 #ifndef ED_NO_MIIBUS
3258 * MII bus support routines.
3261 ed_miibus_readreg(device_t dev, int phy, int reg)
3263 struct ed_softc *sc = device_get_softc(dev);
3273 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3274 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3275 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3276 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3277 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3279 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3280 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3281 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3285 return (failed ? 0 : val);
3289 ed_miibus_writereg(device_t dev, int phy, int reg, int data)
3291 struct ed_softc *sc = device_get_softc(dev);
3300 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3301 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3302 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3303 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3304 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3305 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3306 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3307 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3313 ed_ifmedia_upd(struct ifnet *ifp)
3315 struct ed_softc *sc;
3316 struct mii_data *mii;
3319 if (sc->gone || sc->miibus == NULL)
3322 mii = device_get_softc(sc->miibus);
3323 return mii_mediachg(mii);
3327 ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3329 struct ed_softc *sc;
3330 struct mii_data *mii;
3333 if (sc->gone || sc->miibus == NULL)
3336 mii = device_get_softc(sc->miibus);
3338 ifmr->ifm_active = mii->mii_media_active;
3339 ifmr->ifm_status = mii->mii_media_status;
3343 ed_child_detached(device_t dev, device_t child)
3345 struct ed_softc *sc;
3347 sc = device_get_softc(dev);
3348 if (child == sc->miibus)
3354 ed_setrcr(struct ed_softc *sc)
3356 struct ifnet *ifp = (struct ifnet *)sc;
3360 /* Bit 6 in AX88190 RCR register must be set. */
3361 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3366 /* set page 1 registers */
3367 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3369 if (ifp->if_flags & IFF_PROMISC) {
3372 * Reconfigure the multicast filter.
3374 for (i = 0; i < 8; i++)
3375 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3378 * And turn on promiscuous mode. Also enable reception of
3379 * runts and packets with CRC & alignment errors.
3381 /* Set page 0 registers */
3382 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3384 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3385 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3387 /* set up multicast addresses and filter modes */
3388 if (ifp->if_flags & IFF_MULTICAST) {
3391 if (ifp->if_flags & IFF_ALLMULTI) {
3392 mcaf[0] = 0xffffffff;
3393 mcaf[1] = 0xffffffff;
3395 ds_getmcaf(sc, mcaf);
3398 * Set multicast filter on chip.
3400 for (i = 0; i < 8; i++)
3401 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3403 /* Set page 0 registers */
3404 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3406 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3410 * Initialize multicast address hashing registers to
3411 * not accept multicasts.
3413 for (i = 0; i < 8; ++i)
3414 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3416 /* Set page 0 registers */
3417 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3419 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3426 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3430 * Compute crc for ethernet address
3433 ds_mchash(const uint8_t *addr)
3435 #define ED_POLYNOMIAL 0x04c11db6
3436 uint32_t crc = 0xffffffff;
3437 int carry, idx, bit;
3440 for (idx = 6; --idx >= 0;) {
3441 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3442 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
3445 crc = (crc ^ ED_POLYNOMIAL) | carry;
3453 * Compute the multicast address filter from the
3454 * list of multicast addresses we need to listen to.
3457 ds_getmcaf(struct ed_softc *sc, u_int32_t *mcaf)
3460 u_char *af = (u_char *) mcaf;
3461 struct ifmultiaddr *ifma;
3466 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) {
3467 if (ifma->ifma_addr->sa_family != AF_LINK)
3469 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3471 af[index >> 3] |= 1 << (index & 7);