sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/async.h>
  30 #include <drm/drmP.h>
  31 #include "intel_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include <drm/drm_legacy.h>
  34 #include "i915_drv.h"
  35 #include "i915_vgpu.h"
  36 #include "intel_ringbuffer.h"
  37 #include <linux/workqueue.h>
  38
  39
  40 static int i915_getparam(struct drm_device *dev, void *data,
  41                          struct drm_file *file_priv)
  42 {
  43         struct drm_i915_private *dev_priv = dev->dev_private;
  44         drm_i915_getparam_t *param = data;
  45         int value;
  46
  47         switch (param->param) {
  48         case I915_PARAM_IRQ_ACTIVE:
  49         case I915_PARAM_ALLOW_BATCHBUFFER:
  50         case I915_PARAM_LAST_DISPATCH:
  51                 /* Reject all old ums/dri params. */
  52                 return -ENODEV;
  53         case I915_PARAM_CHIPSET_ID:
  54                 value = dev->pdev->device;
  55                 break;
  56         case I915_PARAM_REVISION:
  57                 value = dev->pdev->revision;
  58                 break;
  59         case I915_PARAM_HAS_GEM:
  60                 value = 1;
  61                 break;
  62         case I915_PARAM_NUM_FENCES_AVAIL:
  63                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  64                 break;
  65         case I915_PARAM_HAS_OVERLAY:
  66                 value = dev_priv->overlay ? 1 : 0;
  67                 break;
  68         case I915_PARAM_HAS_PAGEFLIPPING:
  69                 value = 1;
  70                 break;
  71         case I915_PARAM_HAS_EXECBUF2:
  72                 /* depends on GEM */
  73                 value = 1;
  74                 break;
  75         case I915_PARAM_HAS_BSD:
  76                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  77                 break;
  78         case I915_PARAM_HAS_BLT:
  79                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  80                 break;
  81         case I915_PARAM_HAS_VEBOX:
  82                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  83                 break;
  84         case I915_PARAM_HAS_BSD2:
  85                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
  86                 break;
  87         case I915_PARAM_HAS_RELAXED_FENCING:
  88                 value = 1;
  89                 break;
  90         case I915_PARAM_HAS_COHERENT_RINGS:
  91                 value = 1;
  92                 break;
  93         case I915_PARAM_HAS_EXEC_CONSTANTS:
  94                 value = INTEL_INFO(dev)->gen >= 4;
  95                 break;
  96         case I915_PARAM_HAS_RELAXED_DELTA:
  97                 value = 1;
  98                 break;
  99         case I915_PARAM_HAS_GEN7_SOL_RESET:
 100                 value = 1;
 101                 break;
 102         case I915_PARAM_HAS_LLC:
 103                 value = HAS_LLC(dev);
 104                 break;
 105         case I915_PARAM_HAS_WT:
 106                 value = HAS_WT(dev);
 107                 break;
 108         case I915_PARAM_HAS_ALIASING_PPGTT:
 109                 value = USES_PPGTT(dev);
 110                 break;
 111         case I915_PARAM_HAS_WAIT_TIMEOUT:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_SEMAPHORES:
 115                 value = i915_semaphore_is_enabled(dev);
 116                 break;
 117         case I915_PARAM_HAS_PINNED_BATCHES:
 118                 value = 1;
 119                 break;
 120         case I915_PARAM_HAS_EXEC_NO_RELOC:
 121                 value = 1;
 122                 break;
 123         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 124                 value = 1;
 125                 break;
 126         case I915_PARAM_CMD_PARSER_VERSION:
 127                 value = i915_cmd_parser_get_version();
 128                 break;
 129         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 130                 value = 1;
 131                 break;
 132         case I915_PARAM_SUBSLICE_TOTAL:
 133                 value = INTEL_INFO(dev)->subslice_total;
 134                 if (!value)
 135                         return -ENODEV;
 136                 break;
 137         case I915_PARAM_EU_TOTAL:
 138                 value = INTEL_INFO(dev)->eu_total;
 139                 if (!value)
 140                         return -ENODEV;
 141                 break;
 142         default:
 143                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 144                 return -EINVAL;
 145         }
 146
 147         if (copy_to_user(param->value, &value, sizeof(int))) {
 148                 DRM_ERROR("copy_to_user failed\n");
 149                 return -EFAULT;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int i915_setparam(struct drm_device *dev, void *data,
 156                          struct drm_file *file_priv)
 157 {
 158         struct drm_i915_private *dev_priv = dev->dev_private;
 159         drm_i915_setparam_t *param = data;
 160
 161         switch (param->param) {
 162         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 163         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 164         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 165                 /* Reject all old ums/dri params. */
 166                 return -ENODEV;
 167
 168         case I915_SETPARAM_NUM_USED_FENCES:
 169                 if (param->value > dev_priv->num_fence_regs ||
 170                     param->value < 0)
 171                         return -EINVAL;
 172                 /* Userspace can use first N regs */
 173                 dev_priv->fence_reg_start = param->value;
 174                 break;
 175         default:
 176                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 177                                         param->param);
 178                 return -EINVAL;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int i915_get_bridge_dev(struct drm_device *dev)
 185 {
 186         struct drm_i915_private *dev_priv = dev->dev_private;
 187         static struct pci_dev i915_bridge_dev;
 188
 189         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
 190         if (!i915_bridge_dev.dev) {
 191                 DRM_ERROR("bridge device not found\n");
 192                 return -1;
 193         }
 194
 195         dev_priv->bridge_dev = &i915_bridge_dev;
 196         return 0;
 197 }
 198
 199 #define MCHBAR_I915 0x44
 200 #define MCHBAR_I965 0x48
 201 #define MCHBAR_SIZE (4*4096)
 202
 203 #define DEVEN_REG 0x54
 204 #define   DEVEN_MCHBAR_EN (1 << 28)
 205
 206 /* Allocate space for the MCH regs if needed, return nonzero on error */
 207 static int
 208 intel_alloc_mchbar_resource(struct drm_device *dev)
 209 {
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 212         device_t vga;
 213         u32 temp_lo, temp_hi = 0;
 214         u64 mchbar_addr;
 215
 216         if (INTEL_INFO(dev)->gen >= 4)
 217                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 218         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 219         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 220
 221         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 222 #ifdef CONFIG_PNP
 223         if (mchbar_addr &&
 224             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 225                 return 0;
 226 #endif
 227
 228         /* Get some space for it */
 229         vga = device_get_parent(dev->dev);
 230         dev_priv->mch_res_rid = 0x100;
 231         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
 232             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
 233             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
 234         if (dev_priv->mch_res == NULL) {
 235                 DRM_ERROR("failed mchbar resource alloc\n");
 236                 return (-ENOMEM);
 237         }
 238
 239         if (INTEL_INFO(dev)->gen >= 4)
 240                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 241                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
 242
 243         pci_write_config_dword(dev_priv->bridge_dev, reg,
 244                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
 245         return 0;
 246 }
 247
 248 /* Setup MCHBAR if possible, return true if we should disable it again */
 249 static void
 250 intel_setup_mchbar(struct drm_device *dev)
 251 {
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 254         u32 temp;
 255         bool enabled;
 256
 257         if (IS_VALLEYVIEW(dev))
 258                 return;
 259
 260         dev_priv->mchbar_need_disable = false;
 261
 262         if (IS_I915G(dev) || IS_I915GM(dev)) {
 263                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 264                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 265         } else {
 266                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 267                 enabled = temp & 1;
 268         }
 269
 270         /* If it's already enabled, don't have to do anything */
 271         if (enabled)
 272                 return;
 273
 274         if (intel_alloc_mchbar_resource(dev))
 275                 return;
 276
 277         dev_priv->mchbar_need_disable = true;
 278
 279         /* Space is allocated or reserved, so enable it. */
 280         if (IS_I915G(dev) || IS_I915GM(dev)) {
 281                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 282                                        temp | DEVEN_MCHBAR_EN);
 283         } else {
 284                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 285                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 286         }
 287 }
 288
 289 static void
 290 intel_teardown_mchbar(struct drm_device *dev)
 291 {
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 294         device_t vga;
 295         u32 temp;
 296
 297         if (dev_priv->mchbar_need_disable) {
 298                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 299                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 300                         temp &= ~DEVEN_MCHBAR_EN;
 301                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 302                 } else {
 303                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 304                         temp &= ~1;
 305                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 306                 }
 307         }
 308
 309         if (dev_priv->mch_res != NULL) {
 310                 vga = device_get_parent(dev->dev);
 311                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
 312                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 313                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
 314                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 315                 dev_priv->mch_res = NULL;
 316         }
 317 }
 318
 319 #if 0
 320 /* true = enable decode, false = disable decoder */
 321 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 322 {
 323         struct drm_device *dev = cookie;
 324
 325         intel_modeset_vga_set_state(dev, state);
 326         if (state)
 327                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 328                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 329         else
 330                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 331 }
 332
 333 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 334 {
 335         struct drm_device *dev = pci_get_drvdata(pdev);
 336         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 337
 338         if (state == VGA_SWITCHEROO_ON) {
 339                 pr_info("switched on\n");
 340                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 341                 /* i915 resume handler doesn't set to D0 */
 342                 pci_set_power_state(dev->pdev, PCI_D0);
 343                 i915_resume_legacy(dev);
 344                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 345         } else {
 346                 pr_err("switched off\n");
 347                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 348                 i915_suspend_legacy(dev, pmm);
 349                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 350         }
 351 }
 352
 353 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 354 {
 355         struct drm_device *dev = pci_get_drvdata(pdev);
 356
 357         /*
 358          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 359          * locking inversion with the driver load path. And the access here is
 360          * completely racy anyway. So don't bother with locking for now.
 361          */
 362         return dev->open_count == 0;
 363 }
 364
 365 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 366         .set_gpu_state = i915_switcheroo_set_state,
 367         .reprobe = NULL,
 368         .can_switch = i915_switcheroo_can_switch,
 369 };
 370 #endif
 371
 372 static int i915_load_modeset_init(struct drm_device *dev)
 373 {
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375         int ret;
 376
 377         ret = intel_parse_bios(dev);
 378         if (ret)
 379                 DRM_INFO("failed to find VBIOS tables\n");
 380
 381 #if 0
 382         /* If we have > 1 VGA cards, then we need to arbitrate access
 383          * to the common VGA resources.
 384          *
 385          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 386          * then we do not take part in VGA arbitration and the
 387          * vga_client_register() fails with -ENODEV.
 388          */
 389         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 390         if (ret && ret != -ENODEV)
 391                 goto out;
 392
 393         intel_register_dsm_handler();
 394
 395         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 396         if (ret)
 397                 goto cleanup_vga_client;
 398
 399         /* Initialise stolen first so that we may reserve preallocated
 400          * objects for the BIOS to KMS transition.
 401          */
 402         ret = i915_gem_init_stolen(dev);
 403         if (ret)
 404                 goto cleanup_vga_switcheroo;
 405 #endif
 406
 407         intel_power_domains_init_hw(dev_priv);
 408
 409 #ifdef __DragonFly__
 410         dev_priv->dev->pdev->irq = dev->irq;
 411 #endif
 412         ret = intel_irq_install(dev_priv);
 413         if (ret)
 414                 goto cleanup_gem_stolen;
 415
 416         /* Important: The output setup functions called by modeset_init need
 417          * working irqs for e.g. gmbus and dp aux transfers. */
 418         intel_modeset_init(dev);
 419
 420         ret = i915_gem_init(dev);
 421         if (ret)
 422                 goto cleanup_irq;
 423
 424         intel_modeset_gem_init(dev);
 425
 426         /* Always safe in the mode setting case. */
 427         /* FIXME: do pre/post-mode set stuff in core KMS code */
 428         dev->vblank_disable_allowed = 1;
 429         if (INTEL_INFO(dev)->num_pipes == 0)
 430                 return 0;
 431
 432         ret = intel_fbdev_init(dev);
 433         if (ret)
 434                 goto cleanup_gem;
 435
 436         /* Only enable hotplug handling once the fbdev is fully set up. */
 437         intel_hpd_init(dev_priv);
 438
 439         /*
 440          * Some ports require correctly set-up hpd registers for detection to
 441          * work properly (leading to ghost connected connector status), e.g. VGA
 442          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 443          * irqs are fully enabled. Now we should scan for the initial config
 444          * only once hotplug handling is enabled, but due to screwed-up locking
 445          * around kms/fbdev init we can't protect the fdbev initial config
 446          * scanning against hotplug events. Hence do this first and ignore the
 447          * tiny window where we will loose hotplug notifactions.
 448          */
 449         async_schedule(intel_fbdev_initial_config, dev_priv);
 450
 451         drm_kms_helper_poll_init(dev);
 452
 453         return 0;
 454
 455 cleanup_gem:
 456         mutex_lock(&dev->struct_mutex);
 457         i915_gem_cleanup_ringbuffer(dev);
 458         i915_gem_context_fini(dev);
 459         mutex_unlock(&dev->struct_mutex);
 460 cleanup_irq:
 461         drm_irq_uninstall(dev);
 462 cleanup_gem_stolen:
 463 #if 0
 464         i915_gem_cleanup_stolen(dev);
 465 cleanup_vga_switcheroo:
 466         vga_switcheroo_unregister_client(dev->pdev);
 467 cleanup_vga_client:
 468         vga_client_register(dev->pdev, NULL, NULL, NULL);
 469 out:
 470 #endif
 471         return ret;
 472 }
 473
 474 #if IS_ENABLED(CONFIG_FB)
 475 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 476 {
 477         struct apertures_struct *ap;
 478         struct pci_dev *pdev = dev_priv->dev->pdev;
 479         bool primary;
 480         int ret;
 481
 482         ap = alloc_apertures(1);
 483         if (!ap)
 484                 return -ENOMEM;
 485
 486         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 487         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 488
 489         primary =
 490                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 491
 492         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 493
 494         kfree(ap);
 495
 496         return ret;
 497 }
 498 #else
 499 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 500 {
 501         return 0;
 502 }
 503 #endif
 504
 505 #if !defined(CONFIG_VGA_CONSOLE)
 506 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 507 {
 508         return 0;
 509 }
 510 #elif !defined(CONFIG_DUMMY_CONSOLE)
 511 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 512 {
 513         return -ENODEV;
 514 }
 515 #else
 516 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 517 {
 518         int ret = 0;
 519
 520         DRM_INFO("Replacing VGA console driver\n");
 521
 522         console_lock();
 523         if (con_is_bound(&vga_con))
 524                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 525         if (ret == 0) {
 526                 ret = do_unregister_con_driver(&vga_con);
 527
 528                 /* Ignore "already unregistered". */
 529                 if (ret == -ENODEV)
 530                         ret = 0;
 531         }
 532         console_unlock();
 533
 534         return ret;
 535 }
 536 #endif
 537
 538 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 539 {
 540 #if 0
 541         const struct intel_device_info *info = &dev_priv->info;
 542
 543 #define PRINT_S(name) "%s"
 544 #define SEP_EMPTY
 545 #define PRINT_FLAG(name) info->name ? #name "," : ""
 546 #define SEP_COMMA ,
 547         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 548                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 549                          info->gen,
 550                          dev_priv->dev->pdev->device,
 551                          dev_priv->dev->pdev->revision,
 552                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 553 #undef PRINT_S
 554 #undef SEP_EMPTY
 555 #undef PRINT_FLAG
 556 #undef SEP_COMMA
 557 #endif
 558 }
 559
 560 static void cherryview_sseu_info_init(struct drm_device *dev)
 561 {
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         struct intel_device_info *info;
 564         u32 fuse, eu_dis;
 565
 566         info = (struct intel_device_info *)&dev_priv->info;
 567         fuse = I915_READ(CHV_FUSE_GT);
 568
 569         info->slice_total = 1;
 570
 571         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 572                 info->subslice_per_slice++;
 573                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 574                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 575                 info->eu_total += 8 - hweight32(eu_dis);
 576         }
 577
 578         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 579                 info->subslice_per_slice++;
 580                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 581                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 582                 info->eu_total += 8 - hweight32(eu_dis);
 583         }
 584
 585         info->subslice_total = info->subslice_per_slice;
 586         /*
 587          * CHV expected to always have a uniform distribution of EU
 588          * across subslices.
 589         */
 590         info->eu_per_subslice = info->subslice_total ?
 591                                 info->eu_total / info->subslice_total :
 592                                 0;
 593         /*
 594          * CHV supports subslice power gating on devices with more than
 595          * one subslice, and supports EU power gating on devices with
 596          * more than one EU pair per subslice.
 597         */
 598         info->has_slice_pg = 0;
 599         info->has_subslice_pg = (info->subslice_total > 1);
 600         info->has_eu_pg = (info->eu_per_subslice > 2);
 601 }
 602
 603 static void gen9_sseu_info_init(struct drm_device *dev)
 604 {
 605         struct drm_i915_private *dev_priv = dev->dev_private;
 606         struct intel_device_info *info;
 607         int s_max = 3, ss_max = 4, eu_max = 8;
 608         int s, ss;
 609         u32 fuse2, s_enable, ss_disable, eu_disable;
 610         u8 eu_mask = 0xff;
 611
 612         /*
 613          * BXT has a single slice. BXT also has at most 6 EU per subslice,
 614          * and therefore only the lowest 6 bits of the 8-bit EU disable
 615          * fields are valid.
 616         */
 617         if (IS_BROXTON(dev)) {
 618                 s_max = 1;
 619                 eu_max = 6;
 620                 eu_mask = 0x3f;
 621         }
 622
 623         info = (struct intel_device_info *)&dev_priv->info;
 624         fuse2 = I915_READ(GEN8_FUSE2);
 625         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 626                    GEN8_F2_S_ENA_SHIFT;
 627         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 628                      GEN9_F2_SS_DIS_SHIFT;
 629
 630         info->slice_total = hweight32(s_enable);
 631         /*
 632          * The subslice disable field is global, i.e. it applies
 633          * to each of the enabled slices.
 634         */
 635         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 636         info->subslice_total = info->slice_total *
 637                                info->subslice_per_slice;
 638
 639         /*
 640          * Iterate through enabled slices and subslices to
 641          * count the total enabled EU.
 642         */
 643         for (s = 0; s < s_max; s++) {
 644                 if (!(s_enable & (0x1 << s)))
 645                         /* skip disabled slice */
 646                         continue;
 647
 648                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 649                 for (ss = 0; ss < ss_max; ss++) {
 650                         int eu_per_ss;
 651
 652                         if (ss_disable & (0x1 << ss))
 653                                 /* skip disabled subslice */
 654                                 continue;
 655
 656                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 657                                                       eu_mask);
 658
 659                         /*
 660                          * Record which subslice(s) has(have) 7 EUs. we
 661                          * can tune the hash used to spread work among
 662                          * subslices if they are unbalanced.
 663                          */
 664                         if (eu_per_ss == 7)
 665                                 info->subslice_7eu[s] |= 1 << ss;
 666
 667                         info->eu_total += eu_per_ss;
 668                 }
 669         }
 670
 671         /*
 672          * SKL is expected to always have a uniform distribution
 673          * of EU across subslices with the exception that any one
 674          * EU in any one subslice may be fused off for die
 675          * recovery. BXT is expected to be perfectly uniform in EU
 676          * distribution.
 677         */
 678         info->eu_per_subslice = info->subslice_total ?
 679                                 DIV_ROUND_UP(info->eu_total,
 680                                              info->subslice_total) : 0;
 681         /*
 682          * SKL supports slice power gating on devices with more than
 683          * one slice, and supports EU power gating on devices with
 684          * more than one EU pair per subslice. BXT supports subslice
 685          * power gating on devices with more than one subslice, and
 686          * supports EU power gating on devices with more than one EU
 687          * pair per subslice.
 688         */
 689         info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
 690         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 691         info->has_eu_pg = (info->eu_per_subslice > 2);
 692 }
 693
 694 /*
 695  * Determine various intel_device_info fields at runtime.
 696  *
 697  * Use it when either:
 698  *   - it's judged too laborious to fill n static structures with the limit
 699  *     when a simple if statement does the job,
 700  *   - run-time checks (eg read fuse/strap registers) are needed.
 701  *
 702  * This function needs to be called:
 703  *   - after the MMIO has been setup as we are reading registers,
 704  *   - after the PCH has been detected,
 705  *   - before the first usage of the fields it can tweak.
 706  */
 707 static void intel_device_info_runtime_init(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         struct intel_device_info *info;
 711         enum i915_pipe pipe;
 712
 713         info = (struct intel_device_info *)&dev_priv->info;
 714
 715         if (IS_BROXTON(dev)) {
 716                 info->num_sprites[PIPE_A] = 3;
 717                 info->num_sprites[PIPE_B] = 3;
 718                 info->num_sprites[PIPE_C] = 2;
 719         } else if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
 720                 for_each_pipe(dev_priv, pipe)
 721                         info->num_sprites[pipe] = 2;
 722         else
 723                 for_each_pipe(dev_priv, pipe)
 724                         info->num_sprites[pipe] = 1;
 725
 726         if (i915.disable_display) {
 727                 DRM_INFO("Display disabled (module parameter)\n");
 728                 info->num_pipes = 0;
 729         } else if (info->num_pipes > 0 &&
 730                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 731                    !IS_VALLEYVIEW(dev)) {
 732                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 733                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 734
 735                 /*
 736                  * SFUSE_STRAP is supposed to have a bit signalling the display
 737                  * is fused off. Unfortunately it seems that, at least in
 738                  * certain cases, fused off display means that PCH display
 739                  * reads don't land anywhere. In that case, we read 0s.
 740                  *
 741                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 742                  * should be set when taking over after the firmware.
 743                  */
 744                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 745                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 746                     (dev_priv->pch_type == PCH_CPT &&
 747                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 748                         DRM_INFO("Display fused off, disabling\n");
 749                         info->num_pipes = 0;
 750                 }
 751         }
 752
 753         /* Initialize slice/subslice/EU info */
 754         if (IS_CHERRYVIEW(dev))
 755                 cherryview_sseu_info_init(dev);
 756         else if (INTEL_INFO(dev)->gen >= 9)
 757                 gen9_sseu_info_init(dev);
 758
 759         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 760         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 761         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 762         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 763         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 764         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 765                          info->has_slice_pg ? "y" : "n");
 766         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 767                          info->has_subslice_pg ? "y" : "n");
 768         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 769                          info->has_eu_pg ? "y" : "n");
 770 }
 771
 772 /**
 773  * i915_driver_load - setup chip and create an initial config
 774  * @dev: DRM device
 775  * @flags: startup flags
 776  *
 777  * The driver load routine has to do several things:
 778  *   - drive output discovery via intel_modeset_init()
 779  *   - initialize the memory manager
 780  *   - allocate initial config memory
 781  *   - setup the DRM framebuffer with the allocated memory
 782  */
 783 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 784 {
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct intel_device_info *info, *device_info;
 787         unsigned long base, size;
 788         int ret = 0, mmio_bar, mmio_size;
 789         uint32_t aperture_size;
 790
 791         /* XXX: struct pci_dev */
 792         info = i915_get_device_id(dev->pdev->device);
 793
 794         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 795         if (dev_priv == NULL)
 796                 return -ENOMEM;
 797
 798         dev->dev_private = dev_priv;
 799         dev_priv->dev = dev;
 800
 801         /* Setup the write-once "constant" device info */
 802         device_info = (struct intel_device_info *)&dev_priv->info;
 803         memcpy(device_info, info, sizeof(dev_priv->info));
 804         device_info->device_id = dev->pdev->device;
 805
 806         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
 807         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
 808         lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
 809         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
 810         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
 811         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
 812         lockinit(&dev_priv->sb_lock, "i915sbl", 0, LK_CANRECURSE);
 813         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
 814         lockinit(&dev_priv->csr_lock, "i915csr", 0, LK_CANRECURSE);
 815
 816         intel_pm_setup(dev);
 817
 818         intel_display_crc_init(dev);
 819
 820         i915_dump_device_info(dev_priv);
 821
 822         /* Not all pre-production machines fall into this category, only the
 823          * very first ones. Almost everything should work, except for maybe
 824          * suspend/resume. And we don't implement workarounds that affect only
 825          * pre-production machines. */
 826         if (IS_HSW_EARLY_SDV(dev))
 827                 DRM_INFO("This is an early pre-production Haswell machine. "
 828                          "It may not be fully functional.\n");
 829
 830         if (i915_get_bridge_dev(dev)) {
 831                 ret = -EIO;
 832                 goto free_priv;
 833         }
 834
 835         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 836         /* Before gen4, the registers and the GTT are behind different BARs.
 837          * However, from gen4 onwards, the registers and the GTT are shared
 838          * in the same BAR, so we want to restrict this ioremap from
 839          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 840          * the register BAR remains the same size for all the earlier
 841          * generations up to Ironlake.
 842          */
 843         if (info->gen < 5)
 844                 mmio_size = 512*1024;
 845         else
 846                 mmio_size = 2*1024*1024;
 847
 848         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 849         if (!dev_priv->regs) {
 850                 DRM_ERROR("failed to map registers\n");
 851                 ret = -EIO;
 852                 goto put_bridge;
 853         }
 854 #ifdef __DragonFly__
 855         base = drm_get_resource_start(dev, mmio_bar);
 856         size = drm_get_resource_len(dev, mmio_bar);
 857
 858         ret = drm_legacy_addmap(dev, base, size, _DRM_REGISTERS,
 859             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
 860 #endif
 861
 862         /* This must be called before any calls to HAS_PCH_* */
 863         intel_detect_pch(dev);
 864
 865         intel_uncore_init(dev);
 866
 867         /* Load CSR Firmware for SKL */
 868         intel_csr_ucode_init(dev);
 869
 870         ret = i915_gem_gtt_init(dev);
 871         if (ret)
 872                 goto out_freecsr;
 873
 874         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 875          * otherwise the vga fbdev driver falls over. */
 876         ret = i915_kick_out_firmware_fb(dev_priv);
 877         if (ret) {
 878                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 879                 goto out_gtt;
 880         }
 881
 882         ret = i915_kick_out_vgacon(dev_priv);
 883         if (ret) {
 884                 DRM_ERROR("failed to remove conflicting VGA console\n");
 885                 goto out_gtt;
 886         }
 887
 888 #if 0
 889         pci_set_master(dev->pdev);
 890
 891         /* overlay on gen2 is broken and can't address above 1G */
 892         if (IS_GEN2(dev))
 893                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 894
 895         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 896          * using 32bit addressing, overwriting memory if HWS is located
 897          * above 4GB.
 898          *
 899          * The documentation also mentions an issue with undefined
 900          * behaviour if any general state is accessed within a page above 4GB,
 901          * which also needs to be handled carefully.
 902          */
 903         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 904                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 905 #endif
 906
 907         aperture_size = dev_priv->gtt.mappable_end;
 908
 909         dev_priv->gtt.mappable =
 910                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 911                                      aperture_size);
 912         if (dev_priv->gtt.mappable == NULL) {
 913                 ret = -EIO;
 914                 goto out_gtt;
 915         }
 916
 917         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 918                                               aperture_size);
 919
 920         /* The i915 workqueue is primarily used for batched retirement of
 921          * requests (and thus managing bo) once the task has been completed
 922          * by the GPU. i915_gem_retire_requests() is called directly when we
 923          * need high-priority retirement, such as waiting for an explicit
 924          * bo.
 925          *
 926          * It is also used for periodic low-priority events, such as
 927          * idle-timers and recording error state.
 928          *
 929          * All tasks on the workqueue are expected to acquire the dev mutex
 930          * so there is no point in running more than one instance of the
 931          * workqueue at any time.  Use an ordered one.
 932          */
 933         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 934         if (dev_priv->wq == NULL) {
 935                 DRM_ERROR("Failed to create our workqueue.\n");
 936                 ret = -ENOMEM;
 937                 goto out_mtrrfree;
 938         }
 939
 940         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 941         if (dev_priv->dp_wq == NULL) {
 942                 DRM_ERROR("Failed to create our dp workqueue.\n");
 943                 ret = -ENOMEM;
 944                 goto out_freewq;
 945         }
 946
 947         dev_priv->gpu_error.hangcheck_wq =
 948                 alloc_ordered_workqueue("i915-hangcheck", 0);
 949         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
 950                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
 951                 ret = -ENOMEM;
 952                 goto out_freedpwq;
 953         }
 954
 955         intel_irq_init(dev_priv);
 956         intel_uncore_sanitize(dev);
 957
 958         /* Try to make sure MCHBAR is enabled before poking at it */
 959         intel_setup_mchbar(dev);
 960         intel_setup_gmbus(dev);
 961         intel_opregion_setup(dev);
 962
 963         intel_setup_bios(dev);
 964
 965         i915_gem_load(dev);
 966
 967         /* On the 945G/GM, the chipset reports the MSI capability on the
 968          * integrated graphics even though the support isn't actually there
 969          * according to the published specs.  It doesn't appear to function
 970          * correctly in testing on 945G.
 971          * This may be a side effect of MSI having been made available for PEG
 972          * and the registers being closely associated.
 973          *
 974          * According to chipset errata, on the 965GM, MSI interrupts may
 975          * be lost or delayed, but we use them anyways to avoid
 976          * stuck interrupts on some machines.
 977          */
 978 #if 0
 979         if (!IS_I945G(dev) && !IS_I945GM(dev))
 980                 pci_enable_msi(dev->pdev);
 981 #endif
 982
 983         intel_device_info_runtime_init(dev);
 984
 985         if (INTEL_INFO(dev)->num_pipes) {
 986                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 987                 if (ret)
 988                         goto out_gem_unload;
 989         }
 990
 991         intel_power_domains_init(dev_priv);
 992
 993         ret = i915_load_modeset_init(dev);
 994         if (ret < 0) {
 995                 DRM_ERROR("failed to init modeset\n");
 996                 goto out_power_well;
 997         }
 998
 999         /*
1000          * Notify a valid surface after modesetting,
1001          * when running inside a VM.
1002          */
1003         if (intel_vgpu_active(dev))
1004                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1005
1006         i915_setup_sysfs(dev);
1007
1008         if (INTEL_INFO(dev)->num_pipes) {
1009                 /* Must be done after probing outputs */
1010                 intel_opregion_init(dev);
1011 #if 0
1012                 acpi_video_register();
1013 #endif
1014         }
1015
1016         if (IS_GEN5(dev))
1017                 intel_gpu_ips_init(dev_priv);
1018
1019         intel_runtime_pm_enable(dev_priv);
1020
1021         i915_audio_component_init(dev_priv);
1022
1023         return 0;
1024
1025 out_power_well:
1026         intel_power_domains_fini(dev_priv);
1027         drm_vblank_cleanup(dev);
1028 out_gem_unload:
1029
1030         intel_teardown_gmbus(dev);
1031         intel_teardown_mchbar(dev);
1032         pm_qos_remove_request(&dev_priv->pm_qos);
1033         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1034 out_freedpwq:
1035         destroy_workqueue(dev_priv->dp_wq);
1036 out_freewq:
1037         destroy_workqueue(dev_priv->wq);
1038 out_mtrrfree:
1039         arch_phys_wc_del(dev_priv->gtt.mtrr);
1040 #if 0
1041         io_mapping_free(dev_priv->gtt.mappable);
1042 #endif
1043 out_gtt:
1044         i915_global_gtt_cleanup(dev);
1045 out_freecsr:
1046         intel_csr_ucode_fini(dev);
1047         intel_uncore_fini(dev);
1048 #if 0
1049         pci_iounmap(dev->pdev, dev_priv->regs);
1050 #endif
1051 put_bridge:
1052         pci_dev_put(dev_priv->bridge_dev);
1053 free_priv:
1054         kfree(dev_priv);
1055         return ret;
1056 }
1057
1058 int i915_driver_unload(struct drm_device *dev)
1059 {
1060         struct drm_i915_private *dev_priv = dev->dev_private;
1061         int ret;
1062
1063         i915_audio_component_cleanup(dev_priv);
1064
1065         ret = i915_gem_suspend(dev);
1066         if (ret) {
1067                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1068                 return ret;
1069         }
1070
1071         intel_power_domains_fini(dev_priv);
1072
1073         intel_gpu_ips_teardown();
1074
1075         i915_teardown_sysfs(dev);
1076
1077 #if 0
1078         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1079         unregister_shrinker(&dev_priv->mm.shrinker);
1080
1081         io_mapping_free(dev_priv->gtt.mappable);
1082 #endif
1083         arch_phys_wc_del(dev_priv->gtt.mtrr);
1084
1085 #if 0
1086         acpi_video_unregister();
1087 #endif
1088
1089         intel_fbdev_fini(dev);
1090
1091         drm_vblank_cleanup(dev);
1092
1093         intel_modeset_cleanup(dev);
1094
1095         /*
1096          * free the memory space allocated for the child device
1097          * config parsed from VBT
1098          */
1099         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1100                 kfree(dev_priv->vbt.child_dev);
1101                 dev_priv->vbt.child_dev = NULL;
1102                 dev_priv->vbt.child_dev_num = 0;
1103         }
1104
1105 #if 0
1106         vga_switcheroo_unregister_client(dev->pdev);
1107         vga_client_register(dev->pdev, NULL, NULL, NULL);
1108 #endif
1109
1110         /* Free error state after interrupts are fully disabled. */
1111         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1112 #if 0
1113         i915_destroy_error_state(dev);
1114
1115         if (dev->pdev->msi_enabled)
1116                 pci_disable_msi(dev->pdev);
1117 #endif
1118
1119         intel_opregion_fini(dev);
1120
1121         /* Flush any outstanding unpin_work. */
1122         flush_workqueue(dev_priv->wq);
1123
1124         mutex_lock(&dev->struct_mutex);
1125         i915_gem_cleanup_ringbuffer(dev);
1126         i915_gem_context_fini(dev);
1127         mutex_unlock(&dev->struct_mutex);
1128 #if 0
1129         i915_gem_cleanup_stolen(dev);
1130 #endif
1131
1132         intel_csr_ucode_fini(dev);
1133
1134         intel_teardown_gmbus(dev);
1135         intel_teardown_mchbar(dev);
1136
1137         destroy_workqueue(dev_priv->dp_wq);
1138         destroy_workqueue(dev_priv->wq);
1139         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1140         pm_qos_remove_request(&dev_priv->pm_qos);
1141
1142         i915_global_gtt_cleanup(dev);
1143
1144         intel_uncore_fini(dev);
1145 #if 0
1146         if (dev_priv->regs != NULL)
1147                 pci_iounmap(dev->pdev, dev_priv->regs);
1148
1149         if (dev_priv->slab)
1150                 kmem_cache_destroy(dev_priv->slab);
1151 #endif
1152
1153         pci_dev_put(dev_priv->bridge_dev);
1154         kfree(dev_priv);
1155
1156         return 0;
1157 }
1158
1159 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1160 {
1161         int ret;
1162
1163         ret = i915_gem_open(dev, file);
1164         if (ret)
1165                 return ret;
1166
1167         return 0;
1168 }
1169
1170 /**
1171  * i915_driver_lastclose - clean up after all DRM clients have exited
1172  * @dev: DRM device
1173  *
1174  * Take care of cleaning up after all DRM clients have exited.  In the
1175  * mode setting case, we want to restore the kernel's initial mode (just
1176  * in case the last client left us in a bad state).
1177  *
1178  * Additionally, in the non-mode setting case, we'll tear down the GTT
1179  * and DMA structures, since the kernel won't be using them, and clea
1180  * up any GEM state.
1181  */
1182 void i915_driver_lastclose(struct drm_device *dev)
1183 {
1184         intel_fbdev_restore_mode(dev);
1185 #if 0
1186         vga_switcheroo_process_delayed_switch();
1187 #endif
1188 }
1189
1190 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1191 {
1192         mutex_lock(&dev->struct_mutex);
1193         i915_gem_context_close(dev, file);
1194         i915_gem_release(dev, file);
1195         mutex_unlock(&dev->struct_mutex);
1196
1197         intel_modeset_preclose(dev, file);
1198 }
1199
1200 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1201 {
1202         struct drm_i915_file_private *file_priv = file->driver_priv;
1203
1204         if (file_priv && file_priv->bsd_ring)
1205                 file_priv->bsd_ring = NULL;
1206         kfree(file_priv);
1207 }
1208
1209 static int
1210 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1211                           struct drm_file *file)
1212 {
1213         return -ENODEV;
1214 }
1215
1216 const struct drm_ioctl_desc i915_ioctls[] = {
1217         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1218         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1219         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1220         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1221         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1222         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1223         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1224         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1225         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1226         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1227         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1228         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1229         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1230         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1231         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1232         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1233         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1234         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1235         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1236         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1237         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1238         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1239         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1240         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1241         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1242         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1243         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1244         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1245         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1246         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1247         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1248         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1249         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1250         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1251         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1252         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1253         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1254         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1255         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1256         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1257         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1258         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1259         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1260         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1261         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1262         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1263         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1264         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1265         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1266 #if 0
1267         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1268 #endif
1269         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1270         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1271 };
1272
1273 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
1274
1275 /*
1276  * This is really ugly: Because old userspace abused the linux agp interface to
1277  * manage the gtt, we need to claim that all intel devices are agp.  For
1278  * otherwise the drm core refuses to initialize the agp support code.
1279  */
1280 int i915_driver_device_is_agp(struct drm_device *dev)
1281 {
1282         return 1;
1283 }