sys/dev/netif/jme/if_jme.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
  28  */
  29
  30 #include "opt_polling.h"
  31 #include "opt_jme.h"
  32
  33 #include <sys/param.h>
  34 #include <sys/endian.h>
  35 #include <sys/kernel.h>
  36 #include <sys/bus.h>
  37 #include <sys/interrupt.h>
  38 #include <sys/malloc.h>
  39 #include <sys/proc.h>
  40 #include <sys/rman.h>
  41 #include <sys/serialize.h>
  42 #include <sys/serialize2.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46
  47 #include <net/ethernet.h>
  48 #include <net/if.h>
  49 #include <net/bpf.h>
  50 #include <net/if_arp.h>
  51 #include <net/if_dl.h>
  52 #include <net/if_media.h>
  53 #include <net/ifq_var.h>
  54 #include <net/toeplitz.h>
  55 #include <net/toeplitz2.h>
  56 #include <net/vlan/if_vlan_var.h>
  57 #include <net/vlan/if_vlan_ether.h>
  58
  59 #include <netinet/in.h>
  60
  61 #include <dev/netif/mii_layer/miivar.h>
  62 #include <dev/netif/mii_layer/jmphyreg.h>
  63
  64 #include <bus/pci/pcireg.h>
  65 #include <bus/pci/pcivar.h>
  66 #include <bus/pci/pcidevs.h>
  67
  68 #include <dev/netif/jme/if_jmereg.h>
  69 #include <dev/netif/jme/if_jmevar.h>
  70
  71 #include "miibus_if.h"
  72
  73 #define JME_TX_SERIALIZE        1
  74 #define JME_RX_SERIALIZE        2
  75
  76 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  77
  78 #ifdef JME_RSS_DEBUG
  79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
  80 do { \
  81         if ((sc)->jme_rss_debug >= (lvl)) \
  82                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
  83 } while (0)
  84 #else   /* !JME_RSS_DEBUG */
  85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  86 #endif  /* JME_RSS_DEBUG */
  87
  88 static int      jme_probe(device_t);
  89 static int      jme_attach(device_t);
  90 static int      jme_detach(device_t);
  91 static int      jme_shutdown(device_t);
  92 static int      jme_suspend(device_t);
  93 static int      jme_resume(device_t);
  94
  95 static int      jme_miibus_readreg(device_t, int, int);
  96 static int      jme_miibus_writereg(device_t, int, int, int);
  97 static void     jme_miibus_statchg(device_t);
  98
  99 static void     jme_init(void *);
 100 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 101 static void     jme_start(struct ifnet *);
 102 static void     jme_watchdog(struct ifnet *);
 103 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
 104 static int      jme_mediachange(struct ifnet *);
 105 #ifdef DEVICE_POLLING
 106 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
 107 #endif
 108 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
 109 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
 110 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
 111 #ifdef INVARIANTS
 112 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
 113                     boolean_t);
 114 #endif
 115
 116 static void     jme_intr(void *);
 117 static void     jme_msix_tx(void *);
 118 static void     jme_msix_rx(void *);
 119 static void     jme_txeof(struct jme_softc *);
 120 static void     jme_rxeof(struct jme_rxdata *, int);
 121 static void     jme_rx_intr(struct jme_softc *, uint32_t);
 122
 123 static int      jme_msix_setup(device_t);
 124 static void     jme_msix_teardown(device_t, int);
 125 static int      jme_intr_setup(device_t);
 126 static void     jme_intr_teardown(device_t);
 127 static void     jme_msix_try_alloc(device_t);
 128 static void     jme_msix_free(device_t);
 129 static int      jme_intr_alloc(device_t);
 130 static void     jme_intr_free(device_t);
 131 static int      jme_dma_alloc(struct jme_softc *);
 132 static void     jme_dma_free(struct jme_softc *);
 133 static int      jme_init_rx_ring(struct jme_rxdata *);
 134 static void     jme_init_tx_ring(struct jme_softc *);
 135 static void     jme_init_ssb(struct jme_softc *);
 136 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
 137 static int      jme_encap(struct jme_softc *, struct mbuf **);
 138 static void     jme_rxpkt(struct jme_rxdata *);
 139 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
 140 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
 141
 142 static void     jme_tick(void *);
 143 static void     jme_stop(struct jme_softc *);
 144 static void     jme_reset(struct jme_softc *);
 145 static void     jme_set_msinum(struct jme_softc *);
 146 static void     jme_set_vlan(struct jme_softc *);
 147 static void     jme_set_filter(struct jme_softc *);
 148 static void     jme_stop_tx(struct jme_softc *);
 149 static void     jme_stop_rx(struct jme_softc *);
 150 static void     jme_mac_config(struct jme_softc *);
 151 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
 152 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
 153 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
 154 #ifdef notyet
 155 static void     jme_setwol(struct jme_softc *);
 156 static void     jme_setlinkspeed(struct jme_softc *);
 157 #endif
 158 static void     jme_set_tx_coal(struct jme_softc *);
 159 static void     jme_set_rx_coal(struct jme_softc *);
 160 static void     jme_enable_rss(struct jme_softc *);
 161 static void     jme_disable_rss(struct jme_softc *);
 162
 163 static void     jme_sysctl_node(struct jme_softc *);
 164 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
 165 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
 166 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
 167 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
 168
 169 /*
 170  * Devices supported by this driver.
 171  */
 172 static const struct jme_dev {
 173         uint16_t        jme_vendorid;
 174         uint16_t        jme_deviceid;
 175         uint32_t        jme_caps;
 176         const char      *jme_name;
 177 } jme_devs[] = {
 178         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
 179             JME_CAP_JUMBO,
 180             "JMicron Inc, JMC250 Gigabit Ethernet" },
 181         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
 182             JME_CAP_FASTETH,
 183             "JMicron Inc, JMC260 Fast Ethernet" },
 184         { 0, 0, 0, NULL }
 185 };
 186
 187 static device_method_t jme_methods[] = {
 188         /* Device interface. */
 189         DEVMETHOD(device_probe,         jme_probe),
 190         DEVMETHOD(device_attach,        jme_attach),
 191         DEVMETHOD(device_detach,        jme_detach),
 192         DEVMETHOD(device_shutdown,      jme_shutdown),
 193         DEVMETHOD(device_suspend,       jme_suspend),
 194         DEVMETHOD(device_resume,        jme_resume),
 195
 196         /* Bus interface. */
 197         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 198         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 199
 200         /* MII interface. */
 201         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
 202         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
 203         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
 204
 205         { NULL, NULL }
 206 };
 207
 208 static driver_t jme_driver = {
 209         "jme",
 210         jme_methods,
 211         sizeof(struct jme_softc)
 212 };
 213
 214 static devclass_t jme_devclass;
 215
 216 DECLARE_DUMMY_MODULE(if_jme);
 217 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
 218 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
 219 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
 220
 221 static const struct {
 222         uint32_t        jme_coal;
 223         uint32_t        jme_comp;
 224         uint32_t        jme_empty;
 225 } jme_rx_status[JME_NRXRING_MAX] = {
 226         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
 227           INTR_RXQ0_DESC_EMPTY },
 228         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
 229           INTR_RXQ1_DESC_EMPTY },
 230         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
 231           INTR_RXQ2_DESC_EMPTY },
 232         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
 233           INTR_RXQ3_DESC_EMPTY }
 234 };
 235
 236 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
 237 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
 238 static int      jme_rx_ring_count = 0;
 239 static int      jme_msi_enable = 1;
 240 static int      jme_msix_enable = 1;
 241
 242 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
 243 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
 244 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
 245 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
 246 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
 247
 248 static __inline void
 249 jme_setup_rxdesc(struct jme_rxdesc *rxd)
 250 {
 251         struct jme_desc *desc;
 252
 253         desc = rxd->rx_desc;
 254         desc->buflen = htole32(MCLBYTES);
 255         desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
 256         desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
 257         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
 258 }
 259
 260 /*
 261  *      Read a PHY register on the MII of the JMC250.
 262  */
 263 static int
 264 jme_miibus_readreg(device_t dev, int phy, int reg)
 265 {
 266         struct jme_softc *sc = device_get_softc(dev);
 267         uint32_t val;
 268         int i;
 269
 270         /* For FPGA version, PHY address 0 should be ignored. */
 271         if (sc->jme_caps & JME_CAP_FPGA) {
 272                 if (phy == 0)
 273                         return (0);
 274         } else {
 275                 if (sc->jme_phyaddr != phy)
 276                         return (0);
 277         }
 278
 279         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
 280             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 281
 282         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 283                 DELAY(1);
 284                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 285                         break;
 286         }
 287         if (i == 0) {
 288                 device_printf(sc->jme_dev, "phy read timeout: "
 289                               "phy %d, reg %d\n", phy, reg);
 290                 return (0);
 291         }
 292
 293         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
 294 }
 295
 296 /*
 297  *      Write a PHY register on the MII of the JMC250.
 298  */
 299 static int
 300 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
 301 {
 302         struct jme_softc *sc = device_get_softc(dev);
 303         int i;
 304
 305         /* For FPGA version, PHY address 0 should be ignored. */
 306         if (sc->jme_caps & JME_CAP_FPGA) {
 307                 if (phy == 0)
 308                         return (0);
 309         } else {
 310                 if (sc->jme_phyaddr != phy)
 311                         return (0);
 312         }
 313
 314         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
 315             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
 316             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 317
 318         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 319                 DELAY(1);
 320                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 321                         break;
 322         }
 323         if (i == 0) {
 324                 device_printf(sc->jme_dev, "phy write timeout: "
 325                               "phy %d, reg %d\n", phy, reg);
 326         }
 327
 328         return (0);
 329 }
 330
 331 /*
 332  *      Callback from MII layer when media changes.
 333  */
 334 static void
 335 jme_miibus_statchg(device_t dev)
 336 {
 337         struct jme_softc *sc = device_get_softc(dev);
 338         struct ifnet *ifp = &sc->arpcom.ac_if;
 339         struct mii_data *mii;
 340         struct jme_txdesc *txd;
 341         bus_addr_t paddr;
 342         int i, r;
 343
 344         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 345
 346         if ((ifp->if_flags & IFF_RUNNING) == 0)
 347                 return;
 348
 349         mii = device_get_softc(sc->jme_miibus);
 350
 351         sc->jme_flags &= ~JME_FLAG_LINK;
 352         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 353                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 354                 case IFM_10_T:
 355                 case IFM_100_TX:
 356                         sc->jme_flags |= JME_FLAG_LINK;
 357                         break;
 358                 case IFM_1000_T:
 359                         if (sc->jme_caps & JME_CAP_FASTETH)
 360                                 break;
 361                         sc->jme_flags |= JME_FLAG_LINK;
 362                         break;
 363                 default:
 364                         break;
 365                 }
 366         }
 367
 368         /*
 369          * Disabling Rx/Tx MACs have a side-effect of resetting
 370          * JME_TXNDA/JME_RXNDA register to the first address of
 371          * Tx/Rx descriptor address. So driver should reset its
 372          * internal procucer/consumer pointer and reclaim any
 373          * allocated resources.  Note, just saving the value of
 374          * JME_TXNDA and JME_RXNDA registers before stopping MAC
 375          * and restoring JME_TXNDA/JME_RXNDA register is not
 376          * sufficient to make sure correct MAC state because
 377          * stopping MAC operation can take a while and hardware
 378          * might have updated JME_TXNDA/JME_RXNDA registers
 379          * during the stop operation.
 380          */
 381
 382         /* Disable interrupts */
 383         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
 384
 385         /* Stop driver */
 386         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 387         ifp->if_timer = 0;
 388         callout_stop(&sc->jme_tick_ch);
 389
 390         /* Stop receiver/transmitter. */
 391         jme_stop_rx(sc);
 392         jme_stop_tx(sc);
 393
 394         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 395                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
 396
 397                 jme_rxeof(rdata, -1);
 398                 if (rdata->jme_rxhead != NULL)
 399                         m_freem(rdata->jme_rxhead);
 400                 JME_RXCHAIN_RESET(rdata);
 401
 402                 /*
 403                  * Reuse configured Rx descriptors and reset
 404                  * procuder/consumer index.
 405                  */
 406                 rdata->jme_rx_cons = 0;
 407         }
 408         if (JME_ENABLE_HWRSS(sc))
 409                 jme_enable_rss(sc);
 410         else
 411                 jme_disable_rss(sc);
 412
 413         jme_txeof(sc);
 414         if (sc->jme_cdata.jme_tx_cnt != 0) {
 415                 /* Remove queued packets for transmit. */
 416                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
 417                         txd = &sc->jme_cdata.jme_txdesc[i];
 418                         if (txd->tx_m != NULL) {
 419                                 bus_dmamap_unload(
 420                                     sc->jme_cdata.jme_tx_tag,
 421                                     txd->tx_dmamap);
 422                                 m_freem(txd->tx_m);
 423                                 txd->tx_m = NULL;
 424                                 txd->tx_ndesc = 0;
 425                                 ifp->if_oerrors++;
 426                         }
 427                 }
 428         }
 429         jme_init_tx_ring(sc);
 430
 431         /* Initialize shadow status block. */
 432         jme_init_ssb(sc);
 433
 434         /* Program MAC with resolved speed/duplex/flow-control. */
 435         if (sc->jme_flags & JME_FLAG_LINK) {
 436                 jme_mac_config(sc);
 437
 438                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
 439
 440                 /* Set Tx ring address to the hardware. */
 441                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
 442                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
 443                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
 444
 445                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 446                         CSR_WRITE_4(sc, JME_RXCSR,
 447                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
 448
 449                         /* Set Rx ring address to the hardware. */
 450                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
 451                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
 452                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
 453                 }
 454
 455                 /* Restart receiver/transmitter. */
 456                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
 457                     RXCSR_RXQ_START);
 458                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
 459         }
 460
 461         ifp->if_flags |= IFF_RUNNING;
 462         ifp->if_flags &= ~IFF_OACTIVE;
 463         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
 464
 465 #ifdef DEVICE_POLLING
 466         if (!(ifp->if_flags & IFF_POLLING))
 467 #endif
 468         /* Reenable interrupts. */
 469         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
 470 }
 471
 472 /*
 473  *      Get the current interface media status.
 474  */
 475 static void
 476 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 477 {
 478         struct jme_softc *sc = ifp->if_softc;
 479         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 480
 481         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 482
 483         mii_pollstat(mii);
 484         ifmr->ifm_status = mii->mii_media_status;
 485         ifmr->ifm_active = mii->mii_media_active;
 486 }
 487
 488 /*
 489  *      Set hardware to newly-selected media.
 490  */
 491 static int
 492 jme_mediachange(struct ifnet *ifp)
 493 {
 494         struct jme_softc *sc = ifp->if_softc;
 495         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 496         int error;
 497
 498         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 499
 500         if (mii->mii_instance != 0) {
 501                 struct mii_softc *miisc;
 502
 503                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 504                         mii_phy_reset(miisc);
 505         }
 506         error = mii_mediachg(mii);
 507
 508         return (error);
 509 }
 510
 511 static int
 512 jme_probe(device_t dev)
 513 {
 514         const struct jme_dev *sp;
 515         uint16_t vid, did;
 516
 517         vid = pci_get_vendor(dev);
 518         did = pci_get_device(dev);
 519         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
 520                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
 521                         struct jme_softc *sc = device_get_softc(dev);
 522
 523                         sc->jme_caps = sp->jme_caps;
 524                         device_set_desc(dev, sp->jme_name);
 525                         return (0);
 526                 }
 527         }
 528         return (ENXIO);
 529 }
 530
 531 static int
 532 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
 533 {
 534         uint32_t reg;
 535         int i;
 536
 537         *val = 0;
 538         for (i = JME_TIMEOUT; i > 0; i--) {
 539                 reg = CSR_READ_4(sc, JME_SMBCSR);
 540                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
 541                         break;
 542                 DELAY(1);
 543         }
 544
 545         if (i == 0) {
 546                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
 547                 return (ETIMEDOUT);
 548         }
 549
 550         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
 551         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
 552         for (i = JME_TIMEOUT; i > 0; i--) {
 553                 DELAY(1);
 554                 reg = CSR_READ_4(sc, JME_SMBINTF);
 555                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
 556                         break;
 557         }
 558
 559         if (i == 0) {
 560                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
 561                 return (ETIMEDOUT);
 562         }
 563
 564         reg = CSR_READ_4(sc, JME_SMBINTF);
 565         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
 566
 567         return (0);
 568 }
 569
 570 static int
 571 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 572 {
 573         uint8_t fup, reg, val;
 574         uint32_t offset;
 575         int match;
 576
 577         offset = 0;
 578         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 579             fup != JME_EEPROM_SIG0)
 580                 return (ENOENT);
 581         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 582             fup != JME_EEPROM_SIG1)
 583                 return (ENOENT);
 584         match = 0;
 585         do {
 586                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
 587                         break;
 588                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
 589                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
 590                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
 591                                 break;
 592                         if (reg >= JME_PAR0 &&
 593                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
 594                                 if (jme_eeprom_read_byte(sc, offset + 2,
 595                                     &val) != 0)
 596                                         break;
 597                                 eaddr[reg - JME_PAR0] = val;
 598                                 match++;
 599                         }
 600                 }
 601                 /* Check for the end of EEPROM descriptor. */
 602                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
 603                         break;
 604                 /* Try next eeprom descriptor. */
 605                 offset += JME_EEPROM_DESC_BYTES;
 606         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
 607
 608         if (match == ETHER_ADDR_LEN)
 609                 return (0);
 610
 611         return (ENOENT);
 612 }
 613
 614 static void
 615 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 616 {
 617         uint32_t par0, par1;
 618
 619         /* Read station address. */
 620         par0 = CSR_READ_4(sc, JME_PAR0);
 621         par1 = CSR_READ_4(sc, JME_PAR1);
 622         par1 &= 0xFFFF;
 623         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
 624                 device_printf(sc->jme_dev,
 625                     "generating fake ethernet address.\n");
 626                 par0 = karc4random();
 627                 /* Set OUI to JMicron. */
 628                 eaddr[0] = 0x00;
 629                 eaddr[1] = 0x1B;
 630                 eaddr[2] = 0x8C;
 631                 eaddr[3] = (par0 >> 16) & 0xff;
 632                 eaddr[4] = (par0 >> 8) & 0xff;
 633                 eaddr[5] = par0 & 0xff;
 634         } else {
 635                 eaddr[0] = (par0 >> 0) & 0xFF;
 636                 eaddr[1] = (par0 >> 8) & 0xFF;
 637                 eaddr[2] = (par0 >> 16) & 0xFF;
 638                 eaddr[3] = (par0 >> 24) & 0xFF;
 639                 eaddr[4] = (par1 >> 0) & 0xFF;
 640                 eaddr[5] = (par1 >> 8) & 0xFF;
 641         }
 642 }
 643
 644 static int
 645 jme_attach(device_t dev)
 646 {
 647         struct jme_softc *sc = device_get_softc(dev);
 648         struct ifnet *ifp = &sc->arpcom.ac_if;
 649         uint32_t reg;
 650         uint16_t did;
 651         uint8_t pcie_ptr, rev;
 652         int error = 0, i, j, rx_desc_cnt;
 653         uint8_t eaddr[ETHER_ADDR_LEN];
 654
 655         lwkt_serialize_init(&sc->jme_serialize);
 656         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
 657         for (i = 0; i < JME_NRXRING_MAX; ++i) {
 658                 lwkt_serialize_init(
 659                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
 660         }
 661
 662         rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
 663             jme_rx_desc_count);
 664         rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
 665         if (rx_desc_cnt > JME_NDESC_MAX)
 666                 rx_desc_cnt = JME_NDESC_MAX;
 667
 668         sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
 669             jme_tx_desc_count);
 670         sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
 671             JME_NDESC_ALIGN);
 672         if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
 673                 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
 674
 675         /*
 676          * Calculate rx rings
 677          */
 678         sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
 679             jme_rx_ring_count);
 680         sc->jme_cdata.jme_rx_ring_cnt =
 681             if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
 682
 683         i = 0;
 684         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
 685
 686         KKASSERT(i == JME_TX_SERIALIZE);
 687         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
 688
 689         KKASSERT(i == JME_RX_SERIALIZE);
 690         for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
 691                 sc->jme_serialize_arr[i++] =
 692                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
 693         }
 694         KKASSERT(i <= JME_NSERIALIZE);
 695         sc->jme_serialize_cnt = i;
 696
 697         sc->jme_cdata.jme_sc = sc;
 698         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
 699                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
 700
 701                 rdata->jme_sc = sc;
 702                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
 703                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
 704                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
 705                 rdata->jme_rx_idx = i;
 706                 rdata->jme_rx_desc_cnt = rx_desc_cnt;
 707         }
 708
 709         sc->jme_dev = dev;
 710         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
 711
 712         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 713
 714         callout_init(&sc->jme_tick_ch);
 715
 716 #ifndef BURN_BRIDGES
 717         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 718                 uint32_t irq, mem;
 719
 720                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 721                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
 722
 723                 device_printf(dev, "chip is in D%d power mode "
 724                     "-- setting to D0\n", pci_get_powerstate(dev));
 725
 726                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 727
 728                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 729                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
 730         }
 731 #endif  /* !BURN_BRIDGE */
 732
 733         /* Enable bus mastering */
 734         pci_enable_busmaster(dev);
 735
 736         /*
 737          * Allocate IO memory
 738          *
 739          * JMC250 supports both memory mapped and I/O register space
 740          * access.  Because I/O register access should use different
 741          * BARs to access registers it's waste of time to use I/O
 742          * register spce access.  JMC250 uses 16K to map entire memory
 743          * space.
 744          */
 745         sc->jme_mem_rid = JME_PCIR_BAR;
 746         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 747                                                  &sc->jme_mem_rid, RF_ACTIVE);
 748         if (sc->jme_mem_res == NULL) {
 749                 device_printf(dev, "can't allocate IO memory\n");
 750                 return ENXIO;
 751         }
 752         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
 753         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
 754
 755         /*
 756          * Allocate IRQ
 757          */
 758         error = jme_intr_alloc(dev);
 759         if (error)
 760                 goto fail;
 761
 762         /*
 763          * Extract revisions
 764          */
 765         reg = CSR_READ_4(sc, JME_CHIPMODE);
 766         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
 767             CHIPMODE_NOT_FPGA) {
 768                 sc->jme_caps |= JME_CAP_FPGA;
 769                 if (bootverbose) {
 770                         device_printf(dev, "FPGA revision: 0x%04x\n",
 771                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
 772                                       CHIPMODE_FPGA_REV_SHIFT);
 773                 }
 774         }
 775
 776         /* NOTE: FM revision is put in the upper 4 bits */
 777         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
 778         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
 779         if (bootverbose)
 780                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
 781
 782         did = pci_get_device(dev);
 783         switch (did) {
 784         case PCI_PRODUCT_JMICRON_JMC250:
 785                 if (rev == JME_REV1_A2)
 786                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
 787                 break;
 788
 789         case PCI_PRODUCT_JMICRON_JMC260:
 790                 if (rev == JME_REV2)
 791                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
 792                 break;
 793
 794         default:
 795                 panic("unknown device id 0x%04x", did);
 796         }
 797         if (rev >= JME_REV2) {
 798                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
 799                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
 800                                       GHC_TXMAC_CLKSRC_1000;
 801         }
 802
 803         /* Reset the ethernet controller. */
 804         jme_reset(sc);
 805
 806         /* Map MSI/MSI-X vectors */
 807         jme_set_msinum(sc);
 808
 809         /* Get station address. */
 810         reg = CSR_READ_4(sc, JME_SMBCSR);
 811         if (reg & SMBCSR_EEPROM_PRESENT)
 812                 error = jme_eeprom_macaddr(sc, eaddr);
 813         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
 814                 if (error != 0 && (bootverbose)) {
 815                         device_printf(dev, "ethernet hardware address "
 816                                       "not found in EEPROM.\n");
 817                 }
 818                 jme_reg_macaddr(sc, eaddr);
 819         }
 820
 821         /*
 822          * Save PHY address.
 823          * Integrated JR0211 has fixed PHY address whereas FPGA version
 824          * requires PHY probing to get correct PHY address.
 825          */
 826         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
 827                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
 828                     GPREG0_PHY_ADDR_MASK;
 829                 if (bootverbose) {
 830                         device_printf(dev, "PHY is at address %d.\n",
 831                             sc->jme_phyaddr);
 832                 }
 833         } else {
 834                 sc->jme_phyaddr = 0;
 835         }
 836
 837         /* Set max allowable DMA size. */
 838         pcie_ptr = pci_get_pciecap_ptr(dev);
 839         if (pcie_ptr != 0) {
 840                 uint16_t ctrl;
 841
 842                 sc->jme_caps |= JME_CAP_PCIE;
 843                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 844                 if (bootverbose) {
 845                         device_printf(dev, "Read request size : %d bytes.\n",
 846                             128 << ((ctrl >> 12) & 0x07));
 847                         device_printf(dev, "TLP payload size : %d bytes.\n",
 848                             128 << ((ctrl >> 5) & 0x07));
 849                 }
 850                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
 851                 case PCIEM_DEVCTL_MAX_READRQ_128:
 852                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
 853                         break;
 854                 case PCIEM_DEVCTL_MAX_READRQ_256:
 855                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
 856                         break;
 857                 default:
 858                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 859                         break;
 860                 }
 861                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 862         } else {
 863                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 864                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 865         }
 866
 867 #ifdef notyet
 868         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 869                 sc->jme_caps |= JME_CAP_PMCAP;
 870 #endif
 871
 872         /*
 873          * Create sysctl tree
 874          */
 875         jme_sysctl_node(sc);
 876
 877         /* Allocate DMA stuffs */
 878         error = jme_dma_alloc(sc);
 879         if (error)
 880                 goto fail;
 881
 882         ifp->if_softc = sc;
 883         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 884         ifp->if_init = jme_init;
 885         ifp->if_ioctl = jme_ioctl;
 886         ifp->if_start = jme_start;
 887 #ifdef DEVICE_POLLING
 888         ifp->if_poll = jme_poll;
 889 #endif
 890         ifp->if_watchdog = jme_watchdog;
 891         ifp->if_serialize = jme_serialize;
 892         ifp->if_deserialize = jme_deserialize;
 893         ifp->if_tryserialize = jme_tryserialize;
 894 #ifdef INVARIANTS
 895         ifp->if_serialize_assert = jme_serialize_assert;
 896 #endif
 897         ifq_set_maxlen(&ifp->if_snd,
 898             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
 899         ifq_set_ready(&ifp->if_snd);
 900
 901         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
 902         ifp->if_capabilities = IFCAP_HWCSUM |
 903                                IFCAP_VLAN_MTU |
 904                                IFCAP_VLAN_HWTAGGING;
 905         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
 906                 ifp->if_capabilities |= IFCAP_RSS;
 907         ifp->if_capenable = ifp->if_capabilities;
 908
 909         /*
 910          * Disable TXCSUM by default to improve bulk data
 911          * transmit performance (+20Mbps improvement).
 912          */
 913         ifp->if_capenable &= ~IFCAP_TXCSUM;
 914
 915         if (ifp->if_capenable & IFCAP_TXCSUM)
 916                 ifp->if_hwassist = JME_CSUM_FEATURES;
 917
 918         /* Set up MII bus. */
 919         error = mii_phy_probe(dev, &sc->jme_miibus,
 920                               jme_mediachange, jme_mediastatus);
 921         if (error) {
 922                 device_printf(dev, "no PHY found!\n");
 923                 goto fail;
 924         }
 925
 926         /*
 927          * Save PHYADDR for FPGA mode PHY.
 928          */
 929         if (sc->jme_caps & JME_CAP_FPGA) {
 930                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
 931
 932                 if (mii->mii_instance != 0) {
 933                         struct mii_softc *miisc;
 934
 935                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
 936                                 if (miisc->mii_phy != 0) {
 937                                         sc->jme_phyaddr = miisc->mii_phy;
 938                                         break;
 939                                 }
 940                         }
 941                         if (sc->jme_phyaddr != 0) {
 942                                 device_printf(sc->jme_dev,
 943                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
 944                                 /* vendor magic. */
 945                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
 946                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
 947
 948                                 /* XXX should we clear JME_WA_EXTFIFO */
 949                         }
 950                 }
 951         }
 952
 953         ether_ifattach(ifp, eaddr, NULL);
 954
 955         /* Tell the upper layer(s) we support long frames. */
 956         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 957
 958         error = jme_intr_setup(dev);
 959         if (error) {
 960                 ether_ifdetach(ifp);
 961                 goto fail;
 962         }
 963
 964         return 0;
 965 fail:
 966         jme_detach(dev);
 967         return (error);
 968 }
 969
 970 static int
 971 jme_detach(device_t dev)
 972 {
 973         struct jme_softc *sc = device_get_softc(dev);
 974
 975         if (device_is_attached(dev)) {
 976                 struct ifnet *ifp = &sc->arpcom.ac_if;
 977
 978                 ifnet_serialize_all(ifp);
 979                 jme_stop(sc);
 980                 jme_intr_teardown(dev);
 981                 ifnet_deserialize_all(ifp);
 982
 983                 ether_ifdetach(ifp);
 984         }
 985
 986         if (sc->jme_sysctl_tree != NULL)
 987                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
 988
 989         if (sc->jme_miibus != NULL)
 990                 device_delete_child(dev, sc->jme_miibus);
 991         bus_generic_detach(dev);
 992
 993         jme_intr_free(dev);
 994
 995         if (sc->jme_mem_res != NULL) {
 996                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
 997                                      sc->jme_mem_res);
 998         }
 999
1000         jme_dma_free(sc);
1001
1002         return (0);
1003 }
1004
1005 static void
1006 jme_sysctl_node(struct jme_softc *sc)
1007 {
1008         int coal_max;
1009 #ifdef JME_RSS_DEBUG
1010         int r;
1011 #endif
1012
1013         sysctl_ctx_init(&sc->jme_sysctl_ctx);
1014         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1015                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1016                                 device_get_nameunit(sc->jme_dev),
1017                                 CTLFLAG_RD, 0, "");
1018         if (sc->jme_sysctl_tree == NULL) {
1019                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1020                 return;
1021         }
1022
1023         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1024             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1025             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1026             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1027
1028         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1029             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1030             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1031             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1032
1033         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1034             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1035             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1036             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1037
1038         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1039             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1040             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1041             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1042
1043         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1044                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1045                        "rx_desc_count", CTLFLAG_RD,
1046                        &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1047                        0, "RX desc count");
1048         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1049                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1050                        "tx_desc_count", CTLFLAG_RD,
1051                        &sc->jme_cdata.jme_tx_desc_cnt,
1052                        0, "TX desc count");
1053         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1054                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1055                        "rx_ring_count", CTLFLAG_RD,
1056                        &sc->jme_cdata.jme_rx_ring_cnt,
1057                        0, "RX ring count");
1058 #ifdef JME_RSS_DEBUG
1059         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1060                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1061                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1062                        0, "RSS debug level");
1063         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1064                 char rx_ring_pkt[32];
1065
1066                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1067                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1068                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1069                     rx_ring_pkt, CTLFLAG_RW,
1070                     &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1071         }
1072 #endif
1073
1074         /*
1075          * Set default coalesce valves
1076          */
1077         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1078         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1079         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1080         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1081
1082         /*
1083          * Adjust coalesce valves, in case that the number of TX/RX
1084          * descs are set to small values by users.
1085          *
1086          * NOTE: coal_max will not be zero, since number of descs
1087          * must aligned by JME_NDESC_ALIGN (16 currently)
1088          */
1089         coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1090         if (coal_max < sc->jme_tx_coal_pkt)
1091                 sc->jme_tx_coal_pkt = coal_max;
1092
1093         coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1094         if (coal_max < sc->jme_rx_coal_pkt)
1095                 sc->jme_rx_coal_pkt = coal_max;
1096 }
1097
1098 static int
1099 jme_dma_alloc(struct jme_softc *sc)
1100 {
1101         struct jme_txdesc *txd;
1102         bus_dmamem_t dmem;
1103         int error, i, asize;
1104
1105         sc->jme_cdata.jme_txdesc =
1106         kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1107                 M_DEVBUF, M_WAITOK | M_ZERO);
1108         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1109                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1110
1111                 rdata->jme_rxdesc =
1112                 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1113                         M_DEVBUF, M_WAITOK | M_ZERO);
1114         }
1115
1116         /* Create parent ring tag. */
1117         error = bus_dma_tag_create(NULL,/* parent */
1118             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1119             sc->jme_lowaddr,            /* lowaddr */
1120             BUS_SPACE_MAXADDR,          /* highaddr */
1121             NULL, NULL,                 /* filter, filterarg */
1122             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1123             0,                          /* nsegments */
1124             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1125             0,                          /* flags */
1126             &sc->jme_cdata.jme_ring_tag);
1127         if (error) {
1128                 device_printf(sc->jme_dev,
1129                     "could not create parent ring DMA tag.\n");
1130                 return error;
1131         }
1132
1133         /*
1134          * Create DMA stuffs for TX ring
1135          */
1136         asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1137         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1138                         JME_TX_RING_ALIGN, 0,
1139                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1140                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1141         if (error) {
1142                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1143                 return error;
1144         }
1145         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1146         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1147         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1148         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1149
1150         /*
1151          * Create DMA stuffs for RX rings
1152          */
1153         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1154                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1155                 if (error)
1156                         return error;
1157         }
1158
1159         /* Create parent buffer tag. */
1160         error = bus_dma_tag_create(NULL,/* parent */
1161             1, 0,                       /* algnmnt, boundary */
1162             sc->jme_lowaddr,            /* lowaddr */
1163             BUS_SPACE_MAXADDR,          /* highaddr */
1164             NULL, NULL,                 /* filter, filterarg */
1165             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1166             0,                          /* nsegments */
1167             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1168             0,                          /* flags */
1169             &sc->jme_cdata.jme_buffer_tag);
1170         if (error) {
1171                 device_printf(sc->jme_dev,
1172                     "could not create parent buffer DMA tag.\n");
1173                 return error;
1174         }
1175
1176         /*
1177          * Create DMA stuffs for shadow status block
1178          */
1179         asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1180         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1181                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1182                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1183         if (error) {
1184                 device_printf(sc->jme_dev,
1185                     "could not create shadow status block.\n");
1186                 return error;
1187         }
1188         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1189         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1190         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1191         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1192
1193         /*
1194          * Create DMA stuffs for TX buffers
1195          */
1196
1197         /* Create tag for Tx buffers. */
1198         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1199             1, 0,                       /* algnmnt, boundary */
1200             BUS_SPACE_MAXADDR,          /* lowaddr */
1201             BUS_SPACE_MAXADDR,          /* highaddr */
1202             NULL, NULL,                 /* filter, filterarg */
1203             JME_JUMBO_FRAMELEN,         /* maxsize */
1204             JME_MAXTXSEGS,              /* nsegments */
1205             JME_MAXSEGSIZE,             /* maxsegsize */
1206             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1207             &sc->jme_cdata.jme_tx_tag);
1208         if (error != 0) {
1209                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1210                 return error;
1211         }
1212
1213         /* Create DMA maps for Tx buffers. */
1214         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1215                 txd = &sc->jme_cdata.jme_txdesc[i];
1216                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1217                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1218                                 &txd->tx_dmamap);
1219                 if (error) {
1220                         int j;
1221
1222                         device_printf(sc->jme_dev,
1223                             "could not create %dth Tx dmamap.\n", i);
1224
1225                         for (j = 0; j < i; ++j) {
1226                                 txd = &sc->jme_cdata.jme_txdesc[j];
1227                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1228                                                    txd->tx_dmamap);
1229                         }
1230                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1231                         sc->jme_cdata.jme_tx_tag = NULL;
1232                         return error;
1233                 }
1234         }
1235
1236         /*
1237          * Create DMA stuffs for RX buffers
1238          */
1239         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1240                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1241                 if (error)
1242                         return error;
1243         }
1244         return 0;
1245 }
1246
1247 static void
1248 jme_dma_free(struct jme_softc *sc)
1249 {
1250         struct jme_txdesc *txd;
1251         struct jme_rxdesc *rxd;
1252         struct jme_rxdata *rdata;
1253         int i, r;
1254
1255         /* Tx ring */
1256         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1257                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1258                     sc->jme_cdata.jme_tx_ring_map);
1259                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1260                     sc->jme_cdata.jme_tx_ring,
1261                     sc->jme_cdata.jme_tx_ring_map);
1262                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1263                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1264         }
1265
1266         /* Rx ring */
1267         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1268                 rdata = &sc->jme_cdata.jme_rx_data[r];
1269                 if (rdata->jme_rx_ring_tag != NULL) {
1270                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1271                                           rdata->jme_rx_ring_map);
1272                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1273                                         rdata->jme_rx_ring,
1274                                         rdata->jme_rx_ring_map);
1275                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1276                         rdata->jme_rx_ring_tag = NULL;
1277                 }
1278         }
1279
1280         /* Tx buffers */
1281         if (sc->jme_cdata.jme_tx_tag != NULL) {
1282                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1283                         txd = &sc->jme_cdata.jme_txdesc[i];
1284                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1285                             txd->tx_dmamap);
1286                 }
1287                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1288                 sc->jme_cdata.jme_tx_tag = NULL;
1289         }
1290
1291         /* Rx buffers */
1292         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1293                 rdata = &sc->jme_cdata.jme_rx_data[r];
1294                 if (rdata->jme_rx_tag != NULL) {
1295                         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1296                                 rxd = &rdata->jme_rxdesc[i];
1297                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1298                                                    rxd->rx_dmamap);
1299                         }
1300                         bus_dmamap_destroy(rdata->jme_rx_tag,
1301                                            rdata->jme_rx_sparemap);
1302                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1303                         rdata->jme_rx_tag = NULL;
1304                 }
1305         }
1306
1307         /* Shadow status block. */
1308         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1309                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1310                     sc->jme_cdata.jme_ssb_map);
1311                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1312                     sc->jme_cdata.jme_ssb_block,
1313                     sc->jme_cdata.jme_ssb_map);
1314                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1315                 sc->jme_cdata.jme_ssb_tag = NULL;
1316         }
1317
1318         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1319                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1320                 sc->jme_cdata.jme_buffer_tag = NULL;
1321         }
1322         if (sc->jme_cdata.jme_ring_tag != NULL) {
1323                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1324                 sc->jme_cdata.jme_ring_tag = NULL;
1325         }
1326
1327         if (sc->jme_cdata.jme_txdesc != NULL) {
1328                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1329                 sc->jme_cdata.jme_txdesc = NULL;
1330         }
1331         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1332                 rdata = &sc->jme_cdata.jme_rx_data[r];
1333                 if (rdata->jme_rxdesc != NULL) {
1334                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1335                         rdata->jme_rxdesc = NULL;
1336                 }
1337         }
1338 }
1339
1340 /*
1341  *      Make sure the interface is stopped at reboot time.
1342  */
1343 static int
1344 jme_shutdown(device_t dev)
1345 {
1346         return jme_suspend(dev);
1347 }
1348
1349 #ifdef notyet
1350 /*
1351  * Unlike other ethernet controllers, JMC250 requires
1352  * explicit resetting link speed to 10/100Mbps as gigabit
1353  * link will cunsume more power than 375mA.
1354  * Note, we reset the link speed to 10/100Mbps with
1355  * auto-negotiation but we don't know whether that operation
1356  * would succeed or not as we have no control after powering
1357  * off. If the renegotiation fail WOL may not work. Running
1358  * at 1Gbps draws more power than 375mA at 3.3V which is
1359  * specified in PCI specification and that would result in
1360  * complete shutdowning power to ethernet controller.
1361  *
1362  * TODO
1363  *  Save current negotiated media speed/duplex/flow-control
1364  *  to softc and restore the same link again after resuming.
1365  *  PHY handling such as power down/resetting to 100Mbps
1366  *  may be better handled in suspend method in phy driver.
1367  */
1368 static void
1369 jme_setlinkspeed(struct jme_softc *sc)
1370 {
1371         struct mii_data *mii;
1372         int aneg, i;
1373
1374         JME_LOCK_ASSERT(sc);
1375
1376         mii = device_get_softc(sc->jme_miibus);
1377         mii_pollstat(mii);
1378         aneg = 0;
1379         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1380                 switch IFM_SUBTYPE(mii->mii_media_active) {
1381                 case IFM_10_T:
1382                 case IFM_100_TX:
1383                         return;
1384                 case IFM_1000_T:
1385                         aneg++;
1386                 default:
1387                         break;
1388                 }
1389         }
1390         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1391         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1392             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1393         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1394             BMCR_AUTOEN | BMCR_STARTNEG);
1395         DELAY(1000);
1396         if (aneg != 0) {
1397                 /* Poll link state until jme(4) get a 10/100 link. */
1398                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1399                         mii_pollstat(mii);
1400                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1401                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1402                                 case IFM_10_T:
1403                                 case IFM_100_TX:
1404                                         jme_mac_config(sc);
1405                                         return;
1406                                 default:
1407                                         break;
1408                                 }
1409                         }
1410                         JME_UNLOCK(sc);
1411                         pause("jmelnk", hz);
1412                         JME_LOCK(sc);
1413                 }
1414                 if (i == MII_ANEGTICKS_GIGE)
1415                         device_printf(sc->jme_dev, "establishing link failed, "
1416                             "WOL may not work!");
1417         }
1418         /*
1419          * No link, force MAC to have 100Mbps, full-duplex link.
1420          * This is the last resort and may/may not work.
1421          */
1422         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1423         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1424         jme_mac_config(sc);
1425 }
1426
1427 static void
1428 jme_setwol(struct jme_softc *sc)
1429 {
1430         struct ifnet *ifp = &sc->arpcom.ac_if;
1431         uint32_t gpr, pmcs;
1432         uint16_t pmstat;
1433         int pmc;
1434
1435         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1436                 /* No PME capability, PHY power down. */
1437                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1438                     MII_BMCR, BMCR_PDOWN);
1439                 return;
1440         }
1441
1442         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1443         pmcs = CSR_READ_4(sc, JME_PMCS);
1444         pmcs &= ~PMCS_WOL_ENB_MASK;
1445         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1446                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1447                 /* Enable PME message. */
1448                 gpr |= GPREG0_PME_ENB;
1449                 /* For gigabit controllers, reset link speed to 10/100. */
1450                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1451                         jme_setlinkspeed(sc);
1452         }
1453
1454         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1455         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1456
1457         /* Request PME. */
1458         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1459         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1460         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1461                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1462         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1463         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1464                 /* No WOL, PHY power down. */
1465                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1466                     MII_BMCR, BMCR_PDOWN);
1467         }
1468 }
1469 #endif
1470
1471 static int
1472 jme_suspend(device_t dev)
1473 {
1474         struct jme_softc *sc = device_get_softc(dev);
1475         struct ifnet *ifp = &sc->arpcom.ac_if;
1476
1477         ifnet_serialize_all(ifp);
1478         jme_stop(sc);
1479 #ifdef notyet
1480         jme_setwol(sc);
1481 #endif
1482         ifnet_deserialize_all(ifp);
1483
1484         return (0);
1485 }
1486
1487 static int
1488 jme_resume(device_t dev)
1489 {
1490         struct jme_softc *sc = device_get_softc(dev);
1491         struct ifnet *ifp = &sc->arpcom.ac_if;
1492 #ifdef notyet
1493         int pmc;
1494 #endif
1495
1496         ifnet_serialize_all(ifp);
1497
1498 #ifdef notyet
1499         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1500                 uint16_t pmstat;
1501
1502                 pmstat = pci_read_config(sc->jme_dev,
1503                     pmc + PCIR_POWER_STATUS, 2);
1504                 /* Disable PME clear PME status. */
1505                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1506                 pci_write_config(sc->jme_dev,
1507                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1508         }
1509 #endif
1510
1511         if (ifp->if_flags & IFF_UP)
1512                 jme_init(sc);
1513
1514         ifnet_deserialize_all(ifp);
1515
1516         return (0);
1517 }
1518
1519 static int
1520 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1521 {
1522         struct jme_txdesc *txd;
1523         struct jme_desc *desc;
1524         struct mbuf *m;
1525         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1526         int maxsegs, nsegs;
1527         int error, i, prod, symbol_desc;
1528         uint32_t cflags, flag64;
1529
1530         M_ASSERTPKTHDR((*m_head));
1531
1532         prod = sc->jme_cdata.jme_tx_prod;
1533         txd = &sc->jme_cdata.jme_txdesc[prod];
1534
1535         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1536                 symbol_desc = 1;
1537         else
1538                 symbol_desc = 0;
1539
1540         maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1541                   (JME_TXD_RSVD + symbol_desc);
1542         if (maxsegs > JME_MAXTXSEGS)
1543                 maxsegs = JME_MAXTXSEGS;
1544         KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1545                 ("not enough segments %d", maxsegs));
1546
1547         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1548                         txd->tx_dmamap, m_head,
1549                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1550         if (error)
1551                 goto fail;
1552
1553         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1554                         BUS_DMASYNC_PREWRITE);
1555
1556         m = *m_head;
1557         cflags = 0;
1558
1559         /* Configure checksum offload. */
1560         if (m->m_pkthdr.csum_flags & CSUM_IP)
1561                 cflags |= JME_TD_IPCSUM;
1562         if (m->m_pkthdr.csum_flags & CSUM_TCP)
1563                 cflags |= JME_TD_TCPCSUM;
1564         if (m->m_pkthdr.csum_flags & CSUM_UDP)
1565                 cflags |= JME_TD_UDPCSUM;
1566
1567         /* Configure VLAN. */
1568         if (m->m_flags & M_VLANTAG) {
1569                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1570                 cflags |= JME_TD_VLAN_TAG;
1571         }
1572
1573         desc = &sc->jme_cdata.jme_tx_ring[prod];
1574         desc->flags = htole32(cflags);
1575         desc->addr_hi = htole32(m->m_pkthdr.len);
1576         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1577                 /*
1578                  * Use 64bits TX desc chain format.
1579                  *
1580                  * The first TX desc of the chain, which is setup here,
1581                  * is just a symbol TX desc carrying no payload.
1582                  */
1583                 flag64 = JME_TD_64BIT;
1584                 desc->buflen = 0;
1585                 desc->addr_lo = 0;
1586
1587                 /* No effective TX desc is consumed */
1588                 i = 0;
1589         } else {
1590                 /*
1591                  * Use 32bits TX desc chain format.
1592                  *
1593                  * The first TX desc of the chain, which is setup here,
1594                  * is an effective TX desc carrying the first segment of
1595                  * the mbuf chain.
1596                  */
1597                 flag64 = 0;
1598                 desc->buflen = htole32(txsegs[0].ds_len);
1599                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1600
1601                 /* One effective TX desc is consumed */
1602                 i = 1;
1603         }
1604         sc->jme_cdata.jme_tx_cnt++;
1605         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1606                  sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1607         JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1608
1609         txd->tx_ndesc = 1 - i;
1610         for (; i < nsegs; i++) {
1611                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1612                 desc->buflen = htole32(txsegs[i].ds_len);
1613                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1614                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1615                 desc->flags = htole32(JME_TD_OWN | flag64);
1616
1617                 sc->jme_cdata.jme_tx_cnt++;
1618                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1619                          sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1620                 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1621         }
1622
1623         /* Update producer index. */
1624         sc->jme_cdata.jme_tx_prod = prod;
1625         /*
1626          * Finally request interrupt and give the first descriptor
1627          * owenership to hardware.
1628          */
1629         desc = txd->tx_desc;
1630         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1631
1632         txd->tx_m = m;
1633         txd->tx_ndesc += nsegs;
1634
1635         return 0;
1636 fail:
1637         m_freem(*m_head);
1638         *m_head = NULL;
1639         return error;
1640 }
1641
1642 static void
1643 jme_start(struct ifnet *ifp)
1644 {
1645         struct jme_softc *sc = ifp->if_softc;
1646         struct mbuf *m_head;
1647         int enq = 0;
1648
1649         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1650
1651         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1652                 ifq_purge(&ifp->if_snd);
1653                 return;
1654         }
1655
1656         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1657                 return;
1658
1659         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1660                 jme_txeof(sc);
1661
1662         while (!ifq_is_empty(&ifp->if_snd)) {
1663                 /*
1664                  * Check number of available TX descs, always
1665                  * leave JME_TXD_RSVD free TX descs.
1666                  */
1667                 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1668                     sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1669                         ifp->if_flags |= IFF_OACTIVE;
1670                         break;
1671                 }
1672
1673                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1674                 if (m_head == NULL)
1675                         break;
1676
1677                 /*
1678                  * Pack the data into the transmit ring. If we
1679                  * don't have room, set the OACTIVE flag and wait
1680                  * for the NIC to drain the ring.
1681                  */
1682                 if (jme_encap(sc, &m_head)) {
1683                         KKASSERT(m_head == NULL);
1684                         ifp->if_oerrors++;
1685                         ifp->if_flags |= IFF_OACTIVE;
1686                         break;
1687                 }
1688                 enq++;
1689
1690                 /*
1691                  * If there's a BPF listener, bounce a copy of this frame
1692                  * to him.
1693                  */
1694                 ETHER_BPF_MTAP(ifp, m_head);
1695         }
1696
1697         if (enq > 0) {
1698                 /*
1699                  * Reading TXCSR takes very long time under heavy load
1700                  * so cache TXCSR value and writes the ORed value with
1701                  * the kick command to the TXCSR. This saves one register
1702                  * access cycle.
1703                  */
1704                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1705                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1706                 /* Set a timeout in case the chip goes out to lunch. */
1707                 ifp->if_timer = JME_TX_TIMEOUT;
1708         }
1709 }
1710
1711 static void
1712 jme_watchdog(struct ifnet *ifp)
1713 {
1714         struct jme_softc *sc = ifp->if_softc;
1715
1716         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1717
1718         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1719                 if_printf(ifp, "watchdog timeout (missed link)\n");
1720                 ifp->if_oerrors++;
1721                 jme_init(sc);
1722                 return;
1723         }
1724
1725         jme_txeof(sc);
1726         if (sc->jme_cdata.jme_tx_cnt == 0) {
1727                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1728                           "-- recovering\n");
1729                 if (!ifq_is_empty(&ifp->if_snd))
1730                         if_devstart(ifp);
1731                 return;
1732         }
1733
1734         if_printf(ifp, "watchdog timeout\n");
1735         ifp->if_oerrors++;
1736         jme_init(sc);
1737         if (!ifq_is_empty(&ifp->if_snd))
1738                 if_devstart(ifp);
1739 }
1740
1741 static int
1742 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1743 {
1744         struct jme_softc *sc = ifp->if_softc;
1745         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1746         struct ifreq *ifr = (struct ifreq *)data;
1747         int error = 0, mask;
1748
1749         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1750
1751         switch (cmd) {
1752         case SIOCSIFMTU:
1753                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1754                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1755                      ifr->ifr_mtu > JME_MAX_MTU)) {
1756                         error = EINVAL;
1757                         break;
1758                 }
1759
1760                 if (ifp->if_mtu != ifr->ifr_mtu) {
1761                         /*
1762                          * No special configuration is required when interface
1763                          * MTU is changed but availability of Tx checksum
1764                          * offload should be chcked against new MTU size as
1765                          * FIFO size is just 2K.
1766                          */
1767                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1768                                 ifp->if_capenable &= ~IFCAP_TXCSUM;
1769                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1770                         }
1771                         ifp->if_mtu = ifr->ifr_mtu;
1772                         if (ifp->if_flags & IFF_RUNNING)
1773                                 jme_init(sc);
1774                 }
1775                 break;
1776
1777         case SIOCSIFFLAGS:
1778                 if (ifp->if_flags & IFF_UP) {
1779                         if (ifp->if_flags & IFF_RUNNING) {
1780                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1781                                     (IFF_PROMISC | IFF_ALLMULTI))
1782                                         jme_set_filter(sc);
1783                         } else {
1784                                 jme_init(sc);
1785                         }
1786                 } else {
1787                         if (ifp->if_flags & IFF_RUNNING)
1788                                 jme_stop(sc);
1789                 }
1790                 sc->jme_if_flags = ifp->if_flags;
1791                 break;
1792
1793         case SIOCADDMULTI:
1794         case SIOCDELMULTI:
1795                 if (ifp->if_flags & IFF_RUNNING)
1796                         jme_set_filter(sc);
1797                 break;
1798
1799         case SIOCSIFMEDIA:
1800         case SIOCGIFMEDIA:
1801                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1802                 break;
1803
1804         case SIOCSIFCAP:
1805                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1806
1807                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1808                         ifp->if_capenable ^= IFCAP_TXCSUM;
1809                         if (IFCAP_TXCSUM & ifp->if_capenable)
1810                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1811                         else
1812                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1813                 }
1814                 if (mask & IFCAP_RXCSUM) {
1815                         uint32_t reg;
1816
1817                         ifp->if_capenable ^= IFCAP_RXCSUM;
1818                         reg = CSR_READ_4(sc, JME_RXMAC);
1819                         reg &= ~RXMAC_CSUM_ENB;
1820                         if (ifp->if_capenable & IFCAP_RXCSUM)
1821                                 reg |= RXMAC_CSUM_ENB;
1822                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1823                 }
1824
1825                 if (mask & IFCAP_VLAN_HWTAGGING) {
1826                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1827                         jme_set_vlan(sc);
1828                 }
1829
1830                 if (mask & IFCAP_RSS)
1831                         ifp->if_capenable ^= IFCAP_RSS;
1832                 break;
1833
1834         default:
1835                 error = ether_ioctl(ifp, cmd, data);
1836                 break;
1837         }
1838         return (error);
1839 }
1840
1841 static void
1842 jme_mac_config(struct jme_softc *sc)
1843 {
1844         struct mii_data *mii;
1845         uint32_t ghc, rxmac, txmac, txpause, gp1;
1846         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1847
1848         mii = device_get_softc(sc->jme_miibus);
1849
1850         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1851         DELAY(10);
1852         CSR_WRITE_4(sc, JME_GHC, 0);
1853         ghc = 0;
1854         rxmac = CSR_READ_4(sc, JME_RXMAC);
1855         rxmac &= ~RXMAC_FC_ENB;
1856         txmac = CSR_READ_4(sc, JME_TXMAC);
1857         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1858         txpause = CSR_READ_4(sc, JME_TXPFC);
1859         txpause &= ~TXPFC_PAUSE_ENB;
1860         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1861                 ghc |= GHC_FULL_DUPLEX;
1862                 rxmac &= ~RXMAC_COLL_DET_ENB;
1863                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1864                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1865                     TXMAC_FRAME_BURST);
1866 #ifdef notyet
1867                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1868                         txpause |= TXPFC_PAUSE_ENB;
1869                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1870                         rxmac |= RXMAC_FC_ENB;
1871 #endif
1872                 /* Disable retry transmit timer/retry limit. */
1873                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1874                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1875         } else {
1876                 rxmac |= RXMAC_COLL_DET_ENB;
1877                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1878                 /* Enable retry transmit timer/retry limit. */
1879                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1880                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1881         }
1882
1883         /*
1884          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1885          */
1886         gp1 = CSR_READ_4(sc, JME_GPREG1);
1887         gp1 &= ~GPREG1_WA_HDX;
1888
1889         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1890                 hdx = 1;
1891
1892         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1893         case IFM_10_T:
1894                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1895                 if (hdx)
1896                         gp1 |= GPREG1_WA_HDX;
1897                 break;
1898
1899         case IFM_100_TX:
1900                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1901                 if (hdx)
1902                         gp1 |= GPREG1_WA_HDX;
1903
1904                 /*
1905                  * Use extended FIFO depth to workaround CRC errors
1906                  * emitted by chips before JMC250B
1907                  */
1908                 phyconf = JMPHY_CONF_EXTFIFO;
1909                 break;
1910
1911         case IFM_1000_T:
1912                 if (sc->jme_caps & JME_CAP_FASTETH)
1913                         break;
1914
1915                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1916                 if (hdx)
1917                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1918                 break;
1919
1920         default:
1921                 break;
1922         }
1923         CSR_WRITE_4(sc, JME_GHC, ghc);
1924         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1925         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1926         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1927
1928         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1929                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1930                                     JMPHY_CONF, phyconf);
1931         }
1932         if (sc->jme_workaround & JME_WA_HDX)
1933                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1934 }
1935
1936 static void
1937 jme_intr(void *xsc)
1938 {
1939         struct jme_softc *sc = xsc;
1940         struct ifnet *ifp = &sc->arpcom.ac_if;
1941         uint32_t status;
1942         int r;
1943
1944         ASSERT_SERIALIZED(&sc->jme_serialize);
1945
1946         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1947         if (status == 0 || status == 0xFFFFFFFF)
1948                 return;
1949
1950         /* Disable interrupts. */
1951         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1952
1953         status = CSR_READ_4(sc, JME_INTR_STATUS);
1954         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1955                 goto back;
1956
1957         /* Reset PCC counter/timer and Ack interrupts. */
1958         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1959
1960         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1961                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1962
1963         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1964                 if (status & jme_rx_status[r].jme_coal) {
1965                         status |= jme_rx_status[r].jme_coal |
1966                                   jme_rx_status[r].jme_comp;
1967                 }
1968         }
1969
1970         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1971
1972         if (ifp->if_flags & IFF_RUNNING) {
1973                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1974                         jme_rx_intr(sc, status);
1975
1976                 if (status & INTR_RXQ_DESC_EMPTY) {
1977                         /*
1978                          * Notify hardware availability of new Rx buffers.
1979                          * Reading RXCSR takes very long time under heavy
1980                          * load so cache RXCSR value and writes the ORed
1981                          * value with the kick command to the RXCSR. This
1982                          * saves one register access cycle.
1983                          */
1984                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1985                             RXCSR_RX_ENB | RXCSR_RXQ_START);
1986                 }
1987
1988                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1989                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1990                         jme_txeof(sc);
1991                         if (!ifq_is_empty(&ifp->if_snd))
1992                                 if_devstart(ifp);
1993                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1994                 }
1995         }
1996 back:
1997         /* Reenable interrupts. */
1998         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1999 }
2000
2001 static void
2002 jme_txeof(struct jme_softc *sc)
2003 {
2004         struct ifnet *ifp = &sc->arpcom.ac_if;
2005         struct jme_txdesc *txd;
2006         uint32_t status;
2007         int cons, nsegs;
2008
2009         cons = sc->jme_cdata.jme_tx_cons;
2010         if (cons == sc->jme_cdata.jme_tx_prod)
2011                 return;
2012
2013         /*
2014          * Go through our Tx list and free mbufs for those
2015          * frames which have been transmitted.
2016          */
2017         while (cons != sc->jme_cdata.jme_tx_prod) {
2018                 txd = &sc->jme_cdata.jme_txdesc[cons];
2019                 KASSERT(txd->tx_m != NULL,
2020                         ("%s: freeing NULL mbuf!", __func__));
2021
2022                 status = le32toh(txd->tx_desc->flags);
2023                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2024                         break;
2025
2026                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2027                         ifp->if_oerrors++;
2028                 } else {
2029                         ifp->if_opackets++;
2030                         if (status & JME_TD_COLLISION) {
2031                                 ifp->if_collisions +=
2032                                     le32toh(txd->tx_desc->buflen) &
2033                                     JME_TD_BUF_LEN_MASK;
2034                         }
2035                 }
2036
2037                 /*
2038                  * Only the first descriptor of multi-descriptor
2039                  * transmission is updated so driver have to skip entire
2040                  * chained buffers for the transmiited frame. In other
2041                  * words, JME_TD_OWN bit is valid only at the first
2042                  * descriptor of a multi-descriptor transmission.
2043                  */
2044                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2045                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2046                         JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2047                 }
2048
2049                 /* Reclaim transferred mbufs. */
2050                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2051                 m_freem(txd->tx_m);
2052                 txd->tx_m = NULL;
2053                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2054                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2055                         ("%s: Active Tx desc counter was garbled", __func__));
2056                 txd->tx_ndesc = 0;
2057         }
2058         sc->jme_cdata.jme_tx_cons = cons;
2059
2060         if (sc->jme_cdata.jme_tx_cnt == 0)
2061                 ifp->if_timer = 0;
2062
2063         if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2064             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2065                 ifp->if_flags &= ~IFF_OACTIVE;
2066 }
2067
2068 static __inline void
2069 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2070 {
2071         int i;
2072
2073         for (i = 0; i < count; ++i) {
2074                 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2075                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2076         }
2077 }
2078
2079 static __inline struct pktinfo *
2080 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2081 {
2082         if (flags & JME_RD_IPV4)
2083                 pi->pi_netisr = NETISR_IP;
2084         else if (flags & JME_RD_IPV6)
2085                 pi->pi_netisr = NETISR_IPV6;
2086         else
2087                 return NULL;
2088
2089         pi->pi_flags = 0;
2090         pi->pi_l3proto = IPPROTO_UNKNOWN;
2091
2092         if (flags & JME_RD_MORE_FRAG)
2093                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2094         else if (flags & JME_RD_TCP)
2095                 pi->pi_l3proto = IPPROTO_TCP;
2096         else if (flags & JME_RD_UDP)
2097                 pi->pi_l3proto = IPPROTO_UDP;
2098         else
2099                 pi = NULL;
2100         return pi;
2101 }
2102
2103 /* Receive a frame. */
2104 static void
2105 jme_rxpkt(struct jme_rxdata *rdata)
2106 {
2107         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2108         struct jme_desc *desc;
2109         struct jme_rxdesc *rxd;
2110         struct mbuf *mp, *m;
2111         uint32_t flags, status, hash, hashinfo;
2112         int cons, count, nsegs;
2113
2114         cons = rdata->jme_rx_cons;
2115         desc = &rdata->jme_rx_ring[cons];
2116         flags = le32toh(desc->flags);
2117         status = le32toh(desc->buflen);
2118         hash = le32toh(desc->addr_hi);
2119         hashinfo = le32toh(desc->addr_lo);
2120         nsegs = JME_RX_NSEGS(status);
2121
2122         JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2123                         "hash 0x%08x, hash info 0x%08x\n",
2124                         rdata->jme_rx_idx, flags, hash, hashinfo);
2125
2126         if (status & JME_RX_ERR_STAT) {
2127                 ifp->if_ierrors++;
2128                 jme_discard_rxbufs(rdata, cons, nsegs);
2129 #ifdef JME_SHOW_ERRORS
2130                 if_printf(ifp, "%s : receive error = 0x%b\n",
2131                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2132 #endif
2133                 rdata->jme_rx_cons += nsegs;
2134                 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2135                 return;
2136         }
2137
2138         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2139         for (count = 0; count < nsegs; count++,
2140              JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2141                 rxd = &rdata->jme_rxdesc[cons];
2142                 mp = rxd->rx_m;
2143
2144                 /* Add a new receive buffer to the ring. */
2145                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2146                         ifp->if_iqdrops++;
2147                         /* Reuse buffer. */
2148                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2149                         if (rdata->jme_rxhead != NULL) {
2150                                 m_freem(rdata->jme_rxhead);
2151                                 JME_RXCHAIN_RESET(rdata);
2152                         }
2153                         break;
2154                 }
2155
2156                 /*
2157                  * Assume we've received a full sized frame.
2158                  * Actual size is fixed when we encounter the end of
2159                  * multi-segmented frame.
2160                  */
2161                 mp->m_len = MCLBYTES;
2162
2163                 /* Chain received mbufs. */
2164                 if (rdata->jme_rxhead == NULL) {
2165                         rdata->jme_rxhead = mp;
2166                         rdata->jme_rxtail = mp;
2167                 } else {
2168                         /*
2169                          * Receive processor can receive a maximum frame
2170                          * size of 65535 bytes.
2171                          */
2172                         rdata->jme_rxtail->m_next = mp;
2173                         rdata->jme_rxtail = mp;
2174                 }
2175
2176                 if (count == nsegs - 1) {
2177                         struct pktinfo pi0, *pi;
2178
2179                         /* Last desc. for this frame. */
2180                         m = rdata->jme_rxhead;
2181                         m->m_pkthdr.len = rdata->jme_rxlen;
2182                         if (nsegs > 1) {
2183                                 /* Set first mbuf size. */
2184                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2185                                 /* Set last mbuf size. */
2186                                 mp->m_len = rdata->jme_rxlen -
2187                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2188                                     (MCLBYTES * (nsegs - 2)));
2189                         } else {
2190                                 m->m_len = rdata->jme_rxlen;
2191                         }
2192                         m->m_pkthdr.rcvif = ifp;
2193
2194                         /*
2195                          * Account for 10bytes auto padding which is used
2196                          * to align IP header on 32bit boundary. Also note,
2197                          * CRC bytes is automatically removed by the
2198                          * hardware.
2199                          */
2200                         m->m_data += JME_RX_PAD_BYTES;
2201
2202                         /* Set checksum information. */
2203                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2204                             (flags & JME_RD_IPV4)) {
2205                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2206                                 if (flags & JME_RD_IPCSUM)
2207                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2208                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2209                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2210                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2211                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2212                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2213                                         m->m_pkthdr.csum_flags |=
2214                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2215                                         m->m_pkthdr.csum_data = 0xffff;
2216                                 }
2217                         }
2218
2219                         /* Check for VLAN tagged packets. */
2220                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2221                             (flags & JME_RD_VLAN_TAG)) {
2222                                 m->m_pkthdr.ether_vlantag =
2223                                     flags & JME_RD_VLAN_MASK;
2224                                 m->m_flags |= M_VLANTAG;
2225                         }
2226
2227                         ifp->if_ipackets++;
2228
2229                         if (ifp->if_capenable & IFCAP_RSS)
2230                                 pi = jme_pktinfo(&pi0, flags);
2231                         else
2232                                 pi = NULL;
2233
2234                         if (pi != NULL &&
2235                             (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2236                                 m->m_flags |= M_HASH;
2237                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2238                         }
2239
2240 #ifdef JME_RSS_DEBUG
2241                         if (pi != NULL) {
2242                                 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2243                                     "isr %d flags %08x, l3 %d %s\n",
2244                                     pi->pi_netisr, pi->pi_flags,
2245                                     pi->pi_l3proto,
2246                                     (m->m_flags & M_HASH) ? "hash" : "");
2247                         }
2248 #endif
2249
2250                         /* Pass it on. */
2251                         ether_input_pkt(ifp, m, pi);
2252
2253                         /* Reset mbuf chains. */
2254                         JME_RXCHAIN_RESET(rdata);
2255 #ifdef JME_RSS_DEBUG
2256                         rdata->jme_rx_pkt++;
2257 #endif
2258                 }
2259         }
2260
2261         rdata->jme_rx_cons += nsegs;
2262         rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2263 }
2264
2265 static void
2266 jme_rxeof(struct jme_rxdata *rdata, int count)
2267 {
2268         struct jme_desc *desc;
2269         int nsegs, pktlen;
2270
2271         for (;;) {
2272 #ifdef DEVICE_POLLING
2273                 if (count >= 0 && count-- == 0)
2274                         break;
2275 #endif
2276                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2277                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2278                         break;
2279                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2280                         break;
2281
2282                 /*
2283                  * Check number of segments against received bytes.
2284                  * Non-matching value would indicate that hardware
2285                  * is still trying to update Rx descriptors. I'm not
2286                  * sure whether this check is needed.
2287                  */
2288                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2289                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2290                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2291                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2292                             "RX fragment count(%d) and "
2293                             "packet size(%d) mismach\n", nsegs, pktlen);
2294                         break;
2295                 }
2296
2297                 /*
2298                  * NOTE:
2299                  * RSS hash and hash information may _not_ be set by the
2300                  * hardware even if the OWN bit is cleared and VALID bit
2301                  * is set.
2302                  *
2303                  * If the RSS information is not delivered by the hardware
2304                  * yet, we MUST NOT accept this packet, let alone reusing
2305                  * its RX descriptor.  If this packet was accepted and its
2306                  * RX descriptor was reused before hardware delivering the
2307                  * RSS information, the RX buffer's address would be trashed
2308                  * by the RSS information delivered by the hardware.
2309                  */
2310                 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2311                         struct jme_rxdesc *rxd;
2312                         uint32_t hashinfo;
2313
2314                         hashinfo = le32toh(desc->addr_lo);
2315                         rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2316
2317                         /*
2318                          * This test should be enough to detect the pending
2319                          * RSS information delivery, given:
2320                          * - If RSS hash is not calculated, the hashinfo
2321                          *   will be 0.  Howvever, RX buffers' physical
2322                          *   address will never be 0
2323                          * - If RSS hash is calculated, the lowest 4 bits
2324                          *   of hashinfo will be set, while the RX buffers
2325                          *   are at least 2K aligned.
2326                          */
2327                         if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2328 #ifdef JME_SHOW_RSSWB
2329                                 if_printf(&rdata->jme_sc->arpcom.ac_if,
2330                                     "RSS is not written back yet\n");
2331 #endif
2332                                 break;
2333                         }
2334                 }
2335
2336                 /* Received a frame. */
2337                 jme_rxpkt(rdata);
2338         }
2339 }
2340
2341 static void
2342 jme_tick(void *xsc)
2343 {
2344         struct jme_softc *sc = xsc;
2345         struct ifnet *ifp = &sc->arpcom.ac_if;
2346         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2347
2348         ifnet_serialize_all(ifp);
2349
2350         mii_tick(mii);
2351         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2352
2353         ifnet_deserialize_all(ifp);
2354 }
2355
2356 static void
2357 jme_reset(struct jme_softc *sc)
2358 {
2359         uint32_t val;
2360
2361         /* Make sure that TX and RX are stopped */
2362         jme_stop_tx(sc);
2363         jme_stop_rx(sc);
2364
2365         /* Start reset */
2366         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2367         DELAY(20);
2368
2369         /*
2370          * Hold reset bit before stop reset
2371          */
2372
2373         /* Disable TXMAC and TXOFL clock sources */
2374         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2375         /* Disable RXMAC clock source */
2376         val = CSR_READ_4(sc, JME_GPREG1);
2377         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2378         /* Flush */
2379         CSR_READ_4(sc, JME_GHC);
2380
2381         /* Stop reset */
2382         CSR_WRITE_4(sc, JME_GHC, 0);
2383         /* Flush */
2384         CSR_READ_4(sc, JME_GHC);
2385
2386         /*
2387          * Clear reset bit after stop reset
2388          */
2389
2390         /* Enable TXMAC and TXOFL clock sources */
2391         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2392         /* Enable RXMAC clock source */
2393         val = CSR_READ_4(sc, JME_GPREG1);
2394         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2395         /* Flush */
2396         CSR_READ_4(sc, JME_GHC);
2397
2398         /* Disable TXMAC and TXOFL clock sources */
2399         CSR_WRITE_4(sc, JME_GHC, 0);
2400         /* Disable RXMAC clock source */
2401         val = CSR_READ_4(sc, JME_GPREG1);
2402         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2403         /* Flush */
2404         CSR_READ_4(sc, JME_GHC);
2405
2406         /* Enable TX and RX */
2407         val = CSR_READ_4(sc, JME_TXCSR);
2408         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2409         val = CSR_READ_4(sc, JME_RXCSR);
2410         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2411         /* Flush */
2412         CSR_READ_4(sc, JME_TXCSR);
2413         CSR_READ_4(sc, JME_RXCSR);
2414
2415         /* Enable TXMAC and TXOFL clock sources */
2416         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2417         /* Eisable RXMAC clock source */
2418         val = CSR_READ_4(sc, JME_GPREG1);
2419         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2420         /* Flush */
2421         CSR_READ_4(sc, JME_GHC);
2422
2423         /* Stop TX and RX */
2424         jme_stop_tx(sc);
2425         jme_stop_rx(sc);
2426 }
2427
2428 static void
2429 jme_init(void *xsc)
2430 {
2431         struct jme_softc *sc = xsc;
2432         struct ifnet *ifp = &sc->arpcom.ac_if;
2433         struct mii_data *mii;
2434         uint8_t eaddr[ETHER_ADDR_LEN];
2435         bus_addr_t paddr;
2436         uint32_t reg;
2437         int error, r;
2438
2439         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2440
2441         /*
2442          * Cancel any pending I/O.
2443          */
2444         jme_stop(sc);
2445
2446         /*
2447          * Reset the chip to a known state.
2448          */
2449         jme_reset(sc);
2450
2451         /*
2452          * Setup MSI/MSI-X vectors to interrupts mapping
2453          */
2454         jme_set_msinum(sc);
2455
2456         sc->jme_txd_spare =
2457         howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2458         KKASSERT(sc->jme_txd_spare >= 1);
2459
2460         /*
2461          * If we use 64bit address mode for transmitting, each Tx request
2462          * needs one more symbol descriptor.
2463          */
2464         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2465                 sc->jme_txd_spare += 1;
2466
2467         if (JME_ENABLE_HWRSS(sc))
2468                 jme_enable_rss(sc);
2469         else
2470                 jme_disable_rss(sc);
2471
2472         /* Init RX descriptors */
2473         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2474                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2475                 if (error) {
2476                         if_printf(ifp, "initialization failed: "
2477                                   "no memory for %dth RX ring.\n", r);
2478                         jme_stop(sc);
2479                         return;
2480                 }
2481         }
2482
2483         /* Init TX descriptors */
2484         jme_init_tx_ring(sc);
2485
2486         /* Initialize shadow status block. */
2487         jme_init_ssb(sc);
2488
2489         /* Reprogram the station address. */
2490         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2491         CSR_WRITE_4(sc, JME_PAR0,
2492             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2493         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2494
2495         /*
2496          * Configure Tx queue.
2497          *  Tx priority queue weight value : 0
2498          *  Tx FIFO threshold for processing next packet : 16QW
2499          *  Maximum Tx DMA length : 512
2500          *  Allow Tx DMA burst.
2501          */
2502         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2503         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2504         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2505         sc->jme_txcsr |= sc->jme_tx_dma_size;
2506         sc->jme_txcsr |= TXCSR_DMA_BURST;
2507         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2508
2509         /* Set Tx descriptor counter. */
2510         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2511
2512         /* Set Tx ring address to the hardware. */
2513         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2514         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2515         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2516
2517         /* Configure TxMAC parameters. */
2518         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2519         reg |= TXMAC_THRESH_1_PKT;
2520         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2521         CSR_WRITE_4(sc, JME_TXMAC, reg);
2522
2523         /*
2524          * Configure Rx queue.
2525          *  FIFO full threshold for transmitting Tx pause packet : 128T
2526          *  FIFO threshold for processing next packet : 128QW
2527          *  Rx queue 0 select
2528          *  Max Rx DMA length : 128
2529          *  Rx descriptor retry : 32
2530          *  Rx descriptor retry time gap : 256ns
2531          *  Don't receive runt/bad frame.
2532          */
2533         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2534 #if 0
2535         /*
2536          * Since Rx FIFO size is 4K bytes, receiving frames larger
2537          * than 4K bytes will suffer from Rx FIFO overruns. So
2538          * decrease FIFO threshold to reduce the FIFO overruns for
2539          * frames larger than 4000 bytes.
2540          * For best performance of standard MTU sized frames use
2541          * maximum allowable FIFO threshold, 128QW.
2542          */
2543         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2544             JME_RX_FIFO_SIZE)
2545                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2546         else
2547                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2548 #else
2549         /* Improve PCI Express compatibility */
2550         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2551 #endif
2552         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2553         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2554         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2555         /* XXX TODO DROP_BAD */
2556
2557         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2558                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2559
2560                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2561
2562                 /* Set Rx descriptor counter. */
2563                 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2564
2565                 /* Set Rx ring address to the hardware. */
2566                 paddr = rdata->jme_rx_ring_paddr;
2567                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2568                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2569         }
2570
2571         /* Clear receive filter. */
2572         CSR_WRITE_4(sc, JME_RXMAC, 0);
2573
2574         /* Set up the receive filter. */
2575         jme_set_filter(sc);
2576         jme_set_vlan(sc);
2577
2578         /*
2579          * Disable all WOL bits as WOL can interfere normal Rx
2580          * operation. Also clear WOL detection status bits.
2581          */
2582         reg = CSR_READ_4(sc, JME_PMCS);
2583         reg &= ~PMCS_WOL_ENB_MASK;
2584         CSR_WRITE_4(sc, JME_PMCS, reg);
2585
2586         /*
2587          * Pad 10bytes right before received frame. This will greatly
2588          * help Rx performance on strict-alignment architectures as
2589          * it does not need to copy the frame to align the payload.
2590          */
2591         reg = CSR_READ_4(sc, JME_RXMAC);
2592         reg |= RXMAC_PAD_10BYTES;
2593
2594         if (ifp->if_capenable & IFCAP_RXCSUM)
2595                 reg |= RXMAC_CSUM_ENB;
2596         CSR_WRITE_4(sc, JME_RXMAC, reg);
2597
2598         /* Configure general purpose reg0 */
2599         reg = CSR_READ_4(sc, JME_GPREG0);
2600         reg &= ~GPREG0_PCC_UNIT_MASK;
2601         /* Set PCC timer resolution to micro-seconds unit. */
2602         reg |= GPREG0_PCC_UNIT_US;
2603         /*
2604          * Disable all shadow register posting as we have to read
2605          * JME_INTR_STATUS register in jme_intr. Also it seems
2606          * that it's hard to synchronize interrupt status between
2607          * hardware and software with shadow posting due to
2608          * requirements of bus_dmamap_sync(9).
2609          */
2610         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2611             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2612             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2613             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2614         /* Disable posting of DW0. */
2615         reg &= ~GPREG0_POST_DW0_ENB;
2616         /* Clear PME message. */
2617         reg &= ~GPREG0_PME_ENB;
2618         /* Set PHY address. */
2619         reg &= ~GPREG0_PHY_ADDR_MASK;
2620         reg |= sc->jme_phyaddr;
2621         CSR_WRITE_4(sc, JME_GPREG0, reg);
2622
2623         /* Configure Tx queue 0 packet completion coalescing. */
2624         jme_set_tx_coal(sc);
2625
2626         /* Configure Rx queues packet completion coalescing. */
2627         jme_set_rx_coal(sc);
2628
2629         /* Configure shadow status block but don't enable posting. */
2630         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2631         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2632         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2633
2634         /* Disable Timer 1 and Timer 2. */
2635         CSR_WRITE_4(sc, JME_TIMER1, 0);
2636         CSR_WRITE_4(sc, JME_TIMER2, 0);
2637
2638         /* Configure retry transmit period, retry limit value. */
2639         CSR_WRITE_4(sc, JME_TXTRHD,
2640             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2641             TXTRHD_RT_PERIOD_MASK) |
2642             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2643             TXTRHD_RT_LIMIT_SHIFT));
2644
2645 #ifdef DEVICE_POLLING
2646         if (!(ifp->if_flags & IFF_POLLING))
2647 #endif
2648         /* Initialize the interrupt mask. */
2649         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2650         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2651
2652         /*
2653          * Enabling Tx/Rx DMA engines and Rx queue processing is
2654          * done after detection of valid link in jme_miibus_statchg.
2655          */
2656         sc->jme_flags &= ~JME_FLAG_LINK;
2657
2658         /* Set the current media. */
2659         mii = device_get_softc(sc->jme_miibus);
2660         mii_mediachg(mii);
2661
2662         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2663
2664         ifp->if_flags |= IFF_RUNNING;
2665         ifp->if_flags &= ~IFF_OACTIVE;
2666 }
2667
2668 static void
2669 jme_stop(struct jme_softc *sc)
2670 {
2671         struct ifnet *ifp = &sc->arpcom.ac_if;
2672         struct jme_txdesc *txd;
2673         struct jme_rxdesc *rxd;
2674         struct jme_rxdata *rdata;
2675         int i, r;
2676
2677         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2678
2679         /*
2680          * Mark the interface down and cancel the watchdog timer.
2681          */
2682         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2683         ifp->if_timer = 0;
2684
2685         callout_stop(&sc->jme_tick_ch);
2686         sc->jme_flags &= ~JME_FLAG_LINK;
2687
2688         /*
2689          * Disable interrupts.
2690          */
2691         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2692         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2693
2694         /* Disable updating shadow status block. */
2695         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2696             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2697
2698         /* Stop receiver, transmitter. */
2699         jme_stop_rx(sc);
2700         jme_stop_tx(sc);
2701
2702         /*
2703          * Free partial finished RX segments
2704          */
2705         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2706                 rdata = &sc->jme_cdata.jme_rx_data[r];
2707                 if (rdata->jme_rxhead != NULL)
2708                         m_freem(rdata->jme_rxhead);
2709                 JME_RXCHAIN_RESET(rdata);
2710         }
2711
2712         /*
2713          * Free RX and TX mbufs still in the queues.
2714          */
2715         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2716                 rdata = &sc->jme_cdata.jme_rx_data[r];
2717                 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2718                         rxd = &rdata->jme_rxdesc[i];
2719                         if (rxd->rx_m != NULL) {
2720                                 bus_dmamap_unload(rdata->jme_rx_tag,
2721                                                   rxd->rx_dmamap);
2722                                 m_freem(rxd->rx_m);
2723                                 rxd->rx_m = NULL;
2724                         }
2725                 }
2726         }
2727         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2728                 txd = &sc->jme_cdata.jme_txdesc[i];
2729                 if (txd->tx_m != NULL) {
2730                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2731                             txd->tx_dmamap);
2732                         m_freem(txd->tx_m);
2733                         txd->tx_m = NULL;
2734                         txd->tx_ndesc = 0;
2735                 }
2736         }
2737 }
2738
2739 static void
2740 jme_stop_tx(struct jme_softc *sc)
2741 {
2742         uint32_t reg;
2743         int i;
2744
2745         reg = CSR_READ_4(sc, JME_TXCSR);
2746         if ((reg & TXCSR_TX_ENB) == 0)
2747                 return;
2748         reg &= ~TXCSR_TX_ENB;
2749         CSR_WRITE_4(sc, JME_TXCSR, reg);
2750         for (i = JME_TIMEOUT; i > 0; i--) {
2751                 DELAY(1);
2752                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2753                         break;
2754         }
2755         if (i == 0)
2756                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2757 }
2758
2759 static void
2760 jme_stop_rx(struct jme_softc *sc)
2761 {
2762         uint32_t reg;
2763         int i;
2764
2765         reg = CSR_READ_4(sc, JME_RXCSR);
2766         if ((reg & RXCSR_RX_ENB) == 0)
2767                 return;
2768         reg &= ~RXCSR_RX_ENB;
2769         CSR_WRITE_4(sc, JME_RXCSR, reg);
2770         for (i = JME_TIMEOUT; i > 0; i--) {
2771                 DELAY(1);
2772                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2773                         break;
2774         }
2775         if (i == 0)
2776                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2777 }
2778
2779 static void
2780 jme_init_tx_ring(struct jme_softc *sc)
2781 {
2782         struct jme_chain_data *cd;
2783         struct jme_txdesc *txd;
2784         int i;
2785
2786         sc->jme_cdata.jme_tx_prod = 0;
2787         sc->jme_cdata.jme_tx_cons = 0;
2788         sc->jme_cdata.jme_tx_cnt = 0;
2789
2790         cd = &sc->jme_cdata;
2791         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2792         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2793                 txd = &sc->jme_cdata.jme_txdesc[i];
2794                 txd->tx_m = NULL;
2795                 txd->tx_desc = &cd->jme_tx_ring[i];
2796                 txd->tx_ndesc = 0;
2797         }
2798 }
2799
2800 static void
2801 jme_init_ssb(struct jme_softc *sc)
2802 {
2803         struct jme_chain_data *cd;
2804
2805         cd = &sc->jme_cdata;
2806         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2807 }
2808
2809 static int
2810 jme_init_rx_ring(struct jme_rxdata *rdata)
2811 {
2812         struct jme_rxdesc *rxd;
2813         int i;
2814
2815         KKASSERT(rdata->jme_rxhead == NULL &&
2816                  rdata->jme_rxtail == NULL &&
2817                  rdata->jme_rxlen == 0);
2818         rdata->jme_rx_cons = 0;
2819
2820         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2821         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2822                 int error;
2823
2824                 rxd = &rdata->jme_rxdesc[i];
2825                 rxd->rx_m = NULL;
2826                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2827                 error = jme_newbuf(rdata, rxd, 1);
2828                 if (error)
2829                         return error;
2830         }
2831         return 0;
2832 }
2833
2834 static int
2835 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2836 {
2837         struct mbuf *m;
2838         bus_dma_segment_t segs;
2839         bus_dmamap_t map;
2840         int error, nsegs;
2841
2842         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2843         if (m == NULL)
2844                 return ENOBUFS;
2845         /*
2846          * JMC250 has 64bit boundary alignment limitation so jme(4)
2847          * takes advantage of 10 bytes padding feature of hardware
2848          * in order not to copy entire frame to align IP header on
2849          * 32bit boundary.
2850          */
2851         m->m_len = m->m_pkthdr.len = MCLBYTES;
2852
2853         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2854                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2855                         BUS_DMA_NOWAIT);
2856         if (error) {
2857                 m_freem(m);
2858                 if (init) {
2859                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2860                             "can't load RX mbuf\n");
2861                 }
2862                 return error;
2863         }
2864
2865         if (rxd->rx_m != NULL) {
2866                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2867                                 BUS_DMASYNC_POSTREAD);
2868                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2869         }
2870         map = rxd->rx_dmamap;
2871         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2872         rdata->jme_rx_sparemap = map;
2873         rxd->rx_m = m;
2874         rxd->rx_paddr = segs.ds_addr;
2875
2876         jme_setup_rxdesc(rxd);
2877         return 0;
2878 }
2879
2880 static void
2881 jme_set_vlan(struct jme_softc *sc)
2882 {
2883         struct ifnet *ifp = &sc->arpcom.ac_if;
2884         uint32_t reg;
2885
2886         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2887
2888         reg = CSR_READ_4(sc, JME_RXMAC);
2889         reg &= ~RXMAC_VLAN_ENB;
2890         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2891                 reg |= RXMAC_VLAN_ENB;
2892         CSR_WRITE_4(sc, JME_RXMAC, reg);
2893 }
2894
2895 static void
2896 jme_set_filter(struct jme_softc *sc)
2897 {
2898         struct ifnet *ifp = &sc->arpcom.ac_if;
2899         struct ifmultiaddr *ifma;
2900         uint32_t crc;
2901         uint32_t mchash[2];
2902         uint32_t rxcfg;
2903
2904         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2905
2906         rxcfg = CSR_READ_4(sc, JME_RXMAC);
2907         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2908             RXMAC_ALLMULTI);
2909
2910         /*
2911          * Always accept frames destined to our station address.
2912          * Always accept broadcast frames.
2913          */
2914         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2915
2916         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2917                 if (ifp->if_flags & IFF_PROMISC)
2918                         rxcfg |= RXMAC_PROMISC;
2919                 if (ifp->if_flags & IFF_ALLMULTI)
2920                         rxcfg |= RXMAC_ALLMULTI;
2921                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2922                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2923                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2924                 return;
2925         }
2926
2927         /*
2928          * Set up the multicast address filter by passing all multicast
2929          * addresses through a CRC generator, and then using the low-order
2930          * 6 bits as an index into the 64 bit multicast hash table.  The
2931          * high order bits select the register, while the rest of the bits
2932          * select the bit within the register.
2933          */
2934         rxcfg |= RXMAC_MULTICAST;
2935         bzero(mchash, sizeof(mchash));
2936
2937         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2938                 if (ifma->ifma_addr->sa_family != AF_LINK)
2939                         continue;
2940                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2941                     ifma->ifma_addr), ETHER_ADDR_LEN);
2942
2943                 /* Just want the 6 least significant bits. */
2944                 crc &= 0x3f;
2945
2946                 /* Set the corresponding bit in the hash table. */
2947                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2948         }
2949
2950         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2951         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2952         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2953 }
2954
2955 static int
2956 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2957 {
2958         struct jme_softc *sc = arg1;
2959         struct ifnet *ifp = &sc->arpcom.ac_if;
2960         int error, v;
2961
2962         ifnet_serialize_all(ifp);
2963
2964         v = sc->jme_tx_coal_to;
2965         error = sysctl_handle_int(oidp, &v, 0, req);
2966         if (error || req->newptr == NULL)
2967                 goto back;
2968
2969         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2970                 error = EINVAL;
2971                 goto back;
2972         }
2973
2974         if (v != sc->jme_tx_coal_to) {
2975                 sc->jme_tx_coal_to = v;
2976                 if (ifp->if_flags & IFF_RUNNING)
2977                         jme_set_tx_coal(sc);
2978         }
2979 back:
2980         ifnet_deserialize_all(ifp);
2981         return error;
2982 }
2983
2984 static int
2985 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2986 {
2987         struct jme_softc *sc = arg1;
2988         struct ifnet *ifp = &sc->arpcom.ac_if;
2989         int error, v;
2990
2991         ifnet_serialize_all(ifp);
2992
2993         v = sc->jme_tx_coal_pkt;
2994         error = sysctl_handle_int(oidp, &v, 0, req);
2995         if (error || req->newptr == NULL)
2996                 goto back;
2997
2998         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2999                 error = EINVAL;
3000                 goto back;
3001         }
3002
3003         if (v != sc->jme_tx_coal_pkt) {
3004                 sc->jme_tx_coal_pkt = v;
3005                 if (ifp->if_flags & IFF_RUNNING)
3006                         jme_set_tx_coal(sc);
3007         }
3008 back:
3009         ifnet_deserialize_all(ifp);
3010         return error;
3011 }
3012
3013 static int
3014 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3015 {
3016         struct jme_softc *sc = arg1;
3017         struct ifnet *ifp = &sc->arpcom.ac_if;
3018         int error, v;
3019
3020         ifnet_serialize_all(ifp);
3021
3022         v = sc->jme_rx_coal_to;
3023         error = sysctl_handle_int(oidp, &v, 0, req);
3024         if (error || req->newptr == NULL)
3025                 goto back;
3026
3027         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3028                 error = EINVAL;
3029                 goto back;
3030         }
3031
3032         if (v != sc->jme_rx_coal_to) {
3033                 sc->jme_rx_coal_to = v;
3034                 if (ifp->if_flags & IFF_RUNNING)
3035                         jme_set_rx_coal(sc);
3036         }
3037 back:
3038         ifnet_deserialize_all(ifp);
3039         return error;
3040 }
3041
3042 static int
3043 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3044 {
3045         struct jme_softc *sc = arg1;
3046         struct ifnet *ifp = &sc->arpcom.ac_if;
3047         int error, v;
3048
3049         ifnet_serialize_all(ifp);
3050
3051         v = sc->jme_rx_coal_pkt;
3052         error = sysctl_handle_int(oidp, &v, 0, req);
3053         if (error || req->newptr == NULL)
3054                 goto back;
3055
3056         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3057                 error = EINVAL;
3058                 goto back;
3059         }
3060
3061         if (v != sc->jme_rx_coal_pkt) {
3062                 sc->jme_rx_coal_pkt = v;
3063                 if (ifp->if_flags & IFF_RUNNING)
3064                         jme_set_rx_coal(sc);
3065         }
3066 back:
3067         ifnet_deserialize_all(ifp);
3068         return error;
3069 }
3070
3071 static void
3072 jme_set_tx_coal(struct jme_softc *sc)
3073 {
3074         uint32_t reg;
3075
3076         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3077             PCCTX_COAL_TO_MASK;
3078         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3079             PCCTX_COAL_PKT_MASK;
3080         reg |= PCCTX_COAL_TXQ0;
3081         CSR_WRITE_4(sc, JME_PCCTX, reg);
3082 }
3083
3084 static void
3085 jme_set_rx_coal(struct jme_softc *sc)
3086 {
3087         uint32_t reg;
3088         int r;
3089
3090         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3091             PCCRX_COAL_TO_MASK;
3092         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3093             PCCRX_COAL_PKT_MASK;
3094         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3095                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3096 }
3097
3098 #ifdef DEVICE_POLLING
3099
3100 static void
3101 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3102 {
3103         struct jme_softc *sc = ifp->if_softc;
3104         uint32_t status;
3105         int r;
3106
3107         ASSERT_SERIALIZED(&sc->jme_serialize);
3108
3109         switch (cmd) {
3110         case POLL_REGISTER:
3111                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3112                 break;
3113
3114         case POLL_DEREGISTER:
3115                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3116                 break;
3117
3118         case POLL_AND_CHECK_STATUS:
3119         case POLL_ONLY:
3120                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3121
3122                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3123                         struct jme_rxdata *rdata =
3124                             &sc->jme_cdata.jme_rx_data[r];
3125
3126                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3127                         jme_rxeof(rdata, count);
3128                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3129                 }
3130
3131                 if (status & INTR_RXQ_DESC_EMPTY) {
3132                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3133                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3134                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3135                 }
3136
3137                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3138                 jme_txeof(sc);
3139                 if (!ifq_is_empty(&ifp->if_snd))
3140                         if_devstart(ifp);
3141                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3142                 break;
3143         }
3144 }
3145
3146 #endif  /* DEVICE_POLLING */
3147
3148 static int
3149 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3150 {
3151         bus_dmamem_t dmem;
3152         int error, asize;
3153
3154         asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3155         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3156                         JME_RX_RING_ALIGN, 0,
3157                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3158                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3159         if (error) {
3160                 device_printf(rdata->jme_sc->jme_dev,
3161                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3162                 return error;
3163         }
3164         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3165         rdata->jme_rx_ring_map = dmem.dmem_map;
3166         rdata->jme_rx_ring = dmem.dmem_addr;
3167         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3168
3169         return 0;
3170 }
3171
3172 static int
3173 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3174 {
3175         int i, error;
3176
3177         /* Create tag for Rx buffers. */
3178         error = bus_dma_tag_create(
3179             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3180             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3181             BUS_SPACE_MAXADDR,          /* lowaddr */
3182             BUS_SPACE_MAXADDR,          /* highaddr */
3183             NULL, NULL,                 /* filter, filterarg */
3184             MCLBYTES,                   /* maxsize */
3185             1,                          /* nsegments */
3186             MCLBYTES,                   /* maxsegsize */
3187             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3188             &rdata->jme_rx_tag);
3189         if (error) {
3190                 device_printf(rdata->jme_sc->jme_dev,
3191                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3192                 return error;
3193         }
3194
3195         /* Create DMA maps for Rx buffers. */
3196         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3197                                   &rdata->jme_rx_sparemap);
3198         if (error) {
3199                 device_printf(rdata->jme_sc->jme_dev,
3200                     "could not create %dth spare Rx dmamap.\n",
3201                     rdata->jme_rx_idx);
3202                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3203                 rdata->jme_rx_tag = NULL;
3204                 return error;
3205         }
3206         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3207                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3208
3209                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3210                                           &rxd->rx_dmamap);
3211                 if (error) {
3212                         int j;
3213
3214                         device_printf(rdata->jme_sc->jme_dev,
3215                             "could not create %dth Rx dmamap "
3216                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3217
3218                         for (j = 0; j < i; ++j) {
3219                                 rxd = &rdata->jme_rxdesc[j];
3220                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3221                                                    rxd->rx_dmamap);
3222                         }
3223                         bus_dmamap_destroy(rdata->jme_rx_tag,
3224                                            rdata->jme_rx_sparemap);
3225                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3226                         rdata->jme_rx_tag = NULL;
3227                         return error;
3228                 }
3229         }
3230         return 0;
3231 }
3232
3233 static void
3234 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3235 {
3236         int r;
3237
3238         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3239                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3240
3241                 if (status & rdata->jme_rx_coal) {
3242                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3243                         jme_rxeof(rdata, -1);
3244                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3245                 }
3246         }
3247 }
3248
3249 static void
3250 jme_enable_rss(struct jme_softc *sc)
3251 {
3252         uint32_t rssc, ind;
3253         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3254         int i;
3255
3256         KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3257                 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3258                 ("%s: invalid # of RX rings (%d)",
3259                  sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3260
3261         rssc = RSSC_HASH_64_ENTRY;
3262         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3263         rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3264         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3265         CSR_WRITE_4(sc, JME_RSSC, rssc);
3266
3267         toeplitz_get_key(key, sizeof(key));
3268         for (i = 0; i < RSSKEY_NREGS; ++i) {
3269                 uint32_t keyreg;
3270
3271                 keyreg = RSSKEY_REGVAL(key, i);
3272                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3273
3274                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3275         }
3276
3277         /*
3278          * Create redirect table in following fashion:
3279          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3280          */
3281         ind = 0;
3282         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3283                 int q;
3284
3285                 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3286                 ind |= q << (i * 8);
3287         }
3288         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3289
3290         for (i = 0; i < RSSTBL_NREGS; ++i)
3291                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3292 }
3293
3294 static void
3295 jme_disable_rss(struct jme_softc *sc)
3296 {
3297         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3298 }
3299
3300 static void
3301 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3302 {
3303         struct jme_softc *sc = ifp->if_softc;
3304
3305         ifnet_serialize_array_enter(sc->jme_serialize_arr,
3306             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3307 }
3308
3309 static void
3310 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3311 {
3312         struct jme_softc *sc = ifp->if_softc;
3313
3314         ifnet_serialize_array_exit(sc->jme_serialize_arr,
3315             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3316 }
3317
3318 static int
3319 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3320 {
3321         struct jme_softc *sc = ifp->if_softc;
3322
3323         return ifnet_serialize_array_try(sc->jme_serialize_arr,
3324             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3325 }
3326
3327 #ifdef INVARIANTS
3328
3329 static void
3330 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3331     boolean_t serialized)
3332 {
3333         struct jme_softc *sc = ifp->if_softc;
3334
3335         ifnet_serialize_array_assert(sc->jme_serialize_arr,
3336             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3337             slz, serialized);
3338 }
3339
3340 #endif  /* INVARIANTS */
3341
3342 static void
3343 jme_msix_try_alloc(device_t dev)
3344 {
3345         struct jme_softc *sc = device_get_softc(dev);
3346         struct jme_msix_data *msix;
3347         int error, i, r, msix_enable, msix_count;
3348
3349         msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3350         KKASSERT(msix_count <= JME_NMSIX);
3351
3352         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3353
3354         /*
3355          * We leave the 1st MSI-X vector unused, so we
3356          * actually need msix_count + 1 MSI-X vectors.
3357          */
3358         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3359                 return;
3360
3361         for (i = 0; i < msix_count; ++i)
3362                 sc->jme_msix[i].jme_msix_rid = -1;
3363
3364         i = 0;
3365
3366         msix = &sc->jme_msix[i++];
3367         msix->jme_msix_cpuid = 0;               /* XXX Put TX to cpu0 */
3368         msix->jme_msix_arg = &sc->jme_cdata;
3369         msix->jme_msix_func = jme_msix_tx;
3370         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3371         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3372         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3373             device_get_nameunit(dev));
3374
3375         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3376                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3377
3378                 msix = &sc->jme_msix[i++];
3379                 msix->jme_msix_cpuid = r;       /* XXX Put RX to cpuX */
3380                 msix->jme_msix_arg = rdata;
3381                 msix->jme_msix_func = jme_msix_rx;
3382                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3383                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3384                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3385                     "%s rx%d", device_get_nameunit(dev), r);
3386         }
3387
3388         KKASSERT(i == msix_count);
3389
3390         error = pci_setup_msix(dev);
3391         if (error)
3392                 return;
3393
3394         /* Setup jme_msix_cnt early, so we could cleanup */
3395         sc->jme_msix_cnt = msix_count;
3396
3397         for (i = 0; i < msix_count; ++i) {
3398                 msix = &sc->jme_msix[i];
3399
3400                 msix->jme_msix_vector = i + 1;
3401                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3402                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3403                 if (error)
3404                         goto back;
3405
3406                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3407                     &msix->jme_msix_rid, RF_ACTIVE);
3408                 if (msix->jme_msix_res == NULL) {
3409                         error = ENOMEM;
3410                         goto back;
3411                 }
3412         }
3413
3414         for (i = 0; i < JME_INTR_CNT; ++i) {
3415                 uint32_t intr_mask = (1 << i);
3416                 int x;
3417
3418                 if ((JME_INTRS & intr_mask) == 0)
3419                         continue;
3420
3421                 for (x = 0; x < msix_count; ++x) {
3422                         msix = &sc->jme_msix[x];
3423                         if (msix->jme_msix_intrs & intr_mask) {
3424                                 int reg, shift;
3425
3426                                 reg = i / JME_MSINUM_FACTOR;
3427                                 KKASSERT(reg < JME_MSINUM_CNT);
3428
3429                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3430
3431                                 sc->jme_msinum[reg] |=
3432                                     (msix->jme_msix_vector << shift);
3433
3434                                 break;
3435                         }
3436                 }
3437         }
3438
3439         if (bootverbose) {
3440                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3441                         device_printf(dev, "MSINUM%d: %#x\n", i,
3442                             sc->jme_msinum[i]);
3443                 }
3444         }
3445
3446         pci_enable_msix(dev);
3447         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3448
3449 back:
3450         if (error)
3451                 jme_msix_free(dev);
3452 }
3453
3454 static int
3455 jme_intr_alloc(device_t dev)
3456 {
3457         struct jme_softc *sc = device_get_softc(dev);
3458         u_int irq_flags;
3459
3460         jme_msix_try_alloc(dev);
3461
3462         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3463                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3464                     &sc->jme_irq_rid, &irq_flags);
3465
3466                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3467                     &sc->jme_irq_rid, irq_flags);
3468                 if (sc->jme_irq_res == NULL) {
3469                         device_printf(dev, "can't allocate irq\n");
3470                         return ENXIO;
3471                 }
3472         }
3473         return 0;
3474 }
3475
3476 static void
3477 jme_msix_free(device_t dev)
3478 {
3479         struct jme_softc *sc = device_get_softc(dev);
3480         int i;
3481
3482         KKASSERT(sc->jme_msix_cnt > 1);
3483
3484         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3485                 struct jme_msix_data *msix = &sc->jme_msix[i];
3486
3487                 if (msix->jme_msix_res != NULL) {
3488                         bus_release_resource(dev, SYS_RES_IRQ,
3489                             msix->jme_msix_rid, msix->jme_msix_res);
3490                         msix->jme_msix_res = NULL;
3491                 }
3492                 if (msix->jme_msix_rid >= 0) {
3493                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3494                         msix->jme_msix_rid = -1;
3495                 }
3496         }
3497         pci_teardown_msix(dev);
3498 }
3499
3500 static void
3501 jme_intr_free(device_t dev)
3502 {
3503         struct jme_softc *sc = device_get_softc(dev);
3504
3505         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3506                 if (sc->jme_irq_res != NULL) {
3507                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3508                                              sc->jme_irq_res);
3509                 }
3510                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3511                         pci_release_msi(dev);
3512         } else {
3513                 jme_msix_free(dev);
3514         }
3515 }
3516
3517 static void
3518 jme_msix_tx(void *xcd)
3519 {
3520         struct jme_chain_data *cd = xcd;
3521         struct jme_softc *sc = cd->jme_sc;
3522         struct ifnet *ifp = &sc->arpcom.ac_if;
3523
3524         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3525
3526         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3527
3528         CSR_WRITE_4(sc, JME_INTR_STATUS,
3529             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3530
3531         if (ifp->if_flags & IFF_RUNNING) {
3532                 jme_txeof(sc);
3533                 if (!ifq_is_empty(&ifp->if_snd))
3534                         if_devstart(ifp);
3535         }
3536
3537         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3538 }
3539
3540 static void
3541 jme_msix_rx(void *xrdata)
3542 {
3543         struct jme_rxdata *rdata = xrdata;
3544         struct jme_softc *sc = rdata->jme_sc;
3545         struct ifnet *ifp = &sc->arpcom.ac_if;
3546         uint32_t status;
3547
3548         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3549
3550         CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3551             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3552
3553         status = CSR_READ_4(sc, JME_INTR_STATUS);
3554         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3555
3556         if (status & rdata->jme_rx_coal)
3557                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3558         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3559
3560         if (ifp->if_flags & IFF_RUNNING) {
3561                 if (status & rdata->jme_rx_coal)
3562                         jme_rxeof(rdata, -1);
3563
3564                 if (status & rdata->jme_rx_empty) {
3565                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3566                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3567                 }
3568         }
3569
3570         CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3571             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3572 }
3573
3574 static void
3575 jme_set_msinum(struct jme_softc *sc)
3576 {
3577         int i;
3578
3579         for (i = 0; i < JME_MSINUM_CNT; ++i)
3580                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3581 }
3582
3583 static int
3584 jme_intr_setup(device_t dev)
3585 {
3586         struct jme_softc *sc = device_get_softc(dev);
3587         struct ifnet *ifp = &sc->arpcom.ac_if;
3588         int error;
3589
3590         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3591                 return jme_msix_setup(dev);
3592
3593         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3594             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3595         if (error) {
3596                 device_printf(dev, "could not set up interrupt handler.\n");
3597                 return error;
3598         }
3599
3600         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3601         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3602         return 0;
3603 }
3604
3605 static void
3606 jme_intr_teardown(device_t dev)
3607 {
3608         struct jme_softc *sc = device_get_softc(dev);
3609
3610         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3611                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3612         else
3613                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3614 }
3615
3616 static int
3617 jme_msix_setup(device_t dev)
3618 {
3619         struct jme_softc *sc = device_get_softc(dev);
3620         struct ifnet *ifp = &sc->arpcom.ac_if;
3621         int x;
3622
3623         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3624                 struct jme_msix_data *msix = &sc->jme_msix[x];
3625                 int error;
3626
3627                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3628                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3629                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3630                     msix->jme_msix_desc);
3631                 if (error) {
3632                         device_printf(dev, "could not set up %s "
3633                             "interrupt handler.\n", msix->jme_msix_desc);
3634                         jme_msix_teardown(dev, x);
3635                         return error;
3636                 }
3637         }
3638         ifp->if_cpuid = 0; /* XXX */
3639         return 0;
3640 }
3641
3642 static void
3643 jme_msix_teardown(device_t dev, int msix_count)
3644 {
3645         struct jme_softc *sc = device_get_softc(dev);
3646         int x;
3647
3648         for (x = 0; x < msix_count; ++x) {
3649                 struct jme_msix_data *msix = &sc->jme_msix[x];
3650
3651                 bus_teardown_intr(dev, msix->jme_msix_res,
3652                     msix->jme_msix_handle);
3653         }
3654 }