bge: Don't touch jumbo frame registers on chips which do not support them
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110
111 /* "device miibus" required.  See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
115 #define BGE_MIN_FRAME           60
116
117 static const struct bge_type bge_devs[] = {
118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119                 "3COM 3C996 Gigabit Ethernet" },
120
121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
122                 "Alteon BCM5700 Gigabit Ethernet" },
123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124                 "Alteon BCM5701 Gigabit Ethernet" },
125
126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127                 "Altima AC1000 Gigabit Ethernet" },
128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129                 "Altima AC1002 Gigabit Ethernet" },
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131                 "Altima AC9100 Gigabit Ethernet" },
132
133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134                 "Apple BCM5701 Gigabit Ethernet" },
135
136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137                 "Broadcom BCM5700 Gigabit Ethernet" },
138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139                 "Broadcom BCM5701 Gigabit Ethernet" },
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141                 "Broadcom BCM5702 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
143                 "Broadcom BCM5702X Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147                 "Broadcom BCM5703 Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149                 "Broadcom BCM5703X Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
159                 "Broadcom BCM5705 Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161                 "Broadcom BCM5705F Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163                 "Broadcom BCM5705K Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
165                 "Broadcom BCM5705M Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
167                 "Broadcom BCM5705M Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
169                 "Broadcom BCM5714C Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171                 "Broadcom BCM5714S Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173                 "Broadcom BCM5715 Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175                 "Broadcom BCM5715S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177                 "Broadcom BCM5720 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179                 "Broadcom BCM5721 Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181                 "Broadcom BCM5722 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183                 "Broadcom BCM5723 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185                 "Broadcom BCM5750 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187                 "Broadcom BCM5750M Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189                 "Broadcom BCM5751 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191                 "Broadcom BCM5751F Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193                 "Broadcom BCM5751M Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195                 "Broadcom BCM5752 Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197                 "Broadcom BCM5752M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199                 "Broadcom BCM5753 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201                 "Broadcom BCM5753F Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203                 "Broadcom BCM5753M Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205                 "Broadcom BCM5754 Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207                 "Broadcom BCM5754M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209                 "Broadcom BCM5755 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211                 "Broadcom BCM5755M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213                 "Broadcom BCM5756 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215                 "Broadcom BCM5761 Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217                 "Broadcom BCM5761E Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219                 "Broadcom BCM5761S Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221                 "Broadcom BCM5761SE Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223                 "Broadcom BCM5764 Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225                 "Broadcom BCM5780 Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227                 "Broadcom BCM5780S Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229                 "Broadcom BCM5781 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
231                 "Broadcom BCM5782 Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233                 "Broadcom BCM5784 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235                 "Broadcom BCM5785F Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237                 "Broadcom BCM5785G Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239                 "Broadcom BCM5786 Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241                 "Broadcom BCM5787 Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243                 "Broadcom BCM5787F Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245                 "Broadcom BCM5787M Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
247                 "Broadcom BCM5788 Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249                 "Broadcom BCM5789 Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251                 "Broadcom BCM5901 Fast Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253                 "Broadcom BCM5901A2 Fast Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255                 "Broadcom BCM5903M Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257                 "Broadcom BCM5906 Fast Ethernet"},
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259                 "Broadcom BCM5906M Fast Ethernet"},
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261                 "Broadcom BCM57760 Gigabit Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263                 "Broadcom BCM57780 Gigabit Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265                 "Broadcom BCM57788 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267                 "Broadcom BCM57790 Gigabit Ethernet"},
268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
269                 "SysKonnect Gigabit Ethernet" },
270
271         { 0, 0, NULL }
272 };
273
274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
280
281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
282
283 static int      bge_probe(device_t);
284 static int      bge_attach(device_t);
285 static int      bge_detach(device_t);
286 static void     bge_txeof(struct bge_softc *);
287 static void     bge_rxeof(struct bge_softc *);
288
289 static void     bge_tick(void *);
290 static void     bge_stats_update(struct bge_softc *);
291 static void     bge_stats_update_regs(struct bge_softc *);
292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
293
294 #ifdef DEVICE_POLLING
295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
296 #endif
297 static void     bge_intr(void *);
298 static void     bge_enable_intr(struct bge_softc *);
299 static void     bge_disable_intr(struct bge_softc *);
300 static void     bge_start(struct ifnet *);
301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
302 static void     bge_init(void *);
303 static void     bge_stop(struct bge_softc *);
304 static void     bge_watchdog(struct ifnet *);
305 static void     bge_shutdown(device_t);
306 static int      bge_suspend(device_t);
307 static int      bge_resume(device_t);
308 static int      bge_ifmedia_upd(struct ifnet *);
309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
310
311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
313
314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
316
317 static void     bge_setmulti(struct bge_softc *);
318 static void     bge_setpromisc(struct bge_softc *);
319
320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
321 static void     bge_free_jumbo_mem(struct bge_softc *);
322 static struct bge_jslot
323                 *bge_jalloc(struct bge_softc *);
324 static void     bge_jfree(void *);
325 static void     bge_jref(void *);
326 static int      bge_newbuf_std(struct bge_softc *, int, int);
327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
330 static int      bge_init_rx_ring_std(struct bge_softc *);
331 static void     bge_free_rx_ring_std(struct bge_softc *);
332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
334 static void     bge_free_tx_ring(struct bge_softc *);
335 static int      bge_init_tx_ring(struct bge_softc *);
336
337 static int      bge_chipinit(struct bge_softc *);
338 static int      bge_blockinit(struct bge_softc *);
339
340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
342 #ifdef notdef
343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
344 #endif
345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
347 static void     bge_writembx(struct bge_softc *, int, int);
348
349 static int      bge_miibus_readreg(device_t, int, int);
350 static int      bge_miibus_writereg(device_t, int, int, int);
351 static void     bge_miibus_statchg(device_t);
352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
355
356 static void     bge_reset(struct bge_softc *);
357
358 static int      bge_dma_alloc(struct bge_softc *);
359 static void     bge_dma_free(struct bge_softc *);
360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
361                                     bus_dma_tag_t *, bus_dmamap_t *,
362                                     void **, bus_addr_t *);
363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
364
365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
369
370 static void     bge_coal_change(struct bge_softc *);
371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
376
377 /*
378  * Set following tunable to 1 for some IBM blade servers with the DNLK
379  * switch module. Auto negotiation is broken for those configurations.
380  */
381 static int      bge_fake_autoneg = 0;
382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
383
384 /* Interrupt moderation control variables. */
385 static int      bge_rx_coal_ticks = 100;        /* usec */
386 static int      bge_tx_coal_ticks = 1023;       /* usec */
387 static int      bge_rx_max_coal_bds = 80;
388 static int      bge_tx_max_coal_bds = 128;
389
390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
394
395 #if !defined(KTR_IF_BGE)
396 #define KTR_IF_BGE      KTR_ALL
397 #endif
398 KTR_INFO_MASTER(if_bge);
399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
402 #define logif(name)     KTR_LOG(if_bge_ ## name)
403
404 static device_method_t bge_methods[] = {
405         /* Device interface */
406         DEVMETHOD(device_probe,         bge_probe),
407         DEVMETHOD(device_attach,        bge_attach),
408         DEVMETHOD(device_detach,        bge_detach),
409         DEVMETHOD(device_shutdown,      bge_shutdown),
410         DEVMETHOD(device_suspend,       bge_suspend),
411         DEVMETHOD(device_resume,        bge_resume),
412
413         /* bus interface */
414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
416
417         /* MII interface */
418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
421
422         { 0, 0 }
423 };
424
425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
426 static devclass_t bge_devclass;
427
428 DECLARE_DUMMY_MODULE(if_bge);
429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
431
432 static uint32_t
433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
434 {
435         device_t dev = sc->bge_dev;
436         uint32_t val;
437
438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
441         return (val);
442 }
443
444 static void
445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
446 {
447         device_t dev = sc->bge_dev;
448
449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
452 }
453
454 #ifdef notdef
455 static uint32_t
456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
457 {
458         device_t dev = sc->bge_dev;
459
460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
462 }
463 #endif
464
465 static void
466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
467 {
468         device_t dev = sc->bge_dev;
469
470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
472 }
473
474 static void
475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
476 {
477         CSR_WRITE_4(sc, off, val);
478 }
479
480 static void
481 bge_writembx(struct bge_softc *sc, int off, int val)
482 {
483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
485
486         CSR_WRITE_4(sc, off, val);
487 }
488
489 static uint8_t
490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
491 {
492         uint32_t access, byte = 0;
493         int i;
494
495         /* Lock. */
496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
497         for (i = 0; i < 8000; i++) {
498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
499                         break;
500                 DELAY(20);
501         }
502         if (i == 8000)
503                 return (1);
504
505         /* Enable access. */
506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
508
509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
512                 DELAY(10);
513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
514                         DELAY(10);
515                         break;
516                 }
517         }
518
519         if (i == BGE_TIMEOUT * 10) {
520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
521                 return (1);
522         }
523
524         /* Get result. */
525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
526
527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
528
529         /* Disable access. */
530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
531
532         /* Unlock. */
533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
535
536         return (0);
537 }
538
539 /*
540  * Read a sequence of bytes from NVRAM.
541  */
542 static int
543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
544 {
545         int err = 0, i;
546         uint8_t byte = 0;
547
548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
549                 return (1);
550
551         for (i = 0; i < cnt; i++) {
552                 err = bge_nvram_getbyte(sc, off + i, &byte);
553                 if (err)
554                         break;
555                 *(dest + i) = byte;
556         }
557
558         return (err ? 1 : 0);
559 }
560
561 /*
562  * Read a byte of data stored in the EEPROM at address 'addr.' The
563  * BCM570x supports both the traditional bitbang interface and an
564  * auto access interface for reading the EEPROM. We use the auto
565  * access method.
566  */
567 static uint8_t
568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
569 {
570         int i;
571         uint32_t byte = 0;
572
573         /*
574          * Enable use of auto EEPROM access so we can avoid
575          * having to use the bitbang method.
576          */
577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
578
579         /* Reset the EEPROM, load the clock period. */
580         CSR_WRITE_4(sc, BGE_EE_ADDR,
581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
582         DELAY(20);
583
584         /* Issue the read EEPROM command. */
585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
586
587         /* Wait for completion */
588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
589                 DELAY(10);
590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
591                         break;
592         }
593
594         if (i == BGE_TIMEOUT) {
595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
596                 return(1);
597         }
598
599         /* Get result. */
600         byte = CSR_READ_4(sc, BGE_EE_DATA);
601
602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
603
604         return(0);
605 }
606
607 /*
608  * Read a sequence of bytes from the EEPROM.
609  */
610 static int
611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
612 {
613         size_t i;
614         int err;
615         uint8_t byte;
616
617         for (byte = 0, err = 0, i = 0; i < len; i++) {
618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
619                 if (err)
620                         break;
621                 *(dest + i) = byte;
622         }
623
624         return(err ? 1 : 0);
625 }
626
627 static int
628 bge_miibus_readreg(device_t dev, int phy, int reg)
629 {
630         struct bge_softc *sc = device_get_softc(dev);
631         struct ifnet *ifp = &sc->arpcom.ac_if;
632         uint32_t val, autopoll;
633         int i;
634
635         /*
636          * Broadcom's own driver always assumes the internal
637          * PHY is at GMII address 1. On some chips, the PHY responds
638          * to accesses at all addresses, which could cause us to
639          * bogusly attach the PHY 32 times at probe type. Always
640          * restricting the lookup to address 1 is simpler than
641          * trying to figure out which chips revisions should be
642          * special-cased.
643          */
644         if (phy != 1)
645                 return(0);
646
647         /* Reading with autopolling on may trigger PCI errors */
648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
651                 DELAY(40);
652         }
653
654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
655             BGE_MIPHY(phy)|BGE_MIREG(reg));
656
657         for (i = 0; i < BGE_TIMEOUT; i++) {
658                 DELAY(10);
659                 val = CSR_READ_4(sc, BGE_MI_COMM);
660                 if (!(val & BGE_MICOMM_BUSY))
661                         break;
662         }
663
664         if (i == BGE_TIMEOUT) {
665                 if_printf(ifp, "PHY read timed out "
666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
667                 val = 0;
668                 goto done;
669         }
670
671         DELAY(5);
672         val = CSR_READ_4(sc, BGE_MI_COMM);
673
674 done:
675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
677                 DELAY(40);
678         }
679
680         if (val & BGE_MICOMM_READFAIL)
681                 return(0);
682
683         return(val & 0xFFFF);
684 }
685
686 static int
687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
688 {
689         struct bge_softc *sc = device_get_softc(dev);
690         uint32_t autopoll;
691         int i;
692
693         /*
694          * See the related comment in bge_miibus_readreg()
695          */
696         if (phy != 1)
697                 return(0);
698
699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701                return(0);
702
703         /* Reading with autopolling on may trigger PCI errors */
704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
707                 DELAY(40);
708         }
709
710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
712
713         for (i = 0; i < BGE_TIMEOUT; i++) {
714                 DELAY(10);
715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
716                         DELAY(5);
717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
718                         break;
719                 }
720         }
721
722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
724                 DELAY(40);
725         }
726
727         if (i == BGE_TIMEOUT) {
728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
730                 return(0);
731         }
732
733         return(0);
734 }
735
736 static void
737 bge_miibus_statchg(device_t dev)
738 {
739         struct bge_softc *sc;
740         struct mii_data *mii;
741
742         sc = device_get_softc(dev);
743         mii = device_get_softc(sc->bge_miibus);
744
745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
747                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
748         } else {
749                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
750         }
751
752         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
753                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
754         } else {
755                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
756         }
757 }
758
759 /*
760  * Memory management for jumbo frames.
761  */
762 static int
763 bge_alloc_jumbo_mem(struct bge_softc *sc)
764 {
765         struct ifnet *ifp = &sc->arpcom.ac_if;
766         struct bge_jslot *entry;
767         uint8_t *ptr;
768         bus_addr_t paddr;
769         int i, error;
770
771         /*
772          * Create tag for jumbo mbufs.
773          * This is really a bit of a kludge. We allocate a special
774          * jumbo buffer pool which (thanks to the way our DMA
775          * memory allocation works) will consist of contiguous
776          * pages. This means that even though a jumbo buffer might
777          * be larger than a page size, we don't really need to
778          * map it into more than one DMA segment. However, the
779          * default mbuf tag will result in multi-segment mappings,
780          * so we have to create a special jumbo mbuf tag that
781          * lets us get away with mapping the jumbo buffers as
782          * a single segment. I think eventually the driver should
783          * be changed so that it uses ordinary mbufs and cluster
784          * buffers, i.e. jumbo frames can span multiple DMA
785          * descriptors. But that's a project for another day.
786          */
787
788         /*
789          * Create DMA stuffs for jumbo RX ring.
790          */
791         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
792                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
793                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
794                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
795                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
796         if (error) {
797                 if_printf(ifp, "could not create jumbo RX ring\n");
798                 return error;
799         }
800
801         /*
802          * Create DMA stuffs for jumbo buffer block.
803          */
804         error = bge_dma_block_alloc(sc, BGE_JMEM,
805                                     &sc->bge_cdata.bge_jumbo_tag,
806                                     &sc->bge_cdata.bge_jumbo_map,
807                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
808                                     &paddr);
809         if (error) {
810                 if_printf(ifp, "could not create jumbo buffer\n");
811                 return error;
812         }
813
814         SLIST_INIT(&sc->bge_jfree_listhead);
815
816         /*
817          * Now divide it up into 9K pieces and save the addresses
818          * in an array. Note that we play an evil trick here by using
819          * the first few bytes in the buffer to hold the the address
820          * of the softc structure for this interface. This is because
821          * bge_jfree() needs it, but it is called by the mbuf management
822          * code which will not pass it to us explicitly.
823          */
824         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
825                 entry = &sc->bge_cdata.bge_jslots[i];
826                 entry->bge_sc = sc;
827                 entry->bge_buf = ptr;
828                 entry->bge_paddr = paddr;
829                 entry->bge_inuse = 0;
830                 entry->bge_slot = i;
831                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
832
833                 ptr += BGE_JLEN;
834                 paddr += BGE_JLEN;
835         }
836         return 0;
837 }
838
839 static void
840 bge_free_jumbo_mem(struct bge_softc *sc)
841 {
842         /* Destroy jumbo RX ring. */
843         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
844                            sc->bge_cdata.bge_rx_jumbo_ring_map,
845                            sc->bge_ldata.bge_rx_jumbo_ring);
846
847         /* Destroy jumbo buffer block. */
848         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
849                            sc->bge_cdata.bge_jumbo_map,
850                            sc->bge_ldata.bge_jumbo_buf);
851 }
852
853 /*
854  * Allocate a jumbo buffer.
855  */
856 static struct bge_jslot *
857 bge_jalloc(struct bge_softc *sc)
858 {
859         struct bge_jslot *entry;
860
861         lwkt_serialize_enter(&sc->bge_jslot_serializer);
862         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
863         if (entry) {
864                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
865                 entry->bge_inuse = 1;
866         } else {
867                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
868         }
869         lwkt_serialize_exit(&sc->bge_jslot_serializer);
870         return(entry);
871 }
872
873 /*
874  * Adjust usage count on a jumbo buffer.
875  */
876 static void
877 bge_jref(void *arg)
878 {
879         struct bge_jslot *entry = (struct bge_jslot *)arg;
880         struct bge_softc *sc = entry->bge_sc;
881
882         if (sc == NULL)
883                 panic("bge_jref: can't find softc pointer!");
884
885         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
886                 panic("bge_jref: asked to reference buffer "
887                     "that we don't manage!");
888         } else if (entry->bge_inuse == 0) {
889                 panic("bge_jref: buffer already free!");
890         } else {
891                 atomic_add_int(&entry->bge_inuse, 1);
892         }
893 }
894
895 /*
896  * Release a jumbo buffer.
897  */
898 static void
899 bge_jfree(void *arg)
900 {
901         struct bge_jslot *entry = (struct bge_jslot *)arg;
902         struct bge_softc *sc = entry->bge_sc;
903
904         if (sc == NULL)
905                 panic("bge_jfree: can't find softc pointer!");
906
907         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
908                 panic("bge_jfree: asked to free buffer that we don't manage!");
909         } else if (entry->bge_inuse == 0) {
910                 panic("bge_jfree: buffer already free!");
911         } else {
912                 /*
913                  * Possible MP race to 0, use the serializer.  The atomic insn
914                  * is still needed for races against bge_jref().
915                  */
916                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
917                 atomic_subtract_int(&entry->bge_inuse, 1);
918                 if (entry->bge_inuse == 0) {
919                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
920                                           entry, jslot_link);
921                 }
922                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
923         }
924 }
925
926
927 /*
928  * Intialize a standard receive ring descriptor.
929  */
930 static int
931 bge_newbuf_std(struct bge_softc *sc, int i, int init)
932 {
933         struct mbuf *m_new = NULL;
934         bus_dma_segment_t seg;
935         bus_dmamap_t map;
936         int error, nsegs;
937
938         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
939         if (m_new == NULL)
940                 return ENOBUFS;
941         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
942
943         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
944                 m_adj(m_new, ETHER_ALIGN);
945
946         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
947                         sc->bge_cdata.bge_rx_tmpmap, m_new,
948                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
949         if (error) {
950                 m_freem(m_new);
951                 return error;
952         }
953
954         if (!init) {
955                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
956                                 sc->bge_cdata.bge_rx_std_dmamap[i],
957                                 BUS_DMASYNC_POSTREAD);
958                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
959                         sc->bge_cdata.bge_rx_std_dmamap[i]);
960         }
961
962         map = sc->bge_cdata.bge_rx_tmpmap;
963         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
964         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
965
966         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
967         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
968
969         bge_setup_rxdesc_std(sc, i);
970         return 0;
971 }
972
973 static void
974 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
975 {
976         struct bge_rxchain *rc;
977         struct bge_rx_bd *r;
978
979         rc = &sc->bge_cdata.bge_rx_std_chain[i];
980         r = &sc->bge_ldata.bge_rx_std_ring[i];
981
982         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
983         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
984         r->bge_len = rc->bge_mbuf->m_len;
985         r->bge_idx = i;
986         r->bge_flags = BGE_RXBDFLAG_END;
987 }
988
989 /*
990  * Initialize a jumbo receive ring descriptor. This allocates
991  * a jumbo buffer from the pool managed internally by the driver.
992  */
993 static int
994 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
995 {
996         struct mbuf *m_new = NULL;
997         struct bge_jslot *buf;
998         bus_addr_t paddr;
999
1000         /* Allocate the mbuf. */
1001         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002         if (m_new == NULL)
1003                 return ENOBUFS;
1004
1005         /* Allocate the jumbo buffer */
1006         buf = bge_jalloc(sc);
1007         if (buf == NULL) {
1008                 m_freem(m_new);
1009                 return ENOBUFS;
1010         }
1011
1012         /* Attach the buffer to the mbuf. */
1013         m_new->m_ext.ext_arg = buf;
1014         m_new->m_ext.ext_buf = buf->bge_buf;
1015         m_new->m_ext.ext_free = bge_jfree;
1016         m_new->m_ext.ext_ref = bge_jref;
1017         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019         m_new->m_flags |= M_EXT;
1020
1021         m_new->m_data = m_new->m_ext.ext_buf;
1022         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1023
1024         paddr = buf->bge_paddr;
1025         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1026                 m_adj(m_new, ETHER_ALIGN);
1027                 paddr += ETHER_ALIGN;
1028         }
1029
1030         /* Save necessary information */
1031         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
1034         /* Set up the descriptor. */
1035         bge_setup_rxdesc_jumbo(sc, i);
1036         return 0;
1037 }
1038
1039 static void
1040 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041 {
1042         struct bge_rx_bd *r;
1043         struct bge_rxchain *rc;
1044
1045         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1046         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1047
1048         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050         r->bge_len = rc->bge_mbuf->m_len;
1051         r->bge_idx = i;
1052         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1053 }
1054
1055 static int
1056 bge_init_rx_ring_std(struct bge_softc *sc)
1057 {
1058         int i, error;
1059
1060         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061                 error = bge_newbuf_std(sc, i, 1);
1062                 if (error)
1063                         return error;
1064         };
1065
1066         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return(0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080                 if (rc->bge_mbuf != NULL) {
1081                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1082                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1083                         m_freem(rc->bge_mbuf);
1084                         rc->bge_mbuf = NULL;
1085                 }
1086                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1087                     sizeof(struct bge_rx_bd));
1088         }
1089 }
1090
1091 static int
1092 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         struct bge_rcb *rcb;
1095         int i, error;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 error = bge_newbuf_jumbo(sc, i, 1);
1099                 if (error)
1100                         return error;
1101         };
1102
1103         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1104
1105         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1106         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
1109         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1110
1111         return(0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1120                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122                 if (rc->bge_mbuf != NULL) {
1123                         m_freem(rc->bge_mbuf);
1124                         rc->bge_mbuf = NULL;
1125                 }
1126                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1127                     sizeof(struct bge_rx_bd));
1128         }
1129 }
1130
1131 static void
1132 bge_free_tx_ring(struct bge_softc *sc)
1133 {
1134         int i;
1135
1136         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1139                                           sc->bge_cdata.bge_tx_dmamap[i]);
1140                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1142                 }
1143                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1144                     sizeof(struct bge_tx_bd));
1145         }
1146 }
1147
1148 static int
1149 bge_init_tx_ring(struct bge_softc *sc)
1150 {
1151         sc->bge_txcnt = 0;
1152         sc->bge_tx_saved_considx = 0;
1153         sc->bge_tx_prodidx = 0;
1154
1155         /* Initialize transmit producer index for host-memory send ring. */
1156         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1157
1158         /* 5700 b2 errata */
1159         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1160                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1161
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return(0);
1168 }
1169
1170 static void
1171 bge_setmulti(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174         struct ifmultiaddr *ifma;
1175         uint32_t hashes[4] = { 0, 0, 0, 0 };
1176         int h, i;
1177
1178         ifp = &sc->arpcom.ac_if;
1179
1180         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181                 for (i = 0; i < 4; i++)
1182                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183                 return;
1184         }
1185
1186         /* First, zot all the existing filters. */
1187         for (i = 0; i < 4; i++)
1188                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190         /* Now program new ones. */
1191         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1192                 if (ifma->ifma_addr->sa_family != AF_LINK)
1193                         continue;
1194                 h = ether_crc32_le(
1195                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196                     ETHER_ADDR_LEN) & 0x7f;
1197                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198         }
1199
1200         for (i = 0; i < 4; i++)
1201                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1202 }
1203
1204 /*
1205  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206  * self-test results.
1207  */
1208 static int
1209 bge_chipinit(struct bge_softc *sc)
1210 {
1211         int i;
1212         uint32_t dma_rw_ctl;
1213         uint16_t val;
1214
1215         /* Set endian type before we access any non-PCI registers. */
1216         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1217
1218         /* Clear the MAC control register */
1219         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1220
1221         /*
1222          * Clear the MAC statistics block in the NIC's
1223          * internal memory.
1224          */
1225         for (i = BGE_STATS_BLOCK;
1226             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1227                 BGE_MEMWIN_WRITE(sc, i, 0);
1228
1229         for (i = BGE_STATUS_BLOCK;
1230             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1231                 BGE_MEMWIN_WRITE(sc, i, 0);
1232
1233         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1234                 /*
1235                  * Fix data corruption caused by non-qword write with WB.
1236                  * Fix master abort in PCI mode.
1237                  * Fix PCI latency timer.
1238                  */
1239                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1240                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1241                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1242         }
1243
1244         /* Set up the PCI DMA control register. */
1245         if (sc->bge_flags & BGE_FLAG_PCIE) {
1246                 /* PCI Express */
1247                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1248                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1249                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1250         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1251                 /* PCI-X bus */
1252                 if (BGE_IS_5714_FAMILY(sc)) {
1253                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1254                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1255                         /* XXX magic values, Broadcom-supplied Linux driver */
1256                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1257                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | 
1258                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1259                         } else {
1260                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1261                         }
1262                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1263                         /*
1264                          * In the BCM5703, the DMA read watermark should
1265                          * be set to less than or equal to the maximum
1266                          * memory read byte count of the PCI-X command
1267                          * register.
1268                          */
1269                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1270                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1271                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1272                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1273                         /*
1274                          * The 5704 uses a different encoding of read/write
1275                          * watermarks.
1276                          */
1277                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1278                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1279                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1280                 } else {
1281                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1282                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1283                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1284                             (0x0F);
1285                 }
1286
1287                 /*
1288                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1289                  * for hardware bugs.
1290                  */
1291                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1292                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1293                         uint32_t tmp;
1294
1295                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1296                         if (tmp == 0x6 || tmp == 0x7)
1297                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1298                 }
1299         } else {
1300                 /* Conventional PCI bus */
1301                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1302                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1304                     (0x0F);
1305         }
1306
1307         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1308             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1309             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1310                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1311         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1312
1313         /*
1314          * Set up general mode register.
1315          */
1316         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1317             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1318             BGE_MODECTL_TX_NO_PHDR_CSUM);
1319
1320         /*
1321          * BCM5701 B5 have a bug causing data corruption when using
1322          * 64-bit DMA reads, which can be terminated early and then
1323          * completed later as 32-bit accesses, in combination with
1324          * certain bridges.
1325          */
1326         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1327             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1328                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1329
1330         /*
1331          * Disable memory write invalidate.  Apparently it is not supported
1332          * properly by these devices.
1333          */
1334         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1335
1336         /* Set the timer prescaler (always 66Mhz) */
1337         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1338
1339         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1340                 DELAY(40);      /* XXX */
1341
1342                 /* Put PHY into ready state */
1343                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1344                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1345                 DELAY(40);
1346         }
1347
1348         return(0);
1349 }
1350
1351 static int
1352 bge_blockinit(struct bge_softc *sc)
1353 {
1354         struct bge_rcb *rcb;
1355         bus_size_t vrcb;
1356         bge_hostaddr taddr;
1357         uint32_t val;
1358         int i;
1359
1360         /*
1361          * Initialize the memory window pointer register so that
1362          * we can access the first 32K of internal NIC RAM. This will
1363          * allow us to set up the TX send ring RCBs and the RX return
1364          * ring RCBs, plus other things which live in NIC memory.
1365          */
1366         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1367
1368         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1369
1370         if (!BGE_IS_5705_PLUS(sc)) {
1371                 /* Configure mbuf memory pool */
1372                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1373                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1374                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1375                 else
1376                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1377
1378                 /* Configure DMA resource pool */
1379                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1380                     BGE_DMA_DESCRIPTORS);
1381                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1382         }
1383
1384         /* Configure mbuf pool watermarks */
1385         if (!BGE_IS_5705_PLUS(sc)) {
1386                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1387                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1388                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1389         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1390                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1391                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1392                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1393         } else {
1394                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1395                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1396                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1397         }
1398
1399         /* Configure DMA resource watermarks */
1400         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1401         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1402
1403         /* Enable buffer manager */
1404         if (!BGE_IS_5705_PLUS(sc)) {
1405                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1406                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1407
1408                 /* Poll for buffer manager start indication */
1409                 for (i = 0; i < BGE_TIMEOUT; i++) {
1410                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1411                                 break;
1412                         DELAY(10);
1413                 }
1414
1415                 if (i == BGE_TIMEOUT) {
1416                         if_printf(&sc->arpcom.ac_if,
1417                                   "buffer manager failed to start\n");
1418                         return(ENXIO);
1419                 }
1420         }
1421
1422         /* Enable flow-through queues */
1423         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1424         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1425
1426         /* Wait until queue initialization is complete */
1427         for (i = 0; i < BGE_TIMEOUT; i++) {
1428                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1429                         break;
1430                 DELAY(10);
1431         }
1432
1433         if (i == BGE_TIMEOUT) {
1434                 if_printf(&sc->arpcom.ac_if,
1435                           "flow-through queue init failed\n");
1436                 return(ENXIO);
1437         }
1438
1439         /* Initialize the standard RX ring control block */
1440         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1441         rcb->bge_hostaddr.bge_addr_lo =
1442             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1443         rcb->bge_hostaddr.bge_addr_hi =
1444             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1445         if (BGE_IS_5705_PLUS(sc))
1446                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1447         else
1448                 rcb->bge_maxlen_flags =
1449                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1450         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1451         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1452         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1453         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1454         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1455
1456         /*
1457          * Initialize the jumbo RX ring control block
1458          * We set the 'ring disabled' bit in the flags
1459          * field until we're actually ready to start
1460          * using this ring (i.e. once we set the MTU
1461          * high enough to require it).
1462          */
1463         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1464                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1465
1466                 rcb->bge_hostaddr.bge_addr_lo =
1467                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1468                 rcb->bge_hostaddr.bge_addr_hi =
1469                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1470                 rcb->bge_maxlen_flags =
1471                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1472                     BGE_RCB_FLAG_RING_DISABLED);
1473                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1474                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1475                     rcb->bge_hostaddr.bge_addr_hi);
1476                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1477                     rcb->bge_hostaddr.bge_addr_lo);
1478                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1479                     rcb->bge_maxlen_flags);
1480                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1481
1482                 /* Set up dummy disabled mini ring RCB */
1483                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1484                 rcb->bge_maxlen_flags =
1485                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1486                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1487                     rcb->bge_maxlen_flags);
1488         }
1489
1490         /*
1491          * Set the BD ring replentish thresholds. The recommended
1492          * values are 1/8th the number of descriptors allocated to
1493          * each ring.
1494          */
1495         if (BGE_IS_5705_PLUS(sc))
1496                 val = 8;
1497         else
1498                 val = BGE_STD_RX_RING_CNT / 8;
1499         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1500         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1501                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1502                     BGE_JUMBO_RX_RING_CNT/8);
1503         }
1504
1505         /*
1506          * Disable all unused send rings by setting the 'ring disabled'
1507          * bit in the flags field of all the TX send ring control blocks.
1508          * These are located in NIC memory.
1509          */
1510         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1511         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1512                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1513                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1514                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1515                 vrcb += sizeof(struct bge_rcb);
1516         }
1517
1518         /* Configure TX RCB 0 (we use only the first ring) */
1519         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1520         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1521         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1522         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1523         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1524             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1525         if (!BGE_IS_5705_PLUS(sc)) {
1526                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1527                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1528         }
1529
1530         /* Disable all unused RX return rings */
1531         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1532         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1533                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1534                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1535                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1536                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1537                     BGE_RCB_FLAG_RING_DISABLED));
1538                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1539                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1540                     (i * (sizeof(uint64_t))), 0);
1541                 vrcb += sizeof(struct bge_rcb);
1542         }
1543
1544         /* Initialize RX ring indexes */
1545         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1546         if (BGE_IS_JUMBO_CAPABLE(sc))
1547                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1548         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1549
1550         /*
1551          * Set up RX return ring 0
1552          * Note that the NIC address for RX return rings is 0x00000000.
1553          * The return rings live entirely within the host, so the
1554          * nicaddr field in the RCB isn't used.
1555          */
1556         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1557         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1558         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1559         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1560         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1561         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1562             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1563
1564         /* Set random backoff seed for TX */
1565         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1566             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1567             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1568             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1569             BGE_TX_BACKOFF_SEED_MASK);
1570
1571         /* Set inter-packet gap */
1572         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1573
1574         /*
1575          * Specify which ring to use for packets that don't match
1576          * any RX rules.
1577          */
1578         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1579
1580         /*
1581          * Configure number of RX lists. One interrupt distribution
1582          * list, sixteen active lists, one bad frames class.
1583          */
1584         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1585
1586         /* Inialize RX list placement stats mask. */
1587         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1588         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1589
1590         /* Disable host coalescing until we get it set up */
1591         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1592
1593         /* Poll to make sure it's shut down. */
1594         for (i = 0; i < BGE_TIMEOUT; i++) {
1595                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1596                         break;
1597                 DELAY(10);
1598         }
1599
1600         if (i == BGE_TIMEOUT) {
1601                 if_printf(&sc->arpcom.ac_if,
1602                           "host coalescing engine failed to idle\n");
1603                 return(ENXIO);
1604         }
1605
1606         /* Set up host coalescing defaults */
1607         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1608         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1609         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1610         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1611         if (!BGE_IS_5705_PLUS(sc)) {
1612                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1613                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1614         }
1615         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1616         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1617
1618         /* Set up address of statistics block */
1619         if (!BGE_IS_5705_PLUS(sc)) {
1620                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1621                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1622                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1623                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1624
1625                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1626                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1627                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1628         }
1629
1630         /* Set up address of status block */
1631         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1632             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1633         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1634             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1635         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1636         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1637
1638         /*
1639          * Set up status block partail update size.
1640          *
1641          * Because only single TX ring, RX produce ring and Rx return ring
1642          * are used, ask device to update only minimum part of status block
1643          * except for BCM5700 AX/BX, whose status block partial update size
1644          * can't be configured.
1645          */
1646         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1647             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1648                 /* XXX Actually reserved on BCM5700 AX/BX */
1649                 val = BGE_STATBLKSZ_FULL;
1650         } else {
1651                 val = BGE_STATBLKSZ_32BYTE;
1652         }
1653
1654         /* Turn on host coalescing state machine */
1655         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1656
1657         /* Turn on RX BD completion state machine and enable attentions */
1658         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1659             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1660
1661         /* Turn on RX list placement state machine */
1662         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1663
1664         /* Turn on RX list selector state machine. */
1665         if (!BGE_IS_5705_PLUS(sc))
1666                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1667
1668         /* Turn on DMA, clear stats */
1669         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1670             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1671             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1672             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1673             ((sc->bge_flags & BGE_FLAG_TBI) ?
1674              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1675
1676         /* Set misc. local control, enable interrupts on attentions */
1677         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1678
1679 #ifdef notdef
1680         /* Assert GPIO pins for PHY reset */
1681         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1682             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1683         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1684             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1685 #endif
1686
1687         /* Turn on DMA completion state machine */
1688         if (!BGE_IS_5705_PLUS(sc))
1689                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1690
1691         /* Turn on write DMA state machine */
1692         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1693         if (BGE_IS_5755_PLUS(sc)) {
1694                 /* Enable host coalescing bug fix. */
1695                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1696         }
1697         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1698         DELAY(40);
1699
1700         /* Turn on read DMA state machine */
1701         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1702         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1703             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1704             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1705                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1706                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1707                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1708         if (sc->bge_flags & BGE_FLAG_PCIE)
1709                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1710         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1711         DELAY(40);
1712
1713         /* Turn on RX data completion state machine */
1714         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1715
1716         /* Turn on RX BD initiator state machine */
1717         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1718
1719         /* Turn on RX data and RX BD initiator state machine */
1720         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1721
1722         /* Turn on Mbuf cluster free state machine */
1723         if (!BGE_IS_5705_PLUS(sc))
1724                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1725
1726         /* Turn on send BD completion state machine */
1727         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1728
1729         /* Turn on send data completion state machine */
1730         val = BGE_SDCMODE_ENABLE;
1731         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1732                 val |= BGE_SDCMODE_CDELAY; 
1733         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1734
1735         /* Turn on send data initiator state machine */
1736         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1737
1738         /* Turn on send BD initiator state machine */
1739         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1740
1741         /* Turn on send BD selector state machine */
1742         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1743
1744         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1745         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1746             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1747
1748         /* ack/clear link change events */
1749         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1750             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1751             BGE_MACSTAT_LINK_CHANGED);
1752         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1753
1754         /* Enable PHY auto polling (for MII/GMII only) */
1755         if (sc->bge_flags & BGE_FLAG_TBI) {
1756                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1757         } else {
1758                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1759                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1760                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1761                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1762                             BGE_EVTENB_MI_INTERRUPT);
1763                 }
1764         }
1765
1766         /*
1767          * Clear any pending link state attention.
1768          * Otherwise some link state change events may be lost until attention
1769          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1770          * It's not necessary on newer BCM chips - perhaps enabling link
1771          * state change attentions implies clearing pending attention.
1772          */
1773         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1774             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1775             BGE_MACSTAT_LINK_CHANGED);
1776
1777         /* Enable link state change attentions. */
1778         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1779
1780         return(0);
1781 }
1782
1783 /*
1784  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1785  * against our list and return its name if we find a match. Note
1786  * that since the Broadcom controller contains VPD support, we
1787  * can get the device name string from the controller itself instead
1788  * of the compiled-in string. This is a little slow, but it guarantees
1789  * we'll always announce the right product name.
1790  */
1791 static int
1792 bge_probe(device_t dev)
1793 {
1794         const struct bge_type *t;
1795         uint16_t product, vendor;
1796
1797         product = pci_get_device(dev);
1798         vendor = pci_get_vendor(dev);
1799
1800         for (t = bge_devs; t->bge_name != NULL; t++) {
1801                 if (vendor == t->bge_vid && product == t->bge_did)
1802                         break;
1803         }
1804         if (t->bge_name == NULL)
1805                 return(ENXIO);
1806
1807         device_set_desc(dev, t->bge_name);
1808         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1809                 struct bge_softc *sc = device_get_softc(dev);
1810                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1811         }
1812         return(0);
1813 }
1814
1815 static int
1816 bge_attach(device_t dev)
1817 {
1818         struct ifnet *ifp;
1819         struct bge_softc *sc;
1820         uint32_t hwcfg = 0;
1821         int error = 0, rid;
1822         uint8_t ether_addr[ETHER_ADDR_LEN];
1823
1824         sc = device_get_softc(dev);
1825         sc->bge_dev = dev;
1826         callout_init(&sc->bge_stat_timer);
1827         lwkt_serialize_init(&sc->bge_jslot_serializer);
1828
1829 #ifndef BURN_BRIDGES
1830         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1831                 uint32_t irq, mem;
1832
1833                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1834                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1835
1836                 device_printf(dev, "chip is in D%d power mode "
1837                     "-- setting to D0\n", pci_get_powerstate(dev));
1838
1839                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1840
1841                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1842                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1843         }
1844 #endif  /* !BURN_BRIDGE */
1845
1846         /*
1847          * Map control/status registers.
1848          */
1849         pci_enable_busmaster(dev);
1850
1851         rid = BGE_PCI_BAR0;
1852         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1853             RF_ACTIVE);
1854
1855         if (sc->bge_res == NULL) {
1856                 device_printf(dev, "couldn't map memory\n");
1857                 return ENXIO;
1858         }
1859
1860         sc->bge_btag = rman_get_bustag(sc->bge_res);
1861         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1862
1863         /* Save various chip information */
1864         sc->bge_chipid =
1865             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1866             BGE_PCIMISCCTL_ASICREV_SHIFT;
1867         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1868                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1869         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1870         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1871
1872         /* Save chipset family. */
1873         switch (sc->bge_asicrev) {
1874         case BGE_ASICREV_BCM5755:
1875         case BGE_ASICREV_BCM5761:
1876         case BGE_ASICREV_BCM5784:
1877         case BGE_ASICREV_BCM5785:
1878         case BGE_ASICREV_BCM5787:
1879         case BGE_ASICREV_BCM57780:
1880             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1881                 BGE_FLAG_5705_PLUS;
1882             break;
1883
1884         case BGE_ASICREV_BCM5700:
1885         case BGE_ASICREV_BCM5701:
1886         case BGE_ASICREV_BCM5703:
1887         case BGE_ASICREV_BCM5704:
1888                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1889                 break;
1890
1891         case BGE_ASICREV_BCM5714_A0:
1892         case BGE_ASICREV_BCM5780:
1893         case BGE_ASICREV_BCM5714:
1894                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1895                 /* Fall through */
1896
1897         case BGE_ASICREV_BCM5750:
1898         case BGE_ASICREV_BCM5752:
1899         case BGE_ASICREV_BCM5906:
1900                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1901                 /* Fall through */
1902
1903         case BGE_ASICREV_BCM5705:
1904                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1905                 break;
1906         }
1907
1908         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1909                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1910
1911         /*
1912          * Set various quirk flags.
1913          */
1914
1915         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1916         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1917             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1918              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1919               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1920             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1921                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1922
1923         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1924             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1925                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1926
1927         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1928             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1929                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1930
1931         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1932                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1933
1934         if (BGE_IS_5705_PLUS(sc)) {
1935                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1936                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1937                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1938                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1939                         uint32_t product = pci_get_device(dev);
1940
1941                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1942                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1943                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1944                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1945                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1946                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1947                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1948                 }
1949         }
1950
1951         /* Allocate interrupt */
1952         rid = 0;
1953
1954         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1955             RF_SHAREABLE | RF_ACTIVE);
1956
1957         if (sc->bge_irq == NULL) {
1958                 device_printf(dev, "couldn't map interrupt\n");
1959                 error = ENXIO;
1960                 goto fail;
1961         }
1962
1963         /*
1964          * Check if this is a PCI-X or PCI Express device.
1965          */
1966         if (BGE_IS_5705_PLUS(sc)) {
1967                 if (pci_is_pcie(dev)) {
1968                         sc->bge_flags |= BGE_FLAG_PCIE;
1969                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1970                 }
1971         } else {
1972                 /*
1973                  * Check if the device is in PCI-X Mode.
1974                  * (This bit is not valid on PCI Express controllers.)
1975                  */
1976                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1977                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
1978                         sc->bge_flags |= BGE_FLAG_PCIX;
1979                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
1980                 }
1981         }
1982
1983         device_printf(dev, "CHIP ID 0x%08x; "
1984                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1985                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1986                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1987                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1988                         "PCI-E" : "PCI"));
1989
1990         /*
1991          * All controllers that are not 5755 or higher have 4GB
1992          * boundary DMA bug.
1993          * Whenever an address crosses a multiple of the 4GB boundary
1994          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1995          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1996          * state machine will lockup and cause the device to hang.
1997          */
1998         if (BGE_IS_5755_PLUS(sc) == 0)
1999                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
2000
2001         /*
2002          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2003          * not actually a MAC controller bug but an issue with the embedded
2004          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2005          */
2006         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2007                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2008
2009         ifp = &sc->arpcom.ac_if;
2010         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2011
2012         /* Try to reset the chip. */
2013         bge_reset(sc);
2014
2015         if (bge_chipinit(sc)) {
2016                 device_printf(dev, "chip initialization failed\n");
2017                 error = ENXIO;
2018                 goto fail;
2019         }
2020
2021         /*
2022          * Get station address
2023          */
2024         error = bge_get_eaddr(sc, ether_addr);
2025         if (error) {
2026                 device_printf(dev, "failed to read station address\n");
2027                 goto fail;
2028         }
2029
2030         /* 5705/5750 limits RX return ring to 512 entries. */
2031         if (BGE_IS_5705_PLUS(sc))
2032                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2033         else
2034                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2035
2036         error = bge_dma_alloc(sc);
2037         if (error)
2038                 goto fail;
2039
2040         /* Set default tuneable values. */
2041         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2042         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2043         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2044         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2045         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2046
2047         /* Set up ifnet structure */
2048         ifp->if_softc = sc;
2049         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2050         ifp->if_ioctl = bge_ioctl;
2051         ifp->if_start = bge_start;
2052 #ifdef DEVICE_POLLING
2053         ifp->if_poll = bge_poll;
2054 #endif
2055         ifp->if_watchdog = bge_watchdog;
2056         ifp->if_init = bge_init;
2057         ifp->if_mtu = ETHERMTU;
2058         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2059         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2060         ifq_set_ready(&ifp->if_snd);
2061
2062         /*
2063          * 5700 B0 chips do not support checksumming correctly due
2064          * to hardware bugs.
2065          */
2066         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2067                 ifp->if_capabilities |= IFCAP_HWCSUM;
2068                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2069         }
2070         ifp->if_capenable = ifp->if_capabilities;
2071
2072         /*
2073          * Figure out what sort of media we have by checking the
2074          * hardware config word in the first 32k of NIC internal memory,
2075          * or fall back to examining the EEPROM if necessary.
2076          * Note: on some BCM5700 cards, this value appears to be unset.
2077          * If that's the case, we have to rely on identifying the NIC
2078          * by its PCI subsystem ID, as we do below for the SysKonnect
2079          * SK-9D41.
2080          */
2081         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2082                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2083         else {
2084                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2085                                     sizeof(hwcfg))) {
2086                         device_printf(dev, "failed to read EEPROM\n");
2087                         error = ENXIO;
2088                         goto fail;
2089                 }
2090                 hwcfg = ntohl(hwcfg);
2091         }
2092
2093         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2094                 sc->bge_flags |= BGE_FLAG_TBI;
2095
2096         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2097         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
2098                 sc->bge_flags |= BGE_FLAG_TBI;
2099
2100         if (sc->bge_flags & BGE_FLAG_TBI) {
2101                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2102                     bge_ifmedia_upd, bge_ifmedia_sts);
2103                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2104                 ifmedia_add(&sc->bge_ifmedia,
2105                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2106                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2107                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2108                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2109         } else {
2110                 /*
2111                  * Do transceiver setup.
2112                  */
2113                 if (mii_phy_probe(dev, &sc->bge_miibus,
2114                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2115                         device_printf(dev, "MII without any PHY!\n");
2116                         error = ENXIO;
2117                         goto fail;
2118                 }
2119         }
2120
2121         /*
2122          * When using the BCM5701 in PCI-X mode, data corruption has
2123          * been observed in the first few bytes of some received packets.
2124          * Aligning the packet buffer in memory eliminates the corruption.
2125          * Unfortunately, this misaligns the packet payloads.  On platforms
2126          * which do not support unaligned accesses, we will realign the
2127          * payloads by copying the received packets.
2128          */
2129         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2130             (sc->bge_flags & BGE_FLAG_PCIX))
2131                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2132
2133         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2134             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2135                 sc->bge_link_upd = bge_bcm5700_link_upd;
2136                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2137         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2138                 sc->bge_link_upd = bge_tbi_link_upd;
2139                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2140         } else {
2141                 sc->bge_link_upd = bge_copper_link_upd;
2142                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2143         }
2144
2145         /*
2146          * Create sysctl nodes.
2147          */
2148         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2149         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2150                                               SYSCTL_STATIC_CHILDREN(_hw),
2151                                               OID_AUTO,
2152                                               device_get_nameunit(dev),
2153                                               CTLFLAG_RD, 0, "");
2154         if (sc->bge_sysctl_tree == NULL) {
2155                 device_printf(dev, "can't add sysctl node\n");
2156                 error = ENXIO;
2157                 goto fail;
2158         }
2159
2160         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2161                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2162                         OID_AUTO, "rx_coal_ticks",
2163                         CTLTYPE_INT | CTLFLAG_RW,
2164                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2165                         "Receive coalescing ticks (usec).");
2166         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2167                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2168                         OID_AUTO, "tx_coal_ticks",
2169                         CTLTYPE_INT | CTLFLAG_RW,
2170                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2171                         "Transmit coalescing ticks (usec).");
2172         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2173                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2174                         OID_AUTO, "rx_max_coal_bds",
2175                         CTLTYPE_INT | CTLFLAG_RW,
2176                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2177                         "Receive max coalesced BD count.");
2178         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2179                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2180                         OID_AUTO, "tx_max_coal_bds",
2181                         CTLTYPE_INT | CTLFLAG_RW,
2182                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2183                         "Transmit max coalesced BD count.");
2184
2185         if (sc->bge_flags & BGE_FLAG_PCIE) {
2186                 /*
2187                  * A common design characteristic for many Broadcom
2188                  * client controllers is that they only support a
2189                  * single outstanding DMA read operation on the PCIe
2190                  * bus. This means that it will take twice as long to
2191                  * fetch a TX frame that is split into header and
2192                  * payload buffers as it does to fetch a single,
2193                  * contiguous TX frame (2 reads vs. 1 read). For these
2194                  * controllers, coalescing buffers to reduce the number
2195                  * of memory reads is effective way to get maximum
2196                  * performance(about 940Mbps).  Without collapsing TX
2197                  * buffers the maximum TCP bulk transfer performance
2198                  * is about 850Mbps. However forcing coalescing mbufs
2199                  * consumes a lot of CPU cycles, so leave it off by
2200                  * default.
2201                  */
2202                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2203                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2204                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2205                                &sc->bge_force_defrag, 0,
2206                                "Force defragment on TX path");
2207         }
2208
2209         /*
2210          * Call MI attach routine.
2211          */
2212         ether_ifattach(ifp, ether_addr, NULL);
2213
2214         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2215                                bge_intr, sc, &sc->bge_intrhand, 
2216                                ifp->if_serializer);
2217         if (error) {
2218                 ether_ifdetach(ifp);
2219                 device_printf(dev, "couldn't set up irq\n");
2220                 goto fail;
2221         }
2222
2223         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2224         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2225
2226         return(0);
2227 fail:
2228         bge_detach(dev);
2229         return(error);
2230 }
2231
2232 static int
2233 bge_detach(device_t dev)
2234 {
2235         struct bge_softc *sc = device_get_softc(dev);
2236
2237         if (device_is_attached(dev)) {
2238                 struct ifnet *ifp = &sc->arpcom.ac_if;
2239
2240                 lwkt_serialize_enter(ifp->if_serializer);
2241                 bge_stop(sc);
2242                 bge_reset(sc);
2243                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2244                 lwkt_serialize_exit(ifp->if_serializer);
2245
2246                 ether_ifdetach(ifp);
2247         }
2248
2249         if (sc->bge_flags & BGE_FLAG_TBI)
2250                 ifmedia_removeall(&sc->bge_ifmedia);
2251         if (sc->bge_miibus)
2252                 device_delete_child(dev, sc->bge_miibus);
2253         bus_generic_detach(dev);
2254
2255         if (sc->bge_irq != NULL)
2256                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2257
2258         if (sc->bge_res != NULL)
2259                 bus_release_resource(dev, SYS_RES_MEMORY,
2260                     BGE_PCI_BAR0, sc->bge_res);
2261
2262         if (sc->bge_sysctl_tree != NULL)
2263                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2264
2265         bge_dma_free(sc);
2266
2267         return 0;
2268 }
2269
2270 static void
2271 bge_reset(struct bge_softc *sc)
2272 {
2273         device_t dev;
2274         uint32_t cachesize, command, pcistate, reset;
2275         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2276         int i, val = 0;
2277
2278         dev = sc->bge_dev;
2279
2280         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2281             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2282                 if (sc->bge_flags & BGE_FLAG_PCIE)
2283                         write_op = bge_writemem_direct;
2284                 else
2285                         write_op = bge_writemem_ind;
2286         } else {
2287                 write_op = bge_writereg_ind;
2288         }
2289
2290         /* Save some important PCI state. */
2291         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2292         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2293         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2294
2295         pci_write_config(dev, BGE_PCI_MISC_CTL,
2296             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2297             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2298
2299         /* Disable fastboot on controllers that support it. */
2300         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2301             BGE_IS_5755_PLUS(sc)) {
2302                 if (bootverbose)
2303                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2304                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2305         }
2306
2307         /*
2308          * Write the magic number to SRAM at offset 0xB50.
2309          * When firmware finishes its initialization it will
2310          * write ~BGE_MAGIC_NUMBER to the same location.
2311          */
2312         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2313
2314         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2315
2316         /* XXX: Broadcom Linux driver. */
2317         if (sc->bge_flags & BGE_FLAG_PCIE) {
2318                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2319                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2320                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2321                         /* Prevent PCIE link training during global reset */
2322                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2323                         reset |= (1<<29);
2324                 }
2325         }
2326
2327         /* 
2328          * Set GPHY Power Down Override to leave GPHY
2329          * powered up in D0 uninitialized.
2330          */
2331         if (BGE_IS_5705_PLUS(sc))
2332                 reset |= 0x04000000;
2333
2334         /* Issue global reset */
2335         write_op(sc, BGE_MISC_CFG, reset);
2336
2337         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2338                 uint32_t status, ctrl;
2339
2340                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2341                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2342                     status | BGE_VCPU_STATUS_DRV_RESET);
2343                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2344                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2345                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2346         }
2347
2348         DELAY(1000);
2349
2350         /* XXX: Broadcom Linux driver. */
2351         if (sc->bge_flags & BGE_FLAG_PCIE) {
2352                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2353                         uint32_t v;
2354
2355                         DELAY(500000); /* wait for link training to complete */
2356                         v = pci_read_config(dev, 0xc4, 4);
2357                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2358                 }
2359                 /*
2360                  * Set PCIE max payload size to 128 bytes and
2361                  * clear error status.
2362                  */
2363                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2364         }
2365
2366         /* Reset some of the PCI state that got zapped by reset */
2367         pci_write_config(dev, BGE_PCI_MISC_CTL,
2368             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2369             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2370         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2371         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2372         write_op(sc, BGE_MISC_CFG, (65 << 1));
2373
2374         /*
2375          * Disable PCI-X relaxed ordering to ensure status block update
2376          * comes first then packet buffer DMA. Otherwise driver may
2377          * read stale status block.
2378          */
2379         if (sc->bge_flags & BGE_FLAG_PCIX) {
2380                 uint16_t devctl;
2381
2382                 devctl = pci_read_config(dev,
2383                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2384                 devctl &= ~PCIXM_COMMAND_ERO;
2385                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2386                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2387                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2388                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2389                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2390                             PCIXM_COMMAND_MAX_READ);
2391                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2392                 }
2393                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2394                     devctl, 2);
2395         }
2396
2397         /* Enable memory arbiter. */
2398         if (BGE_IS_5714_FAMILY(sc)) {
2399                 uint32_t val;
2400
2401                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2402                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2403         } else {
2404                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2405         }
2406
2407         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2408                 for (i = 0; i < BGE_TIMEOUT; i++) {
2409                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2410                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2411                                 break;
2412                         DELAY(100);
2413                 }
2414                 if (i == BGE_TIMEOUT) {
2415                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2416                         return;
2417                 }
2418         } else {
2419                 /*
2420                  * Poll until we see the 1's complement of the magic number.
2421                  * This indicates that the firmware initialization
2422                  * is complete.
2423                  */
2424                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2425                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2426                         if (val == ~BGE_MAGIC_NUMBER)
2427                                 break;
2428                         DELAY(10);
2429                 }
2430                 if (i == BGE_FIRMWARE_TIMEOUT) {
2431                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2432                                   "timed out, found 0x%08x\n", val);
2433                         return;
2434                 }
2435         }
2436
2437         /*
2438          * XXX Wait for the value of the PCISTATE register to
2439          * return to its original pre-reset state. This is a
2440          * fairly good indicator of reset completion. If we don't
2441          * wait for the reset to fully complete, trying to read
2442          * from the device's non-PCI registers may yield garbage
2443          * results.
2444          */
2445         for (i = 0; i < BGE_TIMEOUT; i++) {
2446                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2447                         break;
2448                 DELAY(10);
2449         }
2450
2451         if (sc->bge_flags & BGE_FLAG_PCIE) {
2452                 reset = bge_readmem_ind(sc, 0x7c00);
2453                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2454         }
2455
2456         /* Fix up byte swapping */
2457         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2458             BGE_MODECTL_BYTESWAP_DATA);
2459
2460         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2461
2462         /*
2463          * The 5704 in TBI mode apparently needs some special
2464          * adjustment to insure the SERDES drive level is set
2465          * to 1.2V.
2466          */
2467         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2468             (sc->bge_flags & BGE_FLAG_TBI)) {
2469                 uint32_t serdescfg;
2470
2471                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2472                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2473                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2474         }
2475
2476         /* XXX: Broadcom Linux driver. */
2477         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2478             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2479                 uint32_t v;
2480
2481                 v = CSR_READ_4(sc, 0x7c00);
2482                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2483         }
2484
2485         DELAY(10000);
2486 }
2487
2488 /*
2489  * Frame reception handling. This is called if there's a frame
2490  * on the receive return list.
2491  *
2492  * Note: we have to be able to handle two possibilities here:
2493  * 1) the frame is from the jumbo recieve ring
2494  * 2) the frame is from the standard receive ring
2495  */
2496
2497 static void
2498 bge_rxeof(struct bge_softc *sc)
2499 {
2500         struct ifnet *ifp;
2501         int stdcnt = 0, jumbocnt = 0;
2502
2503         if (sc->bge_rx_saved_considx ==
2504             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2505                 return;
2506
2507         ifp = &sc->arpcom.ac_if;
2508
2509         while (sc->bge_rx_saved_considx !=
2510                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2511                 struct bge_rx_bd        *cur_rx;
2512                 uint32_t                rxidx;
2513                 struct mbuf             *m = NULL;
2514                 uint16_t                vlan_tag = 0;
2515                 int                     have_tag = 0;
2516
2517                 cur_rx =
2518             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2519
2520                 rxidx = cur_rx->bge_idx;
2521                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2522                 logif(rx_pkt);
2523
2524                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2525                         have_tag = 1;
2526                         vlan_tag = cur_rx->bge_vlan_tag;
2527                 }
2528
2529                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2530                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2531                         jumbocnt++;
2532
2533                         if (rxidx != sc->bge_jumbo) {
2534                                 ifp->if_ierrors++;
2535                                 if_printf(ifp, "sw jumbo index(%d) "
2536                                     "and hw jumbo index(%d) mismatch, drop!\n",
2537                                     sc->bge_jumbo, rxidx);
2538                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2539                                 continue;
2540                         }
2541
2542                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2543                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2544                                 ifp->if_ierrors++;
2545                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2546                                 continue;
2547                         }
2548                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2549                                 ifp->if_ierrors++;
2550                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2551                                 continue;
2552                         }
2553                 } else {
2554                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2555                         stdcnt++;
2556
2557                         if (rxidx != sc->bge_std) {
2558                                 ifp->if_ierrors++;
2559                                 if_printf(ifp, "sw std index(%d) "
2560                                     "and hw std index(%d) mismatch, drop!\n",
2561                                     sc->bge_std, rxidx);
2562                                 bge_setup_rxdesc_std(sc, rxidx);
2563                                 continue;
2564                         }
2565
2566                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2567                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2568                                 ifp->if_ierrors++;
2569                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2570                                 continue;
2571                         }
2572                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2573                                 ifp->if_ierrors++;
2574                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2575                                 continue;
2576                         }
2577                 }
2578
2579                 ifp->if_ipackets++;
2580 #if !defined(__i386__) && !defined(__x86_64__)
2581                 /*
2582                  * The x86 allows unaligned accesses, but for other
2583                  * platforms we must make sure the payload is aligned.
2584                  */
2585                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2586                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2587                             cur_rx->bge_len);
2588                         m->m_data += ETHER_ALIGN;
2589                 }
2590 #endif
2591                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2592                 m->m_pkthdr.rcvif = ifp;
2593
2594                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2595                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2596                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2597                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2598                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2599                         }
2600                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2601                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2602                                 m->m_pkthdr.csum_data =
2603                                         cur_rx->bge_tcp_udp_csum;
2604                                 m->m_pkthdr.csum_flags |=
2605                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2606                         }
2607                 }
2608
2609                 /*
2610                  * If we received a packet with a vlan tag, pass it
2611                  * to vlan_input() instead of ether_input().
2612                  */
2613                 if (have_tag) {
2614                         m->m_flags |= M_VLANTAG;
2615                         m->m_pkthdr.ether_vlantag = vlan_tag;
2616                         have_tag = vlan_tag = 0;
2617                 }
2618                 ifp->if_input(ifp, m);
2619         }
2620
2621         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2622         if (stdcnt)
2623                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2624         if (jumbocnt)
2625                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2626 }
2627
2628 static void
2629 bge_txeof(struct bge_softc *sc)
2630 {
2631         struct bge_tx_bd *cur_tx = NULL;
2632         struct ifnet *ifp;
2633
2634         if (sc->bge_tx_saved_considx ==
2635             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2636                 return;
2637
2638         ifp = &sc->arpcom.ac_if;
2639
2640         /*
2641          * Go through our tx ring and free mbufs for those
2642          * frames that have been sent.
2643          */
2644         while (sc->bge_tx_saved_considx !=
2645                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2646                 uint32_t idx = 0;
2647
2648                 idx = sc->bge_tx_saved_considx;
2649                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2650                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2651                         ifp->if_opackets++;
2652                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2653                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2654                             sc->bge_cdata.bge_tx_dmamap[idx]);
2655                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2656                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2657                 }
2658                 sc->bge_txcnt--;
2659                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2660                 logif(tx_pkt);
2661         }
2662
2663         if (cur_tx != NULL &&
2664             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2665             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2666                 ifp->if_flags &= ~IFF_OACTIVE;
2667
2668         if (sc->bge_txcnt == 0)
2669                 ifp->if_timer = 0;
2670
2671         if (!ifq_is_empty(&ifp->if_snd))
2672                 if_devstart(ifp);
2673 }
2674
2675 #ifdef DEVICE_POLLING
2676
2677 static void
2678 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2679 {
2680         struct bge_softc *sc = ifp->if_softc;
2681         uint32_t status;
2682
2683         switch(cmd) {
2684         case POLL_REGISTER:
2685                 bge_disable_intr(sc);
2686                 break;
2687         case POLL_DEREGISTER:
2688                 bge_enable_intr(sc);
2689                 break;
2690         case POLL_AND_CHECK_STATUS:
2691                 /*
2692                  * Process link state changes.
2693                  */
2694                 status = CSR_READ_4(sc, BGE_MAC_STS);
2695                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2696                         sc->bge_link_evt = 0;
2697                         sc->bge_link_upd(sc, status);
2698                 }
2699                 /* fall through */
2700         case POLL_ONLY:
2701                 if (ifp->if_flags & IFF_RUNNING) {
2702                         bge_rxeof(sc);
2703                         bge_txeof(sc);
2704                 }
2705                 break;
2706         }
2707 }
2708
2709 #endif
2710
2711 static void
2712 bge_intr(void *xsc)
2713 {
2714         struct bge_softc *sc = xsc;
2715         struct ifnet *ifp = &sc->arpcom.ac_if;
2716         uint32_t status;
2717
2718         logif(intr);
2719
2720         /*
2721          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2722          * disable interrupts by writing nonzero like we used to, since with
2723          * our current organization this just gives complications and
2724          * pessimizations for re-enabling interrupts.  We used to have races
2725          * instead of the necessary complications.  Disabling interrupts
2726          * would just reduce the chance of a status update while we are
2727          * running (by switching to the interrupt-mode coalescence
2728          * parameters), but this chance is already very low so it is more
2729          * efficient to get another interrupt than prevent it.
2730          *
2731          * We do the ack first to ensure another interrupt if there is a
2732          * status update after the ack.  We don't check for the status
2733          * changing later because it is more efficient to get another
2734          * interrupt than prevent it, not quite as above (not checking is
2735          * a smaller optimization than not toggling the interrupt enable,
2736          * since checking doesn't involve PCI accesses and toggling require
2737          * the status check).  So toggling would probably be a pessimization
2738          * even with MSI.  It would only be needed for using a task queue.
2739          */
2740         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2741
2742         /*
2743          * Process link state changes.
2744          */
2745         status = CSR_READ_4(sc, BGE_MAC_STS);
2746         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2747                 sc->bge_link_evt = 0;
2748                 sc->bge_link_upd(sc, status);
2749         }
2750
2751         if (ifp->if_flags & IFF_RUNNING) {
2752                 /* Check RX return ring producer/consumer */
2753                 bge_rxeof(sc);
2754
2755                 /* Check TX ring producer/consumer */
2756                 bge_txeof(sc);
2757         }
2758
2759         if (sc->bge_coal_chg)
2760                 bge_coal_change(sc);
2761 }
2762
2763 static void
2764 bge_tick(void *xsc)
2765 {
2766         struct bge_softc *sc = xsc;
2767         struct ifnet *ifp = &sc->arpcom.ac_if;
2768
2769         lwkt_serialize_enter(ifp->if_serializer);
2770
2771         if (BGE_IS_5705_PLUS(sc))
2772                 bge_stats_update_regs(sc);
2773         else
2774                 bge_stats_update(sc);
2775
2776         if (sc->bge_flags & BGE_FLAG_TBI) {
2777                 /*
2778                  * Since in TBI mode auto-polling can't be used we should poll
2779                  * link status manually. Here we register pending link event
2780                  * and trigger interrupt.
2781                  */
2782                 sc->bge_link_evt++;
2783                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2784         } else if (!sc->bge_link) {
2785                 mii_tick(device_get_softc(sc->bge_miibus));
2786         }
2787
2788         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2789
2790         lwkt_serialize_exit(ifp->if_serializer);
2791 }
2792
2793 static void
2794 bge_stats_update_regs(struct bge_softc *sc)
2795 {
2796         struct ifnet *ifp = &sc->arpcom.ac_if;
2797         struct bge_mac_stats_regs stats;
2798         uint32_t *s;
2799         int i;
2800
2801         s = (uint32_t *)&stats;
2802         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2803                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2804                 s++;
2805         }
2806
2807         ifp->if_collisions +=
2808            (stats.dot3StatsSingleCollisionFrames +
2809            stats.dot3StatsMultipleCollisionFrames +
2810            stats.dot3StatsExcessiveCollisions +
2811            stats.dot3StatsLateCollisions) -
2812            ifp->if_collisions;
2813 }
2814
2815 static void
2816 bge_stats_update(struct bge_softc *sc)
2817 {
2818         struct ifnet *ifp = &sc->arpcom.ac_if;
2819         bus_size_t stats;
2820
2821         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2822
2823 #define READ_STAT(sc, stats, stat)      \
2824         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2825
2826         ifp->if_collisions +=
2827            (READ_STAT(sc, stats,
2828                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2829             READ_STAT(sc, stats,
2830                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2831             READ_STAT(sc, stats,
2832                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2833             READ_STAT(sc, stats,
2834                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2835            ifp->if_collisions;
2836
2837 #undef READ_STAT
2838
2839 #ifdef notdef
2840         ifp->if_collisions +=
2841            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2842            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2843            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2844            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2845            ifp->if_collisions;
2846 #endif
2847 }
2848
2849 /*
2850  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2851  * pointers to descriptors.
2852  */
2853 static int
2854 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2855 {
2856         struct bge_tx_bd *d = NULL;
2857         uint16_t csum_flags = 0;
2858         bus_dma_segment_t segs[BGE_NSEG_NEW];
2859         bus_dmamap_t map;
2860         int error, maxsegs, nsegs, idx, i;
2861         struct mbuf *m_head = *m_head0;
2862
2863         if (m_head->m_pkthdr.csum_flags) {
2864                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2865                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2866                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2867                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2868                 if (m_head->m_flags & M_LASTFRAG)
2869                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2870                 else if (m_head->m_flags & M_FRAG)
2871                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2872         }
2873
2874         idx = *txidx;
2875         map = sc->bge_cdata.bge_tx_dmamap[idx];
2876
2877         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2878         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2879                 ("not enough segments %d", maxsegs));
2880
2881         if (maxsegs > BGE_NSEG_NEW)
2882                 maxsegs = BGE_NSEG_NEW;
2883
2884         /*
2885          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2886          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2887          * but when such padded frames employ the bge IP/TCP checksum
2888          * offload, the hardware checksum assist gives incorrect results
2889          * (possibly from incorporating its own padding into the UDP/TCP
2890          * checksum; who knows).  If we pad such runts with zeros, the
2891          * onboard checksum comes out correct.
2892          */
2893         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2894             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2895                 error = m_devpad(m_head, BGE_MIN_FRAME);
2896                 if (error)
2897                         goto back;
2898         }
2899
2900         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
2901             m_head->m_next != NULL) {
2902                 struct mbuf *m_new;
2903
2904                 /*
2905                  * Forcefully defragment mbuf chain to overcome hardware
2906                  * limitation which only support a single outstanding
2907                  * DMA read operation.  If it fails, keep moving on using
2908                  * the original mbuf chain.
2909                  */
2910                 m_new = m_defrag(m_head, MB_DONTWAIT);
2911                 if (m_new != NULL)
2912                         *m_head0 = m_head = m_new;
2913         }
2914
2915         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2916                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2917         if (error)
2918                 goto back;
2919
2920         m_head = *m_head0;
2921         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2922
2923         for (i = 0; ; i++) {
2924                 d = &sc->bge_ldata.bge_tx_ring[idx];
2925
2926                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2927                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2928                 d->bge_len = segs[i].ds_len;
2929                 d->bge_flags = csum_flags;
2930
2931                 if (i == nsegs - 1)
2932                         break;
2933                 BGE_INC(idx, BGE_TX_RING_CNT);
2934         }
2935         /* Mark the last segment as end of packet... */
2936         d->bge_flags |= BGE_TXBDFLAG_END;
2937
2938         /* Set vlan tag to the first segment of the packet. */
2939         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2940         if (m_head->m_flags & M_VLANTAG) {
2941                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2942                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2943         } else {
2944                 d->bge_vlan_tag = 0;
2945         }
2946
2947         /*
2948          * Insure that the map for this transmission is placed at
2949          * the array index of the last descriptor in this chain.
2950          */
2951         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2952         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2953         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2954         sc->bge_txcnt += nsegs;
2955
2956         BGE_INC(idx, BGE_TX_RING_CNT);
2957         *txidx = idx;
2958 back:
2959         if (error) {
2960                 m_freem(*m_head0);
2961                 *m_head0 = NULL;
2962         }
2963         return error;
2964 }
2965
2966 /*
2967  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2968  * to the mbuf data regions directly in the transmit descriptors.
2969  */
2970 static void
2971 bge_start(struct ifnet *ifp)
2972 {
2973         struct bge_softc *sc = ifp->if_softc;
2974         struct mbuf *m_head = NULL;
2975         uint32_t prodidx;
2976         int need_trans;
2977
2978         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2979                 return;
2980
2981         prodidx = sc->bge_tx_prodidx;
2982
2983         need_trans = 0;
2984         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2985                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2986                 if (m_head == NULL)
2987                         break;
2988
2989                 /*
2990                  * XXX
2991                  * The code inside the if() block is never reached since we
2992                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2993                  * requests to checksum TCP/UDP in a fragmented packet.
2994                  * 
2995                  * XXX
2996                  * safety overkill.  If this is a fragmented packet chain
2997                  * with delayed TCP/UDP checksums, then only encapsulate
2998                  * it if we have enough descriptors to handle the entire
2999                  * chain at once.
3000                  * (paranoia -- may not actually be needed)
3001                  */
3002                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3003                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3004                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3005                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3006                                 ifp->if_flags |= IFF_OACTIVE;
3007                                 ifq_prepend(&ifp->if_snd, m_head);
3008                                 break;
3009                         }
3010                 }
3011
3012                 /*
3013                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3014                  * descriptors of the end of the ring.  Also make
3015                  * sure there are BGE_NSEG_SPARE descriptors for
3016                  * jumbo buffers' defragmentation.
3017                  */
3018                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3019                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3020                         ifp->if_flags |= IFF_OACTIVE;
3021                         ifq_prepend(&ifp->if_snd, m_head);
3022                         break;
3023                 }
3024
3025                 /*
3026                  * Pack the data into the transmit ring. If we
3027                  * don't have room, set the OACTIVE flag and wait
3028                  * for the NIC to drain the ring.
3029                  */
3030                 if (bge_encap(sc, &m_head, &prodidx)) {
3031                         ifp->if_flags |= IFF_OACTIVE;
3032                         ifp->if_oerrors++;
3033                         break;
3034                 }
3035                 need_trans = 1;
3036
3037                 ETHER_BPF_MTAP(ifp, m_head);
3038         }
3039
3040         if (!need_trans)
3041                 return;
3042
3043         /* Transmit */
3044         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3045         /* 5700 b2 errata */
3046         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3047                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3048
3049         sc->bge_tx_prodidx = prodidx;
3050
3051         /*
3052          * Set a timeout in case the chip goes out to lunch.
3053          */
3054         ifp->if_timer = 5;
3055 }
3056
3057 static void
3058 bge_init(void *xsc)
3059 {
3060         struct bge_softc *sc = xsc;
3061         struct ifnet *ifp = &sc->arpcom.ac_if;
3062         uint16_t *m;
3063
3064         ASSERT_SERIALIZED(ifp->if_serializer);
3065
3066         if (ifp->if_flags & IFF_RUNNING)
3067                 return;
3068
3069         /* Cancel pending I/O and flush buffers. */
3070         bge_stop(sc);
3071         bge_reset(sc);
3072         bge_chipinit(sc);
3073
3074         /*
3075          * Init the various state machines, ring
3076          * control blocks and firmware.
3077          */
3078         if (bge_blockinit(sc)) {
3079                 if_printf(ifp, "initialization failure\n");
3080                 bge_stop(sc);
3081                 return;
3082         }
3083
3084         /* Specify MTU. */
3085         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3086             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3087
3088         /* Load our MAC address. */
3089         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3090         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3091         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3092
3093         /* Enable or disable promiscuous mode as needed. */
3094         bge_setpromisc(sc);
3095
3096         /* Program multicast filter. */
3097         bge_setmulti(sc);
3098
3099         /* Init RX ring. */
3100         if (bge_init_rx_ring_std(sc)) {
3101                 if_printf(ifp, "RX ring initialization failed\n");
3102                 bge_stop(sc);
3103                 return;
3104         }
3105
3106         /*
3107          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3108          * memory to insure that the chip has in fact read the first
3109          * entry of the ring.
3110          */
3111         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3112                 uint32_t                v, i;
3113                 for (i = 0; i < 10; i++) {
3114                         DELAY(20);
3115                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3116                         if (v == (MCLBYTES - ETHER_ALIGN))
3117                                 break;
3118                 }
3119                 if (i == 10)
3120                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3121         }
3122
3123         /* Init jumbo RX ring. */
3124         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3125                 if (bge_init_rx_ring_jumbo(sc)) {
3126                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3127                         bge_stop(sc);
3128                         return;
3129                 }
3130         }
3131
3132         /* Init our RX return ring index */
3133         sc->bge_rx_saved_considx = 0;
3134
3135         /* Init TX ring. */
3136         bge_init_tx_ring(sc);
3137
3138         /* Turn on transmitter */
3139         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3140
3141         /* Turn on receiver */
3142         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3143
3144         /* Tell firmware we're alive. */
3145         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3146
3147         /* Enable host interrupts if polling(4) is not enabled. */
3148         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3149 #ifdef DEVICE_POLLING
3150         if (ifp->if_flags & IFF_POLLING)
3151                 bge_disable_intr(sc);
3152         else
3153 #endif
3154         bge_enable_intr(sc);
3155
3156         bge_ifmedia_upd(ifp);
3157
3158         ifp->if_flags |= IFF_RUNNING;
3159         ifp->if_flags &= ~IFF_OACTIVE;
3160
3161         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3162 }
3163
3164 /*
3165  * Set media options.
3166  */
3167 static int
3168 bge_ifmedia_upd(struct ifnet *ifp)
3169 {
3170         struct bge_softc *sc = ifp->if_softc;
3171
3172         /* If this is a 1000baseX NIC, enable the TBI port. */
3173         if (sc->bge_flags & BGE_FLAG_TBI) {
3174                 struct ifmedia *ifm = &sc->bge_ifmedia;
3175
3176                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3177                         return(EINVAL);
3178
3179                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3180                 case IFM_AUTO:
3181                         /*
3182                          * The BCM5704 ASIC appears to have a special
3183                          * mechanism for programming the autoneg
3184                          * advertisement registers in TBI mode.
3185                          */
3186                         if (!bge_fake_autoneg &&
3187                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3188                                 uint32_t sgdig;
3189
3190                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3191                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3192                                 sgdig |= BGE_SGDIGCFG_AUTO |
3193                                          BGE_SGDIGCFG_PAUSE_CAP |
3194                                          BGE_SGDIGCFG_ASYM_PAUSE;
3195                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3196                                             sgdig | BGE_SGDIGCFG_SEND);
3197                                 DELAY(5);
3198                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3199                         }
3200                         break;
3201                 case IFM_1000_SX:
3202                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3203                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3204                                     BGE_MACMODE_HALF_DUPLEX);
3205                         } else {
3206                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3207                                     BGE_MACMODE_HALF_DUPLEX);
3208                         }
3209                         break;
3210                 default:
3211                         return(EINVAL);
3212                 }
3213         } else {
3214                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3215
3216                 sc->bge_link_evt++;
3217                 sc->bge_link = 0;
3218                 if (mii->mii_instance) {
3219                         struct mii_softc *miisc;
3220
3221                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3222                                 mii_phy_reset(miisc);
3223                 }
3224                 mii_mediachg(mii);
3225         }
3226         return(0);
3227 }
3228
3229 /*
3230  * Report current media status.
3231  */
3232 static void
3233 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3234 {
3235         struct bge_softc *sc = ifp->if_softc;
3236
3237         if (sc->bge_flags & BGE_FLAG_TBI) {
3238                 ifmr->ifm_status = IFM_AVALID;
3239                 ifmr->ifm_active = IFM_ETHER;
3240                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3241                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3242                         ifmr->ifm_status |= IFM_ACTIVE;
3243                 } else {
3244                         ifmr->ifm_active |= IFM_NONE;
3245                         return;
3246                 }
3247
3248                 ifmr->ifm_active |= IFM_1000_SX;
3249                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3250                         ifmr->ifm_active |= IFM_HDX;    
3251                 else
3252                         ifmr->ifm_active |= IFM_FDX;
3253         } else {
3254                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3255
3256                 mii_pollstat(mii);
3257                 ifmr->ifm_active = mii->mii_media_active;
3258                 ifmr->ifm_status = mii->mii_media_status;
3259         }
3260 }
3261
3262 static int
3263 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3264 {
3265         struct bge_softc *sc = ifp->if_softc;
3266         struct ifreq *ifr = (struct ifreq *)data;
3267         int mask, error = 0;
3268
3269         ASSERT_SERIALIZED(ifp->if_serializer);
3270
3271         switch (command) {
3272         case SIOCSIFMTU:
3273                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3274                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3275                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3276                         error = EINVAL;
3277                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3278                         ifp->if_mtu = ifr->ifr_mtu;
3279                         ifp->if_flags &= ~IFF_RUNNING;
3280                         bge_init(sc);
3281                 }
3282                 break;
3283         case SIOCSIFFLAGS:
3284                 if (ifp->if_flags & IFF_UP) {
3285                         if (ifp->if_flags & IFF_RUNNING) {
3286                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3287
3288                                 /*
3289                                  * If only the state of the PROMISC flag
3290                                  * changed, then just use the 'set promisc
3291                                  * mode' command instead of reinitializing
3292                                  * the entire NIC. Doing a full re-init
3293                                  * means reloading the firmware and waiting
3294                                  * for it to start up, which may take a
3295                                  * second or two.  Similarly for ALLMULTI.
3296                                  */
3297                                 if (mask & IFF_PROMISC)
3298                                         bge_setpromisc(sc);
3299                                 if (mask & IFF_ALLMULTI)
3300                                         bge_setmulti(sc);
3301                         } else {
3302                                 bge_init(sc);
3303                         }
3304                 } else {
3305                         if (ifp->if_flags & IFF_RUNNING)
3306                                 bge_stop(sc);
3307                 }
3308                 sc->bge_if_flags = ifp->if_flags;
3309                 break;
3310         case SIOCADDMULTI:
3311         case SIOCDELMULTI:
3312                 if (ifp->if_flags & IFF_RUNNING)
3313                         bge_setmulti(sc);
3314                 break;
3315         case SIOCSIFMEDIA:
3316         case SIOCGIFMEDIA:
3317                 if (sc->bge_flags & BGE_FLAG_TBI) {
3318                         error = ifmedia_ioctl(ifp, ifr,
3319                             &sc->bge_ifmedia, command);
3320                 } else {
3321                         struct mii_data *mii;
3322
3323                         mii = device_get_softc(sc->bge_miibus);
3324                         error = ifmedia_ioctl(ifp, ifr,
3325                                               &mii->mii_media, command);
3326                 }
3327                 break;
3328         case SIOCSIFCAP:
3329                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3330                 if (mask & IFCAP_HWCSUM) {
3331                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3332                         if (IFCAP_HWCSUM & ifp->if_capenable)
3333                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3334                         else
3335                                 ifp->if_hwassist = 0;
3336                 }
3337                 break;
3338         default:
3339                 error = ether_ioctl(ifp, command, data);
3340                 break;
3341         }
3342         return error;
3343 }
3344
3345 static void
3346 bge_watchdog(struct ifnet *ifp)
3347 {
3348         struct bge_softc *sc = ifp->if_softc;
3349
3350         if_printf(ifp, "watchdog timeout -- resetting\n");
3351
3352         ifp->if_flags &= ~IFF_RUNNING;
3353         bge_init(sc);
3354
3355         ifp->if_oerrors++;
3356
3357         if (!ifq_is_empty(&ifp->if_snd))
3358                 if_devstart(ifp);
3359 }
3360
3361 /*
3362  * Stop the adapter and free any mbufs allocated to the
3363  * RX and TX lists.
3364  */
3365 static void
3366 bge_stop(struct bge_softc *sc)
3367 {
3368         struct ifnet *ifp = &sc->arpcom.ac_if;
3369
3370         ASSERT_SERIALIZED(ifp->if_serializer);
3371
3372         callout_stop(&sc->bge_stat_timer);
3373
3374         /*
3375          * Disable all of the receiver blocks
3376          */
3377         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3378         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3379         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3380         if (!BGE_IS_5705_PLUS(sc))
3381                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3382         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3383         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3384         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3385
3386         /*
3387          * Disable all of the transmit blocks
3388          */
3389         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3390         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3391         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3392         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3393         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3394         if (!BGE_IS_5705_PLUS(sc))
3395                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3396         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3397
3398         /*
3399          * Shut down all of the memory managers and related
3400          * state machines.
3401          */
3402         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3403         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3404         if (!BGE_IS_5705_PLUS(sc))
3405                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3406         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3407         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3408         if (!BGE_IS_5705_PLUS(sc)) {
3409                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3410                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3411         }
3412
3413         /* Disable host interrupts. */
3414         bge_disable_intr(sc);
3415
3416         /*
3417          * Tell firmware we're shutting down.
3418          */
3419         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3420
3421         /* Free the RX lists. */
3422         bge_free_rx_ring_std(sc);
3423
3424         /* Free jumbo RX list. */
3425         if (BGE_IS_JUMBO_CAPABLE(sc))
3426                 bge_free_rx_ring_jumbo(sc);
3427
3428         /* Free TX buffers. */
3429         bge_free_tx_ring(sc);
3430
3431         sc->bge_link = 0;
3432         sc->bge_coal_chg = 0;
3433
3434         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3435
3436         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3437         ifp->if_timer = 0;
3438 }
3439
3440 /*
3441  * Stop all chip I/O so that the kernel's probe routines don't
3442  * get confused by errant DMAs when rebooting.
3443  */
3444 static void
3445 bge_shutdown(device_t dev)
3446 {
3447         struct bge_softc *sc = device_get_softc(dev);
3448         struct ifnet *ifp = &sc->arpcom.ac_if;
3449
3450         lwkt_serialize_enter(ifp->if_serializer);
3451         bge_stop(sc);
3452         bge_reset(sc);
3453         lwkt_serialize_exit(ifp->if_serializer);
3454 }
3455
3456 static int
3457 bge_suspend(device_t dev)
3458 {
3459         struct bge_softc *sc = device_get_softc(dev);
3460         struct ifnet *ifp = &sc->arpcom.ac_if;
3461
3462         lwkt_serialize_enter(ifp->if_serializer);
3463         bge_stop(sc);
3464         lwkt_serialize_exit(ifp->if_serializer);
3465
3466         return 0;
3467 }
3468
3469 static int
3470 bge_resume(device_t dev)
3471 {
3472         struct bge_softc *sc = device_get_softc(dev);
3473         struct ifnet *ifp = &sc->arpcom.ac_if;
3474
3475         lwkt_serialize_enter(ifp->if_serializer);
3476
3477         if (ifp->if_flags & IFF_UP) {
3478                 bge_init(sc);
3479
3480                 if (!ifq_is_empty(&ifp->if_snd))
3481                         if_devstart(ifp);
3482         }
3483
3484         lwkt_serialize_exit(ifp->if_serializer);
3485
3486         return 0;
3487 }
3488
3489 static void
3490 bge_setpromisc(struct bge_softc *sc)
3491 {
3492         struct ifnet *ifp = &sc->arpcom.ac_if;
3493
3494         if (ifp->if_flags & IFF_PROMISC)
3495                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3496         else
3497                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3498 }
3499
3500 static void
3501 bge_dma_free(struct bge_softc *sc)
3502 {
3503         int i;
3504
3505         /* Destroy RX mbuf DMA stuffs. */
3506         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3507                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3508                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3509                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3510                 }
3511                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3512                                    sc->bge_cdata.bge_rx_tmpmap);
3513                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3514         }
3515
3516         /* Destroy TX mbuf DMA stuffs. */
3517         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3518                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3519                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3520                             sc->bge_cdata.bge_tx_dmamap[i]);
3521                 }
3522                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3523         }
3524
3525         /* Destroy standard RX ring */
3526         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3527                            sc->bge_cdata.bge_rx_std_ring_map,
3528                            sc->bge_ldata.bge_rx_std_ring);
3529
3530         if (BGE_IS_JUMBO_CAPABLE(sc))
3531                 bge_free_jumbo_mem(sc);
3532
3533         /* Destroy RX return ring */
3534         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3535                            sc->bge_cdata.bge_rx_return_ring_map,
3536                            sc->bge_ldata.bge_rx_return_ring);
3537
3538         /* Destroy TX ring */
3539         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3540                            sc->bge_cdata.bge_tx_ring_map,
3541                            sc->bge_ldata.bge_tx_ring);
3542
3543         /* Destroy status block */
3544         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3545                            sc->bge_cdata.bge_status_map,
3546                            sc->bge_ldata.bge_status_block);
3547
3548         /* Destroy statistics block */
3549         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3550                            sc->bge_cdata.bge_stats_map,
3551                            sc->bge_ldata.bge_stats);
3552
3553         /* Destroy the parent tag */
3554         if (sc->bge_cdata.bge_parent_tag != NULL)
3555                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3556 }
3557
3558 static int
3559 bge_dma_alloc(struct bge_softc *sc)
3560 {
3561         struct ifnet *ifp = &sc->arpcom.ac_if;
3562         int i, error;
3563         bus_addr_t lowaddr;
3564         bus_size_t boundary;
3565
3566         boundary = 0;
3567         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3568                 boundary = BGE_DMA_BOUNDARY_4G;
3569
3570         lowaddr = BUS_SPACE_MAXADDR;
3571         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3572                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3573
3574         /*
3575          * Allocate the parent bus DMA tag appropriate for PCI.
3576          */
3577         error = bus_dma_tag_create(NULL, 1, boundary,
3578                                    lowaddr, BUS_SPACE_MAXADDR,
3579                                    NULL, NULL,
3580                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3581                                    BUS_SPACE_MAXSIZE_32BIT,
3582                                    0, &sc->bge_cdata.bge_parent_tag);
3583         if (error) {
3584                 if_printf(ifp, "could not allocate parent dma tag\n");
3585                 return error;
3586         }
3587
3588         /*
3589          * Create DMA tag and maps for RX mbufs.
3590          */
3591         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3592                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3593                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3594                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3595                                    &sc->bge_cdata.bge_rx_mtag);
3596         if (error) {
3597                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3598                 return error;
3599         }
3600
3601         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3602                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3603         if (error) {
3604                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3605                 sc->bge_cdata.bge_rx_mtag = NULL;
3606                 return error;
3607         }
3608
3609         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3610                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3611                                           BUS_DMA_WAITOK,
3612                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3613                 if (error) {
3614                         int j;
3615
3616                         for (j = 0; j < i; ++j) {
3617                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3618                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3619                         }
3620                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3621                         sc->bge_cdata.bge_rx_mtag = NULL;
3622
3623                         if_printf(ifp, "could not create DMA map for RX\n");
3624                         return error;
3625                 }
3626         }
3627
3628         /*
3629          * Create DMA tag and maps for TX mbufs.
3630          */
3631         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3632                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3633                                    NULL, NULL,
3634                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3635                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3636                                    BUS_DMA_ONEBPAGE,
3637                                    &sc->bge_cdata.bge_tx_mtag);
3638         if (error) {
3639                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3640                 return error;
3641         }
3642
3643         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3644                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3645                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3646                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3647                 if (error) {
3648                         int j;
3649
3650                         for (j = 0; j < i; ++j) {
3651                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3652                                         sc->bge_cdata.bge_tx_dmamap[j]);
3653                         }
3654                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3655                         sc->bge_cdata.bge_tx_mtag = NULL;
3656
3657                         if_printf(ifp, "could not create DMA map for TX\n");
3658                         return error;
3659                 }
3660         }
3661
3662         /*
3663          * Create DMA stuffs for standard RX ring.
3664          */
3665         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3666                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3667                                     &sc->bge_cdata.bge_rx_std_ring_map,
3668                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3669                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3670         if (error) {
3671                 if_printf(ifp, "could not create std RX ring\n");
3672                 return error;
3673         }
3674
3675         /*
3676          * Create jumbo buffer pool.
3677          */
3678         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3679                 error = bge_alloc_jumbo_mem(sc);
3680                 if (error) {
3681                         if_printf(ifp, "could not create jumbo buffer pool\n");
3682                         return error;
3683                 }
3684         }
3685
3686         /*
3687          * Create DMA stuffs for RX return ring.
3688          */
3689         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3690                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3691                                     &sc->bge_cdata.bge_rx_return_ring_map,
3692                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3693                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3694         if (error) {
3695                 if_printf(ifp, "could not create RX ret ring\n");
3696                 return error;
3697         }
3698
3699         /*
3700          * Create DMA stuffs for TX ring.
3701          */
3702         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3703                                     &sc->bge_cdata.bge_tx_ring_tag,
3704                                     &sc->bge_cdata.bge_tx_ring_map,
3705                                     (void *)&sc->bge_ldata.bge_tx_ring,
3706                                     &sc->bge_ldata.bge_tx_ring_paddr);
3707         if (error) {
3708                 if_printf(ifp, "could not create TX ring\n");
3709                 return error;
3710         }
3711
3712         /*
3713          * Create DMA stuffs for status block.
3714          */
3715         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3716                                     &sc->bge_cdata.bge_status_tag,
3717                                     &sc->bge_cdata.bge_status_map,
3718                                     (void *)&sc->bge_ldata.bge_status_block,
3719                                     &sc->bge_ldata.bge_status_block_paddr);
3720         if (error) {
3721                 if_printf(ifp, "could not create status block\n");
3722                 return error;
3723         }
3724
3725         /*
3726          * Create DMA stuffs for statistics block.
3727          */
3728         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3729                                     &sc->bge_cdata.bge_stats_tag,
3730                                     &sc->bge_cdata.bge_stats_map,
3731                                     (void *)&sc->bge_ldata.bge_stats,
3732                                     &sc->bge_ldata.bge_stats_paddr);
3733         if (error) {
3734                 if_printf(ifp, "could not create stats block\n");
3735                 return error;
3736         }
3737         return 0;
3738 }
3739
3740 static int
3741 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3742                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3743 {
3744         bus_dmamem_t dmem;
3745         int error;
3746
3747         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3748                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3749                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3750         if (error)
3751                 return error;
3752
3753         *tag = dmem.dmem_tag;
3754         *map = dmem.dmem_map;
3755         *addr = dmem.dmem_addr;
3756         *paddr = dmem.dmem_busaddr;
3757
3758         return 0;
3759 }
3760
3761 static void
3762 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3763 {
3764         if (tag != NULL) {
3765                 bus_dmamap_unload(tag, map);
3766                 bus_dmamem_free(tag, addr, map);
3767                 bus_dma_tag_destroy(tag);
3768         }
3769 }
3770
3771 /*
3772  * Grrr. The link status word in the status block does
3773  * not work correctly on the BCM5700 rev AX and BX chips,
3774  * according to all available information. Hence, we have
3775  * to enable MII interrupts in order to properly obtain
3776  * async link changes. Unfortunately, this also means that
3777  * we have to read the MAC status register to detect link
3778  * changes, thereby adding an additional register access to
3779  * the interrupt handler.
3780  *
3781  * XXX: perhaps link state detection procedure used for
3782  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3783  */
3784 static void
3785 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3786 {
3787         struct ifnet *ifp = &sc->arpcom.ac_if;
3788         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3789
3790         mii_pollstat(mii);
3791
3792         if (!sc->bge_link &&
3793             (mii->mii_media_status & IFM_ACTIVE) &&
3794             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3795                 sc->bge_link++;
3796                 if (bootverbose)
3797                         if_printf(ifp, "link UP\n");
3798         } else if (sc->bge_link &&
3799             (!(mii->mii_media_status & IFM_ACTIVE) ||
3800             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3801                 sc->bge_link = 0;
3802                 if (bootverbose)
3803                         if_printf(ifp, "link DOWN\n");
3804         }
3805
3806         /* Clear the interrupt. */
3807         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3808         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3809         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3810 }
3811
3812 static void
3813 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3814 {
3815         struct ifnet *ifp = &sc->arpcom.ac_if;
3816
3817 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3818
3819         /*
3820          * Sometimes PCS encoding errors are detected in
3821          * TBI mode (on fiber NICs), and for some reason
3822          * the chip will signal them as link changes.
3823          * If we get a link change event, but the 'PCS
3824          * encoding error' bit in the MAC status register
3825          * is set, don't bother doing a link check.
3826          * This avoids spurious "gigabit link up" messages
3827          * that sometimes appear on fiber NICs during
3828          * periods of heavy traffic.
3829          */
3830         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3831                 if (!sc->bge_link) {
3832                         sc->bge_link++;
3833                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3834                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3835                                     BGE_MACMODE_TBI_SEND_CFGS);
3836                         }
3837                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3838
3839                         if (bootverbose)
3840                                 if_printf(ifp, "link UP\n");
3841
3842                         ifp->if_link_state = LINK_STATE_UP;
3843                         if_link_state_change(ifp);
3844                 }
3845         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3846                 if (sc->bge_link) {
3847                         sc->bge_link = 0;
3848
3849                         if (bootverbose)
3850                                 if_printf(ifp, "link DOWN\n");
3851
3852                         ifp->if_link_state = LINK_STATE_DOWN;
3853                         if_link_state_change(ifp);
3854                 }
3855         }
3856
3857 #undef PCS_ENCODE_ERR
3858
3859         /* Clear the attention. */
3860         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3861             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3862             BGE_MACSTAT_LINK_CHANGED);
3863 }
3864
3865 static void
3866 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3867 {
3868         /*
3869          * Check that the AUTOPOLL bit is set before
3870          * processing the event as a real link change.
3871          * Turning AUTOPOLL on and off in the MII read/write
3872          * functions will often trigger a link status
3873          * interrupt for no reason.
3874          */
3875         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3876                 struct ifnet *ifp = &sc->arpcom.ac_if;
3877                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3878
3879                 mii_pollstat(mii);
3880
3881                 if (!sc->bge_link &&
3882                     (mii->mii_media_status & IFM_ACTIVE) &&
3883                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3884                         sc->bge_link++;
3885                         if (bootverbose)
3886                                 if_printf(ifp, "link UP\n");
3887                 } else if (sc->bge_link &&
3888                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3889                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3890                         sc->bge_link = 0;
3891                         if (bootverbose)
3892                                 if_printf(ifp, "link DOWN\n");
3893                 }
3894         }
3895
3896         /* Clear the attention. */
3897         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3898             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3899             BGE_MACSTAT_LINK_CHANGED);
3900 }
3901
3902 static int
3903 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3904 {
3905         struct bge_softc *sc = arg1;
3906
3907         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3908                                    &sc->bge_rx_coal_ticks,
3909                                    BGE_RX_COAL_TICKS_CHG);
3910 }
3911
3912 static int
3913 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3914 {
3915         struct bge_softc *sc = arg1;
3916
3917         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3918                                    &sc->bge_tx_coal_ticks,
3919                                    BGE_TX_COAL_TICKS_CHG);
3920 }
3921
3922 static int
3923 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3924 {
3925         struct bge_softc *sc = arg1;
3926
3927         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3928                                    &sc->bge_rx_max_coal_bds,
3929                                    BGE_RX_MAX_COAL_BDS_CHG);
3930 }
3931
3932 static int
3933 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3934 {
3935         struct bge_softc *sc = arg1;
3936
3937         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3938                                    &sc->bge_tx_max_coal_bds,
3939                                    BGE_TX_MAX_COAL_BDS_CHG);
3940 }
3941
3942 static int
3943 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3944                     uint32_t coal_chg_mask)
3945 {
3946         struct bge_softc *sc = arg1;
3947         struct ifnet *ifp = &sc->arpcom.ac_if;
3948         int error = 0, v;
3949
3950         lwkt_serialize_enter(ifp->if_serializer);
3951
3952         v = *coal;
3953         error = sysctl_handle_int(oidp, &v, 0, req);
3954         if (!error && req->newptr != NULL) {
3955                 if (v < 0) {
3956                         error = EINVAL;
3957                 } else {
3958                         *coal = v;
3959                         sc->bge_coal_chg |= coal_chg_mask;
3960                 }
3961         }
3962
3963         lwkt_serialize_exit(ifp->if_serializer);
3964         return error;
3965 }
3966
3967 static void