1284baef88ad811064bc57d4dea3f57082143738
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_ifpoll.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void     igb_add_sysctl(struct igb_softc *);
142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 #ifdef IFPOLL_ENABLE
147 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
148 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
149 #endif
150
151 static void     igb_vf_init_stats(struct igb_softc *);
152 static void     igb_reset(struct igb_softc *);
153 static void     igb_update_stats_counters(struct igb_softc *);
154 static void     igb_update_vf_stats_counters(struct igb_softc *);
155 static void     igb_update_link_status(struct igb_softc *);
156 static void     igb_init_tx_unit(struct igb_softc *);
157 static void     igb_init_rx_unit(struct igb_softc *);
158
159 static void     igb_set_vlan(struct igb_softc *);
160 static void     igb_set_multi(struct igb_softc *);
161 static void     igb_set_promisc(struct igb_softc *);
162 static void     igb_disable_promisc(struct igb_softc *);
163
164 static int      igb_alloc_rings(struct igb_softc *);
165 static void     igb_free_rings(struct igb_softc *);
166 static int      igb_create_tx_ring(struct igb_tx_ring *);
167 static int      igb_create_rx_ring(struct igb_rx_ring *);
168 static void     igb_free_tx_ring(struct igb_tx_ring *);
169 static void     igb_free_rx_ring(struct igb_rx_ring *);
170 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
171 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
172 static void     igb_init_tx_ring(struct igb_tx_ring *);
173 static int      igb_init_rx_ring(struct igb_rx_ring *);
174 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
175 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
176
177 static void     igb_stop(struct igb_softc *);
178 static void     igb_init(void *);
179 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
180 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
181 static int      igb_media_change(struct ifnet *);
182 static void     igb_timer(void *);
183 static void     igb_watchdog(struct ifnet *);
184 static void     igb_start(struct ifnet *);
185 #ifdef IFPOLL_ENABLE
186 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
187 static void     igb_npoll_rx(struct ifnet *, void *, int);
188 static void     igb_npoll_tx(struct ifnet *, void *, int);
189 static void     igb_npoll_status(struct ifnet *, int);
190 #endif
191 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
192 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
193 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
194 #ifdef INVARIANTS
195 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
196                     boolean_t);
197 #endif
198
199 static void     igb_intr(void *);
200 static void     igb_intr_shared(void *);
201 static void     igb_rxeof(struct igb_rx_ring *, int);
202 static void     igb_txeof(struct igb_tx_ring *);
203 static void     igb_set_eitr(struct igb_softc *, int, int);
204 static void     igb_enable_intr(struct igb_softc *);
205 static void     igb_disable_intr(struct igb_softc *);
206 static void     igb_init_unshared_intr(struct igb_softc *);
207 static void     igb_init_intr(struct igb_softc *);
208 static int      igb_setup_intr(struct igb_softc *);
209 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
210 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
211 static void     igb_set_intr_mask(struct igb_softc *);
212 static int      igb_alloc_intr(struct igb_softc *);
213 static void     igb_free_intr(struct igb_softc *);
214 static void     igb_teardown_intr(struct igb_softc *);
215 static void     igb_msix_try_alloc(struct igb_softc *);
216 static void     igb_msix_free(struct igb_softc *, boolean_t);
217 static int      igb_msix_setup(struct igb_softc *);
218 static void     igb_msix_teardown(struct igb_softc *, int);
219 static void     igb_msix_rx(void *);
220 static void     igb_msix_tx(void *);
221 static void     igb_msix_status(void *);
222
223 /* Management and WOL Support */
224 static void     igb_get_mgmt(struct igb_softc *);
225 static void     igb_rel_mgmt(struct igb_softc *);
226 static void     igb_get_hw_control(struct igb_softc *);
227 static void     igb_rel_hw_control(struct igb_softc *);
228 static void     igb_enable_wol(device_t);
229
230 static device_method_t igb_methods[] = {
231         /* Device interface */
232         DEVMETHOD(device_probe,         igb_probe),
233         DEVMETHOD(device_attach,        igb_attach),
234         DEVMETHOD(device_detach,        igb_detach),
235         DEVMETHOD(device_shutdown,      igb_shutdown),
236         DEVMETHOD(device_suspend,       igb_suspend),
237         DEVMETHOD(device_resume,        igb_resume),
238         { 0, 0 }
239 };
240
241 static driver_t igb_driver = {
242         "igb",
243         igb_methods,
244         sizeof(struct igb_softc),
245 };
246
247 static devclass_t igb_devclass;
248
249 DECLARE_DUMMY_MODULE(if_igb);
250 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
251 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
252
253 static int      igb_rxd = IGB_DEFAULT_RXD;
254 static int      igb_txd = IGB_DEFAULT_TXD;
255 static int      igb_rxr = 0;
256 static int      igb_msi_enable = 1;
257 static int      igb_msix_enable = 1;
258 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
259 static int      igb_fc_setting = e1000_fc_full;
260
261 /*
262  * DMA Coalescing, only for i350 - default to off,
263  * this feature is for power savings
264  */
265 static int      igb_dma_coalesce = 0;
266
267 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
268 TUNABLE_INT("hw.igb.txd", &igb_txd);
269 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
270 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
271 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
272 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
273
274 /* i350 specific */
275 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
276 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
277
278 static __inline void
279 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
280 {
281         /* Ignore Checksum bit is set */
282         if (staterr & E1000_RXD_STAT_IXSM)
283                 return;
284
285         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
286             E1000_RXD_STAT_IPCS)
287                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
288
289         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
290                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
291                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
292                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
293                         mp->m_pkthdr.csum_data = htons(0xffff);
294                 }
295         }
296 }
297
298 static __inline struct pktinfo *
299 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
300     uint32_t hash, uint32_t hashtype, uint32_t staterr)
301 {
302         switch (hashtype) {
303         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
304                 pi->pi_netisr = NETISR_IP;
305                 pi->pi_flags = 0;
306                 pi->pi_l3proto = IPPROTO_TCP;
307                 break;
308
309         case E1000_RXDADV_RSSTYPE_IPV4:
310                 if (staterr & E1000_RXD_STAT_IXSM)
311                         return NULL;
312
313                 if ((staterr &
314                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
315                     E1000_RXD_STAT_TCPCS) {
316                         pi->pi_netisr = NETISR_IP;
317                         pi->pi_flags = 0;
318                         pi->pi_l3proto = IPPROTO_UDP;
319                         break;
320                 }
321                 /* FALL THROUGH */
322         default:
323                 return NULL;
324         }
325
326         m->m_flags |= M_HASH;
327         m->m_pkthdr.hash = toeplitz_hash(hash);
328         return pi;
329 }
330
331 static int
332 igb_probe(device_t dev)
333 {
334         const struct igb_device *d;
335         uint16_t vid, did;
336
337         vid = pci_get_vendor(dev);
338         did = pci_get_device(dev);
339
340         for (d = igb_devices; d->desc != NULL; ++d) {
341                 if (vid == d->vid && did == d->did) {
342                         device_set_desc(dev, d->desc);
343                         return 0;
344                 }
345         }
346         return ENXIO;
347 }
348
349 static int
350 igb_attach(device_t dev)
351 {
352         struct igb_softc *sc = device_get_softc(dev);
353         uint16_t eeprom_data;
354         int error = 0, i, j, ring_max;
355 #ifdef IFPOLL_ENABLE
356         int offset, offset_def;
357 #endif
358
359 #ifdef notyet
360         /* SYSCTL stuff */
361         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
362             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
363             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
364             igb_sysctl_nvm_info, "I", "NVM Information");
365
366         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
367             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
368             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
369             &igb_enable_aim, 1, "Interrupt Moderation");
370
371         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
372             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
373             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
374             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
375 #endif
376
377         callout_init_mp(&sc->timer);
378         lwkt_serialize_init(&sc->main_serialize);
379
380         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
381             device_get_unit(dev));
382         sc->dev = sc->osdep.dev = dev;
383
384         /*
385          * Determine hardware and mac type
386          */
387         sc->hw.vendor_id = pci_get_vendor(dev);
388         sc->hw.device_id = pci_get_device(dev);
389         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
390         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
391         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
392
393         if (e1000_set_mac_type(&sc->hw))
394                 return ENXIO;
395
396         /* Are we a VF device? */
397         if (sc->hw.mac.type == e1000_vfadapt ||
398             sc->hw.mac.type == e1000_vfadapt_i350)
399                 sc->vf_ifp = 1;
400         else
401                 sc->vf_ifp = 0;
402
403         /*
404          * Configure total supported RX/TX ring count
405          */
406         switch (sc->hw.mac.type) {
407         case e1000_82575:
408                 ring_max = IGB_MAX_RING_82575;
409                 break;
410         case e1000_82580:
411                 ring_max = IGB_MAX_RING_82580;
412                 break;
413         case e1000_i350:
414                 ring_max = IGB_MAX_RING_I350;
415                 break;
416         case e1000_82576:
417                 ring_max = IGB_MAX_RING_82576;
418                 break;
419         default:
420                 ring_max = IGB_MIN_RING;
421                 break;
422         }
423         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
424         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
425 #ifdef IGB_RSS_DEBUG
426         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
427 #endif
428         sc->rx_ring_inuse = sc->rx_ring_cnt;
429         sc->tx_ring_cnt = 1; /* XXX */
430
431         if (sc->hw.mac.type == e1000_82575)
432                 sc->flags |= IGB_FLAG_TSO_IPLEN0;
433
434         /* Enable bus mastering */
435         pci_enable_busmaster(dev);
436
437         /*
438          * Allocate IO memory
439          */
440         sc->mem_rid = PCIR_BAR(0);
441         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
442             RF_ACTIVE);
443         if (sc->mem_res == NULL) {
444                 device_printf(dev, "Unable to allocate bus resource: memory\n");
445                 error = ENXIO;
446                 goto failed;
447         }
448         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
449         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
450
451         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
452
453         /* Save PCI command register for Shared Code */
454         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
455         sc->hw.back = &sc->osdep;
456
457         /* Do Shared Code initialization */
458         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
459                 device_printf(dev, "Setup of Shared code failed\n");
460                 error = ENXIO;
461                 goto failed;
462         }
463
464         e1000_get_bus_info(&sc->hw);
465
466         sc->hw.mac.autoneg = DO_AUTO_NEG;
467         sc->hw.phy.autoneg_wait_to_complete = FALSE;
468         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
469
470         /* Copper options */
471         if (sc->hw.phy.media_type == e1000_media_type_copper) {
472                 sc->hw.phy.mdix = AUTO_ALL_MODES;
473                 sc->hw.phy.disable_polarity_correction = FALSE;
474                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
475         }
476
477         /* Set the frame limits assuming  standard ethernet sized frames. */
478         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
479
480         /* Allocate RX/TX rings */
481         error = igb_alloc_rings(sc);
482         if (error)
483                 goto failed;
484
485 #ifdef IFPOLL_ENABLE
486         /*
487          * NPOLLING RX CPU offset
488          */
489         if (sc->rx_ring_cnt == ncpus2) {
490                 offset = 0;
491         } else {
492                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
493                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
494                 if (offset >= ncpus2 ||
495                     offset % sc->rx_ring_cnt != 0) {
496                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
497                             offset, offset_def);
498                         offset = offset_def;
499                 }
500         }
501         sc->rx_npoll_off = offset;
502
503         /*
504          * NPOLLING TX CPU offset
505          */
506         offset_def = sc->rx_npoll_off;
507         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
508         if (offset >= ncpus2) {
509                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
510                     offset, offset_def);
511                 offset = offset_def;
512         }
513         sc->tx_npoll_off = offset;
514 #endif
515
516         /* Allocate interrupt */
517         error = igb_alloc_intr(sc);
518         if (error)
519                 goto failed;
520
521         /*
522          * Setup serializers
523          */
524         i = 0;
525         sc->serializes[i++] = &sc->main_serialize;
526
527         sc->tx_serialize = i;
528         for (j = 0; j < sc->tx_ring_cnt; ++j)
529                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
530
531         sc->rx_serialize = i;
532         for (j = 0; j < sc->rx_ring_cnt; ++j)
533                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
534
535         sc->serialize_cnt = i;
536         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
537
538         /* Allocate the appropriate stats memory */
539         if (sc->vf_ifp) {
540                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
541                     M_WAITOK | M_ZERO);
542                 igb_vf_init_stats(sc);
543         } else {
544                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
545                     M_WAITOK | M_ZERO);
546         }
547
548         /* Allocate multicast array memory. */
549         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
550             M_DEVBUF, M_WAITOK);
551
552         /* Some adapter-specific advanced features */
553         if (sc->hw.mac.type >= e1000_i350) {
554 #ifdef notyet
555                 igb_set_sysctl_value(adapter, "dma_coalesce",
556                     "configure dma coalesce",
557                     &adapter->dma_coalesce, igb_dma_coalesce);
558                 igb_set_sysctl_value(adapter, "eee_disabled",
559                     "enable Energy Efficient Ethernet",
560                     &adapter->hw.dev_spec._82575.eee_disable,
561                     igb_eee_disabled);
562 #else
563                 sc->dma_coalesce = igb_dma_coalesce;
564                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
565 #endif
566                 e1000_set_eee_i350(&sc->hw);
567         }
568
569         /*
570          * Start from a known state, this is important in reading the nvm and
571          * mac from that.
572          */
573         e1000_reset_hw(&sc->hw);
574
575         /* Make sure we have a good EEPROM before we read from it */
576         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
577                 /*
578                  * Some PCI-E parts fail the first check due to
579                  * the link being in sleep state, call it again,
580                  * if it fails a second time its a real issue.
581                  */
582                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
583                         device_printf(dev,
584                             "The EEPROM Checksum Is Not Valid\n");
585                         error = EIO;
586                         goto failed;
587                 }
588         }
589
590         /* Copy the permanent MAC address out of the EEPROM */
591         if (e1000_read_mac_addr(&sc->hw) < 0) {
592                 device_printf(dev, "EEPROM read error while reading MAC"
593                     " address\n");
594                 error = EIO;
595                 goto failed;
596         }
597         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
598                 device_printf(dev, "Invalid MAC address\n");
599                 error = EIO;
600                 goto failed;
601         }
602
603 #ifdef notyet
604         /* 
605         ** Configure Interrupts
606         */
607         if ((adapter->msix > 1) && (igb_enable_msix))
608                 error = igb_allocate_msix(adapter);
609         else /* MSI or Legacy */
610                 error = igb_allocate_legacy(adapter);
611         if (error)
612                 goto err_late;
613 #endif
614
615         /* Setup OS specific network interface */
616         igb_setup_ifp(sc);
617
618         /* Add sysctl tree, must after igb_setup_ifp() */
619         igb_add_sysctl(sc);
620
621         /* Now get a good starting state */
622         igb_reset(sc);
623
624         /* Initialize statistics */
625         igb_update_stats_counters(sc);
626
627         sc->hw.mac.get_link_status = 1;
628         igb_update_link_status(sc);
629
630         /* Indicate SOL/IDER usage */
631         if (e1000_check_reset_block(&sc->hw)) {
632                 device_printf(dev,
633                     "PHY reset is blocked due to SOL/IDER session.\n");
634         }
635
636         /* Determine if we have to control management hardware */
637         if (e1000_enable_mng_pass_thru(&sc->hw))
638                 sc->flags |= IGB_FLAG_HAS_MGMT;
639
640         /*
641          * Setup Wake-on-Lan
642          */
643         /* APME bit in EEPROM is mapped to WUC.APME */
644         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
645         if (eeprom_data)
646                 sc->wol = E1000_WUFC_MAG;
647         /* XXX disable WOL */
648         sc->wol = 0; 
649
650 #ifdef notyet
651         /* Register for VLAN events */
652         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
653              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
654         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
655              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
656 #endif
657
658 #ifdef notyet
659         igb_add_hw_stats(adapter);
660 #endif
661
662         error = igb_setup_intr(sc);
663         if (error) {
664                 ether_ifdetach(&sc->arpcom.ac_if);
665                 goto failed;
666         }
667         return 0;
668
669 failed:
670         igb_detach(dev);
671         return error;
672 }
673
674 static int
675 igb_detach(device_t dev)
676 {
677         struct igb_softc *sc = device_get_softc(dev);
678
679         if (device_is_attached(dev)) {
680                 struct ifnet *ifp = &sc->arpcom.ac_if;
681
682                 ifnet_serialize_all(ifp);
683
684                 igb_stop(sc);
685
686                 e1000_phy_hw_reset(&sc->hw);
687
688                 /* Give control back to firmware */
689                 igb_rel_mgmt(sc);
690                 igb_rel_hw_control(sc);
691
692                 if (sc->wol) {
693                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
694                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
695                         igb_enable_wol(dev);
696                 }
697
698                 igb_teardown_intr(sc);
699
700                 ifnet_deserialize_all(ifp);
701
702                 ether_ifdetach(ifp);
703         } else if (sc->mem_res != NULL) {
704                 igb_rel_hw_control(sc);
705         }
706         bus_generic_detach(dev);
707
708         if (sc->sysctl_tree != NULL)
709                 sysctl_ctx_free(&sc->sysctl_ctx);
710
711         igb_free_intr(sc);
712
713         if (sc->msix_mem_res != NULL) {
714                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
715                     sc->msix_mem_res);
716         }
717         if (sc->mem_res != NULL) {
718                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
719                     sc->mem_res);
720         }
721
722         igb_free_rings(sc);
723
724         if (sc->mta != NULL)
725                 kfree(sc->mta, M_DEVBUF);
726         if (sc->stats != NULL)
727                 kfree(sc->stats, M_DEVBUF);
728
729         return 0;
730 }
731
732 static int
733 igb_shutdown(device_t dev)
734 {
735         return igb_suspend(dev);
736 }
737
738 static int
739 igb_suspend(device_t dev)
740 {
741         struct igb_softc *sc = device_get_softc(dev);
742         struct ifnet *ifp = &sc->arpcom.ac_if;
743
744         ifnet_serialize_all(ifp);
745
746         igb_stop(sc);
747
748         igb_rel_mgmt(sc);
749         igb_rel_hw_control(sc);
750
751         if (sc->wol) {
752                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
753                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
754                 igb_enable_wol(dev);
755         }
756
757         ifnet_deserialize_all(ifp);
758
759         return bus_generic_suspend(dev);
760 }
761
762 static int
763 igb_resume(device_t dev)
764 {
765         struct igb_softc *sc = device_get_softc(dev);
766         struct ifnet *ifp = &sc->arpcom.ac_if;
767
768         ifnet_serialize_all(ifp);
769
770         igb_init(sc);
771         igb_get_mgmt(sc);
772
773         if_devstart(ifp);
774
775         ifnet_deserialize_all(ifp);
776
777         return bus_generic_resume(dev);
778 }
779
780 static int
781 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
782 {
783         struct igb_softc *sc = ifp->if_softc;
784         struct ifreq *ifr = (struct ifreq *)data;
785         int max_frame_size, mask, reinit;
786         int error = 0;
787
788         ASSERT_IFNET_SERIALIZED_ALL(ifp);
789
790         switch (command) {
791         case SIOCSIFMTU:
792                 max_frame_size = 9234;
793                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
794                     ETHER_CRC_LEN) {
795                         error = EINVAL;
796                         break;
797                 }
798
799                 ifp->if_mtu = ifr->ifr_mtu;
800                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
801                     ETHER_CRC_LEN;
802
803                 if (ifp->if_flags & IFF_RUNNING)
804                         igb_init(sc);
805                 break;
806
807         case SIOCSIFFLAGS:
808                 if (ifp->if_flags & IFF_UP) {
809                         if (ifp->if_flags & IFF_RUNNING) {
810                                 if ((ifp->if_flags ^ sc->if_flags) &
811                                     (IFF_PROMISC | IFF_ALLMULTI)) {
812                                         igb_disable_promisc(sc);
813                                         igb_set_promisc(sc);
814                                 }
815                         } else {
816                                 igb_init(sc);
817                         }
818                 } else if (ifp->if_flags & IFF_RUNNING) {
819                         igb_stop(sc);
820                 }
821                 sc->if_flags = ifp->if_flags;
822                 break;
823
824         case SIOCADDMULTI:
825         case SIOCDELMULTI:
826                 if (ifp->if_flags & IFF_RUNNING) {
827                         igb_disable_intr(sc);
828                         igb_set_multi(sc);
829 #ifdef IFPOLL_ENABLE
830                         if (!(ifp->if_flags & IFF_NPOLLING))
831 #endif
832                                 igb_enable_intr(sc);
833                 }
834                 break;
835
836         case SIOCSIFMEDIA:
837                 /*
838                  * As the speed/duplex settings are being
839                  * changed, we need toreset the PHY.
840                  */
841                 sc->hw.phy.reset_disable = FALSE;
842
843                 /* Check SOL/IDER usage */
844                 if (e1000_check_reset_block(&sc->hw)) {
845                         if_printf(ifp, "Media change is "
846                             "blocked due to SOL/IDER session.\n");
847                         break;
848                 }
849                 /* FALL THROUGH */
850
851         case SIOCGIFMEDIA:
852                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
853                 break;
854
855         case SIOCSIFCAP:
856                 reinit = 0;
857                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
858                 if (mask & IFCAP_RXCSUM) {
859                         ifp->if_capenable ^= IFCAP_RXCSUM;
860                         reinit = 1;
861                 }
862                 if (mask & IFCAP_VLAN_HWTAGGING) {
863                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
864                         reinit = 1;
865                 }
866                 if (mask & IFCAP_TXCSUM) {
867                         ifp->if_capenable ^= IFCAP_TXCSUM;
868                         if (ifp->if_capenable & IFCAP_TXCSUM)
869                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
870                         else
871                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
872                 }
873                 if (mask & IFCAP_TSO) {
874                         ifp->if_capenable ^= IFCAP_TSO;
875                         if (ifp->if_capenable & IFCAP_TSO)
876                                 ifp->if_hwassist |= CSUM_TSO;
877                         else
878                                 ifp->if_hwassist &= ~CSUM_TSO;
879                 }
880                 if (mask & IFCAP_RSS)
881                         ifp->if_capenable ^= IFCAP_RSS;
882                 if (reinit && (ifp->if_flags & IFF_RUNNING))
883                         igb_init(sc);
884                 break;
885
886         default:
887                 error = ether_ioctl(ifp, command, data);
888                 break;
889         }
890         return error;
891 }
892
893 static void
894 igb_init(void *xsc)
895 {
896         struct igb_softc *sc = xsc;
897         struct ifnet *ifp = &sc->arpcom.ac_if;
898         boolean_t polling;
899         int i;
900
901         ASSERT_IFNET_SERIALIZED_ALL(ifp);
902
903         igb_stop(sc);
904
905         /* Get the latest mac address, User can use a LAA */
906         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
907
908         /* Put the address into the Receive Address Array */
909         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
910
911         igb_reset(sc);
912         igb_update_link_status(sc);
913
914         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
915
916         /* Configure for OS presence */
917         igb_get_mgmt(sc);
918
919         polling = FALSE;
920 #ifdef IFPOLL_ENABLE
921         if (ifp->if_flags & IFF_NPOLLING)
922                 polling = TRUE;
923 #endif
924
925         /* Configured used RX/TX rings */
926         igb_set_ring_inuse(sc, polling);
927
928         /* Initialize interrupt */
929         igb_init_intr(sc);
930
931         /* Prepare transmit descriptors and buffers */
932         for (i = 0; i < sc->tx_ring_cnt; ++i)
933                 igb_init_tx_ring(&sc->tx_rings[i]);
934         igb_init_tx_unit(sc);
935
936         /* Setup Multicast table */
937         igb_set_multi(sc);
938
939 #if 0
940         /*
941          * Figure out the desired mbuf pool
942          * for doing jumbo/packetsplit
943          */
944         if (adapter->max_frame_size <= 2048)
945                 adapter->rx_mbuf_sz = MCLBYTES;
946         else if (adapter->max_frame_size <= 4096)
947                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
948         else
949                 adapter->rx_mbuf_sz = MJUM9BYTES;
950 #endif
951
952         /* Prepare receive descriptors and buffers */
953         for (i = 0; i < sc->rx_ring_inuse; ++i) {
954                 int error;
955
956                 error = igb_init_rx_ring(&sc->rx_rings[i]);
957                 if (error) {
958                         if_printf(ifp, "Could not setup receive structures\n");
959                         igb_stop(sc);
960                         return;
961                 }
962         }
963         igb_init_rx_unit(sc);
964
965         /* Enable VLAN support */
966         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
967                 igb_set_vlan(sc);
968
969         /* Don't lose promiscuous settings */
970         igb_set_promisc(sc);
971
972         ifp->if_flags |= IFF_RUNNING;
973         ifp->if_flags &= ~IFF_OACTIVE;
974
975         callout_reset(&sc->timer, hz, igb_timer, sc);
976         e1000_clear_hw_cntrs_base_generic(&sc->hw);
977
978         /* This clears any pending interrupts */
979         E1000_READ_REG(&sc->hw, E1000_ICR);
980
981         /*
982          * Only enable interrupts if we are not polling, make sure
983          * they are off otherwise.
984          */
985         if (polling) {
986                 igb_disable_intr(sc);
987         } else {
988                 igb_enable_intr(sc);
989                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
990         }
991
992         /* Set Energy Efficient Ethernet */
993         e1000_set_eee_i350(&sc->hw);
994
995         /* Don't reset the phy next time init gets called */
996         sc->hw.phy.reset_disable = TRUE;
997 }
998
999 static void
1000 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1001 {
1002         struct igb_softc *sc = ifp->if_softc;
1003         u_char fiber_type = IFM_1000_SX;
1004
1005         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1006
1007         igb_update_link_status(sc);
1008
1009         ifmr->ifm_status = IFM_AVALID;
1010         ifmr->ifm_active = IFM_ETHER;
1011
1012         if (!sc->link_active)
1013                 return;
1014
1015         ifmr->ifm_status |= IFM_ACTIVE;
1016
1017         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1018             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1019                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1020         } else {
1021                 switch (sc->link_speed) {
1022                 case 10:
1023                         ifmr->ifm_active |= IFM_10_T;
1024                         break;
1025
1026                 case 100:
1027                         ifmr->ifm_active |= IFM_100_TX;
1028                         break;
1029
1030                 case 1000:
1031                         ifmr->ifm_active |= IFM_1000_T;
1032                         break;
1033                 }
1034                 if (sc->link_duplex == FULL_DUPLEX)
1035                         ifmr->ifm_active |= IFM_FDX;
1036                 else
1037                         ifmr->ifm_active |= IFM_HDX;
1038         }
1039 }
1040
1041 static int
1042 igb_media_change(struct ifnet *ifp)
1043 {
1044         struct igb_softc *sc = ifp->if_softc;
1045         struct ifmedia *ifm = &sc->media;
1046
1047         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1048
1049         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1050                 return EINVAL;
1051
1052         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1053         case IFM_AUTO:
1054                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1055                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1056                 break;
1057
1058         case IFM_1000_LX:
1059         case IFM_1000_SX:
1060         case IFM_1000_T:
1061                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1062                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1063                 break;
1064
1065         case IFM_100_TX:
1066                 sc->hw.mac.autoneg = FALSE;
1067                 sc->hw.phy.autoneg_advertised = 0;
1068                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1069                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1070                 else
1071                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1072                 break;
1073
1074         case IFM_10_T:
1075                 sc->hw.mac.autoneg = FALSE;
1076                 sc->hw.phy.autoneg_advertised = 0;
1077                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1078                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1079                 else
1080                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1081                 break;
1082
1083         default:
1084                 if_printf(ifp, "Unsupported media type\n");
1085                 break;
1086         }
1087
1088         igb_init(sc);
1089
1090         return 0;
1091 }
1092
1093 static void
1094 igb_set_promisc(struct igb_softc *sc)
1095 {
1096         struct ifnet *ifp = &sc->arpcom.ac_if;
1097         struct e1000_hw *hw = &sc->hw;
1098         uint32_t reg;
1099
1100         if (sc->vf_ifp) {
1101                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1102                 return;
1103         }
1104
1105         reg = E1000_READ_REG(hw, E1000_RCTL);
1106         if (ifp->if_flags & IFF_PROMISC) {
1107                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1108                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1109         } else if (ifp->if_flags & IFF_ALLMULTI) {
1110                 reg |= E1000_RCTL_MPE;
1111                 reg &= ~E1000_RCTL_UPE;
1112                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1113         }
1114 }
1115
1116 static void
1117 igb_disable_promisc(struct igb_softc *sc)
1118 {
1119         struct e1000_hw *hw = &sc->hw;
1120         uint32_t reg;
1121
1122         if (sc->vf_ifp) {
1123                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1124                 return;
1125         }
1126         reg = E1000_READ_REG(hw, E1000_RCTL);
1127         reg &= ~E1000_RCTL_UPE;
1128         reg &= ~E1000_RCTL_MPE;
1129         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1130 }
1131
1132 static void
1133 igb_set_multi(struct igb_softc *sc)
1134 {
1135         struct ifnet *ifp = &sc->arpcom.ac_if;
1136         struct ifmultiaddr *ifma;
1137         uint32_t reg_rctl = 0;
1138         uint8_t *mta;
1139         int mcnt = 0;
1140
1141         mta = sc->mta;
1142         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1143
1144         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1145                 if (ifma->ifma_addr->sa_family != AF_LINK)
1146                         continue;
1147
1148                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1149                         break;
1150
1151                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1152                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1153                 mcnt++;
1154         }
1155
1156         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1157                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1158                 reg_rctl |= E1000_RCTL_MPE;
1159                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1160         } else {
1161                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1162         }
1163 }
1164
1165 static void
1166 igb_timer(void *xsc)
1167 {
1168         struct igb_softc *sc = xsc;
1169
1170         lwkt_serialize_enter(&sc->main_serialize);
1171
1172         igb_update_link_status(sc);
1173         igb_update_stats_counters(sc);
1174
1175         callout_reset(&sc->timer, hz, igb_timer, sc);
1176
1177         lwkt_serialize_exit(&sc->main_serialize);
1178 }
1179
1180 static void
1181 igb_update_link_status(struct igb_softc *sc)
1182 {
1183         struct ifnet *ifp = &sc->arpcom.ac_if;
1184         struct e1000_hw *hw = &sc->hw;
1185         uint32_t link_check, thstat, ctrl;
1186
1187         link_check = thstat = ctrl = 0;
1188
1189         /* Get the cached link value or read for real */
1190         switch (hw->phy.media_type) {
1191         case e1000_media_type_copper:
1192                 if (hw->mac.get_link_status) {
1193                         /* Do the work to read phy */
1194                         e1000_check_for_link(hw);
1195                         link_check = !hw->mac.get_link_status;
1196                 } else {
1197                         link_check = TRUE;
1198                 }
1199                 break;
1200
1201         case e1000_media_type_fiber:
1202                 e1000_check_for_link(hw);
1203                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1204                 break;
1205
1206         case e1000_media_type_internal_serdes:
1207                 e1000_check_for_link(hw);
1208                 link_check = hw->mac.serdes_has_link;
1209                 break;
1210
1211         /* VF device is type_unknown */
1212         case e1000_media_type_unknown:
1213                 e1000_check_for_link(hw);
1214                 link_check = !hw->mac.get_link_status;
1215                 /* Fall thru */
1216         default:
1217                 break;
1218         }
1219
1220         /* Check for thermal downshift or shutdown */
1221         if (hw->mac.type == e1000_i350) {
1222                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1223                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1224         }
1225
1226         /* Now we check if a transition has happened */
1227         if (link_check && sc->link_active == 0) {
1228                 e1000_get_speed_and_duplex(hw, 
1229                     &sc->link_speed, &sc->link_duplex);
1230                 if (bootverbose) {
1231                         if_printf(ifp, "Link is up %d Mbps %s\n",
1232                             sc->link_speed,
1233                             sc->link_duplex == FULL_DUPLEX ?
1234                             "Full Duplex" : "Half Duplex");
1235                 }
1236                 sc->link_active = 1;
1237
1238                 ifp->if_baudrate = sc->link_speed * 1000000;
1239                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1240                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1241                         if_printf(ifp, "Link: thermal downshift\n");
1242                 /* This can sleep */
1243                 ifp->if_link_state = LINK_STATE_UP;
1244                 if_link_state_change(ifp);
1245         } else if (!link_check && sc->link_active == 1) {
1246                 ifp->if_baudrate = sc->link_speed = 0;
1247                 sc->link_duplex = 0;
1248                 if (bootverbose)
1249                         if_printf(ifp, "Link is Down\n");
1250                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1251                     (thstat & E1000_THSTAT_PWR_DOWN))
1252                         if_printf(ifp, "Link: thermal shutdown\n");
1253                 sc->link_active = 0;
1254                 /* This can sleep */
1255                 ifp->if_link_state = LINK_STATE_DOWN;
1256                 if_link_state_change(ifp);
1257         }
1258 }
1259
1260 static void
1261 igb_stop(struct igb_softc *sc)
1262 {
1263         struct ifnet *ifp = &sc->arpcom.ac_if;
1264         int i;
1265
1266         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1267
1268         igb_disable_intr(sc);
1269
1270         callout_stop(&sc->timer);
1271
1272         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1273         ifp->if_timer = 0;
1274
1275         e1000_reset_hw(&sc->hw);
1276         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1277
1278         e1000_led_off(&sc->hw);
1279         e1000_cleanup_led(&sc->hw);
1280
1281         for (i = 0; i < sc->tx_ring_cnt; ++i)
1282                 igb_free_tx_ring(&sc->tx_rings[i]);
1283         for (i = 0; i < sc->rx_ring_cnt; ++i)
1284                 igb_free_rx_ring(&sc->rx_rings[i]);
1285 }
1286
1287 static void
1288 igb_reset(struct igb_softc *sc)
1289 {
1290         struct ifnet *ifp = &sc->arpcom.ac_if;
1291         struct e1000_hw *hw = &sc->hw;
1292         struct e1000_fc_info *fc = &hw->fc;
1293         uint32_t pba = 0;
1294         uint16_t hwm;
1295
1296         /* Let the firmware know the OS is in control */
1297         igb_get_hw_control(sc);
1298
1299         /*
1300          * Packet Buffer Allocation (PBA)
1301          * Writing PBA sets the receive portion of the buffer
1302          * the remainder is used for the transmit buffer.
1303          */
1304         switch (hw->mac.type) {
1305         case e1000_82575:
1306                 pba = E1000_PBA_32K;
1307                 break;
1308
1309         case e1000_82576:
1310         case e1000_vfadapt:
1311                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1312                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1313                 break;
1314
1315         case e1000_82580:
1316         case e1000_i350:
1317         case e1000_vfadapt_i350:
1318                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1319                 pba = e1000_rxpbs_adjust_82580(pba);
1320                 break;
1321                 /* XXX pba = E1000_PBA_35K; */
1322
1323         default:
1324                 break;
1325         }
1326
1327         /* Special needs in case of Jumbo frames */
1328         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1329                 uint32_t tx_space, min_tx, min_rx;
1330
1331                 pba = E1000_READ_REG(hw, E1000_PBA);
1332                 tx_space = pba >> 16;
1333                 pba &= 0xffff;
1334
1335                 min_tx = (sc->max_frame_size +
1336                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1337                 min_tx = roundup2(min_tx, 1024);
1338                 min_tx >>= 10;
1339                 min_rx = sc->max_frame_size;
1340                 min_rx = roundup2(min_rx, 1024);
1341                 min_rx >>= 10;
1342                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1343                         pba = pba - (min_tx - tx_space);
1344                         /*
1345                          * if short on rx space, rx wins
1346                          * and must trump tx adjustment
1347                          */
1348                         if (pba < min_rx)
1349                                 pba = min_rx;
1350                 }
1351                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1352         }
1353
1354         /*
1355          * These parameters control the automatic generation (Tx) and
1356          * response (Rx) to Ethernet PAUSE frames.
1357          * - High water mark should allow for at least two frames to be
1358          *   received after sending an XOFF.
1359          * - Low water mark works best when it is very near the high water mark.
1360          *   This allows the receiver to restart by sending XON when it has
1361          *   drained a bit.
1362          */
1363         hwm = min(((pba << 10) * 9 / 10),
1364             ((pba << 10) - 2 * sc->max_frame_size));
1365
1366         if (hw->mac.type < e1000_82576) {
1367                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1368                 fc->low_water = fc->high_water - 8;
1369         } else {
1370                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1371                 fc->low_water = fc->high_water - 16;
1372         }
1373         fc->pause_time = IGB_FC_PAUSE_TIME;
1374         fc->send_xon = TRUE;
1375
1376         /* Issue a global reset */
1377         e1000_reset_hw(hw);
1378         E1000_WRITE_REG(hw, E1000_WUC, 0);
1379
1380         if (e1000_init_hw(hw) < 0)
1381                 if_printf(ifp, "Hardware Initialization Failed\n");
1382
1383         /* Setup DMA Coalescing */
1384         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1385                 uint32_t reg;
1386
1387                 hwm = (pba - 4) << 10;
1388                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1389                     & E1000_DMACR_DMACTHR_MASK;
1390
1391                 /* transition to L0x or L1 if available..*/
1392                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1393
1394                 /* timer = +-1000 usec in 32usec intervals */
1395                 reg |= (1000 >> 5);
1396                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1397
1398                 /* No lower threshold */
1399                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1400
1401                 /* set hwm to PBA -  2 * max frame size */
1402                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1403
1404                 /* Set the interval before transition */
1405                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1406                 reg |= 0x800000FF; /* 255 usec */
1407                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1408
1409                 /* free space in tx packet buffer to wake from DMA coal */
1410                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1411                     (20480 - (2 * sc->max_frame_size)) >> 6);
1412
1413                 /* make low power state decision controlled by DMA coal */
1414                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1415                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1416                     reg | E1000_PCIEMISC_LX_DECISION);
1417                 if_printf(ifp, "DMA Coalescing enabled\n");
1418         }
1419
1420         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1421         e1000_get_phy_info(hw);
1422         e1000_check_for_link(hw);
1423 }
1424
1425 static void
1426 igb_setup_ifp(struct igb_softc *sc)
1427 {
1428         struct ifnet *ifp = &sc->arpcom.ac_if;
1429
1430         ifp->if_softc = sc;
1431         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1432         ifp->if_init = igb_init;
1433         ifp->if_ioctl = igb_ioctl;
1434         ifp->if_start = igb_start;
1435         ifp->if_serialize = igb_serialize;
1436         ifp->if_deserialize = igb_deserialize;
1437         ifp->if_tryserialize = igb_tryserialize;
1438 #ifdef INVARIANTS
1439         ifp->if_serialize_assert = igb_serialize_assert;
1440 #endif
1441 #ifdef IFPOLL_ENABLE
1442         ifp->if_npoll = igb_npoll;
1443 #endif
1444         ifp->if_watchdog = igb_watchdog;
1445
1446         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1447         ifq_set_ready(&ifp->if_snd);
1448
1449         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1450
1451         ifp->if_capabilities =
1452             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1453         if (IGB_ENABLE_HWRSS(sc))
1454                 ifp->if_capabilities |= IFCAP_RSS;
1455         ifp->if_capenable = ifp->if_capabilities;
1456         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1457
1458         /*
1459          * Tell the upper layer(s) we support long frames
1460          */
1461         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1462
1463         /*
1464          * Specify the media types supported by this adapter and register
1465          * callbacks to update media and link information
1466          */
1467         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1468         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1469             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1470                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1471                     0, NULL);
1472                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1473         } else {
1474                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1475                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1476                     0, NULL);
1477                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1478                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1479                     0, NULL);
1480                 if (sc->hw.phy.type != e1000_phy_ife) {
1481                         ifmedia_add(&sc->media,
1482                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1483                         ifmedia_add(&sc->media,
1484                             IFM_ETHER | IFM_1000_T, 0, NULL);
1485                 }
1486         }
1487         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1488         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1489 }
1490
1491 static void
1492 igb_add_sysctl(struct igb_softc *sc)
1493 {
1494         char node[32];
1495         int i;
1496
1497         sysctl_ctx_init(&sc->sysctl_ctx);
1498         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1499             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1500             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1501         if (sc->sysctl_tree == NULL) {
1502                 device_printf(sc->dev, "can't add sysctl node\n");
1503                 return;
1504         }
1505
1506         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1507             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1508         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1509             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1510             "# of RX rings used");
1511         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1512             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1513             "# of RX descs");
1514         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1515             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1516             "# of TX descs");
1517
1518         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1519                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1520                     SYSCTL_CHILDREN(sc->sysctl_tree),
1521                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1522                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1523         } else {
1524                 for (i = 0; i < sc->msix_cnt; ++i) {
1525                         struct igb_msix_data *msix = &sc->msix_data[i];
1526
1527                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1528                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1529                             SYSCTL_CHILDREN(sc->sysctl_tree),
1530                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1531                             msix, 0, igb_sysctl_msix_rate, "I",
1532                             msix->msix_rate_desc);
1533                 }
1534         }
1535
1536         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1538             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1539             "# of segments per TX interrupt");
1540
1541 #ifdef IFPOLL_ENABLE
1542         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1543             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1544             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1545         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1546             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1547             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1548 #endif
1549
1550 #ifdef IGB_RSS_DEBUG
1551         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1552             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1553             "RSS debug level");
1554         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1555                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1556                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1557                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1558                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1559         }
1560 #endif
1561 }
1562
1563 static int
1564 igb_alloc_rings(struct igb_softc *sc)
1565 {
1566         int error, i;
1567
1568         /*
1569          * Create top level busdma tag
1570          */
1571         error = bus_dma_tag_create(NULL, 1, 0,
1572             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1573             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1574             &sc->parent_tag);
1575         if (error) {
1576                 device_printf(sc->dev, "could not create top level DMA tag\n");
1577                 return error;
1578         }
1579
1580         /*
1581          * Allocate TX descriptor rings and buffers
1582          */
1583         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1584             M_DEVBUF, M_WAITOK | M_ZERO);
1585         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1586                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1587
1588                 /* Set up some basics */
1589                 txr->sc = sc;
1590                 txr->me = i;
1591                 lwkt_serialize_init(&txr->tx_serialize);
1592
1593                 error = igb_create_tx_ring(txr);
1594                 if (error)
1595                         return error;
1596         }
1597
1598         /*
1599          * Allocate RX descriptor rings and buffers
1600          */ 
1601         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1602             M_DEVBUF, M_WAITOK | M_ZERO);
1603         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1604                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1605
1606                 /* Set up some basics */
1607                 rxr->sc = sc;
1608                 rxr->me = i;
1609                 lwkt_serialize_init(&rxr->rx_serialize);
1610
1611                 error = igb_create_rx_ring(rxr);
1612                 if (error)
1613                         return error;
1614         }
1615
1616         return 0;
1617 }
1618
1619 static void
1620 igb_free_rings(struct igb_softc *sc)
1621 {
1622         int i;
1623
1624         if (sc->tx_rings != NULL) {
1625                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1626                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1627
1628                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1629                 }
1630                 kfree(sc->tx_rings, M_DEVBUF);
1631         }
1632
1633         if (sc->rx_rings != NULL) {
1634                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1635                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1636
1637                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1638                 }
1639                 kfree(sc->rx_rings, M_DEVBUF);
1640         }
1641 }
1642
1643 static int
1644 igb_create_tx_ring(struct igb_tx_ring *txr)
1645 {
1646         int tsize, error, i;
1647
1648         /*
1649          * Validate number of transmit descriptors. It must not exceed
1650          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1651          */
1652         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1653             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1654                 device_printf(txr->sc->dev,
1655                     "Using %d TX descriptors instead of %d!\n",
1656                     IGB_DEFAULT_TXD, igb_txd);
1657                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1658         } else {
1659                 txr->num_tx_desc = igb_txd;
1660         }
1661
1662         /*
1663          * Allocate TX descriptor ring
1664          */
1665         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1666             IGB_DBA_ALIGN);
1667         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1668             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1669             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1670         if (txr->txdma.dma_vaddr == NULL) {
1671                 device_printf(txr->sc->dev,
1672                     "Unable to allocate TX Descriptor memory\n");
1673                 return ENOMEM;
1674         }
1675         txr->tx_base = txr->txdma.dma_vaddr;
1676         bzero(txr->tx_base, tsize);
1677
1678         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1679             M_DEVBUF, M_WAITOK | M_ZERO);
1680
1681         /*
1682          * Allocate TX head write-back buffer
1683          */
1684         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1685             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1686             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1687         if (txr->tx_hdr == NULL) {
1688                 device_printf(txr->sc->dev,
1689                     "Unable to allocate TX head write-back buffer\n");
1690                 return ENOMEM;
1691         }
1692
1693         /*
1694          * Create DMA tag for TX buffers
1695          */
1696         error = bus_dma_tag_create(txr->sc->parent_tag,
1697             1, 0,               /* alignment, bounds */
1698             BUS_SPACE_MAXADDR,  /* lowaddr */
1699             BUS_SPACE_MAXADDR,  /* highaddr */
1700             NULL, NULL,         /* filter, filterarg */
1701             IGB_TSO_SIZE,       /* maxsize */
1702             IGB_MAX_SCATTER,    /* nsegments */
1703             PAGE_SIZE,          /* maxsegsize */
1704             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1705             BUS_DMA_ONEBPAGE,   /* flags */
1706             &txr->tx_tag);
1707         if (error) {
1708                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1709                 kfree(txr->tx_buf, M_DEVBUF);
1710                 txr->tx_buf = NULL;
1711                 return error;
1712         }
1713
1714         /*
1715          * Create DMA maps for TX buffers
1716          */
1717         for (i = 0; i < txr->num_tx_desc; ++i) {
1718                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1719
1720                 error = bus_dmamap_create(txr->tx_tag,
1721                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1722                 if (error) {
1723                         device_printf(txr->sc->dev,
1724                             "Unable to create TX DMA map\n");
1725                         igb_destroy_tx_ring(txr, i);
1726                         return error;
1727                 }
1728         }
1729
1730         /*
1731          * Initialize various watermark
1732          */
1733         txr->spare_desc = IGB_TX_SPARE;
1734         txr->intr_nsegs = txr->num_tx_desc / 16;
1735         txr->oact_hi_desc = txr->num_tx_desc / 2;
1736         txr->oact_lo_desc = txr->num_tx_desc / 8;
1737         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1738                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1739         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1740                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1741
1742         return 0;
1743 }
1744
1745 static void
1746 igb_free_tx_ring(struct igb_tx_ring *txr)
1747 {
1748         int i;
1749
1750         for (i = 0; i < txr->num_tx_desc; ++i) {
1751                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1752
1753                 if (txbuf->m_head != NULL) {
1754                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1755                         m_freem(txbuf->m_head);
1756                         txbuf->m_head = NULL;
1757                 }
1758         }
1759 }
1760
1761 static void
1762 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1763 {
1764         int i;
1765
1766         if (txr->txdma.dma_vaddr != NULL) {
1767                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1768                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1769                     txr->txdma.dma_map);
1770                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1771                 txr->txdma.dma_vaddr = NULL;
1772         }
1773
1774         if (txr->tx_hdr != NULL) {
1775                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1776                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1777                     txr->tx_hdr_dmap);
1778                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1779                 txr->tx_hdr = NULL;
1780         }
1781
1782         if (txr->tx_buf == NULL)
1783                 return;
1784
1785         for (i = 0; i < ndesc; ++i) {
1786                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1787
1788                 KKASSERT(txbuf->m_head == NULL);
1789                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1790         }
1791         bus_dma_tag_destroy(txr->tx_tag);
1792
1793         kfree(txr->tx_buf, M_DEVBUF);
1794         txr->tx_buf = NULL;
1795 }
1796
1797 static void
1798 igb_init_tx_ring(struct igb_tx_ring *txr)
1799 {
1800         /* Clear the old descriptor contents */
1801         bzero(txr->tx_base,
1802             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1803
1804         /* Clear TX head write-back buffer */
1805         *(txr->tx_hdr) = 0;
1806
1807         /* Reset indices */
1808         txr->next_avail_desc = 0;
1809         txr->next_to_clean = 0;
1810         txr->tx_nsegs = 0;
1811
1812         /* Set number of descriptors available */
1813         txr->tx_avail = txr->num_tx_desc;
1814 }
1815
1816 static void
1817 igb_init_tx_unit(struct igb_softc *sc)
1818 {
1819         struct e1000_hw *hw = &sc->hw;
1820         uint32_t tctl;
1821         int i;
1822
1823         /* Setup the Tx Descriptor Rings */
1824         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1825                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1826                 uint64_t bus_addr = txr->txdma.dma_paddr;
1827                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1828                 uint32_t txdctl = 0;
1829                 uint32_t dca_txctrl;
1830
1831                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1832                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1833                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1834                     (uint32_t)(bus_addr >> 32));
1835                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1836                     (uint32_t)bus_addr);
1837
1838                 /* Setup the HW Tx Head and Tail descriptor pointers */
1839                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1840                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1841
1842                 /*
1843                  * WTHRESH is ignored by the hardware, since header
1844                  * write back mode is used.
1845                  */
1846                 txdctl |= IGB_TX_PTHRESH;
1847                 txdctl |= IGB_TX_HTHRESH << 8;
1848                 txdctl |= IGB_TX_WTHRESH << 16;
1849                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1850                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1851
1852                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1853                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1854                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1855
1856                 /*
1857                  * Don't set WB_on_EITR:
1858                  * - 82575 does not have it
1859                  * - It almost has no effect on 82576, see:
1860                  *   82576 specification update errata #26
1861                  * - It causes unnecessary bus traffic
1862                  */
1863                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1864                     (uint32_t)(hdr_paddr >> 32));
1865                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1866                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1867         }
1868
1869         if (sc->vf_ifp)
1870                 return;
1871
1872         e1000_config_collision_dist(hw);
1873
1874         /* Program the Transmit Control Register */
1875         tctl = E1000_READ_REG(hw, E1000_TCTL);
1876         tctl &= ~E1000_TCTL_CT;
1877         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1878             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1879
1880         /* This write will effectively turn on the transmit unit. */
1881         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1882 }
1883
1884 static boolean_t
1885 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1886 {
1887         struct e1000_adv_tx_context_desc *TXD;
1888         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1889         int ehdrlen, ctxd, ip_hlen = 0;
1890         boolean_t offload = TRUE;
1891
1892         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1893                 offload = FALSE;
1894
1895         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1896
1897         ctxd = txr->next_avail_desc;
1898         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1899
1900         /*
1901          * In advanced descriptors the vlan tag must 
1902          * be placed into the context descriptor, thus
1903          * we need to be here just for that setup.
1904          */
1905         if (mp->m_flags & M_VLANTAG) {
1906                 uint16_t vlantag;
1907
1908                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1909                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1910         } else if (!offload) {
1911                 return FALSE;
1912         }
1913
1914         ehdrlen = mp->m_pkthdr.csum_lhlen;
1915         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1916
1917         /* Set the ether header length */
1918         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1919         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1920                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1921                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1922                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1923         }
1924         vlan_macip_lens |= ip_hlen;
1925
1926         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1927         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1928                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1929         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1930                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1931
1932         /* 82575 needs the queue index added */
1933         if (txr->sc->hw.mac.type == e1000_82575)
1934                 mss_l4len_idx = txr->me << 4;
1935
1936         /* Now copy bits into descriptor */
1937         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1938         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1939         TXD->seqnum_seed = htole32(0);
1940         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1941
1942         /* We've consumed the first desc, adjust counters */
1943         if (++ctxd == txr->num_tx_desc)
1944                 ctxd = 0;
1945         txr->next_avail_desc = ctxd;
1946         --txr->tx_avail;
1947
1948         return offload;
1949 }
1950
1951 static void
1952 igb_txeof(struct igb_tx_ring *txr)
1953 {
1954         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1955         int first, hdr, avail;
1956
1957         if (txr->tx_avail == txr->num_tx_desc)
1958                 return;
1959
1960         first = txr->next_to_clean;
1961         hdr = *(txr->tx_hdr);
1962
1963         if (first == hdr)
1964                 return;
1965
1966         avail = txr->tx_avail;
1967         while (first != hdr) {
1968                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1969
1970                 ++avail;
1971                 if (txbuf->m_head) {
1972                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1973                         m_freem(txbuf->m_head);
1974                         txbuf->m_head = NULL;
1975                         ++ifp->if_opackets;
1976                 }
1977                 if (++first == txr->num_tx_desc)
1978                         first = 0;
1979         }
1980         txr->next_to_clean = first;
1981         txr->tx_avail = avail;
1982
1983         /*
1984          * If we have a minimum free, clear IFF_OACTIVE
1985          * to tell the stack that it is OK to send packets.
1986          */
1987         if (IGB_IS_NOT_OACTIVE(txr)) {
1988                 ifp->if_flags &= ~IFF_OACTIVE;
1989
1990                 /*
1991                  * We have enough TX descriptors, turn off
1992                  * the watchdog.  We allow small amount of
1993                  * packets (roughly intr_nsegs) pending on
1994                  * the transmit ring.
1995                  */
1996                 ifp->if_timer = 0;
1997         }
1998 }
1999
2000 static int
2001 igb_create_rx_ring(struct igb_rx_ring *rxr)
2002 {
2003         int rsize, i, error;
2004
2005         /*
2006          * Validate number of receive descriptors. It must not exceed
2007          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2008          */
2009         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
2010             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
2011                 device_printf(rxr->sc->dev,
2012                     "Using %d RX descriptors instead of %d!\n",
2013                     IGB_DEFAULT_RXD, igb_rxd);
2014                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2015         } else {
2016                 rxr->num_rx_desc = igb_rxd;
2017         }
2018
2019         /*
2020          * Allocate RX descriptor ring
2021          */
2022         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2023             IGB_DBA_ALIGN);
2024         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2025             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2026             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2027             &rxr->rxdma.dma_paddr);
2028         if (rxr->rxdma.dma_vaddr == NULL) {
2029                 device_printf(rxr->sc->dev,
2030                     "Unable to allocate RxDescriptor memory\n");
2031                 return ENOMEM;
2032         }
2033         rxr->rx_base = rxr->rxdma.dma_vaddr;
2034         bzero(rxr->rx_base, rsize);
2035
2036         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2037             M_DEVBUF, M_WAITOK | M_ZERO);
2038
2039         /*
2040          * Create DMA tag for RX buffers
2041          */
2042         error = bus_dma_tag_create(rxr->sc->parent_tag,
2043             1, 0,               /* alignment, bounds */
2044             BUS_SPACE_MAXADDR,  /* lowaddr */
2045             BUS_SPACE_MAXADDR,  /* highaddr */
2046             NULL, NULL,         /* filter, filterarg */
2047             MCLBYTES,           /* maxsize */
2048             1,                  /* nsegments */
2049             MCLBYTES,           /* maxsegsize */
2050             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2051             &rxr->rx_tag);
2052         if (error) {
2053                 device_printf(rxr->sc->dev,
2054                     "Unable to create RX payload DMA tag\n");
2055                 kfree(rxr->rx_buf, M_DEVBUF);
2056                 rxr->rx_buf = NULL;
2057                 return error;
2058         }
2059
2060         /*
2061          * Create spare DMA map for RX buffers
2062          */
2063         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2064             &rxr->rx_sparemap);
2065         if (error) {
2066                 device_printf(rxr->sc->dev,
2067                     "Unable to create spare RX DMA maps\n");
2068                 bus_dma_tag_destroy(rxr->rx_tag);
2069                 kfree(rxr->rx_buf, M_DEVBUF);
2070                 rxr->rx_buf = NULL;
2071                 return error;
2072         }
2073
2074         /*
2075          * Create DMA maps for RX buffers
2076          */
2077         for (i = 0; i < rxr->num_rx_desc; i++) {
2078                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2079
2080                 error = bus_dmamap_create(rxr->rx_tag,
2081                     BUS_DMA_WAITOK, &rxbuf->map);
2082                 if (error) {
2083                         device_printf(rxr->sc->dev,
2084                             "Unable to create RX DMA maps\n");
2085                         igb_destroy_rx_ring(rxr, i);
2086                         return error;
2087                 }
2088         }
2089         return 0;
2090 }
2091
2092 static void
2093 igb_free_rx_ring(struct igb_rx_ring *rxr)
2094 {
2095         int i;
2096
2097         for (i = 0; i < rxr->num_rx_desc; ++i) {
2098                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2099
2100                 if (rxbuf->m_head != NULL) {
2101                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2102                         m_freem(rxbuf->m_head);
2103                         rxbuf->m_head = NULL;
2104                 }
2105         }
2106
2107         if (rxr->fmp != NULL)
2108                 m_freem(rxr->fmp);
2109         rxr->fmp = NULL;
2110         rxr->lmp = NULL;
2111 }
2112
2113 static void
2114 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2115 {
2116         int i;
2117
2118         if (rxr->rxdma.dma_vaddr != NULL) {
2119                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2120                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2121                     rxr->rxdma.dma_map);
2122                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2123                 rxr->rxdma.dma_vaddr = NULL;
2124         }
2125
2126         if (rxr->rx_buf == NULL)
2127                 return;
2128
2129         for (i = 0; i < ndesc; ++i) {
2130                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2131
2132                 KKASSERT(rxbuf->m_head == NULL);
2133                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2134         }
2135         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2136         bus_dma_tag_destroy(rxr->rx_tag);
2137
2138         kfree(rxr->rx_buf, M_DEVBUF);
2139         rxr->rx_buf = NULL;
2140 }
2141
2142 static void
2143 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2144 {
2145         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2146         rxd->wb.upper.status_error = 0;
2147 }
2148
2149 static int
2150 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2151 {
2152         struct mbuf *m;
2153         bus_dma_segment_t seg;
2154         bus_dmamap_t map;
2155         struct igb_rx_buf *rxbuf;
2156         int error, nseg;
2157
2158         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2159         if (m == NULL) {
2160                 if (wait) {
2161                         if_printf(&rxr->sc->arpcom.ac_if,
2162                             "Unable to allocate RX mbuf\n");
2163                 }
2164                 return ENOBUFS;
2165         }
2166         m->m_len = m->m_pkthdr.len = MCLBYTES;
2167
2168         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2169                 m_adj(m, ETHER_ALIGN);
2170
2171         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2172             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2173         if (error) {
2174                 m_freem(m);
2175                 if (wait) {
2176                         if_printf(&rxr->sc->arpcom.ac_if,
2177                             "Unable to load RX mbuf\n");
2178                 }
2179                 return error;
2180         }
2181
2182         rxbuf = &rxr->rx_buf[i];
2183         if (rxbuf->m_head != NULL)
2184                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2185
2186         map = rxbuf->map;
2187         rxbuf->map = rxr->rx_sparemap;
2188         rxr->rx_sparemap = map;
2189
2190         rxbuf->m_head = m;
2191         rxbuf->paddr = seg.ds_addr;
2192
2193         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2194         return 0;
2195 }
2196
2197 static int
2198 igb_init_rx_ring(struct igb_rx_ring *rxr)
2199 {
2200         int i;
2201
2202         /* Clear the ring contents */
2203         bzero(rxr->rx_base,
2204             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2205
2206         /* Now replenish the ring mbufs */
2207         for (i = 0; i < rxr->num_rx_desc; ++i) {
2208                 int error;
2209
2210                 error = igb_newbuf(rxr, i, TRUE);
2211                 if (error)
2212                         return error;
2213         }
2214
2215         /* Setup our descriptor indices */
2216         rxr->next_to_check = 0;
2217
2218         rxr->fmp = NULL;
2219         rxr->lmp = NULL;
2220         rxr->discard = FALSE;
2221
2222         return 0;
2223 }
2224
2225 static void
2226 igb_init_rx_unit(struct igb_softc *sc)
2227 {
2228         struct ifnet *ifp = &sc->arpcom.ac_if;
2229         struct e1000_hw *hw = &sc->hw;
2230         uint32_t rctl, rxcsum, srrctl = 0;
2231         int i;
2232
2233         /*
2234          * Make sure receives are disabled while setting
2235          * up the descriptor ring
2236          */
2237         rctl = E1000_READ_REG(hw, E1000_RCTL);
2238         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2239
2240 #if 0
2241         /*
2242         ** Set up for header split
2243         */
2244         if (igb_header_split) {
2245                 /* Use a standard mbuf for the header */
2246                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2247                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2248         } else
2249 #endif
2250                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2251
2252         /*
2253         ** Set up for jumbo frames
2254         */
2255         if (ifp->if_mtu > ETHERMTU) {
2256                 rctl |= E1000_RCTL_LPE;
2257 #if 0
2258                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2259                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2260                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2261                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2262                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2263                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2264                 }
2265                 /* Set maximum packet len */
2266                 psize = adapter->max_frame_size;
2267                 /* are we on a vlan? */
2268                 if (adapter->ifp->if_vlantrunk != NULL)
2269                         psize += VLAN_TAG_SIZE;
2270                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2271 #else
2272                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2273                 rctl |= E1000_RCTL_SZ_2048;
2274 #endif
2275         } else {
2276                 rctl &= ~E1000_RCTL_LPE;
2277                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2278                 rctl |= E1000_RCTL_SZ_2048;
2279         }
2280
2281         /* Setup the Base and Length of the Rx Descriptor Rings */
2282         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2283                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2284                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2285                 uint32_t rxdctl;
2286
2287                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2288                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2289                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2290                     (uint32_t)(bus_addr >> 32));
2291                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2292                     (uint32_t)bus_addr);
2293                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2294                 /* Enable this Queue */
2295                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2296                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2297                 rxdctl &= 0xFFF00000;
2298                 rxdctl |= IGB_RX_PTHRESH;
2299                 rxdctl |= IGB_RX_HTHRESH << 8;
2300                 /*
2301                  * Don't set WTHRESH to a value above 1 on 82576, see:
2302                  * 82576 specification update errata #26
2303                  */
2304                 rxdctl |= IGB_RX_WTHRESH << 16;
2305                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2306         }
2307
2308         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2309         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2310
2311         /*
2312          * Receive Checksum Offload for TCP and UDP
2313          *
2314          * Checksum offloading is also enabled if multiple receive
2315          * queue is to be supported, since we need it to figure out
2316          * fragments.
2317          */
2318         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2319                 /*
2320                  * NOTE:
2321                  * PCSD must be enabled to enable multiple
2322                  * receive queues.
2323                  */
2324                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2325                     E1000_RXCSUM_PCSD;
2326         } else {
2327                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2328                     E1000_RXCSUM_PCSD);
2329         }
2330         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2331
2332         if (IGB_ENABLE_HWRSS(sc)) {
2333                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2334                 uint32_t reta_shift;
2335                 int j, r;
2336
2337                 /*
2338                  * NOTE:
2339                  * When we reach here, RSS has already been disabled
2340                  * in igb_stop(), so we could safely configure RSS key
2341                  * and redirect table.
2342                  */
2343
2344                 /*
2345                  * Configure RSS key
2346                  */
2347                 toeplitz_get_key(key, sizeof(key));
2348                 for (i = 0; i < IGB_NRSSRK; ++i) {
2349                         uint32_t rssrk;
2350
2351                         rssrk = IGB_RSSRK_VAL(key, i);
2352                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2353
2354                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2355                 }
2356
2357                 /*
2358                  * Configure RSS redirect table in following fashion:
2359                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2360                  */
2361                 reta_shift = IGB_RETA_SHIFT;
2362                 if (hw->mac.type == e1000_82575)
2363                         reta_shift = IGB_RETA_SHIFT_82575;
2364
2365                 r = 0;
2366                 for (j = 0; j < IGB_NRETA; ++j) {
2367                         uint32_t reta = 0;
2368
2369                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2370                                 uint32_t q;
2371
2372                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2373                                 reta |= q << (8 * i);
2374                                 ++r;
2375                         }
2376                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2377                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2378                 }
2379
2380                 /*
2381                  * Enable multiple receive queues.
2382                  * Enable IPv4 RSS standard hash functions.
2383                  * Disable RSS interrupt on 82575
2384                  */
2385                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2386                                 E1000_MRQC_ENABLE_RSS_4Q |
2387                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2388                                 E1000_MRQC_RSS_FIELD_IPV4);
2389         }
2390
2391         /* Setup the Receive Control Register */
2392         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2393         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2394             E1000_RCTL_RDMTS_HALF |
2395             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2396         /* Strip CRC bytes. */
2397         rctl |= E1000_RCTL_SECRC;
2398         /* Make sure VLAN Filters are off */
2399         rctl &= ~E1000_RCTL_VFE;
2400         /* Don't store bad packets */
2401         rctl &= ~E1000_RCTL_SBP;
2402
2403         /* Enable Receives */
2404         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2405
2406         /*
2407          * Setup the HW Rx Head and Tail Descriptor Pointers
2408          *   - needs to be after enable
2409          */
2410         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2411                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2412
2413                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2414                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2415         }
2416 }
2417
2418 static void
2419 igb_rxeof(struct igb_rx_ring *rxr, int count)
2420 {
2421         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2422         union e1000_adv_rx_desc *cur;
2423         uint32_t staterr;
2424         int i;
2425
2426         i = rxr->next_to_check;
2427         cur = &rxr->rx_base[i];
2428         staterr = le32toh(cur->wb.upper.status_error);
2429
2430         if ((staterr & E1000_RXD_STAT_DD) == 0)
2431                 return;
2432
2433         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2434                 struct pktinfo *pi = NULL, pi0;
2435                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2436                 struct mbuf *m = NULL;
2437                 boolean_t eop;
2438
2439                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2440                 if (eop)
2441                         --count;
2442
2443                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2444                     !rxr->discard) {
2445                         struct mbuf *mp = rxbuf->m_head;
2446                         uint32_t hash, hashtype;
2447                         uint16_t vlan;
2448                         int len;
2449
2450                         len = le16toh(cur->wb.upper.length);
2451                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2452                             (staterr & E1000_RXDEXT_STATERR_LB))
2453                                 vlan = be16toh(cur->wb.upper.vlan);
2454                         else
2455                                 vlan = le16toh(cur->wb.upper.vlan);
2456
2457                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2458                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2459                             E1000_RXDADV_RSSTYPE_MASK;
2460
2461                         IGB_RSS_DPRINTF(rxr->sc, 10,
2462                             "ring%d, hash 0x%08x, hashtype %u\n",
2463                             rxr->me, hash, hashtype);
2464
2465                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2466                             BUS_DMASYNC_POSTREAD);
2467
2468                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2469                                 ifp->if_iqdrops++;
2470                                 goto discard;
2471                         }
2472
2473                         mp->m_len = len;
2474                         if (rxr->fmp == NULL) {
2475                                 mp->m_pkthdr.len = len;
2476                                 rxr->fmp = mp;
2477                                 rxr->lmp = mp;
2478                         } else {
2479                                 rxr->lmp->m_next = mp;
2480                                 rxr->lmp = rxr->lmp->m_next;
2481                                 rxr->fmp->m_pkthdr.len += len;
2482                         }
2483
2484                         if (eop) {
2485                                 m = rxr->fmp;
2486                                 rxr->fmp = NULL;
2487                                 rxr->lmp = NULL;
2488
2489                                 m->m_pkthdr.rcvif = ifp;
2490                                 ifp->if_ipackets++;
2491
2492                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2493                                         igb_rxcsum(staterr, m);
2494
2495                                 if (staterr & E1000_RXD_STAT_VP) {
2496                                         m->m_pkthdr.ether_vlantag = vlan;
2497                                         m->m_flags |= M_VLANTAG;
2498                                 }
2499
2500                                 if (ifp->if_capenable & IFCAP_RSS) {
2501                                         pi = igb_rssinfo(m, &pi0,
2502                                             hash, hashtype, staterr);
2503                                 }
2504 #ifdef IGB_RSS_DEBUG
2505                                 rxr->rx_packets++;
2506 #endif
2507                         }
2508                 } else {
2509                         ifp->if_ierrors++;
2510 discard:
2511                         igb_setup_rxdesc(cur, rxbuf);
2512                         if (!eop)
2513                                 rxr->discard = TRUE;
2514                         else
2515                                 rxr->discard = FALSE;
2516                         if (rxr->fmp != NULL) {
2517                                 m_freem(rxr->fmp);
2518                                 rxr->fmp = NULL;
2519                                 rxr->lmp = NULL;
2520                         }
2521                         m = NULL;
2522                 }
2523
2524                 if (m != NULL)
2525                         ether_input_pkt(ifp, m, pi);
2526
2527                 /* Advance our pointers to the next descriptor. */
2528                 if (++i == rxr->num_rx_desc)
2529                         i = 0;
2530
2531                 cur = &rxr->rx_base[i];
2532                 staterr = le32toh(cur->wb.upper.status_error);
2533         }
2534         rxr->next_to_check = i;
2535
2536         if (--i < 0)
2537                 i = rxr->num_rx_desc - 1;
2538         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2539 }
2540
2541
2542 static void
2543 igb_set_vlan(struct igb_softc *sc)
2544 {
2545         struct e1000_hw *hw = &sc->hw;
2546         uint32_t reg;
2547 #if 0
2548         struct ifnet *ifp = sc->arpcom.ac_if;
2549 #endif
2550
2551         if (sc->vf_ifp) {
2552                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2553                 return;
2554         }
2555
2556         reg = E1000_READ_REG(hw, E1000_CTRL);
2557         reg |= E1000_CTRL_VME;
2558         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2559
2560 #if 0
2561         /* Enable the Filter Table */
2562         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2563                 reg = E1000_READ_REG(hw, E1000_RCTL);
2564                 reg &= ~E1000_RCTL_CFIEN;
2565                 reg |= E1000_RCTL_VFE;
2566                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2567         }
2568 #endif
2569
2570         /* Update the frame size */
2571         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2572             sc->max_frame_size + VLAN_TAG_SIZE);
2573
2574 #if 0
2575         /* Don't bother with table if no vlans */
2576         if ((adapter->num_vlans == 0) ||
2577             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2578                 return;
2579         /*
2580         ** A soft reset zero's out the VFTA, so
2581         ** we need to repopulate it now.
2582         */
2583         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2584                 if (adapter->shadow_vfta[i] != 0) {
2585                         if (adapter->vf_ifp)
2586                                 e1000_vfta_set_vf(hw,
2587                                     adapter->shadow_vfta[i], TRUE);
2588                         else
2589                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2590                                  i, adapter->shadow_vfta[i]);
2591                 }
2592 #endif
2593 }
2594
2595 static void
2596 igb_enable_intr(struct igb_softc *sc)
2597 {
2598         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2599                 lwkt_serialize_handler_enable(&sc->main_serialize);
2600         } else {
2601                 int i;
2602
2603                 for (i = 0; i < sc->msix_cnt; ++i) {
2604                         lwkt_serialize_handler_enable(
2605                             sc->msix_data[i].msix_serialize);
2606                 }
2607         }
2608
2609         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2610                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2611                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2612                 else
2613                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2614                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2615                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2616                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2617         } else {
2618                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2619         }
2620         E1000_WRITE_FLUSH(&sc->hw);
2621 }
2622
2623 static void
2624 igb_disable_intr(struct igb_softc *sc)
2625 {
2626         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2627                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2628                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2629         }
2630         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2631         E1000_WRITE_FLUSH(&sc->hw);
2632
2633         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2634                 lwkt_serialize_handler_disable(&sc->main_serialize);
2635         } else {
2636                 int i;
2637
2638                 for (i = 0; i < sc->msix_cnt; ++i) {
2639                         lwkt_serialize_handler_disable(
2640                             sc->msix_data[i].msix_serialize);
2641                 }
2642         }
2643 }
2644
2645 /*
2646  * Bit of a misnomer, what this really means is
2647  * to enable OS management of the system... aka
2648  * to disable special hardware management features 
2649  */
2650 static void
2651 igb_get_mgmt(struct igb_softc *sc)
2652 {
2653         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2654                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2655                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2656
2657                 /* disable hardware interception of ARP */
2658                 manc &= ~E1000_MANC_ARP_EN;
2659
2660                 /* enable receiving management packets to the host */
2661                 manc |= E1000_MANC_EN_MNG2HOST;
2662                 manc2h |= 1 << 5; /* Mng Port 623 */
2663                 manc2h |= 1 << 6; /* Mng Port 664 */
2664                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2665                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2666         }
2667 }
2668
2669 /*
2670  * Give control back to hardware management controller
2671  * if there is one.
2672  */
2673 static void
2674 igb_rel_mgmt(struct igb_softc *sc)
2675 {
2676         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2677                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2678
2679                 /* Re-enable hardware interception of ARP */
2680                 manc |= E1000_MANC_ARP_EN;
2681                 manc &= ~E1000_MANC_EN_MNG2HOST;
2682
2683                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2684         }
2685 }
2686
2687 /*
2688  * Sets CTRL_EXT:DRV_LOAD bit.
2689  *
2690  * For ASF and Pass Through versions of f/w this means that
2691  * the driver is loaded. 
2692  */
2693 static void
2694 igb_get_hw_control(struct igb_softc *sc)
2695 {
2696         uint32_t ctrl_ext;
2697
2698         if (sc->vf_ifp)
2699                 return;
2700
2701         /* Let firmware know the driver has taken over */
2702         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2703         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2704             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2705 }
2706
2707 /*
2708  * Resets CTRL_EXT:DRV_LOAD bit.
2709  *
2710  * For ASF and Pass Through versions of f/w this means that the
2711  * driver is no longer loaded.
2712  */
2713 static void
2714 igb_rel_hw_control(struct igb_softc *sc)
2715 {
2716         uint32_t ctrl_ext;
2717
2718         if (sc->vf_ifp)
2719                 return;
2720
2721         /* Let firmware taken over control of h/w */
2722         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2723         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2724             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2725 }
2726
2727 static int
2728 igb_is_valid_ether_addr(const uint8_t *addr)
2729 {
2730         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2731
2732         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2733                 return FALSE;
2734         return TRUE;
2735 }
2736
2737 /*
2738  * Enable PCI Wake On Lan capability
2739  */
2740 static void
2741 igb_enable_wol(device_t dev)
2742 {
2743         uint16_t cap, status;
2744         uint8_t id;
2745
2746         /* First find the capabilities pointer*/
2747         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2748
2749         /* Read the PM Capabilities */
2750         id = pci_read_config(dev, cap, 1);
2751         if (id != PCIY_PMG)     /* Something wrong */
2752                 return;
2753
2754         /*
2755          * OK, we have the power capabilities,
2756          * so now get the status register
2757          */
2758         cap += PCIR_POWER_STATUS;
2759         status = pci_read_config(dev, cap, 2);
2760         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2761         pci_write_config(dev, cap, status, 2);
2762 }
2763
2764 static void
2765 igb_update_stats_counters(struct igb_softc *sc)
2766 {
2767         struct e1000_hw *hw = &sc->hw;
2768         struct e1000_hw_stats *stats;
2769         struct ifnet *ifp = &sc->arpcom.ac_if;
2770
2771         /* 
2772          * The virtual function adapter has only a
2773          * small controlled set of stats, do only 
2774          * those and return.
2775          */
2776         if (sc->vf_ifp) {
2777                 igb_update_vf_stats_counters(sc);
2778                 return;
2779         }
2780         stats = sc->stats;
2781
2782         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2783             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2784                 stats->symerrs +=
2785                     E1000_READ_REG(hw,E1000_SYMERRS);
2786                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2787         }
2788
2789         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2790         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2791         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2792         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2793
2794         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2795         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2796         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2797         stats->dc += E1000_READ_REG(hw, E1000_DC);
2798         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2799         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2800         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2801
2802         /*
2803          * For watchdog management we need to know if we have been
2804          * paused during the last interval, so capture that here.
2805          */ 
2806         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2807         stats->xoffrxc += sc->pause_frames;
2808         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2809         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2810         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2811         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2812         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2813         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2814         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2815         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2816         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2817         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2818         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2819         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2820
2821         /* For the 64-bit byte counters the low dword must be read first. */
2822         /* Both registers clear on the read of the high dword */
2823
2824         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2825             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2826         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2827             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2828
2829         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2830         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2831         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2832         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2833         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2834
2835         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2836         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2837
2838         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2839         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2840         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2841         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2842         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2843         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2844         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2845         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2846         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2847         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2848
2849         /* Interrupt Counts */
2850
2851         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2852         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2853         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2854         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2855         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2856         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2857         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2858         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2859         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2860
2861         /* Host to Card Statistics */
2862
2863         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2864         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2865         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2866         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2867         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2868         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2869         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2870         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2871             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2872         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2873             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2874         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2875         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2876         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2877
2878         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2879         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2880         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2881         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2882         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2883         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2884
2885         ifp->if_collisions = stats->colc;
2886
2887         /* Rx Errors */
2888         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2889             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2890
2891         /* Tx Errors */
2892         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2893
2894         /* Driver specific counters */
2895         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2896         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2897         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2898         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2899         sc->packet_buf_alloc_tx =
2900             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2901         sc->packet_buf_alloc_rx =
2902             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2903 }
2904
2905 static void
2906 igb_vf_init_stats(struct igb_softc *sc)
2907 {
2908         struct e1000_hw *hw = &sc->hw;
2909         struct e1000_vf_stats *stats;
2910
2911         stats = sc->stats;
2912         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2913         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2914         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2915         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2916         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2917 }
2918  
2919 static void
2920 igb_update_vf_stats_counters(struct igb_softc *sc)
2921 {
2922         struct e1000_hw *hw = &sc->hw;
2923         struct e1000_vf_stats *stats;
2924
2925         if (sc->link_speed == 0)
2926                 return;
2927
2928         stats = sc->stats;
2929         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2930         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2931         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2932         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2933         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2934 }
2935
2936 #ifdef IFPOLL_ENABLE
2937
2938 static void
2939 igb_npoll_status(struct ifnet *ifp, int pollhz __unused)
2940 {
2941         struct igb_softc *sc = ifp->if_softc;
2942         uint32_t reg_icr;
2943
2944         ASSERT_SERIALIZED(&sc->main_serialize);
2945
2946         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2947         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2948                 sc->hw.mac.get_link_status = 1;
2949                 igb_update_link_status(sc);
2950         }
2951 }
2952
2953 static void
2954 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2955 {
2956         struct igb_tx_ring *txr = arg;
2957
2958         ASSERT_SERIALIZED(&txr->tx_serialize);
2959
2960         igb_txeof(txr);
2961         if (!ifq_is_empty(&ifp->if_snd))
2962                 if_devstart(ifp);
2963 }
2964
2965 static void
2966 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
2967 {
2968         struct igb_rx_ring *rxr = arg;
2969
2970         ASSERT_SERIALIZED(&rxr->rx_serialize);
2971
2972         igb_rxeof(rxr, cycle);
2973 }
2974
2975 static void
2976 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2977 {
2978         struct igb_softc *sc = ifp->if_softc;
2979
2980         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2981
2982         if (info) {
2983                 struct igb_tx_ring *txr;
2984                 int i, off;
2985
2986                 info->ifpi_status.status_func = igb_npoll_status;
2987                 info->ifpi_status.serializer = &sc->main_serialize;
2988
2989                 off = sc->tx_npoll_off;
2990                 KKASSERT(off < ncpus2);
2991                 txr = &sc->tx_rings[0];
2992                 info->ifpi_tx[off].poll_func = igb_npoll_tx;
2993                 info->ifpi_tx[off].arg = txr;
2994                 info->ifpi_tx[off].serializer = &txr->tx_serialize;
2995
2996                 off = sc->rx_npoll_off;
2997                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2998                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2999                         int idx = i + off;
3000
3001                         KKASSERT(idx < ncpus2);
3002                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3003                         info->ifpi_rx[idx].arg = rxr;
3004                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3005                 }
3006
3007                 if (ifp->if_flags & IFF_RUNNING) {
3008                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3009                                 igb_disable_intr(sc);
3010                         else
3011                                 igb_init(sc);
3012                 }
3013                 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3014         } else {
3015                 if (ifp->if_flags & IFF_RUNNING) {
3016                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3017                                 igb_enable_intr(sc);
3018                         else
3019                                 igb_init(sc);
3020                 }
3021                 ifp->if_npoll_cpuid = -1;
3022         }
3023 }
3024
3025 #endif /* IFPOLL_ENABLE */
3026
3027 static void
3028 igb_intr(void *xsc)
3029 {
3030         struct igb_softc *sc = xsc;
3031         struct ifnet *ifp = &sc->arpcom.ac_if;
3032         uint32_t eicr;
3033
3034         ASSERT_SERIALIZED(&sc->main_serialize);
3035
3036         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3037
3038         if (eicr == 0)
3039                 return;
3040
3041         if (ifp->if_flags & IFF_RUNNING) {
3042                 struct igb_tx_ring *txr;
3043                 int i;
3044
3045                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3046                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3047
3048                         if (eicr & rxr->rx_intr_mask) {
3049                                 lwkt_serialize_enter(&rxr->rx_serialize);
3050                                 igb_rxeof(rxr, -1);
3051                                 lwkt_serialize_exit(&rxr->rx_serialize);
3052                         }
3053                 }
3054
3055                 txr = &sc->tx_rings[0];
3056                 if (eicr & txr->tx_intr_mask) {
3057                         lwkt_serialize_enter(&txr->tx_serialize);
3058                         igb_txeof(txr);
3059                         if (!ifq_is_empty(&ifp->if_snd))
3060                                 if_devstart(ifp);
3061                         lwkt_serialize_exit(&txr->tx_serialize);
3062                 }
3063         }
3064
3065         if (eicr & E1000_EICR_OTHER) {
3066                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3067
3068                 /* Link status change */
3069                 if (icr & E1000_ICR_LSC) {
3070                         sc->hw.mac.get_link_status = 1;
3071                         igb_update_link_status(sc);
3072                 }
3073         }
3074
3075         /*
3076          * Reading EICR has the side effect to clear interrupt mask,
3077          * so all interrupts need to be enabled here.
3078          */
3079         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3080 }
3081
3082 static void
3083 igb_intr_shared(void *xsc)
3084 {
3085         struct igb_softc *sc = xsc;
3086         struct ifnet *ifp = &sc->arpcom.ac_if;
3087         uint32_t reg_icr;
3088
3089         ASSERT_SERIALIZED(&sc->main_serialize);
3090
3091         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3092
3093         /* Hot eject?  */
3094         if (reg_icr == 0xffffffff)
3095                 return;
3096
3097         /* Definitely not our interrupt.  */
3098         if (reg_icr == 0x0)
3099                 return;
3100
3101         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3102                 return;
3103
3104         if (ifp->if_flags & IFF_RUNNING) {
3105                 if (reg_icr &
3106                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3107                         int i;
3108
3109                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3110                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3111
3112                                 lwkt_serialize_enter(&rxr->rx_serialize);
3113                                 igb_rxeof(rxr, -1);
3114                                 lwkt_serialize_exit(&rxr->rx_serialize);
3115                         }
3116                 }
3117
3118                 if (reg_icr & E1000_ICR_TXDW) {
3119                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3120
3121                         lwkt_serialize_enter(&txr->tx_serialize);
3122                         igb_txeof(txr);
3123                         if (!ifq_is_empty(&ifp->if_snd))
3124                                 if_devstart(ifp);
3125                         lwkt_serialize_exit(&txr->tx_serialize);
3126                 }
3127         }
3128
3129         /* Link status change */
3130         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3131                 sc->hw.mac.get_link_status = 1;
3132                 igb_update_link_status(sc);
3133         }
3134
3135         if (reg_icr & E1000_ICR_RXO)
3136                 sc->rx_overruns++;
3137 }
3138
3139 static int
3140 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3141 {
3142         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3143         bus_dmamap_t map;
3144         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3145         union e1000_adv_tx_desc *txd = NULL;
3146         struct mbuf *m_head = *m_headp;
3147         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3148         int maxsegs, nsegs, i, j, error, last = 0;
3149         uint32_t hdrlen = 0;
3150
3151         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3152                 error = igb_tso_pullup(txr, m_headp);
3153                 if (error)
3154                         return error;
3155                 m_head = *m_headp;
3156         }
3157
3158         /* Set basic descriptor constants */
3159         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3160         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3161         if (m_head->m_flags & M_VLANTAG)
3162                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3163
3164         /*
3165          * Map the packet for DMA.
3166          */
3167         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3168         tx_buf_mapped = tx_buf;
3169         map = tx_buf->map;
3170
3171         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3172         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3173         if (maxsegs > IGB_MAX_SCATTER)
3174                 maxsegs = IGB_MAX_SCATTER;
3175
3176         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3177             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3178         if (error) {
3179                 if (error == ENOBUFS)
3180                         txr->sc->mbuf_defrag_failed++;
3181                 else
3182                         txr->sc->no_tx_dma_setup++;
3183
3184                 m_freem(*m_headp);
3185                 *m_headp = NULL;
3186                 return error;
3187         }
3188         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3189
3190         m_head = *m_headp;
3191
3192         /*
3193          * Set up the TX context descriptor, if any hardware offloading is
3194          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3195          * TX descriptor.
3196          *
3197          * Unlike these chips' predecessors (em/emx), TX context descriptor
3198          * will _not_ interfere TX data fetching pipelining.
3199          */
3200         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3201                 igb_tso_ctx(txr, m_head, &hdrlen);
3202                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3203                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3204                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3205                 txr->tx_nsegs++;
3206         } else if (igb_txcsum_ctx(txr, m_head)) {
3207                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3208                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3209                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3210                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3211                 txr->tx_nsegs++;
3212         }
3213
3214         txr->tx_nsegs += nsegs;
3215         if (txr->tx_nsegs >= txr->intr_nsegs) {
3216                 /*
3217                  * Report Status (RS) is turned on every intr_nsegs
3218                  * descriptors (roughly).
3219                  */
3220                 txr->tx_nsegs = 0;
3221                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3222         }
3223
3224         /* Calculate payload length */
3225         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3226             << E1000_ADVTXD_PAYLEN_SHIFT);
3227
3228         /* 82575 needs the queue index added */
3229         if (txr->sc->hw.mac.type == e1000_82575)
3230                 olinfo_status |= txr->me << 4;
3231
3232         /* Set up our transmit descriptors */
3233         i = txr->next_avail_desc;
3234         for (j = 0; j < nsegs; j++) {
3235                 bus_size_t seg_len;
3236                 bus_addr_t seg_addr;
3237
3238                 tx_buf = &txr->tx_buf[i];
3239                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3240                 seg_addr = segs[j].ds_addr;
3241                 seg_len = segs[j].ds_len;
3242
3243                 txd->read.buffer_addr = htole64(seg_addr);
3244                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3245                 txd->read.olinfo_status = htole32(olinfo_status);
3246                 last = i;
3247                 if (++i == txr->num_tx_desc)
3248                         i = 0;
3249                 tx_buf->m_head = NULL;
3250         }
3251
3252         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3253         txr->next_avail_desc = i;
3254         txr->tx_avail -= nsegs;
3255
3256         tx_buf->m_head = m_head;
3257         tx_buf_mapped->map = tx_buf->map;
3258         tx_buf->map = map;
3259
3260         /*
3261          * Last Descriptor of Packet needs End Of Packet (EOP)
3262          */
3263         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3264
3265         /*
3266          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3267          * that this frame is available to transmit.
3268          */
3269         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3270         ++txr->tx_packets;
3271
3272         return 0;
3273 }
3274
3275 static void
3276 igb_start(struct ifnet *ifp)
3277 {
3278         struct igb_softc *sc = ifp->if_softc;
3279         struct igb_tx_ring *txr = &sc->tx_rings[0];
3280         struct mbuf *m_head;
3281
3282         ASSERT_SERIALIZED(&txr->tx_serialize);
3283
3284         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3285                 return;
3286
3287         if (!sc->link_active) {
3288                 ifq_purge(&ifp->if_snd);
3289                 return;
3290         }
3291
3292         if (!IGB_IS_NOT_OACTIVE(txr))
3293                 igb_txeof(txr);
3294
3295         while (!ifq_is_empty(&ifp->if_snd)) {
3296                 if (IGB_IS_OACTIVE(txr)) {
3297                         ifp->if_flags |= IFF_OACTIVE;
3298                         /* Set watchdog on */
3299                         ifp->if_timer = 5;
3300                         break;
3301                 }
3302
3303                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3304                 if (m_head == NULL)
3305                         break;
3306
3307                 if (igb_encap(txr, &m_head)) {
3308                         ifp->if_oerrors++;
3309                         continue;
3310                 }
3311
3312                 /* Send a copy of the frame to the BPF listener */
3313                 ETHER_BPF_MTAP(ifp, m_head);
3314         }
3315 }
3316
3317 static void
3318 igb_watchdog(struct ifnet *ifp)
3319 {
3320         struct igb_softc *sc = ifp->if_softc;
3321         struct igb_tx_ring *txr = &sc->tx_rings[0];
3322
3323         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3324
3325         /* 
3326          * If flow control has paused us since last checking
3327          * it invalidates the watchdog timing, so dont run it.
3328          */
3329         if (sc->pause_frames) {
3330                 sc->pause_frames = 0;
3331                 ifp->if_timer = 5;
3332                 return;
3333         }
3334
3335         if_printf(ifp, "Watchdog timeout -- resetting\n");
3336         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3337             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3338             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3339         if_printf(ifp, "TX(%d) desc avail = %d, "
3340             "Next TX to Clean = %d\n",
3341             txr->me, txr->tx_avail, txr->next_to_clean);
3342
3343         ifp->if_oerrors++;
3344         sc->watchdog_events++;
3345
3346         igb_init(sc);
3347         if (!ifq_is_empty(&ifp->if_snd))
3348                 if_devstart(ifp);
3349 }
3350
3351 static void
3352 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3353 {
3354         uint32_t eitr = 0;
3355
3356         if (rate > 0) {
3357                 if (sc->hw.mac.type == e1000_82575) {
3358                         eitr = 1000000000 / 256 / rate;
3359                         /*
3360                          * NOTE:
3361                          * Document is wrong on the 2 bits left shift
3362                          */
3363                 } else {
3364                         eitr = 1000000 / rate;
3365                         eitr <<= IGB_EITR_INTVL_SHIFT;
3366                 }
3367
3368                 if (eitr == 0) {
3369                         /* Don't disable it */
3370                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3371                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3372                         /* Don't allow it to be too large */
3373                         eitr = IGB_EITR_INTVL_MASK;
3374                 }
3375         }
3376         if (sc->hw.mac.type == e1000_82575)
3377                 eitr |= eitr << 16;
3378         else
3379                 eitr |= E1000_EITR_CNT_IGNR;
3380         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3381 }
3382
3383 static int
3384 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3385 {
3386         struct igb_softc *sc = (void *)arg1;
3387         struct ifnet *ifp = &sc->arpcom.ac_if;
3388         int error, intr_rate;
3389
3390         intr_rate = sc->intr_rate;
3391         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3392         if (error || req->newptr == NULL)
3393                 return error;
3394         if (intr_rate < 0)
3395                 return EINVAL;
3396
3397         ifnet_serialize_all(ifp);
3398
3399         sc->intr_rate = intr_rate;
3400         if (ifp->if_flags & IFF_RUNNING)
3401                 igb_set_eitr(sc, 0, sc->intr_rate);
3402
3403         if (bootverbose)
3404                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3405
3406         ifnet_deserialize_all(ifp);
3407
3408         return 0;
3409 }
3410
3411 static int
3412 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3413 {
3414         struct igb_msix_data *msix = (void *)arg1;
3415         struct igb_softc *sc = msix->msix_sc;
3416         struct ifnet *ifp = &sc->arpcom.ac_if;
3417         int error, msix_rate;
3418
3419         msix_rate = msix->msix_rate;
3420         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3421         if (error || req->newptr == NULL)
3422                 return error;
3423         if (msix_rate < 0)
3424                 return EINVAL;
3425
3426         lwkt_serialize_enter(msix->msix_serialize);
3427
3428         msix->msix_rate = msix_rate;
3429         if (ifp->if_flags & IFF_RUNNING)
3430                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3431
3432         if (bootverbose) {
3433                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3434                     msix->msix_rate);
3435         }
3436
3437         lwkt_serialize_exit(msix->msix_serialize);
3438
3439         return 0;
3440 }
3441
3442 static int
3443 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3444 {
3445         struct igb_softc *sc = (void *)arg1;
3446         struct ifnet *ifp = &sc->arpcom.ac_if;
3447         struct igb_tx_ring *txr = &sc->tx_rings[0];
3448         int error, nsegs;
3449
3450         nsegs = txr->intr_nsegs;
3451         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3452         if (error || req->newptr == NULL)
3453                 return error;
3454         if (nsegs <= 0)
3455                 return EINVAL;
3456
3457         ifnet_serialize_all(ifp);
3458
3459         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3460             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3461                 error = EINVAL;
3462         } else {
3463                 error = 0;
3464                 txr->intr_nsegs = nsegs;
3465         }
3466
3467         ifnet_deserialize_all(ifp);
3468
3469         return error;
3470 }
3471
3472 #ifdef IFPOLL_ENABLE
3473
3474 static int
3475 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3476 {
3477         struct igb_softc *sc = (void *)arg1;
3478         struct ifnet *ifp = &sc->arpcom.ac_if;
3479         int error, off;
3480
3481         off = sc->rx_npoll_off;
3482         error = sysctl_handle_int(oidp, &off, 0, req);
3483         if (error || req->newptr == NULL)
3484                 return error;
3485         if (off < 0)
3486                 return EINVAL;
3487
3488         ifnet_serialize_all(ifp);
3489         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3490                 error = EINVAL;
3491         } else {
3492                 error = 0;
3493                 sc->rx_npoll_off = off;
3494         }
3495         ifnet_deserialize_all(ifp);
3496
3497         return error;
3498 }
3499
3500 static int
3501 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3502 {
3503         struct igb_softc *sc = (void *)arg1;
3504         struct ifnet *ifp = &sc->arpcom.ac_if;
3505         int error, off;
3506
3507         off = sc->tx_npoll_off;
3508         error = sysctl_handle_int(oidp, &off, 0, req);
3509         if (error || req->newptr == NULL)
3510                 return error;
3511         if (off < 0)
3512                 return EINVAL;
3513
3514         ifnet_serialize_all(ifp);
3515         if (off >= ncpus2) {
3516                 error = EINVAL;
3517         } else {
3518                 error = 0;
3519                 sc->tx_npoll_off = off;
3520         }
3521         ifnet_deserialize_all(ifp);
3522
3523         return error;
3524 }
3525
3526 #endif  /* IFPOLL_ENABLE */
3527
3528 static void
3529 igb_init_intr(struct igb_softc *sc)
3530 {
3531         igb_set_intr_mask(sc);
3532
3533         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3534                 igb_init_unshared_intr(sc);
3535
3536         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3537                 igb_set_eitr(sc, 0, sc->intr_rate);
3538         } else {
3539                 int i;
3540
3541                 for (i = 0; i < sc->msix_cnt; ++i)
3542                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3543         }
3544 }
3545
3546 static void
3547 igb_init_unshared_intr(struct igb_softc *sc)
3548 {
3549         struct e1000_hw *hw = &sc->hw;
3550         const struct igb_rx_ring *rxr;
3551         const struct igb_tx_ring *txr;
3552         uint32_t ivar, index;
3553         int i;
3554
3555         /*
3556          * Enable extended mode
3557          */
3558         if (sc->hw.mac.type != e1000_82575) {
3559                 uint32_t gpie;
3560                 int ivar_max;
3561
3562                 gpie = E1000_GPIE_NSICR;
3563                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3564                         gpie |= E1000_GPIE_MSIX_MODE |
3565                             E1000_GPIE_EIAME |
3566                             E1000_GPIE_PBA;
3567                 }
3568                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3569
3570                 /*
3571                  * Clear IVARs
3572                  */
3573                 switch (sc->hw.mac.type) {
3574                 case e1000_82580:
3575                         ivar_max = IGB_MAX_IVAR_82580;
3576                         break;
3577
3578                 case e1000_i350:
3579                         ivar_max = IGB_MAX_IVAR_I350;
3580                         break;
3581
3582                 case e1000_vfadapt:
3583                 case e1000_vfadapt_i350:
3584                         ivar_max = IGB_MAX_IVAR_VF;
3585                         break;
3586
3587                 case e1000_82576:
3588                         ivar_max = IGB_MAX_IVAR_82576;
3589                         break;
3590
3591                 default:
3592                         panic("unknown mac type %d\n", sc->hw.mac.type);
3593                 }
3594                 for (i = 0; i < ivar_max; ++i)
3595                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3596                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3597         } else {
3598                 uint32_t tmp;
3599
3600                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3601                     ("82575 w/ MSI-X"));
3602                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3603                 tmp |= E1000_CTRL_EXT_IRCA;
3604                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3605         }
3606
3607         /*
3608          * Map TX/RX interrupts to EICR
3609          */
3610         switch (sc->hw.mac.type) {
3611         case e1000_82580:
3612         case e1000_i350:
3613         case e1000_vfadapt:
3614         case e1000_vfadapt_i350:
3615                 /* RX entries */
3616                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3617                         rxr = &sc->rx_rings[i];
3618
3619                         index = i >> 1;
3620                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3621
3622                         if (i & 1) {
3623                                 ivar &= 0xff00ffff;
3624                                 ivar |=
3625                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3626                         } else {
3627                                 ivar &= 0xffffff00;
3628                                 ivar |=
3629                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3630                         }
3631                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3632                 }
3633                 /* TX entries */
3634                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3635                         txr = &sc->tx_rings[i];
3636
3637                         index = i >> 1;
3638                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3639
3640                         if (i & 1) {
3641                                 ivar &= 0x00ffffff;
3642                                 ivar |=
3643                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3644                         } else {
3645                                 ivar &= 0xffff00ff;
3646                                 ivar |=
3647                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3648                         }
3649                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3650                 }
3651                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3652                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3653                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3654                 }
3655                 break;
3656
3657         case e1000_82576:
3658                 /* RX entries */
3659                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3660                         rxr = &sc->rx_rings[i];
3661
3662                         index = i & 0x7; /* Each IVAR has two entries */
3663                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3664
3665                         if (i < 8) {
3666                                 ivar &= 0xffffff00;
3667                                 ivar |=
3668                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3669                         } else {
3670                                 ivar &= 0xff00ffff;
3671                                 ivar |=
3672                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3673                         }
3674                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3675                 }
3676                 /* TX entries */
3677                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3678                         txr = &sc->tx_rings[i];
3679
3680                         index = i & 0x7; /* Each IVAR has two entries */
3681                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3682
3683                         if (i < 8) {
3684                                 ivar &= 0xffff00ff;
3685                                 ivar |=
3686                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3687                         } else {
3688                                 ivar &= 0x00ffffff;
3689                                 ivar |=
3690                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3691                         }
3692                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3693                 }
3694                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3695                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3696                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3697                 }
3698                 break;
3699
3700         case e1000_82575:
3701                 /*
3702                  * Enable necessary interrupt bits.
3703                  *
3704                  * The name of the register is confusing; in addition to
3705                  * configuring the first vector of MSI-X, it also configures
3706                  * which bits of EICR could be set by the hardware even when
3707                  * MSI or line interrupt is used; it thus controls interrupt
3708                  * generation.  It MUST be configured explicitly; the default
3709                  * value mentioned in the datasheet is wrong: RX queue0 and
3710                  * TX queue0 are NOT enabled by default.
3711                  */
3712                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3713                 break;
3714
3715         default:
3716                 panic("unknown mac type %d\n", sc->hw.mac.type);
3717         }
3718 }
3719
3720 static int
3721 igb_setup_intr(struct igb_softc *sc)
3722 {
3723         struct ifnet *ifp = &sc->arpcom.ac_if;
3724         int error;
3725
3726         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3727                 return igb_msix_setup(sc);
3728
3729         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3730             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3731             sc, &sc->intr_tag, &sc->main_serialize);
3732         if (error) {
3733                 device_printf(sc->dev, "Failed to register interrupt handler");
3734                 return error;
3735         }
3736
3737         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3738         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3739
3740         return 0;
3741 }
3742
3743 static void
3744 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3745 {
3746         if (txr->sc->hw.mac.type == e1000_82575) {
3747                 txr->tx_intr_bit = 0;   /* unused */
3748                 switch (txr->me) {
3749                 case 0:
3750                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3751                         break;
3752                 case 1:
3753                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3754                         break;
3755                 case 2:
3756                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3757                         break;
3758                 case 3:
3759                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3760                         break;
3761                 default:
3762                         panic("unsupported # of TX ring, %d\n", txr->me);
3763                 }
3764         } else {
3765                 int intr_bit = *intr_bit0;
3766
3767                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3768                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3769
3770                 *intr_bit0 = intr_bit + 1;
3771         }
3772 }
3773
3774 static void
3775 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3776 {
3777         if (rxr->sc->hw.mac.type == e1000_82575) {
3778                 rxr->rx_intr_bit = 0;   /* unused */
3779                 switch (rxr->me) {
3780                 case 0:
3781                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3782                         break;
3783                 case 1:
3784                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3785                         break;
3786                 case 2:
3787                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3788                         break;
3789                 case 3:
3790                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3791                         break;
3792                 default:
3793                         panic("unsupported # of RX ring, %d\n", rxr->me);
3794                 }
3795         } else {
3796                 int intr_bit = *intr_bit0;
3797
3798                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3799                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3800
3801                 *intr_bit0 = intr_bit + 1;
3802         }
3803 }
3804
3805 static void
3806 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3807 {
3808         struct igb_softc *sc = ifp->if_softc;
3809
3810         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3811             sc->tx_serialize, sc->rx_serialize, slz);
3812 }
3813
3814 static void
3815 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3816 {
3817         struct igb_softc *sc = ifp->if_softc;
3818
3819         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3820             sc->tx_serialize, sc->rx_serialize, slz);
3821 }
3822
3823 static int
3824 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3825 {
3826         struct igb_softc *sc = ifp->if_softc;
3827
3828         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3829             sc->tx_serialize, sc->rx_serialize, slz);
3830 }
3831
3832 #ifdef INVARIANTS
3833
3834 static void
3835 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3836     boolean_t serialized)
3837 {
3838         struct igb_softc *sc = ifp->if_softc;
3839
3840         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3841             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3842 }
3843
3844 #endif  /* INVARIANTS */
3845
3846 static void
3847 igb_set_intr_mask(struct igb_softc *sc)
3848 {
3849         int i;
3850
3851         sc->intr_mask = sc->sts_intr_mask;
3852         for (i = 0; i < sc->rx_ring_inuse; ++i)
3853                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3854         for (i = 0; i < sc->tx_ring_cnt; ++i)
3855                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3856         if (bootverbose) {
3857                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3858                     sc->intr_mask);
3859         }
3860 }
3861
3862 static int
3863 igb_alloc_intr(struct igb_softc *sc)
3864 {
3865         int i, intr_bit, intr_bitmax;
3866         u_int intr_flags;
3867
3868         igb_msix_try_alloc(sc);
3869         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3870                 goto done;
3871
3872         /*
3873          * Allocate MSI/legacy interrupt resource
3874          */
3875         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3876             &sc->intr_rid, &intr_flags);
3877
3878         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3879                 int unshared;
3880
3881                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3882                 if (!unshared) {
3883                         sc->flags |= IGB_FLAG_SHARED_INTR;
3884                         if (bootverbose)
3885                                 device_printf(sc->dev, "IRQ shared\n");
3886                 } else {
3887                         intr_flags &= ~RF_SHAREABLE;
3888                         if (bootverbose)
3889                                 device_printf(sc->dev, "IRQ unshared\n");
3890                 }
3891         }
3892
3893         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3894             &sc->intr_rid, intr_flags);
3895         if (sc->intr_res == NULL) {
3896                 device_printf(sc->dev, "Unable to allocate bus resource: "
3897                     "interrupt\n");
3898                 return ENXIO;
3899         }
3900
3901         /*
3902          * Setup MSI/legacy interrupt mask
3903          */
3904         switch (sc->hw.mac.type) {
3905         case e1000_82575:
3906                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3907                 break;
3908         case e1000_82580:
3909                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3910                 break;
3911         case e1000_i350:
3912                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3913                 break;
3914         case e1000_82576:
3915                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3916                 break;
3917         default:
3918                 intr_bitmax = IGB_MIN_TXRXINT;
3919                 break;
3920         }
3921         intr_bit = 0;
3922         for (i = 0; i < sc->tx_ring_cnt; ++i)
3923                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3924         for (i = 0; i < sc->rx_ring_cnt; ++i)
3925                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3926         sc->sts_intr_bit = 0;
3927         sc->sts_intr_mask = E1000_EICR_OTHER;
3928
3929         /* Initialize interrupt rate */
3930         sc->intr_rate = IGB_INTR_RATE;
3931 done:
3932         igb_set_ring_inuse(sc, FALSE);
3933         igb_set_intr_mask(sc);
3934         return 0;
3935 }
3936
3937 static void
3938 igb_free_intr(struct igb_softc *sc)
3939 {
3940         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3941                 if (sc->intr_res != NULL) {
3942                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3943                             sc->intr_res);
3944                 }
3945                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3946                         pci_release_msi(sc->dev);
3947         } else {
3948                 igb_msix_free(sc, TRUE);
3949         }
3950 }
3951
3952 static void
3953 igb_teardown_intr(struct igb_softc *sc)
3954 {
3955         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3956                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3957         else
3958                 igb_msix_teardown(sc, sc->msix_cnt);
3959 }
3960
3961 static void
3962 igb_msix_try_alloc(struct igb_softc *sc)
3963 {
3964         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3965         int i, x, error;
3966         struct igb_msix_data *msix;
3967         boolean_t aggregate, setup = FALSE;
3968
3969         /*
3970          * Don't enable MSI-X on 82575, see:
3971          * 82575 specification update errata #25
3972          */
3973         if (sc->hw.mac.type == e1000_82575)
3974                 return;
3975
3976         /* Don't enable MSI-X on VF */
3977         if (sc->vf_ifp)
3978                 return;
3979
3980         msix_enable = device_getenv_int(sc->dev, "msix.enable",
3981             igb_msix_enable);
3982         if (!msix_enable)
3983                 return;
3984
3985         msix_cnt = pci_msix_count(sc->dev);
3986 #ifdef IGB_MSIX_DEBUG
3987         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3988 #endif
3989         if (msix_cnt <= 1) {
3990                 /* One MSI-X model does not make sense */
3991                 return;
3992         }
3993
3994         i = 0;
3995         while ((1 << (i + 1)) <= msix_cnt)
3996                 ++i;
3997         msix_cnt2 = 1 << i;
3998
3999         if (bootverbose) {
4000                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4001                     msix_cnt2, msix_cnt);
4002         }
4003
4004         KKASSERT(msix_cnt2 <= msix_cnt);
4005         if (msix_cnt == msix_cnt2) {
4006                 /* We need at least one MSI-X for link status */
4007                 msix_cnt2 >>= 1;
4008                 if (msix_cnt2 <= 1) {
4009                         /* One MSI-X for RX/TX does not make sense */
4010                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4011                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4012                         return;
4013                 }
4014                 KKASSERT(msix_cnt > msix_cnt2);
4015
4016                 if (bootverbose) {
4017                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4018                             msix_cnt2, msix_cnt);
4019                 }
4020         }
4021
4022         sc->rx_ring_msix = sc->rx_ring_cnt;
4023         if (sc->rx_ring_msix > msix_cnt2)
4024                 sc->rx_ring_msix = msix_cnt2;
4025
4026         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4027                 /*
4028                  * Independent TX/RX MSI-X
4029                  */
4030                 aggregate = FALSE;
4031                 if (bootverbose)
4032                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4033                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4034         } else {
4035                 /*
4036                  * Aggregate TX/RX MSI-X
4037                  */
4038                 aggregate = TRUE;
4039                 if (bootverbose)
4040                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4041                 alloc_cnt = msix_cnt2;
4042                 if (alloc_cnt > ncpus2)
4043                         alloc_cnt = ncpus2;
4044                 if (sc->rx_ring_msix > alloc_cnt)
4045                         sc->rx_ring_msix = alloc_cnt;
4046         }
4047         ++alloc_cnt;    /* For link status */
4048
4049         if (bootverbose) {
4050                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4051                     alloc_cnt, sc->rx_ring_msix);
4052         }
4053
4054         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4055         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4056             &sc->msix_mem_rid, RF_ACTIVE);
4057         if (sc->msix_mem_res == NULL) {
4058                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4059                 return;
4060         }
4061
4062         sc->msix_cnt = alloc_cnt;
4063         sc->msix_data = kmalloc(sizeof(struct igb_msix_data) * sc->msix_cnt,
4064             M_DEVBUF, M_WAITOK | M_ZERO);
4065         for (x = 0; x < sc->msix_cnt; ++x) {
4066                 msix =&n