2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/cputypes.h>
36 #include <machine/md_var.h>
37 #include <machine/pmap.h>
38 #include <machine_base/apic/mpapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine/segments.h>
41 #include <sys/thread2.h>
43 #include <machine/intr_machdep.h>
46 extern pt_entry_t *SMPpt;
48 /* EISA Edge/Level trigger control registers */
49 #define ELCR0 0x4d0 /* eisa irq 0-7 */
50 #define ELCR1 0x4d1 /* eisa irq 8-15 */
59 TAILQ_ENTRY(ioapic_info) io_link;
61 TAILQ_HEAD(ioapic_info_list, ioapic_info);
64 struct ioapic_info_list ioc_list;
65 int ioc_intsrc[16]; /* XXX magic number */
68 static void lapic_timer_calibrate(void);
69 static void lapic_timer_set_divisor(int);
70 static void lapic_timer_fixup_handler(void *);
71 static void lapic_timer_restart_handler(void *);
73 void lapic_timer_process(void);
74 void lapic_timer_process_frame(struct intrframe *);
76 static int lapic_timer_enable = 1;
77 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
79 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
80 static void lapic_timer_intr_enable(struct cputimer_intr *);
81 static void lapic_timer_intr_restart(struct cputimer_intr *);
82 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
84 static void ioapic_setup(const struct ioapic_info *);
85 static void ioapic_set_apic_id(const struct ioapic_info *);
86 static void ioapic_gsi_setup(int);
87 static const struct ioapic_info *
88 ioapic_gsi_search(int);
89 static void ioapic_pin_prog(void *, int, int,
90 enum intr_trigger, enum intr_polarity, uint32_t);
92 static struct cputimer_intr lapic_cputimer_intr = {
94 .reload = lapic_timer_intr_reload,
95 .enable = lapic_timer_intr_enable,
96 .config = cputimer_intr_default_config,
97 .restart = lapic_timer_intr_restart,
98 .pmfixup = lapic_timer_intr_pmfixup,
99 .initclock = cputimer_intr_default_initclock,
100 .next = SLIST_ENTRY_INITIALIZER,
102 .type = CPUTIMER_INTR_LAPIC,
103 .prio = CPUTIMER_INTR_PRIO_LAPIC,
104 .caps = CPUTIMER_INTR_CAP_NONE
108 * pointers to pmapped apic hardware.
111 volatile ioapic_t **ioapic;
113 static int lapic_timer_divisor_idx = -1;
114 static const uint32_t lapic_timer_divisors[] = {
115 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
116 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
118 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
122 static struct ioapic_conf ioapic_conf;
125 * Enable LAPIC, configure interrupts.
128 lapic_init(boolean_t bsp)
136 * Since IDT is shared between BSP and APs, these vectors
137 * only need to be installed once; we do it on BSP.
140 /* Install a 'Spurious INTerrupt' vector */
141 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
142 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
144 /* Install an inter-CPU IPI for TLB invalidation */
145 setidt(XINVLTLB_OFFSET, Xinvltlb,
146 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
148 /* Install an inter-CPU IPI for IPIQ messaging */
149 setidt(XIPIQ_OFFSET, Xipiq,
150 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
152 /* Install a timer vector */
153 setidt(XTIMER_OFFSET, Xtimer,
154 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
156 /* Install an inter-CPU IPI for CPU stop/restart */
157 setidt(XCPUSTOP_OFFSET, Xcpustop,
158 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
162 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
163 * aggregate interrupt input from the 8259. The INTA cycle
164 * will be routed to the external controller (the 8259) which
165 * is expected to supply the vector.
167 * Must be setup edge triggered, active high.
169 * Disable LINT0 on BSP, if I/O APIC is enabled.
171 * Disable LINT0 on the APs. It doesn't matter what delivery
172 * mode we use because we leave it masked.
174 temp = lapic.lvt_lint0;
175 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
176 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
178 temp |= APIC_LVT_DM_EXTINT;
180 temp |= APIC_LVT_MASKED;
182 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
184 lapic.lvt_lint0 = temp;
187 * Setup LINT1 as NMI.
189 * Must be setup edge trigger, active high.
191 * Enable LINT1 on BSP, if I/O APIC is enabled.
193 * Disable LINT1 on the APs.
195 temp = lapic.lvt_lint1;
196 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
197 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
198 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
199 if (bsp && apic_io_enable)
200 temp &= ~APIC_LVT_MASKED;
201 lapic.lvt_lint1 = temp;
204 * Mask the LAPIC error interrupt, LAPIC performance counter
207 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
208 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
211 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
213 timer = lapic.lvt_timer;
214 timer &= ~APIC_LVTT_VECTOR;
215 timer |= XTIMER_OFFSET;
216 timer |= APIC_LVTT_MASKED;
217 lapic.lvt_timer = timer;
220 * Set the Task Priority Register as needed. At the moment allow
221 * interrupts on all cpus (the APs will remain CLId until they are
222 * ready to deal). We could disable all but IPIs by setting
223 * temp |= TPR_IPI for cpu != 0.
226 temp &= ~APIC_TPR_PRIO; /* clear priority field */
227 #ifdef SMP /* APIC-IO */
228 if (!apic_io_enable) {
231 * If we are NOT running the IO APICs, the LAPIC will only be used
232 * for IPIs. Set the TPR to prevent any unintentional interrupts.
235 #ifdef SMP /* APIC-IO */
245 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
246 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
249 * Set the spurious interrupt vector. The low 4 bits of the vector
252 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
253 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
254 temp &= ~APIC_SVR_VECTOR;
255 temp |= XSPURIOUSINT_OFFSET;
260 * Pump out a few EOIs to clean out interrupts that got through
261 * before we were able to set the TPR.
268 lapic_timer_calibrate();
269 if (lapic_timer_enable) {
270 cputimer_intr_register(&lapic_cputimer_intr);
271 cputimer_intr_select(&lapic_cputimer_intr, 0);
274 lapic_timer_set_divisor(lapic_timer_divisor_idx);
278 apic_dump("apic_initialize()");
282 lapic_timer_set_divisor(int divisor_idx)
284 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
285 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
289 lapic_timer_oneshot(u_int count)
293 value = lapic.lvt_timer;
294 value &= ~APIC_LVTT_PERIODIC;
295 lapic.lvt_timer = value;
296 lapic.icr_timer = count;
300 lapic_timer_oneshot_quick(u_int count)
302 lapic.icr_timer = count;
306 lapic_timer_calibrate(void)
310 /* Try to calibrate the local APIC timer. */
311 for (lapic_timer_divisor_idx = 0;
312 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
313 lapic_timer_divisor_idx++) {
314 lapic_timer_set_divisor(lapic_timer_divisor_idx);
315 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
317 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
318 if (value != APIC_TIMER_MAX_COUNT)
321 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
322 panic("lapic: no proper timer divisor?!\n");
323 lapic_cputimer_intr.freq = value / 2;
325 kprintf("lapic: divisor index %d, frequency %u Hz\n",
326 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
330 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
334 gd->gd_timer_running = 0;
336 count = sys_cputimer->count();
337 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
338 systimer_intr(&count, 0, frame);
342 lapic_timer_process(void)
344 lapic_timer_process_oncpu(mycpu, NULL);
348 lapic_timer_process_frame(struct intrframe *frame)
350 lapic_timer_process_oncpu(mycpu, frame);
354 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
356 struct globaldata *gd = mycpu;
358 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
362 if (gd->gd_timer_running) {
363 if (reload < lapic.ccr_timer)
364 lapic_timer_oneshot_quick(reload);
366 gd->gd_timer_running = 1;
367 lapic_timer_oneshot_quick(reload);
372 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
376 timer = lapic.lvt_timer;
377 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
378 lapic.lvt_timer = timer;
380 lapic_timer_fixup_handler(NULL);
384 lapic_timer_fixup_handler(void *arg)
391 if (cpu_vendor_id == CPU_VENDOR_AMD) {
393 * Detect the presence of C1E capability mostly on latest
394 * dual-cores (or future) k8 family. This feature renders
395 * the local APIC timer dead, so we disable it by reading
396 * the Interrupt Pending Message register and clearing both
397 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
400 * "BIOS and Kernel Developer's Guide for AMD NPT
401 * Family 0Fh Processors"
402 * #32559 revision 3.00
404 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
405 (cpu_id & 0x0fff0000) >= 0x00040000) {
408 msr = rdmsr(0xc0010055);
409 if (msr & 0x18000000) {
410 struct globaldata *gd = mycpu;
412 kprintf("cpu%d: AMD C1E detected\n",
414 wrmsr(0xc0010055, msr & ~0x18000000ULL);
417 * We are kinda stalled;
420 gd->gd_timer_running = 1;
421 lapic_timer_oneshot_quick(2);
431 lapic_timer_restart_handler(void *dummy __unused)
435 lapic_timer_fixup_handler(&started);
437 struct globaldata *gd = mycpu;
439 gd->gd_timer_running = 1;
440 lapic_timer_oneshot_quick(2);
445 * This function is called only by ACPI-CA code currently:
446 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
447 * module controls PM. So once ACPI-CA is attached, we try
448 * to apply the fixup to prevent LAPIC timer from hanging.
451 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
453 lwkt_send_ipiq_mask(smp_active_mask,
454 lapic_timer_fixup_handler, NULL);
458 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
460 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
465 * dump contents of local APIC registers
470 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
471 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
472 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
476 #ifdef SMP /* APIC-IO */
482 #define IOAPIC_ISA_INTS 16
483 #define REDIRCNT_IOAPIC(A) \
484 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
486 static int trigger (int apic, int pin, u_int32_t * flags);
487 static void polarity (int apic, int pin, u_int32_t * flags, int level);
489 #define DEFAULT_FLAGS \
495 #define DEFAULT_ISA_FLAGS \
504 io_apic_set_id(int apic, int id)
508 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
509 if (((ux & APIC_ID_MASK) >> 24) != id) {
510 kprintf("Changing APIC ID for IO APIC #%d"
511 " from %d to %d on chip\n",
512 apic, ((ux & APIC_ID_MASK) >> 24), id);
513 ux &= ~APIC_ID_MASK; /* clear the ID field */
515 ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
516 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
517 if (((ux & APIC_ID_MASK) >> 24) != id)
518 panic("can't control IO APIC #%d ID, reg: 0x%08x",
525 io_apic_get_id(int apic)
527 return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
536 io_apic_setup_intpin(int apic, int pin)
538 int bus, bustype, irq;
539 u_char select; /* the select register is 8 bits */
540 u_int32_t flags; /* the window register is 32 bits */
541 u_int32_t target; /* the window register is 32 bits */
542 u_int32_t vector; /* the window register is 32 bits */
547 select = pin * 2 + IOAPIC_REDTBL0; /* register */
550 * Always clear an IO APIC pin before [re]programming it. This is
551 * particularly important if the pin is set up for a level interrupt
552 * as the IOART_REM_IRR bit might be set. When we reprogram the
553 * vector any EOI from pending ints on this pin could be lost and
554 * IRR might never get reset.
556 * To fix this problem, clear the vector and make sure it is
557 * programmed as an edge interrupt. This should theoretically
558 * clear IRR so we can later, safely program it as a level
563 flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
564 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
565 flags |= IOART_DESTPHY | IOART_DELFIXED;
567 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
568 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
572 ioapic_write(ioapic[apic], select, flags | vector);
573 ioapic_write(ioapic[apic], select + 1, target);
578 * We only deal with vectored interrupts here. ? documentation is
579 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
582 * This test also catches unconfigured pins.
584 if (apic_int_type(apic, pin) != 0)
588 * Leave the pin unprogrammed if it does not correspond to
591 irq = apic_irq(apic, pin);
595 /* determine the bus type for this pin */
596 bus = apic_src_bus_id(apic, pin);
599 bustype = apic_bus_type(bus);
601 if ((bustype == ISA) &&
602 (pin < IOAPIC_ISA_INTS) &&
604 (apic_polarity(apic, pin) == 0x1) &&
605 (apic_trigger(apic, pin) == 0x3)) {
607 * A broken BIOS might describe some ISA
608 * interrupts as active-high level-triggered.
609 * Use default ISA flags for those interrupts.
611 flags = DEFAULT_ISA_FLAGS;
614 * Program polarity and trigger mode according to
617 flags = DEFAULT_FLAGS;
618 level = trigger(apic, pin, &flags);
620 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
621 polarity(apic, pin, &flags, level);
625 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
626 kgetenv_int(envpath, &cpuid);
628 /* ncpus may not be available yet */
633 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
634 apic, pin, irq, cpuid);
638 * Program the appropriate registers. This routing may be
639 * overridden when an interrupt handler for a device is
640 * actually added (see register_int(), which calls through
641 * the MACHINTR ABI to set up an interrupt handler/vector).
643 * The order in which we must program the two registers for
644 * safety is unclear! XXX
648 vector = IDT_OFFSET + irq; /* IDT vec */
649 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
650 /* Deliver all interrupts to CPU0 (BSP) */
651 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
653 flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
654 ioapic_write(ioapic[apic], select, flags | vector);
655 ioapic_write(ioapic[apic], select + 1, target);
661 io_apic_setup(int apic)
666 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
667 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
669 for (pin = 0; pin < maxpin; ++pin) {
670 io_apic_setup_intpin(apic, pin);
673 if (apic_int_type(apic, pin) >= 0) {
674 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
675 " cannot program!\n", apic, pin);
680 /* return GOOD status */
683 #undef DEFAULT_ISA_FLAGS
687 #define DEFAULT_EXTINT_FLAGS \
696 * XXX this function is only used by 8254 setup
697 * Setup the source of External INTerrupts.
700 ext_int_setup(int apic, int intr)
702 u_char select; /* the select register is 8 bits */
703 u_int32_t flags; /* the window register is 32 bits */
704 u_int32_t target; /* the window register is 32 bits */
705 u_int32_t vector; /* the window register is 32 bits */
709 if (apic_int_type(apic, intr) != 3)
713 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
714 kgetenv_int(envpath, &cpuid);
716 /* ncpus may not be available yet */
720 /* Deliver interrupts to CPU0 (BSP) */
721 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
723 select = IOAPIC_REDTBL0 + (2 * intr);
724 vector = IDT_OFFSET + intr;
725 flags = DEFAULT_EXTINT_FLAGS;
727 ioapic_write(ioapic[apic], select, flags | vector);
728 ioapic_write(ioapic[apic], select + 1, target);
732 #undef DEFAULT_EXTINT_FLAGS
736 * Set the trigger level for an IO APIC pin.
739 trigger(int apic, int pin, u_int32_t * flags)
744 static int intcontrol = -1;
746 switch (apic_trigger(apic, pin)) {
752 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
756 *flags |= IOART_TRGRLVL;
764 if ((id = apic_src_bus_id(apic, pin)) == -1)
767 switch (apic_bus_type(id)) {
769 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
773 eirq = apic_src_bus_irq(apic, pin);
775 if (eirq < 0 || eirq > 15) {
776 kprintf("EISA IRQ %d?!?!\n", eirq);
780 if (intcontrol == -1) {
781 intcontrol = inb(ELCR1) << 8;
782 intcontrol |= inb(ELCR0);
783 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
786 /* Use ELCR settings to determine level or edge mode */
787 level = (intcontrol >> eirq) & 1;
790 * Note that on older Neptune chipset based systems, any
791 * pci interrupts often show up here and in the ELCR as well
792 * as level sensitive interrupts attributed to the EISA bus.
796 *flags |= IOART_TRGRLVL;
798 *flags &= ~IOART_TRGRLVL;
803 *flags |= IOART_TRGRLVL;
812 panic("bad APIC IO INT flags");
817 * Set the polarity value for an IO APIC pin.
820 polarity(int apic, int pin, u_int32_t * flags, int level)
824 switch (apic_polarity(apic, pin)) {
830 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
834 *flags |= IOART_INTALO;
842 if ((id = apic_src_bus_id(apic, pin)) == -1)
845 switch (apic_bus_type(id)) {
847 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
851 /* polarity converter always gives active high */
852 *flags &= ~IOART_INTALO;
856 *flags |= IOART_INTALO;
865 panic("bad APIC IO INT flags");
870 * Print contents of unmasked IRQs.
877 kprintf("SMP: enabled INTs: ");
878 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
879 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
887 * Inter Processor Interrupt functions.
890 #endif /* SMP APIC-IO */
893 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
895 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
896 * vector is any valid SYSTEM INT vector
897 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
899 * A backlog of requests can create a deadlock between cpus. To avoid this
900 * we have to be able to accept IPIs at the same time we are trying to send
901 * them. The critical section prevents us from attempting to send additional
902 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
903 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
904 * to occur but fortunately it does not happen too often.
907 apic_ipi(int dest_type, int vector, int delivery_mode)
912 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
913 unsigned int eflags = read_eflags();
915 DEBUG_PUSH_INFO("apic_ipi");
916 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
920 write_eflags(eflags);
923 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
924 delivery_mode | vector;
925 lapic.icr_lo = icr_lo;
931 single_apic_ipi(int cpu, int vector, int delivery_mode)
937 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
938 unsigned int eflags = read_eflags();
940 DEBUG_PUSH_INFO("single_apic_ipi");
941 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
945 write_eflags(eflags);
947 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
948 icr_hi |= (CPU_TO_ID(cpu) << 24);
949 lapic.icr_hi = icr_hi;
952 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
953 | APIC_DEST_DESTFLD | delivery_mode | vector;
956 lapic.icr_lo = icr_lo;
963 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
965 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
966 * to the target, and the scheduler does not 'poll' for IPI messages.
969 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
975 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
979 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
980 icr_hi |= (CPU_TO_ID(cpu) << 24);
981 lapic.icr_hi = icr_hi;
984 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
985 | APIC_DEST_DESTFLD | delivery_mode | vector;
988 lapic.icr_lo = icr_lo;
996 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
998 * target is a bitmask of destination cpus. Vector is any
999 * valid system INT vector. Delivery mode may be either
1000 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
1003 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
1007 int n = BSFCPUMASK(target);
1008 target &= ~CPUMASK(n);
1009 single_apic_ipi(n, vector, delivery_mode);
1015 * Timer code, in development...
1016 * - suggested by rgrimes@gndrsh.aac.dev.com
1019 get_apic_timer_frequency(void)
1021 return(lapic_cputimer_intr.freq);
1025 * Load a 'downcount time' in uSeconds.
1028 set_apic_timer(int us)
1033 * When we reach here, lapic timer's frequency
1034 * must have been calculated as well as the
1035 * divisor (lapic.dcr_timer is setup during the
1036 * divisor calculation).
1038 KKASSERT(lapic_cputimer_intr.freq != 0 &&
1039 lapic_timer_divisor_idx >= 0);
1041 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
1042 lapic_timer_oneshot(count);
1047 * Read remaining time in timer.
1050 read_apic_timer(void)
1053 /** XXX FIXME: we need to return the actual remaining time,
1054 * for now we just return the remaining count.
1057 return lapic.ccr_timer;
1063 * Spin-style delay, set delay time in uS, spin till it drains.
1068 set_apic_timer(count);
1069 while (read_apic_timer())
1074 lapic_map(vm_offset_t lapic_addr)
1076 /* Local apic is mapped on last page */
1077 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1078 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1080 kprintf("lapic: at %p\n", (void *)lapic_addr);
1083 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1084 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1089 struct lapic_enumerator *e;
1092 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1093 error = e->lapic_probe(e);
1098 panic("can't config lapic\n");
1100 e->lapic_enumerate(e);
1104 lapic_enumerator_register(struct lapic_enumerator *ne)
1106 struct lapic_enumerator *e;
1108 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1109 if (e->lapic_prio < ne->lapic_prio) {
1110 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1114 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1117 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
1118 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
1123 struct ioapic_enumerator *e;
1127 TAILQ_INIT(&ioapic_conf.ioc_list);
1128 /* XXX magic number */
1129 for (i = 0; i < 16; ++i)
1130 ioapic_conf.ioc_intsrc[i] = -1;
1132 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1133 error = e->ioapic_probe(e);
1139 panic("can't config I/O APIC\n");
1141 kprintf("no I/O APIC\n");
1146 if (!ioapic_use_old) {
1153 * Switch to I/O APIC MachIntrABI and reconfigure
1154 * the default IDT entries.
1156 MachIntrABI = MachIntrABI_IOAPIC;
1157 MachIntrABI.setdefault();
1160 e->ioapic_enumerate(e);
1162 if (!ioapic_use_old) {
1163 struct ioapic_info *info;
1166 * Fixup the rest of the fields of ioapic_info
1169 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1170 const struct ioapic_info *prev_info;
1173 info->io_apic_id = info->io_idx + lapic_id_max + 1;
1176 kprintf("IOAPIC: idx %d, apic id %d, "
1177 "gsi base %d, npin %d\n",
1184 /* Warning about possible GSI hole */
1185 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
1186 if (prev_info != NULL) {
1187 if (info->io_gsi_base !=
1188 prev_info->io_gsi_base + prev_info->io_npin) {
1189 kprintf("IOAPIC: warning gsi hole "
1191 prev_info->io_gsi_base +
1193 info->io_gsi_base - 1);
1199 * Setup all I/O APIC
1201 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1203 ioapic_abi_fixup_irqmap();
1207 MachIntrABI.cleanup();
1214 ioapic_enumerator_register(struct ioapic_enumerator *ne)
1216 struct ioapic_enumerator *e;
1218 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1219 if (e->ioapic_prio < ne->ioapic_prio) {
1220 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
1224 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
1228 ioapic_add(void *addr, int gsi_base, int npin)
1230 struct ioapic_info *info, *ninfo;
1233 gsi_end = gsi_base + npin - 1;
1234 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1235 if ((gsi_base >= info->io_gsi_base &&
1236 gsi_base < info->io_gsi_base + info->io_npin) ||
1237 (gsi_end >= info->io_gsi_base &&
1238 gsi_end < info->io_gsi_base + info->io_npin)) {
1239 panic("ioapic_add: overlapped gsi, base %d npin %d, "
1240 "hit base %d, npin %d\n", gsi_base, npin,
1241 info->io_gsi_base, info->io_npin);
1243 if (info->io_addr == addr)
1244 panic("ioapic_add: duplicated addr %p\n", addr);
1247 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
1248 ninfo->io_addr = addr;
1249 ninfo->io_npin = npin;
1250 ninfo->io_gsi_base = gsi_base;
1253 * Create IOAPIC list in ascending order of GSI base
1255 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
1256 ioapic_info_list, io_link) {
1257 if (ninfo->io_gsi_base > info->io_gsi_base) {
1258 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
1259 info, ninfo, io_link);
1264 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
1268 ioapic_intsrc(int irq, int gsi)
1270 KKASSERT(irq != gsi);
1274 /* Don't allow mixed mode */
1275 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
1279 if (ioapic_conf.ioc_intsrc[irq] != -1 &&
1280 ioapic_conf.ioc_intsrc[irq] != gsi) {
1281 kprintf("IOAPIC: warning intsrc irq %d, gsi %d -> gsi %d\n",
1282 irq, ioapic_conf.ioc_intsrc[irq], gsi);
1284 ioapic_conf.ioc_intsrc[irq] = gsi;
1288 ioapic_set_apic_id(const struct ioapic_info *info)
1292 id = ioapic_read(info->io_addr, IOAPIC_ID);
1294 id &= ~APIC_ID_MASK;
1295 id |= (info->io_apic_id << 24);
1297 ioapic_write(info->io_addr, IOAPIC_ID, id);
1302 id = ioapic_read(info->io_addr, IOAPIC_ID);
1303 if (((id & APIC_ID_MASK) >> 24) != info->io_apic_id) {
1304 panic("ioapic_set_apic_id: can't set apic id to %d\n",
1310 ioapic_gsi_setup(int gsi)
1312 enum intr_trigger trig;
1313 enum intr_polarity pola;
1319 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
1320 ioapic_gsi_pin(gsi), 0);
1325 for (irq = 0; irq < 16; ++irq) {
1326 if (gsi == ioapic_conf.ioc_intsrc[irq]) {
1327 trig = INTR_TRIGGER_EDGE;
1328 pola = INTR_POLARITY_HIGH;
1335 trig = INTR_TRIGGER_EDGE;
1336 pola = INTR_POLARITY_HIGH;
1338 trig = INTR_TRIGGER_LEVEL;
1339 pola = INTR_POLARITY_LOW;
1344 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
1348 ioapic_gsi_ioaddr(int gsi)
1350 const struct ioapic_info *info;
1352 info = ioapic_gsi_search(gsi);
1353 return info->io_addr;
1357 ioapic_gsi_pin(int gsi)
1359 const struct ioapic_info *info;
1361 info = ioapic_gsi_search(gsi);
1362 return gsi - info->io_gsi_base;
1365 static const struct ioapic_info *
1366 ioapic_gsi_search(int gsi)
1368 const struct ioapic_info *info;
1370 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1371 if (gsi >= info->io_gsi_base &&
1372 gsi < info->io_gsi_base + info->io_npin)
1375 panic("ioapic_gsi_search: no I/O APIC\n");
1379 ioapic_gsi(int idx, int pin)
1381 const struct ioapic_info *info;
1383 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1384 if (info->io_idx == idx)
1389 if (pin >= info->io_npin)
1391 return info->io_gsi_base + pin;
1395 ioapic_extpin_setup(void *addr, int pin, int vec)
1397 ioapic_pin_prog(addr, pin, vec,
1398 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
1402 ioapic_extpin_gsi(void)
1408 ioapic_pin_setup(void *addr, int pin, int vec,
1409 enum intr_trigger trig, enum intr_polarity pola)
1412 * Always clear an I/O APIC pin before [re]programming it. This is
1413 * particularly important if the pin is set up for a level interrupt
1414 * as the IOART_REM_IRR bit might be set. When we reprogram the
1415 * vector any EOI from pending ints on this pin could be lost and
1416 * IRR might never get reset.
1418 * To fix this problem, clear the vector and make sure it is
1419 * programmed as an edge interrupt. This should theoretically
1420 * clear IRR so we can later, safely program it as a level
1423 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
1425 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
1429 ioapic_pin_prog(void *addr, int pin, int vec,
1430 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
1432 uint32_t flags, target;
1435 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
1437 select = IOAPIC_REDTBL0 + (2 * pin);
1439 flags = ioapic_read(addr, select) & IOART_RESV;
1440 flags |= IOART_INTMSET | IOART_DESTPHY | del_mode;
1442 if (del_mode == IOART_DELEXINT) {
1443 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
1444 pola == INTR_POLARITY_CONFORM);
1445 flags |= IOART_TRGREDG | IOART_INTAHI;
1448 case INTR_TRIGGER_EDGE:
1449 flags |= IOART_TRGREDG;
1452 case INTR_TRIGGER_LEVEL:
1453 flags |= IOART_TRGRLVL;
1456 case INTR_TRIGGER_CONFORM:
1457 panic("ioapic_pin_prog: trig conform is not "
1461 case INTR_POLARITY_HIGH:
1462 flags |= IOART_INTAHI;
1465 case INTR_POLARITY_LOW:
1466 flags |= IOART_INTALO;
1469 case INTR_POLARITY_CONFORM:
1470 panic("ioapic_pin_prog: pola conform is not "
1475 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
1478 ioapic_write(addr, select, flags | vec);
1479 ioapic_write(addr, select + 1, target);
1483 ioapic_setup(const struct ioapic_info *info)
1487 ioapic_set_apic_id(info);
1489 for (i = 0; i < info->io_npin; ++i)
1490 ioapic_gsi_setup(info->io_gsi_base + i);