2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine_base/apic/apicvar.h>
41 #include <machine_base/icu/icu_var.h>
42 #include <machine/segments.h>
43 #include <sys/thread2.h>
45 #include <machine/cputypes.h>
46 #include <machine/intr_machdep.h>
50 volatile lapic_t *lapic;
52 static void lapic_timer_calibrate(void);
53 static void lapic_timer_set_divisor(int);
54 static void lapic_timer_fixup_handler(void *);
55 static void lapic_timer_restart_handler(void *);
57 void lapic_timer_process(void);
58 void lapic_timer_process_frame(struct intrframe *);
59 void lapic_timer_always(struct intrframe *);
61 static int lapic_timer_enable = 1;
62 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
64 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
65 static void lapic_timer_intr_enable(struct cputimer_intr *);
66 static void lapic_timer_intr_restart(struct cputimer_intr *);
67 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
69 static struct cputimer_intr lapic_cputimer_intr = {
71 .reload = lapic_timer_intr_reload,
72 .enable = lapic_timer_intr_enable,
73 .config = cputimer_intr_default_config,
74 .restart = lapic_timer_intr_restart,
75 .pmfixup = lapic_timer_intr_pmfixup,
76 .initclock = cputimer_intr_default_initclock,
77 .next = SLIST_ENTRY_INITIALIZER,
79 .type = CPUTIMER_INTR_LAPIC,
80 .prio = CPUTIMER_INTR_PRIO_LAPIC,
81 .caps = CPUTIMER_INTR_CAP_NONE
84 static int lapic_timer_divisor_idx = -1;
85 static const uint32_t lapic_timer_divisors[] = {
86 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
87 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
89 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
92 * APIC ID <-> CPU ID mapping structures.
94 int cpu_id_to_apic_id[NAPICID];
95 int apic_id_to_cpu_id[NAPICID];
99 * Enable LAPIC, configure interrupts.
102 lapic_init(boolean_t bsp)
110 * Since IDT is shared between BSP and APs, these vectors
111 * only need to be installed once; we do it on BSP.
114 /* Install a 'Spurious INTerrupt' vector */
115 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
116 SDT_SYSIGT, SEL_KPL, 0);
118 /* Install a timer vector */
119 setidt(XTIMER_OFFSET, Xtimer,
120 SDT_SYSIGT, SEL_KPL, 0);
123 /* Install an inter-CPU IPI for TLB invalidation */
124 setidt(XINVLTLB_OFFSET, Xinvltlb,
125 SDT_SYSIGT, SEL_KPL, 0);
127 /* Install an inter-CPU IPI for IPIQ messaging */
128 setidt(XIPIQ_OFFSET, Xipiq,
129 SDT_SYSIGT, SEL_KPL, 0);
131 /* Install an inter-CPU IPI for CPU stop/restart */
132 setidt(XCPUSTOP_OFFSET, Xcpustop,
133 SDT_SYSIGT, SEL_KPL, 0);
138 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
139 * aggregate interrupt input from the 8259. The INTA cycle
140 * will be routed to the external controller (the 8259) which
141 * is expected to supply the vector.
143 * Must be setup edge triggered, active high.
145 * Disable LINT0 on BSP, if I/O APIC is enabled.
147 * Disable LINT0 on the APs. It doesn't matter what delivery
148 * mode we use because we leave it masked.
150 temp = lapic->lvt_lint0;
151 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
152 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
154 temp |= APIC_LVT_DM_EXTINT;
156 temp |= APIC_LVT_MASKED;
158 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
160 lapic->lvt_lint0 = temp;
163 * Setup LINT1 as NMI.
165 * Must be setup edge trigger, active high.
167 * Enable LINT1 on BSP, if I/O APIC is enabled.
169 * Disable LINT1 on the APs.
171 temp = lapic->lvt_lint1;
172 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
173 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
174 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
175 if (bsp && ioapic_enable)
176 temp &= ~APIC_LVT_MASKED;
177 lapic->lvt_lint1 = temp;
180 * Mask the LAPIC error interrupt, LAPIC performance counter
183 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
184 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
187 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
189 timer = lapic->lvt_timer;
190 timer &= ~APIC_LVTT_VECTOR;
191 timer |= XTIMER_OFFSET;
192 timer |= APIC_LVTT_MASKED;
193 lapic->lvt_timer = timer;
196 * Set the Task Priority Register as needed. At the moment allow
197 * interrupts on all cpus (the APs will remain CLId until they are
201 temp &= ~APIC_TPR_PRIO; /* clear priority field */
208 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
209 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
212 * Set the spurious interrupt vector. The low 4 bits of the vector
215 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
216 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
217 temp &= ~APIC_SVR_VECTOR;
218 temp |= XSPURIOUSINT_OFFSET;
223 * Pump out a few EOIs to clean out interrupts that got through
224 * before we were able to set the TPR.
231 lapic_timer_calibrate();
232 if (lapic_timer_enable) {
233 cputimer_intr_register(&lapic_cputimer_intr);
234 cputimer_intr_select(&lapic_cputimer_intr, 0);
237 lapic_timer_set_divisor(lapic_timer_divisor_idx);
241 apic_dump("apic_initialize()");
245 lapic_timer_set_divisor(int divisor_idx)
247 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
248 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
252 lapic_timer_oneshot(u_int count)
256 value = lapic->lvt_timer;
257 value &= ~APIC_LVTT_PERIODIC;
258 lapic->lvt_timer = value;
259 lapic->icr_timer = count;
263 lapic_timer_oneshot_quick(u_int count)
265 lapic->icr_timer = count;
269 lapic_timer_calibrate(void)
273 /* Try to calibrate the local APIC timer. */
274 for (lapic_timer_divisor_idx = 0;
275 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
276 lapic_timer_divisor_idx++) {
277 lapic_timer_set_divisor(lapic_timer_divisor_idx);
278 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
280 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
281 if (value != APIC_TIMER_MAX_COUNT)
284 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
285 panic("lapic: no proper timer divisor?!\n");
286 lapic_cputimer_intr.freq = value / 2;
288 kprintf("lapic: divisor index %d, frequency %u Hz\n",
289 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
293 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
297 gd->gd_timer_running = 0;
299 count = sys_cputimer->count();
300 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
301 systimer_intr(&count, 0, frame);
305 lapic_timer_process(void)
307 lapic_timer_process_oncpu(mycpu, NULL);
311 lapic_timer_process_frame(struct intrframe *frame)
313 lapic_timer_process_oncpu(mycpu, frame);
317 * This manual debugging code is called unconditionally from Xtimer
318 * (the lapic timer interrupt) whether the current thread is in a
319 * critical section or not) and can be useful in tracking down lockups.
321 * NOTE: MANUAL DEBUG CODE
324 static int saveticks[SMP_MAXCPU];
325 static int savecounts[SMP_MAXCPU];
329 lapic_timer_always(struct intrframe *frame)
332 globaldata_t gd = mycpu;
333 int cpu = gd->gd_cpuid;
339 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
340 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
343 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
344 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
346 for (i = 0; buf[i]; ++i) {
347 gptr[i] = 0x0700 | (unsigned char)buf[i];
351 if (saveticks[gd->gd_cpuid] != ticks) {
352 saveticks[gd->gd_cpuid] = ticks;
353 savecounts[gd->gd_cpuid] = 0;
355 ++savecounts[gd->gd_cpuid];
356 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
357 panic("cpud %d panicing on ticks failure",
360 for (i = 0; i < ncpus; ++i) {
362 if (saveticks[i] && panicstr == NULL) {
363 delta = saveticks[i] - ticks;
364 if (delta < -10 || delta > 10) {
365 panic("cpu %d panicing on cpu %d watchdog",
375 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
377 struct globaldata *gd = mycpu;
379 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
383 if (gd->gd_timer_running) {
384 if (reload < lapic->ccr_timer)
385 lapic_timer_oneshot_quick(reload);
387 gd->gd_timer_running = 1;
388 lapic_timer_oneshot_quick(reload);
393 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
397 timer = lapic->lvt_timer;
398 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
399 lapic->lvt_timer = timer;
401 lapic_timer_fixup_handler(NULL);
405 lapic_timer_fixup_handler(void *arg)
412 if (cpu_vendor_id == CPU_VENDOR_AMD) {
414 * Detect the presence of C1E capability mostly on latest
415 * dual-cores (or future) k8 family. This feature renders
416 * the local APIC timer dead, so we disable it by reading
417 * the Interrupt Pending Message register and clearing both
418 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
421 * "BIOS and Kernel Developer's Guide for AMD NPT
422 * Family 0Fh Processors"
423 * #32559 revision 3.00
425 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
426 (cpu_id & 0x0fff0000) >= 0x00040000) {
429 msr = rdmsr(0xc0010055);
430 if (msr & 0x18000000) {
431 struct globaldata *gd = mycpu;
433 kprintf("cpu%d: AMD C1E detected\n",
435 wrmsr(0xc0010055, msr & ~0x18000000ULL);
438 * We are kinda stalled;
441 gd->gd_timer_running = 1;
442 lapic_timer_oneshot_quick(2);
452 lapic_timer_restart_handler(void *dummy __unused)
456 lapic_timer_fixup_handler(&started);
458 struct globaldata *gd = mycpu;
460 gd->gd_timer_running = 1;
461 lapic_timer_oneshot_quick(2);
466 * This function is called only by ACPI-CA code currently:
467 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
468 * module controls PM. So once ACPI-CA is attached, we try
469 * to apply the fixup to prevent LAPIC timer from hanging.
472 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
475 lwkt_send_ipiq_mask(smp_active_mask,
476 lapic_timer_fixup_handler, NULL);
478 lapic_timer_fixup_handler(NULL);
483 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
486 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
488 lapic_timer_restart_handler(NULL);
494 * dump contents of local APIC registers
499 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
500 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
501 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
507 * Inter Processor Interrupt functions.
511 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
513 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
514 * vector is any valid SYSTEM INT vector
515 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
517 * A backlog of requests can create a deadlock between cpus. To avoid this
518 * we have to be able to accept IPIs at the same time we are trying to send
519 * them. The critical section prevents us from attempting to send additional
520 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
521 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
522 * to occur but fortunately it does not happen too often.
525 apic_ipi(int dest_type, int vector, int delivery_mode)
530 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
531 unsigned long rflags = read_rflags();
533 DEBUG_PUSH_INFO("apic_ipi");
534 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
538 write_rflags(rflags);
541 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
542 delivery_mode | vector;
543 lapic->icr_lo = icr_lo;
549 single_apic_ipi(int cpu, int vector, int delivery_mode)
555 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
556 unsigned long rflags = read_rflags();
558 DEBUG_PUSH_INFO("single_apic_ipi");
559 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
563 write_rflags(rflags);
565 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
566 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
567 lapic->icr_hi = icr_hi;
570 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
571 | APIC_DEST_DESTFLD | delivery_mode | vector;
574 lapic->icr_lo = icr_lo;
581 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
583 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
584 * to the target, and the scheduler does not 'poll' for IPI messages.
587 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
593 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
597 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
598 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
599 lapic->icr_hi = icr_hi;
602 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
603 | APIC_DEST_DESTFLD | delivery_mode | vector;
606 lapic->icr_lo = icr_lo;
614 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
616 * target is a bitmask of destination cpus. Vector is any
617 * valid system INT vector. Delivery mode may be either
618 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
621 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
625 int n = BSFCPUMASK(target);
626 target &= ~CPUMASK(n);
627 single_apic_ipi(n, vector, delivery_mode);
635 * Timer code, in development...
636 * - suggested by rgrimes@gndrsh.aac.dev.com
639 get_apic_timer_frequency(void)
641 return(lapic_cputimer_intr.freq);
645 * Load a 'downcount time' in uSeconds.
648 set_apic_timer(int us)
653 * When we reach here, lapic timer's frequency
654 * must have been calculated as well as the
655 * divisor (lapic->dcr_timer is setup during the
656 * divisor calculation).
658 KKASSERT(lapic_cputimer_intr.freq != 0 &&
659 lapic_timer_divisor_idx >= 0);
661 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
662 lapic_timer_oneshot(count);
667 * Read remaining time in timer.
670 read_apic_timer(void)
673 /** XXX FIXME: we need to return the actual remaining time,
674 * for now we just return the remaining count.
677 return lapic->ccr_timer;
683 * Spin-style delay, set delay time in uS, spin till it drains.
688 set_apic_timer(count);
689 while (read_apic_timer())
694 lapic_unused_apic_id(int start)
698 for (i = start; i < NAPICID; ++i) {
699 if (APICID_TO_CPUID(i) == -1)
706 lapic_map(vm_paddr_t lapic_addr)
708 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
711 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
712 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
717 struct lapic_enumerator *e;
718 int error, i, ap_max;
720 KKASSERT(lapic_enable);
722 for (i = 0; i < NAPICID; ++i)
723 APICID_TO_CPUID(i) = -1;
725 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
726 error = e->lapic_probe(e);
731 kprintf("LAPIC: Can't find LAPIC\n");
735 e->lapic_enumerate(e);
738 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
739 if (ap_max > MAXCPU - 1)
743 kprintf("LAPIC: Warning use only %d out of %d "
753 lapic_enumerator_register(struct lapic_enumerator *ne)
755 struct lapic_enumerator *e;
757 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
758 if (e->lapic_prio < ne->lapic_prio) {
759 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
763 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
767 lapic_set_cpuid(int cpu_id, int apic_id)
769 CPUID_TO_APICID(cpu_id) = apic_id;
770 APICID_TO_CPUID(apic_id) = cpu_id;
774 lapic_fixup_noioapic(void)
778 /* Only allowed on BSP */
779 KKASSERT(mycpuid == 0);
780 KKASSERT(!ioapic_enable);
782 temp = lapic->lvt_lint0;
783 temp &= ~APIC_LVT_MASKED;
784 lapic->lvt_lint0 = temp;
786 temp = lapic->lvt_lint1;
787 temp |= APIC_LVT_MASKED;
788 lapic->lvt_lint1 = temp;
792 lapic_sysinit(void *dummy __unused)
797 error = lapic_config();
803 /* Initialize BSP's local APIC */
805 } else if (ioapic_enable) {
807 icu_reinit_noioapic();
810 SYSINIT(lapic, SI_BOOT2_LAPIC, SI_ORDER_FIRST, lapic_sysinit, NULL)