2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ar5210reg.h,v 1.4 2008/11/10 01:19:37 sam Exp $
19 #ifndef _DEV_ATH_AR5210REG_H
20 #define _DEV_ATH_AR5210REG_H
23 * Register defintions for the Atheros AR5210/5110 MAC/Basedband
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
27 #ifndef PCI_VENDOR_ATHEROS
28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
41 #define AR_IER 0x0024 /* Interrupt global enable register */
42 #define AR_BCR 0x0028 /* Beacon control register */
43 #define AR_BSR 0x002c /* Beacon status register */
44 #define AR_TXCFG 0x0030 /* TX configuration register */
45 #define AR_RXCFG 0x0034 /* RX configuration register */
46 #define AR_MIBC 0x0040 /* MIB control register */
47 #define AR_TOPS 0x0044 /* Timeout prescale register */
48 #define AR_RXNOFRM 0x0048 /* RX no frame timeout register */
49 #define AR_TXNOFRM 0x004c /* TX no frame timeout register */
50 #define AR_RPGTO 0x0050 /* RX frame gap timeout register */
51 #define AR_RFCNT 0x0054 /* RX frame count limit register */
52 #define AR_MISC 0x0058 /* Misc control and status register */
53 #define AR_RC 0x4000 /* Reset control */
54 #define AR_SCR 0x4004 /* Sleep control */
55 #define AR_INTPEND 0x4008 /* Interrupt pending */
56 #define AR_SFR 0x400c /* Force sleep */
57 #define AR_PCICFG 0x4010 /* PCI configuration */
58 #define AR_GPIOCR 0x4014 /* GPIO configuration */
59 #define AR_GPIODO 0x4018 /* GPIO data output */
60 #define AR_GPIODI 0x401c /* GPIO data input */
61 #define AR_SREV 0x4020 /* Silicon revision */
62 /* EEPROM Access Registers */
63 #define AR_EP_AIR_BASE 0x6000 /* EEPROM access initiation regs base */
64 #define AR_EP_AIR(n) (AR_EP_AIR_BASE + (n)*4)
65 #define AR_EP_RDATA 0x6800 /* EEPROM read data register */
66 #define AR_EP_STA 0x6c00 /* EEPROM access status register */
68 #define AR_STA_ID0 0x8000 /* Lower 32bits of MAC address */
69 #define AR_STA_ID1 0x8004 /* Upper 16bits of MAC address */
70 #define AR_BSS_ID0 0x8008 /* Lower 32bits of BSSID */
71 #define AR_BSS_ID1 0x800c /* Upper 16bits of BSSID */
72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off */
73 #define AR_TIME_OUT 0x8014 /* Timeout to wait for ACK and CTS */
74 #define AR_RSSI_THR 0x8018 /* Beacon RSSI warning threshold */
75 #define AR_RETRY_LMT 0x801c /* Short and long frame retry limit */
76 #define AR_USEC 0x8020 /* Transmit latency */
77 #define AR_BEACON 0x8024 /* Beacon control */
78 #define AR_CFP_PERIOD 0x8028 /* CFP period */
79 #define AR_TIMER0 0x802c /* Next beacon time */
80 #define AR_TIMER1 0x8030 /* Next DMA beacon alert time */
81 #define AR_TIMER2 0x8034 /* Next software beacon alert time */
82 #define AR_TIMER3 0x8038 /* Next ATIM window time */
83 #define AR_IFS0 0x8040 /* Protocol timers */
84 #define AR_IFS1 0x8044 /* Protocol time and control */
85 #define AR_CFP_DUR 0x8048 /* Maximum CFP duration */
86 #define AR_RX_FILTER 0x804c /* Receive filter */
87 #define AR_MCAST_FIL0 0x8050 /* Lower 32bits of mcast filter mask */
88 #define AR_MCAST_FIL1 0x8054 /* Upper 16bits of mcast filter mask */
89 #define AR_TX_MASK0 0x8058 /* Lower 32bits of TX mask */
90 #define AR_TX_MASK1 0x805c /* Upper 16bits of TX mask */
91 #define AR_CLR_TMASK 0x8060 /* Clear TX mask */
92 #define AR_TRIG_LEV 0x8064 /* Minimum FIFO fill level before TX */
93 #define AR_DIAG_SW 0x8068 /* PCU control */
94 #define AR_TSF_L32 0x806c /* Lower 32bits of local clock */
95 #define AR_TSF_U32 0x8070 /* Upper 32bits of local clock */
96 #define AR_LAST_TSTP 0x8080 /* Lower 32bits of last beacon tstamp */
97 #define AR_RETRY_CNT 0x8084 /* Current short or long retry cnt */
98 #define AR_BACKOFF 0x8088 /* Back-off status */
99 #define AR_NAV 0x808c /* Current NAV value */
100 #define AR_RTS_OK 0x8090 /* RTS success counter */
101 #define AR_RTS_FAIL 0x8094 /* RTS failure counter */
102 #define AR_ACK_FAIL 0x8098 /* ACK failure counter */
103 #define AR_FCS_FAIL 0x809c /* FCS failure counter */
104 #define AR_BEACON_CNT 0x80a0 /* Valid beacon counter */
105 #define AR_KEYTABLE_0 0x9000 /* Encryption key table */
106 #define AR_KEYTABLE(n) (AR_KEYTABLE_0 + ((n)*32))
108 #define AR_CR_TXE0 0x00000001 /* TX queue 0 enable */
109 #define AR_CR_TXE1 0x00000002 /* TX queue 1 enable */
110 #define AR_CR_RXE 0x00000004 /* RX enable */
111 #define AR_CR_TXD0 0x00000008 /* TX queue 0 disable */
112 #define AR_CR_TXD1 0x00000010 /* TX queue 1 disable */
113 #define AR_CR_RXD 0x00000020 /* RX disable */
114 #define AR_CR_SWI 0x00000040 /* software interrupt */
116 "\20\1TXE0\2TXE1\3RXE\4TXD0\5TXD1\6RXD\7SWI"
118 #define AR_CFG_SWTD 0x00000001 /* BE for TX desc */
119 #define AR_CFG_SWTB 0x00000002 /* BE for TX data */
120 #define AR_CFG_SWRD 0x00000004 /* BE for RX desc */
121 #define AR_CFG_SWRB 0x00000008 /* BE for RX data */
122 #define AR_CFG_SWRG 0x00000010 /* BE for registers */
123 #define AR_CFG_EEBS 0x00000200 /* EEPROM busy */
124 #define AR_CFG_TXCNT 0x00007800 /* number of TX desc in Q */
125 #define AR_CFG_TXCNT_S 11
126 #define AR_CFG_TXFSTAT 0x00008000 /* TX DMA status */
127 #define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */
128 #define AR_CFG_BITS \
129 "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\14EEBS\17TXFSTAT\20TXFSTRT"
131 #define AR_ISR_RXOK_INT 0x00000001 /* RX frame OK */
132 #define AR_ISR_RXDESC_INT 0x00000002 /* RX intr request */
133 #define AR_ISR_RXERR_INT 0x00000004 /* RX error */
134 #define AR_ISR_RXNOFRM_INT 0x00000008 /* no frame received */
135 #define AR_ISR_RXEOL_INT 0x00000010 /* RX desc empty */
136 #define AR_ISR_RXORN_INT 0x00000020 /* RX fifo overrun */
137 #define AR_ISR_TXOK_INT 0x00000040 /* TX frame OK */
138 #define AR_ISR_TXDESC_INT 0x00000080 /* TX intr request */
139 #define AR_ISR_TXERR_INT 0x00000100 /* TX error */
140 #define AR_ISR_TXNOFRM_INT 0x00000200 /* no frame transmitted */
141 #define AR_ISR_TXEOL_INT 0x00000400 /* TX desc empty */
142 #define AR_ISR_TXURN_INT 0x00000800 /* TX fifo underrun */
143 #define AR_ISR_MIB_INT 0x00001000 /* MIB interrupt */
144 #define AR_ISR_SWI_INT 0x00002000 /* software interrupt */
145 #define AR_ISR_RXPHY_INT 0x00004000 /* PHY RX error */
146 #define AR_ISR_RXKCM_INT 0x00008000 /* Key cache miss */
147 #define AR_ISR_SWBA_INT 0x00010000 /* software beacon alert */
148 #define AR_ISR_BRSSI_INT 0x00020000 /* beacon threshold */
149 #define AR_ISR_BMISS_INT 0x00040000 /* beacon missed */
150 #define AR_ISR_MCABT_INT 0x00100000 /* master cycle abort */
151 #define AR_ISR_SSERR_INT 0x00200000 /* SERR on PCI */
152 #define AR_ISR_DPERR_INT 0x00400000 /* Parity error on PCI */
153 #define AR_ISR_GPIO_INT 0x01000000 /* GPIO interrupt */
154 #define AR_ISR_BITS \
155 "\20\1RXOK\2RXDESC\3RXERR\4RXNOFM\5RXEOL\6RXORN\7TXOK\10TXDESC"\
156 "\11TXERR\12TXNOFRM\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"\
157 "\21SWBA\22BRSSI\23BMISS\24MCABT\25SSERR\26DPERR\27GPIO"
159 #define AR_IMR_RXOK_INT 0x00000001 /* RX frame OK */
160 #define AR_IMR_RXDESC_INT 0x00000002 /* RX intr request */
161 #define AR_IMR_RXERR_INT 0x00000004 /* RX error */
162 #define AR_IMR_RXNOFRM_INT 0x00000008 /* no frame received */
163 #define AR_IMR_RXEOL_INT 0x00000010 /* RX desc empty */
164 #define AR_IMR_RXORN_INT 0x00000020 /* RX fifo overrun */
165 #define AR_IMR_TXOK_INT 0x00000040 /* TX frame OK */
166 #define AR_IMR_TXDESC_INT 0x00000080 /* TX intr request */
167 #define AR_IMR_TXERR_INT 0x00000100 /* TX error */
168 #define AR_IMR_TXNOFRM_INT 0x00000200 /* no frame transmitted */
169 #define AR_IMR_TXEOL_INT 0x00000400 /* TX desc empty */
170 #define AR_IMR_TXURN_INT 0x00000800 /* TX fifo underrun */
171 #define AR_IMR_MIB_INT 0x00001000 /* MIB interrupt */
172 #define AR_IMR_SWI_INT 0x00002000 /* software interrupt */
173 #define AR_IMR_RXPHY_INT 0x00004000 /* PHY RX error */
174 #define AR_IMR_RXKCM_INT 0x00008000 /* Key cache miss */
175 #define AR_IMR_SWBA_INT 0x00010000 /* software beacon alert */
176 #define AR_IMR_BRSSI_INT 0x00020000 /* beacon threshold */
177 #define AR_IMR_BMISS_INT 0x00040000 /* beacon missed */
178 #define AR_IMR_MCABT_INT 0x00100000 /* master cycle abort */
179 #define AR_IMR_SSERR_INT 0x00200000 /* SERR on PCI */
180 #define AR_IMR_DPERR_INT 0x00400000 /* Parity error on PCI */
181 #define AR_IMR_GPIO_INT 0x01000000 /* GPIO interrupt */
182 #define AR_IMR_BITS AR_ISR_BITS
184 #define AR_IER_DISABLE 0x00000000 /* pseudo-flag */
185 #define AR_IER_ENABLE 0x00000001 /* global interrupt enable */
186 #define AR_IER_BITS "\20\1ENABLE"
188 #define AR_BCR_BCMD 0x00000001 /* ad hoc beacon mode */
189 #define AR_BCR_BDMAE 0x00000002 /* beacon DMA enable */
190 #define AR_BCR_TQ1FV 0x00000004 /* use TXQ1 for non-beacon */
191 #define AR_BCR_TQ1V 0x00000008 /* TXQ1 valid for beacon */
192 #define AR_BCR_BCGET 0x00000010 /* force a beacon fetch */
193 #define AR_BCR_BITS "\20\1BCMD\2BDMAE\3TQ1FV\4TQ1V\5BCGET"
195 #define AR_BSR_BDLYSW 0x00000001 /* software beacon delay */
196 #define AR_BSR_BDLYDMA 0x00000002 /* DMA beacon delay */
197 #define AR_BSR_TXQ1F 0x00000004 /* TXQ1 fetch */
198 #define AR_BSR_ATIMDLY 0x00000008 /* ATIM delay */
199 #define AR_BSR_SNPBCMD 0x00000100 /* snapshot of BCMD */
200 #define AR_BSR_SNPBDMAE 0x00000200 /* snapshot of BDMAE */
201 #define AR_BSR_SNPTQ1FV 0x00000400 /* snapshot of TQ1FV */
202 #define AR_BSR_SNPTQ1V 0x00000800 /* snapshot of TQ1V */
203 #define AR_BSR_SNAPPEDBCRVALID 0x00001000 /* snapshot of BCR are valid */
204 #define AR_BSR_SWBA_CNT 0x00ff0000 /* software beacon alert cnt */
205 #define AR_BSR_BITS \
206 "\20\1BDLYSW\2BDLYDMA\3TXQ1F\4ATIMDLY\11SNPBCMD\12SNPBDMAE"\
207 "\13SNPTQ1FV\14SNPTQ1V\15SNAPPEDBCRVALID"
209 #define AR_TXCFG_SDMAMR 0x00000007 /* DMA burst size 2^(2+x) */
210 #define AR_TXCFG_TXFSTP 0x00000008 /* Stop TX DMA on filtered */
211 #define AR_TXCFG_TXFULL 0x00000070 /* TX DMA desc Q full thresh */
212 #define AR_TXCFG_TXCONT_EN 0x00000080 /* Enable continuous TX mode */
213 #define AR_TXCFG_BITS "\20\3TXFSTP\7TXCONT_EN"
215 #define AR_RXCFG_SDMAMW 0x00000007 /* DMA burst size 2^(2+x) */
216 #define AR_RXCFG_ZLFDMA 0x00000010 /* enable zero length DMA */
218 /* DMA sizes used for both AR_TXCFG_SDMAMR and AR_RXCFG_SDMAMW */
219 #define AR_DMASIZE_4B 0 /* DMA size 4 bytes */
220 #define AR_DMASIZE_8B 1 /* DMA size 8 bytes */
221 #define AR_DMASIZE_16B 2 /* DMA size 16 bytes */
222 #define AR_DMASIZE_32B 3 /* DMA size 32 bytes */
223 #define AR_DMASIZE_64B 4 /* DMA size 64 bytes */
224 #define AR_DMASIZE_128B 5 /* DMA size 128 bytes */
225 #define AR_DMASIZE_256B 6 /* DMA size 256 bytes */
226 #define AR_DMASIZE_512B 7 /* DMA size 512 bytes */
228 #define AR_MIBC_COW 0x00000001 /* counter overflow warning */
229 #define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */
230 #define AR_MIBC_CMC 0x00000004 /* clear MIB counters */
231 #define AR_MIBC_MCS 0x00000008 /* MIB counter strobe */
233 #define AR_RFCNT_RFCL 0x0000000f /* RX frame count limit */
235 #define AR_MISC_LED_DECAY 0x001c0000 /* LED decay rate */
236 #define AR_MISC_LED_BLINK 0x00e00000 /* LED blink rate */
238 #define AR_RC_RPCU 0x00000001 /* PCU Warm Reset */
239 #define AR_RC_RDMA 0x00000002 /* DMA Warm Reset */
240 #define AR_RC_RMAC 0x00000004 /* MAC Warm Reset */
241 #define AR_RC_RPHY 0x00000008 /* PHY Warm Reset */
242 #define AR_RC_RPCI 0x00000010 /* PCI Core Warm Reset */
243 #define AR_RC_BITS "\20\1RPCU\2RDMA\3RMAC\4RPHY\5RPCI"
245 #define AR_SCR_SLDUR 0x0000ffff /* sleep duration */
246 #define AR_SCR_SLE 0x00030000 /* sleep enable */
247 #define AR_SCR_SLE_S 16
248 #define AR_SCR_SLE_WAKE 0x00000000 /* force wake */
249 #define AR_SCR_SLE_SLP 0x00010000 /* force sleep */
250 #define AR_SCR_SLE_ALLOW 0x00020000 /* allow to control sleep */
251 #define AR_SCR_BITS "\20\20SLE_SLP\21SLE_ALLOW"
253 #define AR_INTPEND_IP 0x00000001 /* interrupt pending */
254 #define AR_INTPEND_BITS "\20\1IP"
256 #define AR_SFR_SF 0x00000001 /* force sleep immediately */
258 #define AR_PCICFG_EEPROMSEL 0x00000001 /* EEPROM access enable */
259 #define AR_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable */
260 #define AR_PCICFG_LED_PEND 0x00000020 /* LED for assoc pending */
261 #define AR_PCICFG_LED_ACT 0x00000040 /* LED for assoc active */
262 #define AR_PCICFG_SL_INTEN 0x00000800 /* Enable sleep intr */
263 #define AR_PCICFG_LED_BCTL 0x00001000 /* LED blink for local act */
264 #define AR_PCICFG_SL_INPEN 0x00002800 /* sleep even intr pending */
265 #define AR_PCICFG_SPWR_DN 0x00010000 /* sleep indication */
266 #define AR_PCICFG_BITS \
267 "\20\1EEPROMSEL\3CLKRUNEN\5LED_PEND\6LED_ACT\13SL_INTEN"\
268 "\14LED_BCTL\20SPWR_DN"
270 #define AR_GPIOCR_IN(n) (0<<((n)*2)) /* input-only */
271 #define AR_GPIOCR_OUT0(n) (1<<((n)*2)) /* output-only if GPIODO = 0 */
272 #define AR_GPIOCR_OUT1(n) (2<<((n)*2)) /* output-only if GPIODO = 1 */
273 #define AR_GPIOCR_OUT(n) (3<<((n)*2)) /* always output */
274 #define AR_GPIOCR_ALL(n) (3<<((n)*2)) /* all bits for pin */
275 #define AR_GPIOCR_INT_SEL(n) ((n)<<12) /* GPIO interrupt pin select */
276 #define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */
277 #define AR_GPIOCR_INT_SELL 0x00000000 /* Interrupt if pin is low */
278 #define AR_GPIOCR_INT_SELH 0x00010000 /* Interrupt if pin is high */
280 #define AR_SREV_CRETE 4 /* Crete 1st version */
281 #define AR_SREV_CRETE_MS 5 /* Crete FCS version */
282 #define AR_SREV_CRETE_23 8 /* Crete version 2.3 */
284 #define AR_EP_STA_RDERR 0x00000001 /* read error */
285 #define AR_EP_STA_RDCMPLT 0x00000002 /* read complete */
286 #define AR_EP_STA_WRERR 0x00000004 /* write error */
287 #define AR_EP_STA_WRCMPLT 0x00000008 /* write complete */
288 #define AR_EP_STA_BITS \
289 "\20\1RDERR\2RDCMPLT\3WRERR\4WRCMPLT"
291 #define AR_STA_ID1_AP 0x00010000 /* Access Point Operation */
292 #define AR_STA_ID1_ADHOC 0x00020000 /* ad hoc Operation */
293 #define AR_STA_ID1_PWR_SV 0x00040000 /* power save report enable */
294 #define AR_STA_ID1_NO_KEYSRCH 0x00080000 /* key table search disable */
295 #define AR_STA_ID1_NO_PSPOLL 0x00100000 /* auto PS-POLL disable */
296 #define AR_STA_ID1_PCF 0x00200000 /* PCF observation enable */
297 #define AR_STA_ID1_DESC_ANTENNA 0x00400000 /* use antenna in TX desc */
298 #define AR_STA_ID1_DEFAULT_ANTENNA 0x00800000 /* toggle default antenna */
299 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* use 6Mbps for ACK/CTS */
300 #define AR_STA_ID1_BITS \
301 "\20\20AP\21ADHOC\22PWR_SV\23NO_KEYSRCH\24NO_PSPOLL\25PCF"\
302 "\26DESC_ANTENNA\27DEFAULT_ANTENNA\30ACKCTS_6MB"
304 #define AR_BSS_ID1_AID 0xffff0000 /* association ID */
305 #define AR_BSS_ID1_AID_S 16
307 #define AR_TIME_OUT_ACK 0x00001fff /* ACK timeout */
308 #define AR_TIME_OUT_ACK_S 0
309 #define AR_TIME_OUT_CTS 0x1fff0000 /* CTS timeout */
310 #define AR_TIME_OUT_CTS_S 16
312 #define AR_RSSI_THR_BM_THR 0x00000700 /* missed beacon threshold */
313 #define AR_RSSI_THR_BM_THR_S 8
315 #define AR_RETRY_LMT_SH_RETRY 0x0000000f /* short frame retry limit */
316 #define AR_RETRY_LMT_SH_RETRY_S 0
317 #define AR_RETRY_LMT_LG_RETRY 0x000000f0 /* long frame retry limit */
318 #define AR_RETRY_LMT_LG_RETRY_S 4
319 #define AR_RETRY_LMT_SSH_RETRY 0x00003f00 /* short station retry limit */
320 #define AR_RETRY_LMT_SSH_RETRY_S 8
321 #define AR_RETRY_LMT_SLG_RETRY 0x000fc000 /* long station retry limit */
322 #define AR_RETRY_LMT_SLG_RETRY_S 14
323 #define AR_RETRY_LMT_CW_MIN 0x3ff00000 /* minimum contention window */
324 #define AR_RETRY_LMT_CW_MIN_S 20
326 #define AR_USEC_1 0x0000007f /* number of clk in 1us */
327 #define AR_USEC_1_S 0
328 #define AR_USEC_32 0x00003f80 /* number of 32MHz clk in 1us */
329 #define AR_USEC_32_S 7
330 #define AR_USEC_TX_LATENCY 0x000fc000 /* transmit latency in us */
331 #define AR_USEC_TX_LATENCY_S 14
332 #define AR_USEC_RX_LATENCY 0x03f00000 /* receive latency in us */
333 #define AR_USEC_RX_LATENCY_S 20
335 #define AR_BEACON_PERIOD 0x0000ffff /* beacon period in TU/ms */
336 #define AR_BEACON_PERIOD_S 0
337 #define AR_BEACON_TIM 0x007f0000 /* byte offset */
338 #define AR_BEACON_TIM_S 16
339 #define AR_BEACON_EN 0x00800000 /* beacon transmission enable */
340 #define AR_BEACON_RESET_TSF 0x01000000 /* TSF reset oneshot */
341 #define AR_BEACON_BITS "\20\27ENABLE\30RESET_TSF"
343 #define AR_IFS0_SIFS 0x000007ff /* SIFS in core clock cycles */
344 #define AR_IFS0_SIFS_S 0
345 #define AR_IFS0_DIFS 0x007ff800 /* DIFS in core clock cycles */
346 #define AR_IFS0_DIFS_S 11
348 #define AR_IFS1_PIFS 0x00000fff /* Programmable IFS */
349 #define AR_IFS1_PIFS_S 0
350 #define AR_IFS1_EIFS 0x03fff000 /* EIFS in core clock cycles */
351 #define AR_IFS1_EIFS_S 12
352 #define AR_IFS1_CS_EN 0x04000000 /* carrier sense enable */
354 #define AR_RX_FILTER_UNICAST 0x00000001 /* unicast frame enable */
355 #define AR_RX_FILTER_MULTICAST 0x00000002 /* multicast frame enable */
356 #define AR_RX_FILTER_BROADCAST 0x00000004 /* broadcast frame enable */
357 #define AR_RX_FILTER_CONTROL 0x00000008 /* control frame enable */
358 #define AR_RX_FILTER_BEACON 0x00000010 /* beacon frame enable */
359 #define AR_RX_FILTER_PROMISCUOUS 0x00000020 /* promiscuous receive enable */
360 #define AR_RX_FILTER_BITS \
361 "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC"
363 #define AR_DIAG_SW_DIS_WEP_ACK 0x00000001 /* disable ACK if no key found*/
364 #define AR_DIAG_SW_DIS_ACK 0x00000002 /* disable ACK generation */
365 #define AR_DIAG_SW_DIS_CTS 0x00000004 /* disable CTS generation */
366 #define AR_DIAG_SW_DIS_ENC 0x00000008 /* encryption disable */
367 #define AR_DIAG_SW_DIS_DEC 0x00000010 /* decryption disable */
368 #define AR_DIAG_SW_DIS_TX 0x00000020 /* TX disable */
369 #define AR_DIAG_SW_DIS_RX 0x00000040 /* RX disable */
370 #define AR_DIAG_SW_LOOP_BACK 0x00000080 /* TX data loopback enable */
371 #define AR_DIAG_SW_CORR_FCS 0x00000100 /* corrupt FCS enable */
372 #define AR_DIAG_SW_CHAN_INFO 0x00000200 /* channel information enable */
373 #define AR_DIAG_SW_EN_SCRAM_SEED 0x00000400 /* use fixed scrambler seed */
374 #define AR_DIAG_SW_SCVRAM_SEED 0x0003f800 /* fixed scrambler seed */
375 #define AR_DIAG_SW_DIS_SEQ_INC 0x00040000 /* seq increment disable */
376 #define AR_DIAG_SW_FRAME_NV0 0x00080000 /* accept frame vers != 0 */
377 #define AR_DIAG_SW_BITS \
378 "\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\
379 "\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\
380 "\22DIS_SEQ_INC\24FRAME_NV0"
382 #define AR_RETRY_CNT_SSH 0x0000003f /* current short retry count */
383 #define AR_RETRY_CNT_SLG 0x00000fc0 /* current long retry count */
385 #define AR_BACKOFF_CW 0x000003ff /* current contention window */
386 #define AR_BACKOFF_CNT 0x03ff0000 /* backoff count */
388 #define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */
389 #define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */
390 #define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */
391 #define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */
392 #define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */
393 #define AR_KEYTABLE_TYPE(n) (AR_KEYTABLE(n) + 20) /* key type */
394 #define AR_KEYTABLE_TYPE_40 0x00000000 /* 40 bit key */
395 #define AR_KEYTABLE_TYPE_104 0x00000001 /* 104 bit key */
396 #define AR_KEYTABLE_TYPE_128 0x00000003 /* 128 bit key */
397 #define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */
398 #define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */
399 #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */
401 #endif /* _DEV_ATH_AR5210REG_H */
projects / dragonfly.git / blob