2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42 * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.7 2003/11/14 22:58:33 dillon Exp $
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
53 #include <machine/asmacros.h>
54 #include <machine/clock.h>
55 #include <machine/cputypes.h>
56 #include <machine/segments.h>
57 #include <machine/specialreg.h>
58 #include <machine/md_var.h>
60 #include <i386/isa/intr_machdep.h>
62 #define IDENTBLUE_CYRIX486 0
63 #define IDENTBLUE_IBMCPU 1
64 #define IDENTBLUE_CYRIXM2 2
66 /* XXX - should be in header file: */
67 void printcpuinfo(void);
68 void finishidentcpu(void);
69 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70 void enable_K5_wt_alloc(void);
71 void enable_K6_wt_alloc(void);
72 void enable_K6_2_wt_alloc(void);
74 void panicifcpuunsupported(void);
76 static void identifycyrix(void);
77 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78 static void print_AMD_features(void);
80 static void print_AMD_info(void);
81 static void print_AMD_assoc(int i);
82 static void print_transmeta_info(void);
83 static void setup_tmx86_longrun(void);
85 int cpu_class = CPUCLASS_386;
86 u_int cpu_exthigh; /* Highest arg to extended CPUID */
87 u_int cyrix_did; /* Device ID of Cyrix CPU */
88 char machine[] = "i386";
89 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
92 static char cpu_model[128];
93 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
96 static char cpu_brand[48];
98 #define MAX_BRAND_INDEX 8
100 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
104 "Intel Pentium III Xeon",
112 static struct cpu_nameclass i386_cpus[] = {
113 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
114 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
115 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
116 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
117 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
118 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
119 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
120 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
121 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
122 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
123 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
124 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
125 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
126 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
127 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
128 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
129 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
132 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
133 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
139 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
144 cpu_class = i386_cpus[cpu].cpu_class;
146 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
148 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
149 /* Check for extended CPUID information and a processor name. */
151 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
152 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
153 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
154 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
155 do_cpuid(0x80000000, regs);
156 if (regs[0] >= 0x80000000) {
157 cpu_exthigh = regs[0];
158 if (cpu_exthigh >= 0x80000004) {
160 for (i = 0x80000002; i < 0x80000005; i++) {
162 memcpy(brand, regs, sizeof(regs));
163 brand += sizeof(regs);
169 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
170 if ((cpu_id & 0xf00) > 0x300) {
175 switch (cpu_id & 0x3000) {
177 strcpy(cpu_model, "Overdrive ");
180 strcpy(cpu_model, "Dual ");
184 switch (cpu_id & 0xf00) {
186 strcat(cpu_model, "i486 ");
187 /* Check the particular flavor of 486 */
188 switch (cpu_id & 0xf0) {
191 strcat(cpu_model, "DX");
194 strcat(cpu_model, "SX");
197 strcat(cpu_model, "DX2");
200 strcat(cpu_model, "SL");
203 strcat(cpu_model, "SX2");
207 "DX2 Write-Back Enhanced");
210 strcat(cpu_model, "DX4");
215 /* Check the particular flavor of 586 */
216 strcat(cpu_model, "Pentium");
217 switch (cpu_id & 0xf0) {
219 strcat(cpu_model, " A-step");
222 strcat(cpu_model, "/P5");
225 strcat(cpu_model, "/P54C");
228 strcat(cpu_model, "/P54T Overdrive");
231 strcat(cpu_model, "/P55C");
234 strcat(cpu_model, "/P54C");
237 strcat(cpu_model, "/P55C (quarter-micron)");
243 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
245 * XXX - If/when Intel fixes the bug, this
246 * should also check the version of the
247 * CPU, not just that it's a Pentium.
253 /* Check the particular flavor of 686 */
254 switch (cpu_id & 0xf0) {
256 strcat(cpu_model, "Pentium Pro A-step");
259 strcat(cpu_model, "Pentium Pro");
265 "Pentium II/Pentium II Xeon/Celeron");
273 "Pentium III/Pentium III Xeon/Celeron");
277 strcat(cpu_model, "Unknown 80686");
282 strcat(cpu_model, "Pentium 4");
286 strcat(cpu_model, "unknown");
291 * If we didn't get a brand name from the extended
292 * CPUID, try to look it up in the brand table.
294 if (cpu_high > 0 && *cpu_brand == '\0') {
295 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
296 if (brand_index <= MAX_BRAND_INDEX &&
297 cpu_brandtable[brand_index] != NULL)
299 cpu_brandtable[brand_index]);
302 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
304 * Values taken from AMD Processor Recognition
305 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
306 * (also describes ``Features'' encodings.
308 strcpy(cpu_model, "AMD ");
309 switch (cpu_id & 0xFF0) {
311 strcat(cpu_model, "Standard Am486DX");
314 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
317 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
320 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
323 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
326 strcat(cpu_model, "Am5x86 Write-Through");
329 strcat(cpu_model, "Am5x86 Write-Back");
332 strcat(cpu_model, "K5 model 0");
336 strcat(cpu_model, "K5 model 1");
339 strcat(cpu_model, "K5 PR166 (model 2)");
342 strcat(cpu_model, "K5 PR200 (model 3)");
345 strcat(cpu_model, "K6");
348 strcat(cpu_model, "K6 266 (model 1)");
351 strcat(cpu_model, "K6-2");
354 strcat(cpu_model, "K6-III");
357 strcat(cpu_model, "Unknown");
360 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
361 if ((cpu_id & 0xf00) == 0x500) {
362 if (((cpu_id & 0x0f0) > 0)
363 && ((cpu_id & 0x0f0) < 0x60)
364 && ((cpu_id & 0x00f) > 3))
365 enable_K5_wt_alloc();
366 else if (((cpu_id & 0x0f0) > 0x80)
367 || (((cpu_id & 0x0f0) == 0x80)
368 && (cpu_id & 0x00f) > 0x07))
369 enable_K6_2_wt_alloc();
370 else if ((cpu_id & 0x0f0) > 0x50)
371 enable_K6_wt_alloc();
374 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
375 strcpy(cpu_model, "Cyrix ");
376 switch (cpu_id & 0xff0) {
378 strcat(cpu_model, "MediaGX");
381 strcat(cpu_model, "6x86");
384 cpu_class = CPUCLASS_586;
385 strcat(cpu_model, "GXm");
388 strcat(cpu_model, "6x86MX");
392 * Even though CPU supports the cpuid
393 * instruction, it can be disabled.
394 * Therefore, this routine supports all Cyrix
397 switch (cyrix_did & 0xf0) {
399 switch (cyrix_did & 0x0f) {
401 strcat(cpu_model, "486SLC");
404 strcat(cpu_model, "486DLC");
407 strcat(cpu_model, "486SLC2");
410 strcat(cpu_model, "486DLC2");
413 strcat(cpu_model, "486SRx");
416 strcat(cpu_model, "486DRx");
419 strcat(cpu_model, "486SRx2");
422 strcat(cpu_model, "486DRx2");
425 strcat(cpu_model, "486SRu");
428 strcat(cpu_model, "486DRu");
431 strcat(cpu_model, "486SRu2");
434 strcat(cpu_model, "486DRu2");
437 strcat(cpu_model, "Unknown");
442 switch (cyrix_did & 0x0f) {
444 strcat(cpu_model, "486S");
447 strcat(cpu_model, "486S2");
450 strcat(cpu_model, "486Se");
453 strcat(cpu_model, "486S2e");
456 strcat(cpu_model, "486DX");
459 strcat(cpu_model, "486DX2");
462 strcat(cpu_model, "486DX4");
465 strcat(cpu_model, "Unknown");
470 if ((cyrix_did & 0x0f) < 8)
471 strcat(cpu_model, "6x86"); /* Where did you get it? */
473 strcat(cpu_model, "5x86");
476 strcat(cpu_model, "6x86");
479 if ((cyrix_did & 0xf000) == 0x3000) {
480 cpu_class = CPUCLASS_586;
481 strcat(cpu_model, "GXm");
483 strcat(cpu_model, "MediaGX");
486 strcat(cpu_model, "6x86MX");
489 switch (cyrix_did & 0x0f) {
491 strcat(cpu_model, "Overdrive CPU");
493 strcpy(cpu_model, "Texas Instruments 486SXL");
496 strcat(cpu_model, "486SLC/DLC");
499 strcat(cpu_model, "Unknown");
504 strcat(cpu_model, "Unknown");
509 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
510 strcpy(cpu_model, "Rise ");
511 switch (cpu_id & 0xff0) {
513 strcat(cpu_model, "mP6");
516 strcat(cpu_model, "Unknown");
518 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
519 switch (cpu_id & 0xff0) {
521 strcpy(cpu_model, "IDT WinChip C6");
525 strcpy(cpu_model, "IDT WinChip 2");
528 strcpy(cpu_model, "VIA C3 Samuel 2");
531 strcpy(cpu_model, "VIA/IDT Unknown");
533 } else if (strcmp(cpu_vendor, "IBM") == 0) {
534 strcpy(cpu_model, "Blue Lightning CPU");
538 * Replace cpu_model with cpu_brand minus leading spaces if
542 while (*brand == ' ')
545 strcpy(cpu_model, brand);
549 printf("%s (", cpu_model);
554 #if defined(I386_CPU)
559 #if defined(I486_CPU)
565 #if defined(I586_CPU)
567 printf("%d.%02d-MHz ",
568 (tsc_freq + 4999) / 1000000,
569 ((tsc_freq + 4999) / 10000) % 100);
573 #if defined(I686_CPU)
575 printf("%d.%02d-MHz ",
576 (tsc_freq + 4999) / 1000000,
577 ((tsc_freq + 4999) / 10000) % 100);
582 printf("Unknown"); /* will panic below... */
584 printf("-class CPU)\n");
585 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
587 printf(" Origin = \"%s\"",cpu_vendor);
589 printf(" Id = 0x%x", cpu_id);
591 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
592 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
593 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
594 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
595 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
596 ((cpu_id & 0xf00) > 0x500))) {
597 printf(" Stepping = %u", cpu_id & 0xf);
598 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
599 printf(" DIR=0x%04x", cyrix_did);
602 * Here we should probably set up flags indicating
603 * whether or not various features are available.
604 * The interesting ones are probably VME, PSE, PAE,
605 * and PGE. The code already assumes without bothering
606 * to check that all CPUs >= Pentium have a TSC and
609 printf("\n Features=0x%b", cpu_feature,
611 "\001FPU" /* Integral FPU */
612 "\002VME" /* Extended VM86 mode support */
613 "\003DE" /* Debugging Extensions (CR4.DE) */
614 "\004PSE" /* 4MByte page tables */
615 "\005TSC" /* Timestamp counter */
616 "\006MSR" /* Machine specific registers */
617 "\007PAE" /* Physical address extension */
618 "\010MCE" /* Machine Check support */
619 "\011CX8" /* CMPEXCH8 instruction */
620 "\012APIC" /* SMP local APIC */
621 "\013oldMTRR" /* Previous implementation of MTRR */
622 "\014SEP" /* Fast System Call */
623 "\015MTRR" /* Memory Type Range Registers */
624 "\016PGE" /* PG_G (global bit) support */
625 "\017MCA" /* Machine Check Architecture */
626 "\020CMOV" /* CMOV instruction */
627 "\021PAT" /* Page attributes table */
628 "\022PSE36" /* 36 bit address space support */
629 "\023PN" /* Processor Serial number */
630 "\024CLFLUSH" /* Has the CLFLUSH instruction */
632 "\026DTS" /* Debug Trace Store */
633 "\027ACPI" /* ACPI support */
634 "\030MMX" /* MMX instructions */
635 "\031FXSR" /* FXSAVE/FXRSTOR */
636 "\032SSE" /* Streaming SIMD Extensions */
637 "\033SSE2" /* Streaming SIMD Extensions #2 */
638 "\034SS" /* Self snoop */
639 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
640 "\036TM" /* Thermal Monitor clock slowdown */
641 "\037IA64" /* CPU can execute IA64 instructions */
642 "\040PBE" /* Pending Break Enable */
646 * If this CPU supports hyperthreading then mention
647 * the number of logical CPU's it contains.
649 if (cpu_feature & CPUID_HTT &&
650 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
651 printf("\n Hyperthreading: %d logical CPUs",
652 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
654 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
655 cpu_exthigh >= 0x80000001)
656 print_AMD_features();
657 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
658 printf(" DIR=0x%04x", cyrix_did);
659 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
660 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
661 #ifndef CYRIX_CACHE_REALLY_WORKS
662 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
663 printf("\n CPU cache: write-through mode");
666 /* Avoid ugly blank lines: only print newline when we have to. */
667 if (*cpu_vendor || cpu_id)
671 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
672 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
673 setup_tmx86_longrun();
679 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
681 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
682 strcmp(cpu_vendor, "TransmetaCPU") == 0)
683 print_transmeta_info();
687 * XXX - Do PPro CPUID level=2 stuff here?
689 * No, but maybe in a print_Intel_info() function called from here.
695 panicifcpuunsupported(void)
698 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
699 #error This kernel is not configured for one of the supported CPUs
702 * Now that we have told the user what they have,
703 * let them know if that machine type isn't configured.
706 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
707 #if !defined(I386_CPU)
710 #if !defined(I486_CPU)
713 #if !defined(I586_CPU)
716 #if !defined(I686_CPU)
719 panic("CPU class not configured");
726 static volatile u_int trap_by_rdmsr;
729 * Special exception 6 handler.
730 * The rdmsr instruction generates invalid opcodes fault on 486-class
731 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
732 * function identblue() when this handler is called. Stacked eip should
739 " .p2align 2,0x90 \n"
740 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
741 __XSTRING(CNAME(bluetrap6)) ": \n"
743 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
744 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
749 * Special exception 13 handler.
750 * Accessing non-existent MSR generates general protection fault.
752 inthand_t bluetrap13;
756 " .p2align 2,0x90 \n"
757 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
758 __XSTRING(CNAME(bluetrap13)) ": \n"
760 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
761 " popl %eax # discard errorcode. \n"
762 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
767 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
768 * support cpuid instruction. This function should be called after
769 * loading interrupt descriptor table register.
771 * I don't like this method that handles fault, but I couldn't get
772 * information for any other methods. Does blue giant know?
781 * Cyrix 486-class CPU does not support rdmsr instruction.
782 * The rdmsr instruction generates invalid opcode fault, and exception
783 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
784 * bluetrap6() set the magic number to trap_by_rdmsr.
786 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
789 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
790 * In this case, rdmsr generates general protection fault, and
791 * exception will be trapped by bluetrap13().
793 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
795 rdmsr(0x1002); /* Cyrix CPU generates fault. */
797 if (trap_by_rdmsr == 0xa8c1d)
798 return IDENTBLUE_CYRIX486;
799 else if (trap_by_rdmsr == 0xa89c4)
800 return IDENTBLUE_CYRIXM2;
801 return IDENTBLUE_IBMCPU;
806 * identifycyrix() set lower 16 bits of cyrix_did as follows:
808 * F E D C B A 9 8 7 6 5 4 3 2 1 0
809 * +-------+-------+---------------+
810 * | SID | RID | Device ID |
811 * | (DIR 1) | (DIR 0) |
812 * +-------+-------+---------------+
817 int ccr2_test = 0, dir_test = 0;
822 ccr2 = read_cyrix_reg(CCR2);
823 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
824 read_cyrix_reg(CCR2);
825 if (read_cyrix_reg(CCR2) != ccr2)
827 write_cyrix_reg(CCR2, ccr2);
829 ccr3 = read_cyrix_reg(CCR3);
830 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
831 read_cyrix_reg(CCR3);
832 if (read_cyrix_reg(CCR3) != ccr3)
833 dir_test = 1; /* CPU supports DIRs. */
834 write_cyrix_reg(CCR3, ccr3);
837 /* Device ID registers are available. */
838 cyrix_did = read_cyrix_reg(DIR1) << 8;
839 cyrix_did += read_cyrix_reg(DIR0);
840 } else if (ccr2_test)
841 cyrix_did = 0x0010; /* 486S A-step */
843 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
849 * Final stage of CPU identification. -- Should I check TI?
858 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
859 if (cpu == CPU_486) {
861 * These conditions are equivalent to:
862 * - CPU does not support cpuid instruction.
863 * - Cyrix/IBM CPU is detected.
865 isblue = identblue();
866 if (isblue == IDENTBLUE_IBMCPU) {
867 strcpy(cpu_vendor, "IBM");
872 switch (cpu_id & 0xf00) {
875 * Cyrix's datasheet does not describe DIRs.
876 * Therefor, I assume it does not have them
877 * and use the result of the cpuid instruction.
878 * XXX they seem to have it for now at least. -Peter
886 * This routine contains a trick.
887 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
889 switch (cyrix_did & 0x00f0) {
898 if ((cyrix_did & 0x000f) < 8)
911 /* M2 and later CPUs are treated as M2. */
915 * enable cpuid instruction.
917 ccr3 = read_cyrix_reg(CCR3);
918 write_cyrix_reg(CCR3, CCR3_MAPEN0);
919 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
920 write_cyrix_reg(CCR3, ccr3);
923 cpu_high = regs[0]; /* eax */
925 cpu_id = regs[0]; /* eax */
926 cpu_feature = regs[3]; /* edx */
930 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
932 * There are BlueLightning CPUs that do not change
933 * undefined flags by dividing 5 by 2. In this case,
934 * the CPU identification routine in locore.s leaves
935 * cpu_vendor null string and puts CPU_486 into the
938 isblue = identblue();
939 if (isblue == IDENTBLUE_IBMCPU) {
940 strcpy(cpu_vendor, "IBM");
948 print_AMD_assoc(int i)
951 printf(", fully associative\n");
953 printf(", %d-way associative\n", i);
961 if (cpu_exthigh >= 0x80000005) {
964 do_cpuid(0x80000005, regs);
965 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
966 print_AMD_assoc(regs[1] >> 24);
967 printf("Instruction TLB: %d entries", regs[1] & 0xff);
968 print_AMD_assoc((regs[1] >> 8) & 0xff);
969 printf("L1 data cache: %d kbytes", regs[2] >> 24);
970 printf(", %d bytes/line", regs[2] & 0xff);
971 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
972 print_AMD_assoc((regs[2] >> 16) & 0xff);
973 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
974 printf(", %d bytes/line", regs[3] & 0xff);
975 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
976 print_AMD_assoc((regs[3] >> 16) & 0xff);
977 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
978 do_cpuid(0x80000006, regs);
980 * Report right L2 cache size on Duron rev. A0.
982 if ((cpu_id & 0xFF0) == 0x630)
983 printf("L2 internal cache: 64 kbytes");
985 printf("L2 internal cache: %d kbytes",
988 printf(", %d bytes/line", regs[2] & 0xff);
989 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
990 print_AMD_assoc((regs[2] >> 12) & 0x0f);
993 if (((cpu_id & 0xf00) == 0x500)
994 && (((cpu_id & 0x0f0) > 0x80)
995 || (((cpu_id & 0x0f0) == 0x80)
996 && (cpu_id & 0x00f) > 0x07))) {
997 /* K6-2(new core [Stepping 8-F]), K6-III or later */
998 amd_whcr = rdmsr(0xc0000082);
999 if (!(amd_whcr & (0x3ff << 22))) {
1000 printf("Write Allocate Disable\n");
1002 printf("Write Allocate Enable Limit: %dM bytes\n",
1003 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1004 printf("Write Allocate 15-16M bytes: %s\n",
1005 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1007 } else if (((cpu_id & 0xf00) == 0x500)
1008 && ((cpu_id & 0x0f0) > 0x50)) {
1009 /* K6, K6-2(old core) */
1010 amd_whcr = rdmsr(0xc0000082);
1011 if (!(amd_whcr & (0x7f << 1))) {
1012 printf("Write Allocate Disable\n");
1014 printf("Write Allocate Enable Limit: %dM bytes\n",
1015 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1016 printf("Write Allocate 15-16M bytes: %s\n",
1017 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1018 printf("Hardware Write Allocate Control: %s\n",
1019 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1024 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1026 print_AMD_features(void)
1031 * Values taken from AMD Processor Recognition
1032 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1034 do_cpuid(0x80000001, regs);
1035 printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
1037 "\001FPU" /* Integral FPU */
1038 "\002VME" /* Extended VM86 mode support */
1039 "\003DE" /* Debug extensions */
1040 "\004PSE" /* 4MByte page tables */
1041 "\005TSC" /* Timestamp counter */
1042 "\006MSR" /* Machine specific registers */
1043 "\007PAE" /* Physical address extension */
1044 "\010MCE" /* Machine Check support */
1045 "\011CX8" /* CMPEXCH8 instruction */
1046 "\012APIC" /* SMP local APIC */
1048 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1049 "\015MTRR" /* Memory Type Range Registers */
1050 "\016PGE" /* PG_G (global bit) support */
1051 "\017MCA" /* Machine Check Architecture */
1052 "\020ICMOV" /* CMOV instruction */
1053 "\021PAT" /* Page attributes table */
1054 "\022PGE36" /* 36 bit address space support */
1055 "\023RSVD" /* Reserved, unknown */
1056 "\024MP" /* Multiprocessor Capable */
1059 "\027AMIE" /* AMD MMX Instruction Extensions */
1061 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1067 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1074 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1077 #define MSR_TMx86_LONGRUN 0x80868010
1078 #define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1080 #define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1081 #define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1082 #define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1084 #define LONGRUN_MODE_MINFREQUENCY 0x00
1085 #define LONGRUN_MODE_ECONOMY 0x01
1086 #define LONGRUN_MODE_PERFORMANCE 0x02
1087 #define LONGRUN_MODE_MAXFREQUENCY 0x03
1088 #define LONGRUN_MODE_UNKNOWN 0x04
1089 #define LONGRUN_MODE_MAX 0x04
1096 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1097 /* MSR low, MSR high, flags bit0 */
1098 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1099 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1100 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1101 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1105 tmx86_get_longrun_mode(void)
1107 union msrinfo msrinfo;
1108 u_int low, high, flags, mode;
1112 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1113 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1114 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1115 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1117 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1118 if (low == longrun_modes[mode][0] &&
1119 high == longrun_modes[mode][1] &&
1120 flags == longrun_modes[mode][2]) {
1124 mode = LONGRUN_MODE_UNKNOWN;
1131 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1137 do_cpuid(0x80860007, regs);
1138 *frequency = regs[0];
1140 *percentage = regs[2];
1147 tmx86_set_longrun_mode(u_int mode)
1149 union msrinfo msrinfo;
1151 if (mode >= LONGRUN_MODE_UNKNOWN) {
1157 /* Write LongRun mode values to Model Specific Register. */
1158 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1159 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1160 longrun_modes[mode][0]);
1161 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1162 longrun_modes[mode][1]);
1163 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1165 /* Write LongRun mode flags to Model Specific Register. */
1166 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1167 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1168 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1174 static u_int crusoe_longrun;
1175 static u_int crusoe_frequency;
1176 static u_int crusoe_voltage;
1177 static u_int crusoe_percentage;
1178 static struct sysctl_ctx_list crusoe_sysctl_ctx;
1179 static struct sysctl_oid *crusoe_sysctl_tree;
1182 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1187 crusoe_longrun = tmx86_get_longrun_mode();
1188 mode = crusoe_longrun;
1189 error = sysctl_handle_int(oidp, &mode, 0, req);
1190 if (error || !req->newptr) {
1193 if (mode >= LONGRUN_MODE_UNKNOWN) {
1197 if (crusoe_longrun != mode) {
1198 crusoe_longrun = mode;
1199 tmx86_set_longrun_mode(crusoe_longrun);
1206 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1211 tmx86_get_longrun_status(&crusoe_frequency,
1212 &crusoe_voltage, &crusoe_percentage);
1213 val = *(u_int *)oidp->oid_arg1;
1214 error = sysctl_handle_int(oidp, &val, 0, req);
1219 setup_tmx86_longrun(void)
1221 static int done = 0;
1227 sysctl_ctx_init(&crusoe_sysctl_ctx);
1228 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1229 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1230 "crusoe", CTLFLAG_RD, 0,
1231 "Transmeta Crusoe LongRun support");
1232 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1233 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1234 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1235 "LongRun mode [0-3]");
1236 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1237 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1238 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1239 "Current frequency (MHz)");
1240 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1241 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1242 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1243 "Current voltage (mV)");
1244 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1245 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1246 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1247 "Processing performance (%)");
1251 print_transmeta_info()
1253 u_int regs[4], nreg = 0;
1255 do_cpuid(0x80860000, regs);
1257 if (nreg >= 0x80860001) {
1258 do_cpuid(0x80860001, regs);
1259 printf(" Processor revision %u.%u.%u.%u\n",
1260 (regs[1] >> 24) & 0xff,
1261 (regs[1] >> 16) & 0xff,
1262 (regs[1] >> 8) & 0xff,
1265 if (nreg >= 0x80860002) {
1266 do_cpuid(0x80860002, regs);
1267 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1268 (regs[1] >> 24) & 0xff,
1269 (regs[1] >> 16) & 0xff,
1270 (regs[1] >> 8) & 0xff,
1274 if (nreg >= 0x80860006) {
1276 do_cpuid(0x80860003, (u_int*) &info[0]);
1277 do_cpuid(0x80860004, (u_int*) &info[16]);
1278 do_cpuid(0x80860005, (u_int*) &info[32]);
1279 do_cpuid(0x80860006, (u_int*) &info[48]);
1281 printf(" %s\n", info);
1284 crusoe_longrun = tmx86_get_longrun_mode();
1285 tmx86_get_longrun_status(&crusoe_frequency,
1286 &crusoe_voltage, &crusoe_percentage);
1287 printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
1288 crusoe_frequency, crusoe_voltage, crusoe_percentage);