1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 unsigned int negated; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c);
153 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS *);
160 static int i386_intel_parse_name (const char *, expressionS *);
161 static const reg_entry *parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template *match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry *build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS *, offsetT);
180 static void output_disp (fragS *, offsetT);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED);
188 static const char *default_arch = DEFAULT_ARCH;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry *regs;
254 operand_size_mismatch,
255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
261 unsupported_with_intel_mnemonic,
264 invalid_vsib_address,
265 invalid_vector_register_set,
266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
271 mask_not_on_destination,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types[MAX_OPERANDS];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op[MAX_OPERANDS];
304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry *seg[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation *mask;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default = 0,
358 const char *rep_prefix;
361 const char *hle_prefix;
363 /* Have BND prefix. */
364 const char *bnd_prefix;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error;
373 typedef struct _i386_insn i386_insn;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable[] =
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars = "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars = "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars[] = "#/";
435 const char line_separator_chars[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars[256];
448 static char register_chars[256];
449 static char operand_chars[256];
450 static char identifier_chars[256];
451 static char digit_chars[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack[32];
469 static char *save_stack_p;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates *current_templates;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
485 /* Current operand we are working on. */
486 static int this_operand = -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code;
497 static unsigned int object_64bit;
498 static unsigned int disallow_64bit_reloc;
499 static int use_rela_relocations = 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi = I386_ABI;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj = 0;
521 /* 1 for intel syntax,
523 static int intel_syntax = 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic = !SYSV386_COMPAT;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc = OLDGCC_COMPAT;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg = 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg = 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix = 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg = 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix = 0;
550 static enum check_kind
556 sse_check, operand_check = check_warning;
558 /* Register prefix used for error message. */
559 static const char *register_prefix = "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size = '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code = 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings = 0;
573 static const char *cpu_arch_name = NULL;
574 static char *cpu_sub_arch_name = NULL;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set = 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion = 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig = rne;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS *GOT_symbol;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
719 CPU_GENERIC32_FLAGS, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
721 CPU_GENERIC64_FLAGS, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
723 CPU_NONE_FLAGS, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
725 CPU_I186_FLAGS, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
727 CPU_I286_FLAGS, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
729 CPU_I386_FLAGS, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
731 CPU_I486_FLAGS, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
733 CPU_I586_FLAGS, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
735 CPU_I686_FLAGS, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
737 CPU_I586_FLAGS, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
741 CPU_P2_FLAGS, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
743 CPU_P3_FLAGS, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
745 CPU_P4_FLAGS, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
747 CPU_CORE_FLAGS, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
749 CPU_NOCONA_FLAGS, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
751 CPU_CORE_FLAGS, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
753 CPU_CORE_FLAGS, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
755 CPU_CORE2_FLAGS, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
757 CPU_CORE2_FLAGS, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
759 CPU_COREI7_FLAGS, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
761 CPU_L1OM_FLAGS, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
765 CPU_K6_FLAGS, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
767 CPU_K6_2_FLAGS, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
769 CPU_ATHLON_FLAGS, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
771 CPU_K8_FLAGS, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
773 CPU_K8_FLAGS, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
775 CPU_K8_FLAGS, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
777 CPU_AMDFAM10_FLAGS, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
779 CPU_BDVER1_FLAGS, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
781 CPU_BDVER2_FLAGS, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
791 CPU_8087_FLAGS, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
793 CPU_287_FLAGS, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
795 CPU_387_FLAGS, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
797 CPU_ANY87_FLAGS, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
799 CPU_MMX_FLAGS, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
801 CPU_3DNOWA_FLAGS, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
803 CPU_SSE_FLAGS, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
805 CPU_SSE2_FLAGS, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
807 CPU_SSE3_FLAGS, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
809 CPU_SSSE3_FLAGS, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
811 CPU_SSE4_1_FLAGS, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
813 CPU_SSE4_2_FLAGS, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
815 CPU_SSE4_2_FLAGS, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
817 CPU_ANY_SSE_FLAGS, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
819 CPU_AVX_FLAGS, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
831 CPU_AVX512DQ_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
833 CPU_AVX512BW_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
835 CPU_AVX512VL_FLAGS, 0, 0 },
836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
837 CPU_ANY_AVX_FLAGS, 0, 1 },
838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
839 CPU_VMX_FLAGS, 0, 0 },
840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
841 CPU_VMFUNC_FLAGS, 0, 0 },
842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
843 CPU_SMX_FLAGS, 0, 0 },
844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
845 CPU_XSAVE_FLAGS, 0, 0 },
846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
847 CPU_XSAVEOPT_FLAGS, 0, 0 },
848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
849 CPU_XSAVEC_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
851 CPU_XSAVES_FLAGS, 0, 0 },
852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
853 CPU_AES_FLAGS, 0, 0 },
854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
855 CPU_PCLMUL_FLAGS, 0, 0 },
856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
857 CPU_PCLMUL_FLAGS, 1, 0 },
858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
859 CPU_FSGSBASE_FLAGS, 0, 0 },
860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
861 CPU_RDRND_FLAGS, 0, 0 },
862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
863 CPU_F16C_FLAGS, 0, 0 },
864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
865 CPU_BMI2_FLAGS, 0, 0 },
866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
867 CPU_FMA_FLAGS, 0, 0 },
868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
869 CPU_FMA4_FLAGS, 0, 0 },
870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
871 CPU_XOP_FLAGS, 0, 0 },
872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
873 CPU_LWP_FLAGS, 0, 0 },
874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
875 CPU_MOVBE_FLAGS, 0, 0 },
876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
877 CPU_CX16_FLAGS, 0, 0 },
878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
879 CPU_EPT_FLAGS, 0, 0 },
880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
881 CPU_LZCNT_FLAGS, 0, 0 },
882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
883 CPU_HLE_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
885 CPU_RTM_FLAGS, 0, 0 },
886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
887 CPU_INVPCID_FLAGS, 0, 0 },
888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
889 CPU_CLFLUSH_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
891 CPU_NOP_FLAGS, 0, 0 },
892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
893 CPU_SYSCALL_FLAGS, 0, 0 },
894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
895 CPU_RDTSCP_FLAGS, 0, 0 },
896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
897 CPU_3DNOW_FLAGS, 0, 0 },
898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
899 CPU_3DNOWA_FLAGS, 0, 0 },
900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
901 CPU_PADLOCK_FLAGS, 0, 0 },
902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
903 CPU_SVME_FLAGS, 1, 0 },
904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
905 CPU_SVME_FLAGS, 0, 0 },
906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
907 CPU_SSE4A_FLAGS, 0, 0 },
908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
909 CPU_ABM_FLAGS, 0, 0 },
910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
911 CPU_BMI_FLAGS, 0, 0 },
912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
913 CPU_TBM_FLAGS, 0, 0 },
914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
915 CPU_ADX_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
917 CPU_RDSEED_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
919 CPU_PRFCHW_FLAGS, 0, 0 },
920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
921 CPU_SMAP_FLAGS, 0, 0 },
922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
923 CPU_MPX_FLAGS, 0, 0 },
924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
925 CPU_SHA_FLAGS, 0, 0 },
926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
927 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
929 CPU_PREFETCHWT1_FLAGS, 0, 0 },
930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
931 CPU_SE1_FLAGS, 0, 0 },
932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
933 CPU_CLWB_FLAGS, 0, 0 },
934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
935 CPU_PCOMMIT_FLAGS, 0, 0 },
936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
937 CPU_AVX512IFMA_FLAGS, 0, 0 },
938 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
939 CPU_AVX512VBMI_FLAGS, 0, 0 },
943 /* Like s_lcomm_internal in gas/read.c but the alignment string
944 is allowed to be optional. */
947 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
954 && *input_line_pointer == ',')
956 align = parse_align (needs_align - 1);
958 if (align == (addressT) -1)
973 bss_alloc (symbolP, size, align);
978 pe_lcomm (int needs_align)
980 s_comm_internal (needs_align * 2, pe_lcomm_internal);
984 const pseudo_typeS md_pseudo_table[] =
986 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
987 {"align", s_align_bytes, 0},
989 {"align", s_align_ptwo, 0},
991 {"arch", set_cpu_arch, 0},
995 {"lcomm", pe_lcomm, 1},
997 {"ffloat", float_cons, 'f'},
998 {"dfloat", float_cons, 'd'},
999 {"tfloat", float_cons, 'x'},
1001 {"slong", signed_cons, 4},
1002 {"noopt", s_ignore, 0},
1003 {"optim", s_ignore, 0},
1004 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1005 {"code16", set_code_flag, CODE_16BIT},
1006 {"code32", set_code_flag, CODE_32BIT},
1007 {"code64", set_code_flag, CODE_64BIT},
1008 {"intel_syntax", set_intel_syntax, 1},
1009 {"att_syntax", set_intel_syntax, 0},
1010 {"intel_mnemonic", set_intel_mnemonic, 1},
1011 {"att_mnemonic", set_intel_mnemonic, 0},
1012 {"allow_index_reg", set_allow_index_reg, 1},
1013 {"disallow_index_reg", set_allow_index_reg, 0},
1014 {"sse_check", set_check, 0},
1015 {"operand_check", set_check, 1},
1016 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1017 {"largecomm", handle_large_common, 0},
1019 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1020 {"loc", dwarf2_directive_loc, 0},
1021 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1024 {"secrel32", pe_directive_secrel, 0},
1029 /* For interface with expression (). */
1030 extern char *input_line_pointer;
1032 /* Hash table for instruction mnemonic lookup. */
1033 static struct hash_control *op_hash;
1035 /* Hash table for register lookup. */
1036 static struct hash_control *reg_hash;
1039 i386_align_code (fragS *fragP, int count)
1041 /* Various efficient no-op patterns for aligning code labels.
1042 Note: Don't try to assemble the instructions in the comments.
1043 0L and 0w are not legal. */
1044 static const char f32_1[] =
1046 static const char f32_2[] =
1047 {0x66,0x90}; /* xchg %ax,%ax */
1048 static const char f32_3[] =
1049 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1050 static const char f32_4[] =
1051 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1052 static const char f32_5[] =
1054 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1055 static const char f32_6[] =
1056 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1057 static const char f32_7[] =
1058 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1059 static const char f32_8[] =
1061 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1062 static const char f32_9[] =
1063 {0x89,0xf6, /* movl %esi,%esi */
1064 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1065 static const char f32_10[] =
1066 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1067 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1068 static const char f32_11[] =
1069 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1070 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1071 static const char f32_12[] =
1072 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1073 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1074 static const char f32_13[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_14[] =
1078 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f16_3[] =
1081 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1082 static const char f16_4[] =
1083 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1084 static const char f16_5[] =
1086 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1087 static const char f16_6[] =
1088 {0x89,0xf6, /* mov %si,%si */
1089 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1090 static const char f16_7[] =
1091 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1092 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1093 static const char f16_8[] =
1094 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1095 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1096 static const char jump_31[] =
1097 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1099 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1100 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1101 static const char *const f32_patt[] = {
1102 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1103 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1105 static const char *const f16_patt[] = {
1106 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1108 /* nopl (%[re]ax) */
1109 static const char alt_3[] =
1111 /* nopl 0(%[re]ax) */
1112 static const char alt_4[] =
1113 {0x0f,0x1f,0x40,0x00};
1114 /* nopl 0(%[re]ax,%[re]ax,1) */
1115 static const char alt_5[] =
1116 {0x0f,0x1f,0x44,0x00,0x00};
1117 /* nopw 0(%[re]ax,%[re]ax,1) */
1118 static const char alt_6[] =
1119 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1120 /* nopl 0L(%[re]ax) */
1121 static const char alt_7[] =
1122 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1123 /* nopl 0L(%[re]ax,%[re]ax,1) */
1124 static const char alt_8[] =
1125 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* nopw 0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_9[] =
1128 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_10[] =
1131 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1132 static const char *const alt_patt[] = {
1133 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1137 /* Only align for at least a positive non-zero boundary. */
1138 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1141 /* We need to decide which NOP sequence to use for 32bit and
1142 64bit. When -mtune= is used:
1144 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1145 PROCESSOR_GENERIC32, f32_patt will be used.
1146 2. For the rest, alt_patt will be used.
1148 When -mtune= isn't used, alt_patt will be used if
1149 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1152 When -march= or .arch is used, we can't use anything beyond
1153 cpu_arch_isa_flags. */
1155 if (flag_code == CODE_16BIT)
1159 memcpy (fragP->fr_literal + fragP->fr_fix,
1161 /* Adjust jump offset. */
1162 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1165 memcpy (fragP->fr_literal + fragP->fr_fix,
1166 f16_patt[count - 1], count);
1170 const char *const *patt = NULL;
1172 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1174 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1175 switch (cpu_arch_tune)
1177 case PROCESSOR_UNKNOWN:
1178 /* We use cpu_arch_isa_flags to check if we SHOULD
1179 optimize with nops. */
1180 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1185 case PROCESSOR_PENTIUM4:
1186 case PROCESSOR_NOCONA:
1187 case PROCESSOR_CORE:
1188 case PROCESSOR_CORE2:
1189 case PROCESSOR_COREI7:
1190 case PROCESSOR_L1OM:
1191 case PROCESSOR_K1OM:
1192 case PROCESSOR_GENERIC64:
1194 case PROCESSOR_ATHLON:
1196 case PROCESSOR_AMDFAM10:
1201 case PROCESSOR_I386:
1202 case PROCESSOR_I486:
1203 case PROCESSOR_PENTIUM:
1204 case PROCESSOR_PENTIUMPRO:
1205 case PROCESSOR_GENERIC32:
1212 switch (fragP->tc_frag_data.tune)
1214 case PROCESSOR_UNKNOWN:
1215 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1216 PROCESSOR_UNKNOWN. */
1220 case PROCESSOR_I386:
1221 case PROCESSOR_I486:
1222 case PROCESSOR_PENTIUM:
1224 case PROCESSOR_ATHLON:
1226 case PROCESSOR_AMDFAM10:
1229 case PROCESSOR_GENERIC32:
1230 /* We use cpu_arch_isa_flags to check if we CAN optimize
1232 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1237 case PROCESSOR_PENTIUMPRO:
1238 case PROCESSOR_PENTIUM4:
1239 case PROCESSOR_NOCONA:
1240 case PROCESSOR_CORE:
1241 case PROCESSOR_CORE2:
1242 case PROCESSOR_COREI7:
1243 case PROCESSOR_L1OM:
1244 case PROCESSOR_K1OM:
1245 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1250 case PROCESSOR_GENERIC64:
1256 if (patt == f32_patt)
1258 /* If the padding is less than 15 bytes, we use the normal
1259 ones. Otherwise, we use a jump instruction and adjust
1263 /* For 64bit, the limit is 3 bytes. */
1264 if (flag_code == CODE_64BIT
1265 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1270 memcpy (fragP->fr_literal + fragP->fr_fix,
1271 patt[count - 1], count);
1274 memcpy (fragP->fr_literal + fragP->fr_fix,
1276 /* Adjust jump offset. */
1277 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1282 /* Maximum length of an instruction is 10 byte. If the
1283 padding is greater than 10 bytes and we don't use jump,
1284 we have to break it into smaller pieces. */
1285 int padding = count;
1286 while (padding > 10)
1289 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1294 memcpy (fragP->fr_literal + fragP->fr_fix,
1295 patt [padding - 1], padding);
1298 fragP->fr_var = count;
1302 operand_type_all_zero (const union i386_operand_type *x)
1304 switch (ARRAY_SIZE(x->array))
1313 return !x->array[0];
1320 operand_type_set (union i386_operand_type *x, unsigned int v)
1322 switch (ARRAY_SIZE(x->array))
1337 operand_type_equal (const union i386_operand_type *x,
1338 const union i386_operand_type *y)
1340 switch (ARRAY_SIZE(x->array))
1343 if (x->array[2] != y->array[2])
1346 if (x->array[1] != y->array[1])
1349 return x->array[0] == y->array[0];
1357 cpu_flags_all_zero (const union i386_cpu_flags *x)
1359 switch (ARRAY_SIZE(x->array))
1368 return !x->array[0];
1375 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1377 switch (ARRAY_SIZE(x->array))
1392 cpu_flags_equal (const union i386_cpu_flags *x,
1393 const union i386_cpu_flags *y)
1395 switch (ARRAY_SIZE(x->array))
1398 if (x->array[2] != y->array[2])
1401 if (x->array[1] != y->array[1])
1404 return x->array[0] == y->array[0];
1412 cpu_flags_check_cpu64 (i386_cpu_flags f)
1414 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1415 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1418 static INLINE i386_cpu_flags
1419 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1421 switch (ARRAY_SIZE (x.array))
1424 x.array [2] &= y.array [2];
1426 x.array [1] &= y.array [1];
1428 x.array [0] &= y.array [0];
1436 static INLINE i386_cpu_flags
1437 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1439 switch (ARRAY_SIZE (x.array))
1442 x.array [2] |= y.array [2];
1444 x.array [1] |= y.array [1];
1446 x.array [0] |= y.array [0];
1454 static INLINE i386_cpu_flags
1455 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1457 switch (ARRAY_SIZE (x.array))
1460 x.array [2] &= ~y.array [2];
1462 x.array [1] &= ~y.array [1];
1464 x.array [0] &= ~y.array [0];
1472 #define CPU_FLAGS_ARCH_MATCH 0x1
1473 #define CPU_FLAGS_64BIT_MATCH 0x2
1474 #define CPU_FLAGS_AES_MATCH 0x4
1475 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1476 #define CPU_FLAGS_AVX_MATCH 0x10
1478 #define CPU_FLAGS_32BIT_MATCH \
1479 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1480 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1481 #define CPU_FLAGS_PERFECT_MATCH \
1482 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1484 /* Return CPU flags match bits. */
1487 cpu_flags_match (const insn_template *t)
1489 i386_cpu_flags x = t->cpu_flags;
1490 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1492 x.bitfield.cpu64 = 0;
1493 x.bitfield.cpuno64 = 0;
1495 if (cpu_flags_all_zero (&x))
1497 /* This instruction is available on all archs. */
1498 match |= CPU_FLAGS_32BIT_MATCH;
1502 /* This instruction is available only on some archs. */
1503 i386_cpu_flags cpu = cpu_arch_flags;
1505 cpu.bitfield.cpu64 = 0;
1506 cpu.bitfield.cpuno64 = 0;
1507 cpu = cpu_flags_and (x, cpu);
1508 if (!cpu_flags_all_zero (&cpu))
1510 if (x.bitfield.cpuavx)
1512 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1513 if (cpu.bitfield.cpuavx)
1515 /* Check SSE2AVX. */
1516 if (!t->opcode_modifier.sse2avx|| sse2avx)
1518 match |= (CPU_FLAGS_ARCH_MATCH
1519 | CPU_FLAGS_AVX_MATCH);
1521 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1522 match |= CPU_FLAGS_AES_MATCH;
1524 if (!x.bitfield.cpupclmul
1525 || cpu.bitfield.cpupclmul)
1526 match |= CPU_FLAGS_PCLMUL_MATCH;
1530 match |= CPU_FLAGS_ARCH_MATCH;
1533 match |= CPU_FLAGS_32BIT_MATCH;
1539 static INLINE i386_operand_type
1540 operand_type_and (i386_operand_type x, i386_operand_type y)
1542 switch (ARRAY_SIZE (x.array))
1545 x.array [2] &= y.array [2];
1547 x.array [1] &= y.array [1];
1549 x.array [0] &= y.array [0];
1557 static INLINE i386_operand_type
1558 operand_type_or (i386_operand_type x, i386_operand_type y)
1560 switch (ARRAY_SIZE (x.array))
1563 x.array [2] |= y.array [2];
1565 x.array [1] |= y.array [1];
1567 x.array [0] |= y.array [0];
1575 static INLINE i386_operand_type
1576 operand_type_xor (i386_operand_type x, i386_operand_type y)
1578 switch (ARRAY_SIZE (x.array))
1581 x.array [2] ^= y.array [2];
1583 x.array [1] ^= y.array [1];
1585 x.array [0] ^= y.array [0];
1593 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1594 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1595 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1596 static const i386_operand_type inoutportreg
1597 = OPERAND_TYPE_INOUTPORTREG;
1598 static const i386_operand_type reg16_inoutportreg
1599 = OPERAND_TYPE_REG16_INOUTPORTREG;
1600 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1601 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1602 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1603 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1604 static const i386_operand_type anydisp
1605 = OPERAND_TYPE_ANYDISP;
1606 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1607 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1608 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1609 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1610 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1611 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1612 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1613 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1614 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1615 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1616 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1617 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1618 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1619 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1630 operand_type_check (i386_operand_type t, enum operand_type c)
1635 return (t.bitfield.reg8
1638 || t.bitfield.reg64);
1641 return (t.bitfield.imm8
1645 || t.bitfield.imm32s
1646 || t.bitfield.imm64);
1649 return (t.bitfield.disp8
1650 || t.bitfield.disp16
1651 || t.bitfield.disp32
1652 || t.bitfield.disp32s
1653 || t.bitfield.disp64);
1656 return (t.bitfield.disp8
1657 || t.bitfield.disp16
1658 || t.bitfield.disp32
1659 || t.bitfield.disp32s
1660 || t.bitfield.disp64
1661 || t.bitfield.baseindex);
1670 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1671 operand J for instruction template T. */
1674 match_reg_size (const insn_template *t, unsigned int j)
1676 return !((i.types[j].bitfield.byte
1677 && !t->operand_types[j].bitfield.byte)
1678 || (i.types[j].bitfield.word
1679 && !t->operand_types[j].bitfield.word)
1680 || (i.types[j].bitfield.dword
1681 && !t->operand_types[j].bitfield.dword)
1682 || (i.types[j].bitfield.qword
1683 && !t->operand_types[j].bitfield.qword));
1686 /* Return 1 if there is no conflict in any size on operand J for
1687 instruction template T. */
1690 match_mem_size (const insn_template *t, unsigned int j)
1692 return (match_reg_size (t, j)
1693 && !((i.types[j].bitfield.unspecified
1694 && !t->operand_types[j].bitfield.unspecified)
1695 || (i.types[j].bitfield.fword
1696 && !t->operand_types[j].bitfield.fword)
1697 || (i.types[j].bitfield.tbyte
1698 && !t->operand_types[j].bitfield.tbyte)
1699 || (i.types[j].bitfield.xmmword
1700 && !t->operand_types[j].bitfield.xmmword)
1701 || (i.types[j].bitfield.ymmword
1702 && !t->operand_types[j].bitfield.ymmword)
1703 || (i.types[j].bitfield.zmmword
1704 && !t->operand_types[j].bitfield.zmmword)));
1707 /* Return 1 if there is no size conflict on any operands for
1708 instruction template T. */
1711 operand_size_match (const insn_template *t)
1716 /* Don't check jump instructions. */
1717 if (t->opcode_modifier.jump
1718 || t->opcode_modifier.jumpbyte
1719 || t->opcode_modifier.jumpdword
1720 || t->opcode_modifier.jumpintersegment)
1723 /* Check memory and accumulator operand size. */
1724 for (j = 0; j < i.operands; j++)
1726 if (t->operand_types[j].bitfield.anysize)
1729 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1735 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1744 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1747 i.error = operand_size_mismatch;
1751 /* Check reverse. */
1752 gas_assert (i.operands == 2);
1755 for (j = 0; j < 2; j++)
1757 if (t->operand_types[j].bitfield.acc
1758 && !match_reg_size (t, j ? 0 : 1))
1761 if (i.types[j].bitfield.mem
1762 && !match_mem_size (t, j ? 0 : 1))
1770 operand_type_match (i386_operand_type overlap,
1771 i386_operand_type given)
1773 i386_operand_type temp = overlap;
1775 temp.bitfield.jumpabsolute = 0;
1776 temp.bitfield.unspecified = 0;
1777 temp.bitfield.byte = 0;
1778 temp.bitfield.word = 0;
1779 temp.bitfield.dword = 0;
1780 temp.bitfield.fword = 0;
1781 temp.bitfield.qword = 0;
1782 temp.bitfield.tbyte = 0;
1783 temp.bitfield.xmmword = 0;
1784 temp.bitfield.ymmword = 0;
1785 temp.bitfield.zmmword = 0;
1786 if (operand_type_all_zero (&temp))
1789 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1790 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1794 i.error = operand_type_mismatch;
1798 /* If given types g0 and g1 are registers they must be of the same type
1799 unless the expected operand type register overlap is null.
1800 Note that Acc in a template matches every size of reg. */
1803 operand_type_register_match (i386_operand_type m0,
1804 i386_operand_type g0,
1805 i386_operand_type t0,
1806 i386_operand_type m1,
1807 i386_operand_type g1,
1808 i386_operand_type t1)
1810 if (!operand_type_check (g0, reg))
1813 if (!operand_type_check (g1, reg))
1816 if (g0.bitfield.reg8 == g1.bitfield.reg8
1817 && g0.bitfield.reg16 == g1.bitfield.reg16
1818 && g0.bitfield.reg32 == g1.bitfield.reg32
1819 && g0.bitfield.reg64 == g1.bitfield.reg64)
1822 if (m0.bitfield.acc)
1824 t0.bitfield.reg8 = 1;
1825 t0.bitfield.reg16 = 1;
1826 t0.bitfield.reg32 = 1;
1827 t0.bitfield.reg64 = 1;
1830 if (m1.bitfield.acc)
1832 t1.bitfield.reg8 = 1;
1833 t1.bitfield.reg16 = 1;
1834 t1.bitfield.reg32 = 1;
1835 t1.bitfield.reg64 = 1;
1838 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1839 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1840 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1841 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1844 i.error = register_type_mismatch;
1849 static INLINE unsigned int
1850 register_number (const reg_entry *r)
1852 unsigned int nr = r->reg_num;
1854 if (r->reg_flags & RegRex)
1860 static INLINE unsigned int
1861 mode_from_disp_size (i386_operand_type t)
1863 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1865 else if (t.bitfield.disp16
1866 || t.bitfield.disp32
1867 || t.bitfield.disp32s)
1874 fits_in_signed_byte (addressT num)
1876 return num + 0x80 <= 0xff;
1880 fits_in_unsigned_byte (addressT num)
1886 fits_in_unsigned_word (addressT num)
1888 return num <= 0xffff;
1892 fits_in_signed_word (addressT num)
1894 return num + 0x8000 <= 0xffff;
1898 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
1903 return num + 0x80000000 <= 0xffffffff;
1905 } /* fits_in_signed_long() */
1908 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
1913 return num <= 0xffffffff;
1915 } /* fits_in_unsigned_long() */
1918 fits_in_vec_disp8 (offsetT num)
1920 int shift = i.memshift;
1926 mask = (1 << shift) - 1;
1928 /* Return 0 if NUM isn't properly aligned. */
1932 /* Check if NUM will fit in 8bit after shift. */
1933 return fits_in_signed_byte (num >> shift);
1937 fits_in_imm4 (offsetT num)
1939 return (num & 0xf) == num;
1942 static i386_operand_type
1943 smallest_imm_type (offsetT num)
1945 i386_operand_type t;
1947 operand_type_set (&t, 0);
1948 t.bitfield.imm64 = 1;
1950 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1952 /* This code is disabled on the 486 because all the Imm1 forms
1953 in the opcode table are slower on the i486. They're the
1954 versions with the implicitly specified single-position
1955 displacement, which has another syntax if you really want to
1957 t.bitfield.imm1 = 1;
1958 t.bitfield.imm8 = 1;
1959 t.bitfield.imm8s = 1;
1960 t.bitfield.imm16 = 1;
1961 t.bitfield.imm32 = 1;
1962 t.bitfield.imm32s = 1;
1964 else if (fits_in_signed_byte (num))
1966 t.bitfield.imm8 = 1;
1967 t.bitfield.imm8s = 1;
1968 t.bitfield.imm16 = 1;
1969 t.bitfield.imm32 = 1;
1970 t.bitfield.imm32s = 1;
1972 else if (fits_in_unsigned_byte (num))
1974 t.bitfield.imm8 = 1;
1975 t.bitfield.imm16 = 1;
1976 t.bitfield.imm32 = 1;
1977 t.bitfield.imm32s = 1;
1979 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1981 t.bitfield.imm16 = 1;
1982 t.bitfield.imm32 = 1;
1983 t.bitfield.imm32s = 1;
1985 else if (fits_in_signed_long (num))
1987 t.bitfield.imm32 = 1;
1988 t.bitfield.imm32s = 1;
1990 else if (fits_in_unsigned_long (num))
1991 t.bitfield.imm32 = 1;
1997 offset_in_range (offsetT val, int size)
2003 case 1: mask = ((addressT) 1 << 8) - 1; break;
2004 case 2: mask = ((addressT) 1 << 16) - 1; break;
2005 case 4: mask = ((addressT) 2 << 31) - 1; break;
2007 case 8: mask = ((addressT) 2 << 63) - 1; break;
2013 /* If BFD64, sign extend val for 32bit address mode. */
2014 if (flag_code != CODE_64BIT
2015 || i.prefix[ADDR_PREFIX])
2016 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2017 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2020 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2022 char buf1[40], buf2[40];
2024 sprint_value (buf1, val);
2025 sprint_value (buf2, val & mask);
2026 as_warn (_("%s shortened to %s"), buf1, buf2);
2040 a. PREFIX_EXIST if attempting to add a prefix where one from the
2041 same class already exists.
2042 b. PREFIX_LOCK if lock prefix is added.
2043 c. PREFIX_REP if rep/repne prefix is added.
2044 d. PREFIX_OTHER if other prefix is added.
2047 static enum PREFIX_GROUP
2048 add_prefix (unsigned int prefix)
2050 enum PREFIX_GROUP ret = PREFIX_OTHER;
2053 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2054 && flag_code == CODE_64BIT)
2056 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2057 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2058 && (prefix & (REX_R | REX_X | REX_B))))
2069 case CS_PREFIX_OPCODE:
2070 case DS_PREFIX_OPCODE:
2071 case ES_PREFIX_OPCODE:
2072 case FS_PREFIX_OPCODE:
2073 case GS_PREFIX_OPCODE:
2074 case SS_PREFIX_OPCODE:
2078 case REPNE_PREFIX_OPCODE:
2079 case REPE_PREFIX_OPCODE:
2084 case LOCK_PREFIX_OPCODE:
2093 case ADDR_PREFIX_OPCODE:
2097 case DATA_PREFIX_OPCODE:
2101 if (i.prefix[q] != 0)
2109 i.prefix[q] |= prefix;
2112 as_bad (_("same type of prefix used twice"));
2118 update_code_flag (int value, int check)
2120 PRINTF_LIKE ((*as_error));
2122 flag_code = (enum flag_code) value;
2123 if (flag_code == CODE_64BIT)
2125 cpu_arch_flags.bitfield.cpu64 = 1;
2126 cpu_arch_flags.bitfield.cpuno64 = 0;
2130 cpu_arch_flags.bitfield.cpu64 = 0;
2131 cpu_arch_flags.bitfield.cpuno64 = 1;
2133 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2136 as_error = as_fatal;
2139 (*as_error) (_("64bit mode not supported on `%s'."),
2140 cpu_arch_name ? cpu_arch_name : default_arch);
2142 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2145 as_error = as_fatal;
2148 (*as_error) (_("32bit mode not supported on `%s'."),
2149 cpu_arch_name ? cpu_arch_name : default_arch);
2151 stackop_size = '\0';
2155 set_code_flag (int value)
2157 update_code_flag (value, 0);
2161 set_16bit_gcc_code_flag (int new_code_flag)
2163 flag_code = (enum flag_code) new_code_flag;
2164 if (flag_code != CODE_16BIT)
2166 cpu_arch_flags.bitfield.cpu64 = 0;
2167 cpu_arch_flags.bitfield.cpuno64 = 1;
2168 stackop_size = LONG_MNEM_SUFFIX;
2172 set_intel_syntax (int syntax_flag)
2174 /* Find out if register prefixing is specified. */
2175 int ask_naked_reg = 0;
2178 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2180 char *string = input_line_pointer;
2181 int e = get_symbol_end ();
2183 if (strcmp (string, "prefix") == 0)
2185 else if (strcmp (string, "noprefix") == 0)
2188 as_bad (_("bad argument to syntax directive."));
2189 *input_line_pointer = e;
2191 demand_empty_rest_of_line ();
2193 intel_syntax = syntax_flag;
2195 if (ask_naked_reg == 0)
2196 allow_naked_reg = (intel_syntax
2197 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2199 allow_naked_reg = (ask_naked_reg < 0);
2201 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2203 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2204 identifier_chars['$'] = intel_syntax ? '$' : 0;
2205 register_prefix = allow_naked_reg ? "" : "%";
2209 set_intel_mnemonic (int mnemonic_flag)
2211 intel_mnemonic = mnemonic_flag;
2215 set_allow_index_reg (int flag)
2217 allow_index_reg = flag;
2221 set_check (int what)
2223 enum check_kind *kind;
2228 kind = &operand_check;
2239 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2241 char *string = input_line_pointer;
2242 int e = get_symbol_end ();
2244 if (strcmp (string, "none") == 0)
2246 else if (strcmp (string, "warning") == 0)
2247 *kind = check_warning;
2248 else if (strcmp (string, "error") == 0)
2249 *kind = check_error;
2251 as_bad (_("bad argument to %s_check directive."), str);
2252 *input_line_pointer = e;
2255 as_bad (_("missing argument for %s_check directive"), str);
2257 demand_empty_rest_of_line ();
2261 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2262 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2264 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2265 static const char *arch;
2267 /* Intel LIOM is only supported on ELF. */
2273 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2274 use default_arch. */
2275 arch = cpu_arch_name;
2277 arch = default_arch;
2280 /* If we are targeting Intel L1OM, we must enable it. */
2281 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2282 || new_flag.bitfield.cpul1om)
2285 /* If we are targeting Intel K1OM, we must enable it. */
2286 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2287 || new_flag.bitfield.cpuk1om)
2290 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2295 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2299 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2301 char *string = input_line_pointer;
2302 int e = get_symbol_end ();
2304 i386_cpu_flags flags;
2306 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2308 if (strcmp (string, cpu_arch[j].name) == 0)
2310 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2314 cpu_arch_name = cpu_arch[j].name;
2315 cpu_sub_arch_name = NULL;
2316 cpu_arch_flags = cpu_arch[j].flags;
2317 if (flag_code == CODE_64BIT)
2319 cpu_arch_flags.bitfield.cpu64 = 1;
2320 cpu_arch_flags.bitfield.cpuno64 = 0;
2324 cpu_arch_flags.bitfield.cpu64 = 0;
2325 cpu_arch_flags.bitfield.cpuno64 = 1;
2327 cpu_arch_isa = cpu_arch[j].type;
2328 cpu_arch_isa_flags = cpu_arch[j].flags;
2329 if (!cpu_arch_tune_set)
2331 cpu_arch_tune = cpu_arch_isa;
2332 cpu_arch_tune_flags = cpu_arch_isa_flags;
2337 if (!cpu_arch[j].negated)
2338 flags = cpu_flags_or (cpu_arch_flags,
2341 flags = cpu_flags_and_not (cpu_arch_flags,
2343 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2345 if (cpu_sub_arch_name)
2347 char *name = cpu_sub_arch_name;
2348 cpu_sub_arch_name = concat (name,
2350 (const char *) NULL);
2354 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2355 cpu_arch_flags = flags;
2356 cpu_arch_isa_flags = flags;
2358 *input_line_pointer = e;
2359 demand_empty_rest_of_line ();
2363 if (j >= ARRAY_SIZE (cpu_arch))
2364 as_bad (_("no such architecture: `%s'"), string);
2366 *input_line_pointer = e;
2369 as_bad (_("missing cpu architecture"));
2371 no_cond_jump_promotion = 0;
2372 if (*input_line_pointer == ','
2373 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2375 char *string = ++input_line_pointer;
2376 int e = get_symbol_end ();
2378 if (strcmp (string, "nojumps") == 0)
2379 no_cond_jump_promotion = 1;
2380 else if (strcmp (string, "jumps") == 0)
2383 as_bad (_("no such architecture modifier: `%s'"), string);
2385 *input_line_pointer = e;
2388 demand_empty_rest_of_line ();
2391 enum bfd_architecture
2394 if (cpu_arch_isa == PROCESSOR_L1OM)
2396 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2397 || flag_code != CODE_64BIT)
2398 as_fatal (_("Intel L1OM is 64bit ELF only"));
2399 return bfd_arch_l1om;
2401 else if (cpu_arch_isa == PROCESSOR_K1OM)
2403 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2404 || flag_code != CODE_64BIT)
2405 as_fatal (_("Intel K1OM is 64bit ELF only"));
2406 return bfd_arch_k1om;
2409 return bfd_arch_i386;
2415 if (!strncmp (default_arch, "x86_64", 6))
2417 if (cpu_arch_isa == PROCESSOR_L1OM)
2419 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2420 || default_arch[6] != '\0')
2421 as_fatal (_("Intel L1OM is 64bit ELF only"));
2422 return bfd_mach_l1om;
2424 else if (cpu_arch_isa == PROCESSOR_K1OM)
2426 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2427 || default_arch[6] != '\0')
2428 as_fatal (_("Intel K1OM is 64bit ELF only"));
2429 return bfd_mach_k1om;
2431 else if (default_arch[6] == '\0')
2432 return bfd_mach_x86_64;
2434 return bfd_mach_x64_32;
2436 else if (!strcmp (default_arch, "i386"))
2437 return bfd_mach_i386_i386;
2439 as_fatal (_("unknown architecture"));
2445 const char *hash_err;
2447 /* Initialize op_hash hash table. */
2448 op_hash = hash_new ();
2451 const insn_template *optab;
2452 templates *core_optab;
2454 /* Setup for loop. */
2456 core_optab = (templates *) xmalloc (sizeof (templates));
2457 core_optab->start = optab;
2462 if (optab->name == NULL
2463 || strcmp (optab->name, (optab - 1)->name) != 0)
2465 /* different name --> ship out current template list;
2466 add to hash table; & begin anew. */
2467 core_optab->end = optab;
2468 hash_err = hash_insert (op_hash,
2470 (void *) core_optab);
2473 as_fatal (_("can't hash %s: %s"),
2477 if (optab->name == NULL)
2479 core_optab = (templates *) xmalloc (sizeof (templates));
2480 core_optab->start = optab;
2485 /* Initialize reg_hash hash table. */
2486 reg_hash = hash_new ();
2488 const reg_entry *regtab;
2489 unsigned int regtab_size = i386_regtab_size;
2491 for (regtab = i386_regtab; regtab_size--; regtab++)
2493 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2495 as_fatal (_("can't hash %s: %s"),
2501 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2506 for (c = 0; c < 256; c++)
2511 mnemonic_chars[c] = c;
2512 register_chars[c] = c;
2513 operand_chars[c] = c;
2515 else if (ISLOWER (c))
2517 mnemonic_chars[c] = c;
2518 register_chars[c] = c;
2519 operand_chars[c] = c;
2521 else if (ISUPPER (c))
2523 mnemonic_chars[c] = TOLOWER (c);
2524 register_chars[c] = mnemonic_chars[c];
2525 operand_chars[c] = c;
2527 else if (c == '{' || c == '}')
2528 operand_chars[c] = c;
2530 if (ISALPHA (c) || ISDIGIT (c))
2531 identifier_chars[c] = c;
2534 identifier_chars[c] = c;
2535 operand_chars[c] = c;
2540 identifier_chars['@'] = '@';
2543 identifier_chars['?'] = '?';
2544 operand_chars['?'] = '?';
2546 digit_chars['-'] = '-';
2547 mnemonic_chars['_'] = '_';
2548 mnemonic_chars['-'] = '-';
2549 mnemonic_chars['.'] = '.';
2550 identifier_chars['_'] = '_';
2551 identifier_chars['.'] = '.';
2553 for (p = operand_special_chars; *p != '\0'; p++)
2554 operand_chars[(unsigned char) *p] = *p;
2557 if (flag_code == CODE_64BIT)
2559 #if defined (OBJ_COFF) && defined (TE_PE)
2560 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2563 x86_dwarf2_return_column = 16;
2565 x86_cie_data_alignment = -8;
2569 x86_dwarf2_return_column = 8;
2570 x86_cie_data_alignment = -4;
2575 i386_print_statistics (FILE *file)
2577 hash_print_statistics (file, "i386 opcode", op_hash);
2578 hash_print_statistics (file, "i386 register", reg_hash);
2583 /* Debugging routines for md_assemble. */
2584 static void pte (insn_template *);
2585 static void pt (i386_operand_type);
2586 static void pe (expressionS *);
2587 static void ps (symbolS *);
2590 pi (char *line, i386_insn *x)
2594 fprintf (stdout, "%s: template ", line);
2596 fprintf (stdout, " address: base %s index %s scale %x\n",
2597 x->base_reg ? x->base_reg->reg_name : "none",
2598 x->index_reg ? x->index_reg->reg_name : "none",
2599 x->log2_scale_factor);
2600 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2601 x->rm.mode, x->rm.reg, x->rm.regmem);
2602 fprintf (stdout, " sib: base %x index %x scale %x\n",
2603 x->sib.base, x->sib.index, x->sib.scale);
2604 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2605 (x->rex & REX_W) != 0,
2606 (x->rex & REX_R) != 0,
2607 (x->rex & REX_X) != 0,
2608 (x->rex & REX_B) != 0);
2609 for (j = 0; j < x->operands; j++)
2611 fprintf (stdout, " #%d: ", j + 1);
2613 fprintf (stdout, "\n");
2614 if (x->types[j].bitfield.reg8
2615 || x->types[j].bitfield.reg16
2616 || x->types[j].bitfield.reg32
2617 || x->types[j].bitfield.reg64
2618 || x->types[j].bitfield.regmmx
2619 || x->types[j].bitfield.regxmm
2620 || x->types[j].bitfield.regymm
2621 || x->types[j].bitfield.regzmm
2622 || x->types[j].bitfield.sreg2
2623 || x->types[j].bitfield.sreg3
2624 || x->types[j].bitfield.control
2625 || x->types[j].bitfield.debug
2626 || x->types[j].bitfield.test)
2627 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2628 if (operand_type_check (x->types[j], imm))
2630 if (operand_type_check (x->types[j], disp))
2631 pe (x->op[j].disps);
2636 pte (insn_template *t)
2639 fprintf (stdout, " %d operands ", t->operands);
2640 fprintf (stdout, "opcode %x ", t->base_opcode);
2641 if (t->extension_opcode != None)
2642 fprintf (stdout, "ext %x ", t->extension_opcode);
2643 if (t->opcode_modifier.d)
2644 fprintf (stdout, "D");
2645 if (t->opcode_modifier.w)
2646 fprintf (stdout, "W");
2647 fprintf (stdout, "\n");
2648 for (j = 0; j < t->operands; j++)
2650 fprintf (stdout, " #%d type ", j + 1);
2651 pt (t->operand_types[j]);
2652 fprintf (stdout, "\n");
2659 fprintf (stdout, " operation %d\n", e->X_op);
2660 fprintf (stdout, " add_number %ld (%lx)\n",
2661 (long) e->X_add_number, (long) e->X_add_number);
2662 if (e->X_add_symbol)
2664 fprintf (stdout, " add_symbol ");
2665 ps (e->X_add_symbol);
2666 fprintf (stdout, "\n");
2670 fprintf (stdout, " op_symbol ");
2671 ps (e->X_op_symbol);
2672 fprintf (stdout, "\n");
2679 fprintf (stdout, "%s type %s%s",
2681 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2682 segment_name (S_GET_SEGMENT (s)));
2685 static struct type_name
2687 i386_operand_type mask;
2690 const type_names[] =
2692 { OPERAND_TYPE_REG8, "r8" },
2693 { OPERAND_TYPE_REG16, "r16" },
2694 { OPERAND_TYPE_REG32, "r32" },
2695 { OPERAND_TYPE_REG64, "r64" },
2696 { OPERAND_TYPE_IMM8, "i8" },
2697 { OPERAND_TYPE_IMM8, "i8s" },
2698 { OPERAND_TYPE_IMM16, "i16" },
2699 { OPERAND_TYPE_IMM32, "i32" },
2700 { OPERAND_TYPE_IMM32S, "i32s" },
2701 { OPERAND_TYPE_IMM64, "i64" },
2702 { OPERAND_TYPE_IMM1, "i1" },
2703 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2704 { OPERAND_TYPE_DISP8, "d8" },
2705 { OPERAND_TYPE_DISP16, "d16" },
2706 { OPERAND_TYPE_DISP32, "d32" },
2707 { OPERAND_TYPE_DISP32S, "d32s" },
2708 { OPERAND_TYPE_DISP64, "d64" },
2709 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2710 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2711 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2712 { OPERAND_TYPE_CONTROL, "control reg" },
2713 { OPERAND_TYPE_TEST, "test reg" },
2714 { OPERAND_TYPE_DEBUG, "debug reg" },
2715 { OPERAND_TYPE_FLOATREG, "FReg" },
2716 { OPERAND_TYPE_FLOATACC, "FAcc" },
2717 { OPERAND_TYPE_SREG2, "SReg2" },
2718 { OPERAND_TYPE_SREG3, "SReg3" },
2719 { OPERAND_TYPE_ACC, "Acc" },
2720 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2721 { OPERAND_TYPE_REGMMX, "rMMX" },
2722 { OPERAND_TYPE_REGXMM, "rXMM" },
2723 { OPERAND_TYPE_REGYMM, "rYMM" },
2724 { OPERAND_TYPE_REGZMM, "rZMM" },
2725 { OPERAND_TYPE_REGMASK, "Mask reg" },
2726 { OPERAND_TYPE_ESSEG, "es" },
2730 pt (i386_operand_type t)
2733 i386_operand_type a;
2735 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2737 a = operand_type_and (t, type_names[j].mask);
2738 if (!operand_type_all_zero (&a))
2739 fprintf (stdout, "%s, ", type_names[j].name);
2744 #endif /* DEBUG386 */
2746 static bfd_reloc_code_real_type
2747 reloc (unsigned int size,
2750 bfd_reloc_code_real_type other)
2752 if (other != NO_RELOC)
2754 reloc_howto_type *rel;
2759 case BFD_RELOC_X86_64_GOT32:
2760 return BFD_RELOC_X86_64_GOT64;
2762 case BFD_RELOC_X86_64_PLTOFF64:
2763 return BFD_RELOC_X86_64_PLTOFF64;
2765 case BFD_RELOC_X86_64_GOTPC32:
2766 other = BFD_RELOC_X86_64_GOTPC64;
2768 case BFD_RELOC_X86_64_GOTPCREL:
2769 other = BFD_RELOC_X86_64_GOTPCREL64;
2771 case BFD_RELOC_X86_64_TPOFF32:
2772 other = BFD_RELOC_X86_64_TPOFF64;
2774 case BFD_RELOC_X86_64_DTPOFF32:
2775 other = BFD_RELOC_X86_64_DTPOFF64;
2781 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2782 if (other == BFD_RELOC_SIZE32)
2785 other = BFD_RELOC_SIZE64;
2788 as_bad (_("there are no pc-relative size relocations"));
2794 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2795 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2798 rel = bfd_reloc_type_lookup (stdoutput, other);
2800 as_bad (_("unknown relocation (%u)"), other);
2801 else if (size != bfd_get_reloc_size (rel))
2802 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2803 bfd_get_reloc_size (rel),
2805 else if (pcrel && !rel->pc_relative)
2806 as_bad (_("non-pc-relative relocation for pc-relative field"));
2807 else if ((rel->complain_on_overflow == complain_overflow_signed
2809 || (rel->complain_on_overflow == complain_overflow_unsigned
2811 as_bad (_("relocated field and relocation type differ in signedness"));
2820 as_bad (_("there are no unsigned pc-relative relocations"));
2823 case 1: return BFD_RELOC_8_PCREL;
2824 case 2: return BFD_RELOC_16_PCREL;
2825 case 4: return BFD_RELOC_32_PCREL;
2826 case 8: return BFD_RELOC_64_PCREL;
2828 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2835 case 4: return BFD_RELOC_X86_64_32S;
2840 case 1: return BFD_RELOC_8;
2841 case 2: return BFD_RELOC_16;
2842 case 4: return BFD_RELOC_32;
2843 case 8: return BFD_RELOC_64;
2845 as_bad (_("cannot do %s %u byte relocation"),
2846 sign > 0 ? "signed" : "unsigned", size);
2852 /* Here we decide which fixups can be adjusted to make them relative to
2853 the beginning of the section instead of the symbol. Basically we need
2854 to make sure that the dynamic relocations are done correctly, so in
2855 some cases we force the original symbol to be used. */
2858 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2860 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2864 /* Don't adjust pc-relative references to merge sections in 64-bit
2866 if (use_rela_relocations
2867 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2871 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2872 and changed later by validate_fix. */
2873 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2874 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2877 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2878 for size relocations. */
2879 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2880 || fixP->fx_r_type == BFD_RELOC_SIZE64
2881 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2882 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2883 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2884 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2885 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2886 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2887 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2888 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2889 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2890 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2891 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2892 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2893 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2894 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2895 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2896 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2897 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2898 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2899 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2900 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2901 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2902 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2903 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2904 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2905 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2906 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2907 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2908 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2915 intel_float_operand (const char *mnemonic)
2917 /* Note that the value returned is meaningful only for opcodes with (memory)
2918 operands, hence the code here is free to improperly handle opcodes that
2919 have no operands (for better performance and smaller code). */
2921 if (mnemonic[0] != 'f')
2922 return 0; /* non-math */
2924 switch (mnemonic[1])
2926 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2927 the fs segment override prefix not currently handled because no
2928 call path can make opcodes without operands get here */
2930 return 2 /* integer op */;
2932 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2933 return 3; /* fldcw/fldenv */
2936 if (mnemonic[2] != 'o' /* fnop */)
2937 return 3; /* non-waiting control op */
2940 if (mnemonic[2] == 's')
2941 return 3; /* frstor/frstpm */
2944 if (mnemonic[2] == 'a')
2945 return 3; /* fsave */
2946 if (mnemonic[2] == 't')
2948 switch (mnemonic[3])
2950 case 'c': /* fstcw */
2951 case 'd': /* fstdw */
2952 case 'e': /* fstenv */
2953 case 's': /* fsts[gw] */
2959 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2960 return 0; /* fxsave/fxrstor are not really math ops */
2967 /* Build the VEX prefix. */
2970 build_vex_prefix (const insn_template *t)
2972 unsigned int register_specifier;
2973 unsigned int implied_prefix;
2974 unsigned int vector_length;
2976 /* Check register specifier. */
2977 if (i.vex.register_specifier)
2979 register_specifier =
2980 ~register_number (i.vex.register_specifier) & 0xf;
2981 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
2984 register_specifier = 0xf;
2986 /* Use 2-byte VEX prefix by swappping destination and source
2989 && i.operands == i.reg_operands
2990 && i.tm.opcode_modifier.vexopcode == VEX0F
2991 && i.tm.opcode_modifier.s
2994 unsigned int xchg = i.operands - 1;
2995 union i386_op temp_op;
2996 i386_operand_type temp_type;
2998 temp_type = i.types[xchg];
2999 i.types[xchg] = i.types[0];
3000 i.types[0] = temp_type;
3001 temp_op = i.op[xchg];
3002 i.op[xchg] = i.op[0];
3005 gas_assert (i.rm.mode == 3);
3009 i.rm.regmem = i.rm.reg;
3012 /* Use the next insn. */
3016 if (i.tm.opcode_modifier.vex == VEXScalar)
3017 vector_length = avxscalar;
3019 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3021 switch ((i.tm.base_opcode >> 8) & 0xff)
3026 case DATA_PREFIX_OPCODE:
3029 case REPE_PREFIX_OPCODE:
3032 case REPNE_PREFIX_OPCODE:
3039 /* Use 2-byte VEX prefix if possible. */
3040 if (i.tm.opcode_modifier.vexopcode == VEX0F
3041 && i.tm.opcode_modifier.vexw != VEXW1
3042 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3044 /* 2-byte VEX prefix. */
3048 i.vex.bytes[0] = 0xc5;
3050 /* Check the REX.R bit. */
3051 r = (i.rex & REX_R) ? 0 : 1;
3052 i.vex.bytes[1] = (r << 7
3053 | register_specifier << 3
3054 | vector_length << 2
3059 /* 3-byte VEX prefix. */
3064 switch (i.tm.opcode_modifier.vexopcode)
3068 i.vex.bytes[0] = 0xc4;
3072 i.vex.bytes[0] = 0xc4;
3076 i.vex.bytes[0] = 0xc4;
3080 i.vex.bytes[0] = 0x8f;
3084 i.vex.bytes[0] = 0x8f;
3088 i.vex.bytes[0] = 0x8f;
3094 /* The high 3 bits of the second VEX byte are 1's compliment
3095 of RXB bits from REX. */
3096 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3098 /* Check the REX.W bit. */
3099 w = (i.rex & REX_W) ? 1 : 0;
3100 if (i.tm.opcode_modifier.vexw == VEXW1)
3103 i.vex.bytes[2] = (w << 7
3104 | register_specifier << 3
3105 | vector_length << 2
3110 /* Build the EVEX prefix. */
3113 build_evex_prefix (void)
3115 unsigned int register_specifier;
3116 unsigned int implied_prefix;
3118 rex_byte vrex_used = 0;
3120 /* Check register specifier. */
3121 if (i.vex.register_specifier)
3123 gas_assert ((i.vrex & REX_X) == 0);
3125 register_specifier = i.vex.register_specifier->reg_num;
3126 if ((i.vex.register_specifier->reg_flags & RegRex))
3127 register_specifier += 8;
3128 /* The upper 16 registers are encoded in the fourth byte of the
3130 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3131 i.vex.bytes[3] = 0x8;
3132 register_specifier = ~register_specifier & 0xf;
3136 register_specifier = 0xf;
3138 /* Encode upper 16 vector index register in the fourth byte of
3140 if (!(i.vrex & REX_X))
3141 i.vex.bytes[3] = 0x8;
3146 switch ((i.tm.base_opcode >> 8) & 0xff)
3151 case DATA_PREFIX_OPCODE:
3154 case REPE_PREFIX_OPCODE:
3157 case REPNE_PREFIX_OPCODE:
3164 /* 4 byte EVEX prefix. */
3166 i.vex.bytes[0] = 0x62;
3169 switch (i.tm.opcode_modifier.vexopcode)
3185 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3187 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3189 /* The fifth bit of the second EVEX byte is 1's compliment of the
3190 REX_R bit in VREX. */
3191 if (!(i.vrex & REX_R))
3192 i.vex.bytes[1] |= 0x10;
3196 if ((i.reg_operands + i.imm_operands) == i.operands)
3198 /* When all operands are registers, the REX_X bit in REX is not
3199 used. We reuse it to encode the upper 16 registers, which is
3200 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3201 as 1's compliment. */
3202 if ((i.vrex & REX_B))
3205 i.vex.bytes[1] &= ~0x40;
3209 /* EVEX instructions shouldn't need the REX prefix. */
3210 i.vrex &= ~vrex_used;
3211 gas_assert (i.vrex == 0);
3213 /* Check the REX.W bit. */
3214 w = (i.rex & REX_W) ? 1 : 0;
3215 if (i.tm.opcode_modifier.vexw)
3217 if (i.tm.opcode_modifier.vexw == VEXW1)
3220 /* If w is not set it means we are dealing with WIG instruction. */
3223 if (evexwig == evexw1)
3227 /* Encode the U bit. */
3228 implied_prefix |= 0x4;
3230 /* The third byte of the EVEX prefix. */
3231 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3233 /* The fourth byte of the EVEX prefix. */
3234 /* The zeroing-masking bit. */
3235 if (i.mask && i.mask->zeroing)
3236 i.vex.bytes[3] |= 0x80;
3238 /* Don't always set the broadcast bit if there is no RC. */
3241 /* Encode the vector length. */
3242 unsigned int vec_length;
3244 switch (i.tm.opcode_modifier.evex)
3246 case EVEXLIG: /* LL' is ignored */
3247 vec_length = evexlig << 5;
3250 vec_length = 0 << 5;
3253 vec_length = 1 << 5;
3256 vec_length = 2 << 5;
3262 i.vex.bytes[3] |= vec_length;
3263 /* Encode the broadcast bit. */
3265 i.vex.bytes[3] |= 0x10;
3269 if (i.rounding->type != saeonly)
3270 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3272 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3275 if (i.mask && i.mask->mask)
3276 i.vex.bytes[3] |= i.mask->mask->reg_num;
3280 process_immext (void)
3284 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3287 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3288 with an opcode suffix which is coded in the same place as an
3289 8-bit immediate field would be.
3290 Here we check those operands and remove them afterwards. */
3293 for (x = 0; x < i.operands; x++)
3294 if (register_number (i.op[x].regs) != x)
3295 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3296 register_prefix, i.op[x].regs->reg_name, x + 1,
3302 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3303 which is coded in the same place as an 8-bit immediate field
3304 would be. Here we fake an 8-bit immediate operand from the
3305 opcode suffix stored in tm.extension_opcode.
3307 AVX instructions also use this encoding, for some of
3308 3 argument instructions. */
3310 gas_assert (i.imm_operands <= 1
3312 || ((i.tm.opcode_modifier.vex
3313 || i.tm.opcode_modifier.evex)
3314 && i.operands <= 4)));
3316 exp = &im_expressions[i.imm_operands++];
3317 i.op[i.operands].imms = exp;
3318 i.types[i.operands] = imm8;
3320 exp->X_op = O_constant;
3321 exp->X_add_number = i.tm.extension_opcode;
3322 i.tm.extension_opcode = None;
3329 switch (i.tm.opcode_modifier.hleprefixok)
3334 as_bad (_("invalid instruction `%s' after `%s'"),
3335 i.tm.name, i.hle_prefix);
3338 if (i.prefix[LOCK_PREFIX])
3340 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3344 case HLEPrefixRelease:
3345 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3347 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3351 if (i.mem_operands == 0
3352 || !operand_type_check (i.types[i.operands - 1], anymem))
3354 as_bad (_("memory destination needed for instruction `%s'"
3355 " after `xrelease'"), i.tm.name);
3362 /* This is the guts of the machine-dependent assembler. LINE points to a
3363 machine dependent instruction. This function is supposed to emit
3364 the frags/bytes it assembles to. */
3367 md_assemble (char *line)
3370 char mnemonic[MAX_MNEM_SIZE];
3371 const insn_template *t;
3373 /* Initialize globals. */
3374 memset (&i, '\0', sizeof (i));
3375 for (j = 0; j < MAX_OPERANDS; j++)
3376 i.reloc[j] = NO_RELOC;
3377 memset (disp_expressions, '\0', sizeof (disp_expressions));
3378 memset (im_expressions, '\0', sizeof (im_expressions));
3379 save_stack_p = save_stack;
3381 /* First parse an instruction mnemonic & call i386_operand for the operands.
3382 We assume that the scrubber has arranged it so that line[0] is the valid
3383 start of a (possibly prefixed) mnemonic. */
3385 line = parse_insn (line, mnemonic);
3389 line = parse_operands (line, mnemonic);
3394 /* Now we've parsed the mnemonic into a set of templates, and have the
3395 operands at hand. */
3397 /* All intel opcodes have reversed operands except for "bound" and
3398 "enter". We also don't reverse intersegment "jmp" and "call"
3399 instructions with 2 immediate operands so that the immediate segment
3400 precedes the offset, as it does when in AT&T mode. */
3403 && (strcmp (mnemonic, "bound") != 0)
3404 && (strcmp (mnemonic, "invlpga") != 0)
3405 && !(operand_type_check (i.types[0], imm)
3406 && operand_type_check (i.types[1], imm)))
3409 /* The order of the immediates should be reversed
3410 for 2 immediates extrq and insertq instructions */
3411 if (i.imm_operands == 2
3412 && (strcmp (mnemonic, "extrq") == 0
3413 || strcmp (mnemonic, "insertq") == 0))
3414 swap_2_operands (0, 1);
3419 /* Don't optimize displacement for movabs since it only takes 64bit
3422 && i.disp_encoding != disp_encoding_32bit
3423 && (flag_code != CODE_64BIT
3424 || strcmp (mnemonic, "movabs") != 0))
3427 /* Next, we find a template that matches the given insn,
3428 making sure the overlap of the given operands types is consistent
3429 with the template operand types. */
3431 if (!(t = match_template ()))
3434 if (sse_check != check_none
3435 && !i.tm.opcode_modifier.noavx
3436 && (i.tm.cpu_flags.bitfield.cpusse
3437 || i.tm.cpu_flags.bitfield.cpusse2
3438 || i.tm.cpu_flags.bitfield.cpusse3
3439 || i.tm.cpu_flags.bitfield.cpussse3
3440 || i.tm.cpu_flags.bitfield.cpusse4_1
3441 || i.tm.cpu_flags.bitfield.cpusse4_2))
3443 (sse_check == check_warning
3445 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3448 /* Zap movzx and movsx suffix. The suffix has been set from
3449 "word ptr" or "byte ptr" on the source operand in Intel syntax
3450 or extracted from mnemonic in AT&T syntax. But we'll use
3451 the destination register to choose the suffix for encoding. */
3452 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3454 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3455 there is no suffix, the default will be byte extension. */
3456 if (i.reg_operands != 2
3459 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3464 if (i.tm.opcode_modifier.fwait)
3465 if (!add_prefix (FWAIT_OPCODE))
3468 /* Check if REP prefix is OK. */
3469 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3471 as_bad (_("invalid instruction `%s' after `%s'"),
3472 i.tm.name, i.rep_prefix);
3476 /* Check for lock without a lockable instruction. Destination operand
3477 must be memory unless it is xchg (0x86). */
3478 if (i.prefix[LOCK_PREFIX]
3479 && (!i.tm.opcode_modifier.islockable
3480 || i.mem_operands == 0
3481 || (i.tm.base_opcode != 0x86
3482 && !operand_type_check (i.types[i.operands - 1], anymem))))
3484 as_bad (_("expecting lockable instruction after `lock'"));
3488 /* Check if HLE prefix is OK. */
3489 if (i.hle_prefix && !check_hle ())
3492 /* Check BND prefix. */
3493 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3494 as_bad (_("expecting valid branch instruction after `bnd'"));
3496 if (i.tm.cpu_flags.bitfield.cpumpx
3497 && flag_code == CODE_64BIT
3498 && i.prefix[ADDR_PREFIX])
3499 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3501 /* Insert BND prefix. */
3503 && i.tm.opcode_modifier.bndprefixok
3504 && !i.prefix[BND_PREFIX])
3505 add_prefix (BND_PREFIX_OPCODE);
3507 /* Check string instruction segment overrides. */
3508 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3510 if (!check_string ())
3512 i.disp_operands = 0;
3515 if (!process_suffix ())
3518 /* Update operand types. */
3519 for (j = 0; j < i.operands; j++)
3520 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3522 /* Make still unresolved immediate matches conform to size of immediate
3523 given in i.suffix. */
3524 if (!finalize_imm ())
3527 if (i.types[0].bitfield.imm1)
3528 i.imm_operands = 0; /* kludge for shift insns. */
3530 /* We only need to check those implicit registers for instructions
3531 with 3 operands or less. */
3532 if (i.operands <= 3)
3533 for (j = 0; j < i.operands; j++)
3534 if (i.types[j].bitfield.inoutportreg
3535 || i.types[j].bitfield.shiftcount
3536 || i.types[j].bitfield.acc
3537 || i.types[j].bitfield.floatacc)
3540 /* ImmExt should be processed after SSE2AVX. */
3541 if (!i.tm.opcode_modifier.sse2avx
3542 && i.tm.opcode_modifier.immext)
3545 /* For insns with operands there are more diddles to do to the opcode. */
3548 if (!process_operands ())
3551 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3553 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3554 as_warn (_("translating to `%sp'"), i.tm.name);
3557 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3559 if (flag_code == CODE_16BIT)
3561 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3566 if (i.tm.opcode_modifier.vex)
3567 build_vex_prefix (t);
3569 build_evex_prefix ();
3572 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3573 instructions may define INT_OPCODE as well, so avoid this corner
3574 case for those instructions that use MODRM. */
3575 if (i.tm.base_opcode == INT_OPCODE
3576 && !i.tm.opcode_modifier.modrm
3577 && i.op[0].imms->X_add_number == 3)
3579 i.tm.base_opcode = INT3_OPCODE;
3583 if ((i.tm.opcode_modifier.jump
3584 || i.tm.opcode_modifier.jumpbyte
3585 || i.tm.opcode_modifier.jumpdword)
3586 && i.op[0].disps->X_op == O_constant)
3588 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3589 the absolute address given by the constant. Since ix86 jumps and
3590 calls are pc relative, we need to generate a reloc. */
3591 i.op[0].disps->X_add_symbol = &abs_symbol;
3592 i.op[0].disps->X_op = O_symbol;
3595 if (i.tm.opcode_modifier.rex64)
3598 /* For 8 bit registers we need an empty rex prefix. Also if the
3599 instruction already has a prefix, we need to convert old
3600 registers to new ones. */
3602 if ((i.types[0].bitfield.reg8
3603 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3604 || (i.types[1].bitfield.reg8
3605 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3606 || ((i.types[0].bitfield.reg8
3607 || i.types[1].bitfield.reg8)
3612 i.rex |= REX_OPCODE;
3613 for (x = 0; x < 2; x++)
3615 /* Look for 8 bit operand that uses old registers. */
3616 if (i.types[x].bitfield.reg8
3617 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3619 /* In case it is "hi" register, give up. */
3620 if (i.op[x].regs->reg_num > 3)
3621 as_bad (_("can't encode register '%s%s' in an "
3622 "instruction requiring REX prefix."),
3623 register_prefix, i.op[x].regs->reg_name);
3625 /* Otherwise it is equivalent to the extended register.
3626 Since the encoding doesn't change this is merely
3627 cosmetic cleanup for debug output. */
3629 i.op[x].regs = i.op[x].regs + 8;
3635 add_prefix (REX_OPCODE | i.rex);
3637 /* We are ready to output the insn. */
3642 parse_insn (char *line, char *mnemonic)
3645 char *token_start = l;
3648 const insn_template *t;
3654 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3659 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3661 as_bad (_("no such instruction: `%s'"), token_start);
3666 if (!is_space_char (*l)
3667 && *l != END_OF_INSN
3669 || (*l != PREFIX_SEPARATOR
3672 as_bad (_("invalid character %s in mnemonic"),
3673 output_invalid (*l));
3676 if (token_start == l)
3678 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3679 as_bad (_("expecting prefix; got nothing"));
3681 as_bad (_("expecting mnemonic; got nothing"));
3685 /* Look up instruction (or prefix) via hash table. */
3686 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3688 if (*l != END_OF_INSN
3689 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3690 && current_templates
3691 && current_templates->start->opcode_modifier.isprefix)
3693 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3695 as_bad ((flag_code != CODE_64BIT
3696 ? _("`%s' is only supported in 64-bit mode")
3697 : _("`%s' is not supported in 64-bit mode")),
3698 current_templates->start->name);
3701 /* If we are in 16-bit mode, do not allow addr16 or data16.
3702 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3703 if ((current_templates->start->opcode_modifier.size16
3704 || current_templates->start->opcode_modifier.size32)
3705 && flag_code != CODE_64BIT
3706 && (current_templates->start->opcode_modifier.size32
3707 ^ (flag_code == CODE_16BIT)))
3709 as_bad (_("redundant %s prefix"),
3710 current_templates->start->name);
3713 /* Add prefix, checking for repeated prefixes. */
3714 switch (add_prefix (current_templates->start->base_opcode))
3719 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3720 i.hle_prefix = current_templates->start->name;
3721 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3722 i.bnd_prefix = current_templates->start->name;
3724 i.rep_prefix = current_templates->start->name;
3729 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3736 if (!current_templates)
3738 /* Check if we should swap operand or force 32bit displacement in
3740 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3742 else if (mnem_p - 3 == dot_p
3745 i.disp_encoding = disp_encoding_8bit;
3746 else if (mnem_p - 4 == dot_p
3750 i.disp_encoding = disp_encoding_32bit;
3755 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3758 if (!current_templates)
3761 /* See if we can get a match by trimming off a suffix. */
3764 case WORD_MNEM_SUFFIX:
3765 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3766 i.suffix = SHORT_MNEM_SUFFIX;
3768 case BYTE_MNEM_SUFFIX:
3769 case QWORD_MNEM_SUFFIX:
3770 i.suffix = mnem_p[-1];
3772 current_templates = (const templates *) hash_find (op_hash,
3775 case SHORT_MNEM_SUFFIX:
3776 case LONG_MNEM_SUFFIX:
3779 i.suffix = mnem_p[-1];
3781 current_templates = (const templates *) hash_find (op_hash,
3790 if (intel_float_operand (mnemonic) == 1)
3791 i.suffix = SHORT_MNEM_SUFFIX;
3793 i.suffix = LONG_MNEM_SUFFIX;
3795 current_templates = (const templates *) hash_find (op_hash,
3800 if (!current_templates)
3802 as_bad (_("no such instruction: `%s'"), token_start);
3807 if (current_templates->start->opcode_modifier.jump
3808 || current_templates->start->opcode_modifier.jumpbyte)
3810 /* Check for a branch hint. We allow ",pt" and ",pn" for
3811 predict taken and predict not taken respectively.
3812 I'm not sure that branch hints actually do anything on loop
3813 and jcxz insns (JumpByte) for current Pentium4 chips. They
3814 may work in the future and it doesn't hurt to accept them
3816 if (l[0] == ',' && l[1] == 'p')
3820 if (!add_prefix (DS_PREFIX_OPCODE))
3824 else if (l[2] == 'n')
3826 if (!add_prefix (CS_PREFIX_OPCODE))
3832 /* Any other comma loses. */
3835 as_bad (_("invalid character %s in mnemonic"),
3836 output_invalid (*l));
3840 /* Check if instruction is supported on specified architecture. */
3842 for (t = current_templates->start; t < current_templates->end; ++t)
3844 supported |= cpu_flags_match (t);
3845 if (supported == CPU_FLAGS_PERFECT_MATCH)
3849 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3851 as_bad (flag_code == CODE_64BIT
3852 ? _("`%s' is not supported in 64-bit mode")
3853 : _("`%s' is only supported in 64-bit mode"),
3854 current_templates->start->name);
3857 if (supported != CPU_FLAGS_PERFECT_MATCH)
3859 as_bad (_("`%s' is not supported on `%s%s'"),
3860 current_templates->start->name,
3861 cpu_arch_name ? cpu_arch_name : default_arch,
3862 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3867 if (!cpu_arch_flags.bitfield.cpui386
3868 && (flag_code != CODE_16BIT))
3870 as_warn (_("use .code16 to ensure correct addressing mode"));
3877 parse_operands (char *l, const char *mnemonic)
3881 /* 1 if operand is pending after ','. */
3882 unsigned int expecting_operand = 0;
3884 /* Non-zero if operand parens not balanced. */
3885 unsigned int paren_not_balanced;
3887 while (*l != END_OF_INSN)
3889 /* Skip optional white space before operand. */
3890 if (is_space_char (*l))
3892 if (!is_operand_char (*l) && *l != END_OF_INSN)
3894 as_bad (_("invalid character %s before operand %d"),
3895 output_invalid (*l),
3899 token_start = l; /* after white space */
3900 paren_not_balanced = 0;
3901 while (paren_not_balanced || *l != ',')
3903 if (*l == END_OF_INSN)
3905 if (paren_not_balanced)
3908 as_bad (_("unbalanced parenthesis in operand %d."),
3911 as_bad (_("unbalanced brackets in operand %d."),
3916 break; /* we are done */
3918 else if (!is_operand_char (*l) && !is_space_char (*l))
3920 as_bad (_("invalid character %s in operand %d"),
3921 output_invalid (*l),
3928 ++paren_not_balanced;
3930 --paren_not_balanced;
3935 ++paren_not_balanced;
3937 --paren_not_balanced;
3941 if (l != token_start)
3942 { /* Yes, we've read in another operand. */
3943 unsigned int operand_ok;
3944 this_operand = i.operands++;
3945 i.types[this_operand].bitfield.unspecified = 1;
3946 if (i.operands > MAX_OPERANDS)
3948 as_bad (_("spurious operands; (%d operands/instruction max)"),
3952 /* Now parse operand adding info to 'i' as we go along. */
3953 END_STRING_AND_SAVE (l);
3957 i386_intel_operand (token_start,
3958 intel_float_operand (mnemonic));
3960 operand_ok = i386_att_operand (token_start);
3962 RESTORE_END_STRING (l);
3968 if (expecting_operand)
3970 expecting_operand_after_comma:
3971 as_bad (_("expecting operand after ','; got nothing"));
3976 as_bad (_("expecting operand before ','; got nothing"));
3981 /* Now *l must be either ',' or END_OF_INSN. */
3984 if (*++l == END_OF_INSN)
3986 /* Just skip it, if it's \n complain. */
3987 goto expecting_operand_after_comma;
3989 expecting_operand = 1;
3996 swap_2_operands (int xchg1, int xchg2)
3998 union i386_op temp_op;
3999 i386_operand_type temp_type;
4000 enum bfd_reloc_code_real temp_reloc;
4002 temp_type = i.types[xchg2];
4003 i.types[xchg2] = i.types[xchg1];
4004 i.types[xchg1] = temp_type;
4005 temp_op = i.op[xchg2];
4006 i.op[xchg2] = i.op[xchg1];
4007 i.op[xchg1] = temp_op;
4008 temp_reloc = i.reloc[xchg2];
4009 i.reloc[xchg2] = i.reloc[xchg1];
4010 i.reloc[xchg1] = temp_reloc;
4014 if (i.mask->operand == xchg1)
4015 i.mask->operand = xchg2;
4016 else if (i.mask->operand == xchg2)
4017 i.mask->operand = xchg1;
4021 if (i.broadcast->operand == xchg1)
4022 i.broadcast->operand = xchg2;
4023 else if (i.broadcast->operand == xchg2)
4024 i.broadcast->operand = xchg1;
4028 if (i.rounding->operand == xchg1)
4029 i.rounding->operand = xchg2;
4030 else if (i.rounding->operand == xchg2)
4031 i.rounding->operand = xchg1;
4036 swap_operands (void)
4042 swap_2_operands (1, i.operands - 2);
4045 swap_2_operands (0, i.operands - 1);
4051 if (i.mem_operands == 2)
4053 const seg_entry *temp_seg;
4054 temp_seg = i.seg[0];
4055 i.seg[0] = i.seg[1];
4056 i.seg[1] = temp_seg;
4060 /* Try to ensure constant immediates are represented in the smallest
4065 char guess_suffix = 0;
4069 guess_suffix = i.suffix;
4070 else if (i.reg_operands)
4072 /* Figure out a suffix from the last register operand specified.
4073 We can't do this properly yet, ie. excluding InOutPortReg,
4074 but the following works for instructions with immediates.
4075 In any case, we can't set i.suffix yet. */
4076 for (op = i.operands; --op >= 0;)
4077 if (i.types[op].bitfield.reg8)
4079 guess_suffix = BYTE_MNEM_SUFFIX;
4082 else if (i.types[op].bitfield.reg16)
4084 guess_suffix = WORD_MNEM_SUFFIX;
4087 else if (i.types[op].bitfield.reg32)
4089 guess_suffix = LONG_MNEM_SUFFIX;
4092 else if (i.types[op].bitfield.reg64)
4094 guess_suffix = QWORD_MNEM_SUFFIX;
4098 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4099 guess_suffix = WORD_MNEM_SUFFIX;
4101 for (op = i.operands; --op >= 0;)
4102 if (operand_type_check (i.types[op], imm))
4104 switch (i.op[op].imms->X_op)
4107 /* If a suffix is given, this operand may be shortened. */
4108 switch (guess_suffix)
4110 case LONG_MNEM_SUFFIX:
4111 i.types[op].bitfield.imm32 = 1;
4112 i.types[op].bitfield.imm64 = 1;
4114 case WORD_MNEM_SUFFIX:
4115 i.types[op].bitfield.imm16 = 1;
4116 i.types[op].bitfield.imm32 = 1;
4117 i.types[op].bitfield.imm32s = 1;
4118 i.types[op].bitfield.imm64 = 1;
4120 case BYTE_MNEM_SUFFIX:
4121 i.types[op].bitfield.imm8 = 1;
4122 i.types[op].bitfield.imm8s = 1;
4123 i.types[op].bitfield.imm16 = 1;
4124 i.types[op].bitfield.imm32 = 1;
4125 i.types[op].bitfield.imm32s = 1;
4126 i.types[op].bitfield.imm64 = 1;
4130 /* If this operand is at most 16 bits, convert it
4131 to a signed 16 bit number before trying to see
4132 whether it will fit in an even smaller size.
4133 This allows a 16-bit operand such as $0xffe0 to
4134 be recognised as within Imm8S range. */
4135 if ((i.types[op].bitfield.imm16)
4136 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4138 i.op[op].imms->X_add_number =
4139 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4141 if ((i.types[op].bitfield.imm32)
4142 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4145 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4146 ^ ((offsetT) 1 << 31))
4147 - ((offsetT) 1 << 31));
4150 = operand_type_or (i.types[op],
4151 smallest_imm_type (i.op[op].imms->X_add_number));
4153 /* We must avoid matching of Imm32 templates when 64bit
4154 only immediate is available. */
4155 if (guess_suffix == QWORD_MNEM_SUFFIX)
4156 i.types[op].bitfield.imm32 = 0;
4163 /* Symbols and expressions. */
4165 /* Convert symbolic operand to proper sizes for matching, but don't
4166 prevent matching a set of insns that only supports sizes other
4167 than those matching the insn suffix. */
4169 i386_operand_type mask, allowed;
4170 const insn_template *t;
4172 operand_type_set (&mask, 0);
4173 operand_type_set (&allowed, 0);
4175 for (t = current_templates->start;
4176 t < current_templates->end;
4178 allowed = operand_type_or (allowed,
4179 t->operand_types[op]);
4180 switch (guess_suffix)
4182 case QWORD_MNEM_SUFFIX:
4183 mask.bitfield.imm64 = 1;
4184 mask.bitfield.imm32s = 1;
4186 case LONG_MNEM_SUFFIX:
4187 mask.bitfield.imm32 = 1;
4189 case WORD_MNEM_SUFFIX:
4190 mask.bitfield.imm16 = 1;
4192 case BYTE_MNEM_SUFFIX:
4193 mask.bitfield.imm8 = 1;
4198 allowed = operand_type_and (mask, allowed);
4199 if (!operand_type_all_zero (&allowed))
4200 i.types[op] = operand_type_and (i.types[op], mask);
4207 /* Try to use the smallest displacement type too. */
4209 optimize_disp (void)
4213 for (op = i.operands; --op >= 0;)
4214 if (operand_type_check (i.types[op], disp))
4216 if (i.op[op].disps->X_op == O_constant)
4218 offsetT op_disp = i.op[op].disps->X_add_number;
4220 if (i.types[op].bitfield.disp16
4221 && (op_disp & ~(offsetT) 0xffff) == 0)
4223 /* If this operand is at most 16 bits, convert
4224 to a signed 16 bit number and don't use 64bit
4226 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4227 i.types[op].bitfield.disp64 = 0;
4229 if (i.types[op].bitfield.disp32
4230 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4232 /* If this operand is at most 32 bits, convert
4233 to a signed 32 bit number and don't use 64bit
4235 op_disp &= (((offsetT) 2 << 31) - 1);
4236 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4237 i.types[op].bitfield.disp64 = 0;
4239 if (!op_disp && i.types[op].bitfield.baseindex)
4241 i.types[op].bitfield.disp8 = 0;
4242 i.types[op].bitfield.disp16 = 0;
4243 i.types[op].bitfield.disp32 = 0;
4244 i.types[op].bitfield.disp32s = 0;
4245 i.types[op].bitfield.disp64 = 0;
4249 else if (flag_code == CODE_64BIT)
4251 if (fits_in_signed_long (op_disp))
4253 i.types[op].bitfield.disp64 = 0;
4254 i.types[op].bitfield.disp32s = 1;
4256 if (i.prefix[ADDR_PREFIX]
4257 && fits_in_unsigned_long (op_disp))
4258 i.types[op].bitfield.disp32 = 1;
4260 if ((i.types[op].bitfield.disp32
4261 || i.types[op].bitfield.disp32s
4262 || i.types[op].bitfield.disp16)
4263 && fits_in_signed_byte (op_disp))
4264 i.types[op].bitfield.disp8 = 1;
4266 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4267 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4269 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4270 i.op[op].disps, 0, i.reloc[op]);
4271 i.types[op].bitfield.disp8 = 0;
4272 i.types[op].bitfield.disp16 = 0;
4273 i.types[op].bitfield.disp32 = 0;
4274 i.types[op].bitfield.disp32s = 0;
4275 i.types[op].bitfield.disp64 = 0;
4278 /* We only support 64bit displacement on constants. */
4279 i.types[op].bitfield.disp64 = 0;
4283 /* Check if operands are valid for the instruction. */
4286 check_VecOperands (const insn_template *t)
4290 /* Without VSIB byte, we can't have a vector register for index. */
4291 if (!t->opcode_modifier.vecsib
4293 && (i.index_reg->reg_type.bitfield.regxmm
4294 || i.index_reg->reg_type.bitfield.regymm
4295 || i.index_reg->reg_type.bitfield.regzmm))
4297 i.error = unsupported_vector_index_register;
4301 /* Check if default mask is allowed. */
4302 if (t->opcode_modifier.nodefmask
4303 && (!i.mask || i.mask->mask->reg_num == 0))
4305 i.error = no_default_mask;
4309 /* For VSIB byte, we need a vector register for index, and all vector
4310 registers must be distinct. */
4311 if (t->opcode_modifier.vecsib)
4314 || !((t->opcode_modifier.vecsib == VecSIB128
4315 && i.index_reg->reg_type.bitfield.regxmm)
4316 || (t->opcode_modifier.vecsib == VecSIB256
4317 && i.index_reg->reg_type.bitfield.regymm)
4318 || (t->opcode_modifier.vecsib == VecSIB512
4319 && i.index_reg->reg_type.bitfield.regzmm)))
4321 i.error = invalid_vsib_address;
4325 gas_assert (i.reg_operands == 2 || i.mask);
4326 if (i.reg_operands == 2 && !i.mask)
4328 gas_assert (i.types[0].bitfield.regxmm
4329 || i.types[0].bitfield.regymm);
4330 gas_assert (i.types[2].bitfield.regxmm
4331 || i.types[2].bitfield.regymm);
4332 if (operand_check == check_none)
4334 if (register_number (i.op[0].regs)
4335 != register_number (i.index_reg)
4336 && register_number (i.op[2].regs)
4337 != register_number (i.index_reg)
4338 && register_number (i.op[0].regs)
4339 != register_number (i.op[2].regs))
4341 if (operand_check == check_error)
4343 i.error = invalid_vector_register_set;
4346 as_warn (_("mask, index, and destination registers should be distinct"));
4348 else if (i.reg_operands == 1 && i.mask)
4350 if ((i.types[1].bitfield.regymm
4351 || i.types[1].bitfield.regzmm)
4352 && (register_number (i.op[1].regs)
4353 == register_number (i.index_reg)))
4355 if (operand_check == check_error)
4357 i.error = invalid_vector_register_set;
4360 if (operand_check != check_none)
4361 as_warn (_("index and destination registers should be distinct"));
4366 /* Check if broadcast is supported by the instruction and is applied
4367 to the memory operand. */
4370 int broadcasted_opnd_size;
4372 /* Check if specified broadcast is supported in this instruction,
4373 and it's applied to memory operand of DWORD or QWORD type,
4374 depending on VecESize. */
4375 if (i.broadcast->type != t->opcode_modifier.broadcast
4376 || !i.types[i.broadcast->operand].bitfield.mem
4377 || (t->opcode_modifier.vecesize == 0
4378 && !i.types[i.broadcast->operand].bitfield.dword
4379 && !i.types[i.broadcast->operand].bitfield.unspecified)
4380 || (t->opcode_modifier.vecesize == 1
4381 && !i.types[i.broadcast->operand].bitfield.qword
4382 && !i.types[i.broadcast->operand].bitfield.unspecified))
4385 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4386 if (i.broadcast->type == BROADCAST_1TO16)
4387 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4388 else if (i.broadcast->type == BROADCAST_1TO8)
4389 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4390 else if (i.broadcast->type == BROADCAST_1TO4)
4391 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4392 else if (i.broadcast->type == BROADCAST_1TO2)
4393 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4397 if ((broadcasted_opnd_size == 256
4398 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4399 || (broadcasted_opnd_size == 512
4400 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4403 i.error = unsupported_broadcast;
4407 /* If broadcast is supported in this instruction, we need to check if
4408 operand of one-element size isn't specified without broadcast. */
4409 else if (t->opcode_modifier.broadcast && i.mem_operands)
4411 /* Find memory operand. */
4412 for (op = 0; op < i.operands; op++)
4413 if (operand_type_check (i.types[op], anymem))
4415 gas_assert (op < i.operands);
4416 /* Check size of the memory operand. */
4417 if ((t->opcode_modifier.vecesize == 0
4418 && i.types[op].bitfield.dword)
4419 || (t->opcode_modifier.vecesize == 1
4420 && i.types[op].bitfield.qword))
4422 i.error = broadcast_needed;
4427 /* Check if requested masking is supported. */
4429 && (!t->opcode_modifier.masking
4431 && t->opcode_modifier.masking == MERGING_MASKING)))
4433 i.error = unsupported_masking;
4437 /* Check if masking is applied to dest operand. */
4438 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4440 i.error = mask_not_on_destination;
4447 if ((i.rounding->type != saeonly
4448 && !t->opcode_modifier.staticrounding)
4449 || (i.rounding->type == saeonly
4450 && (t->opcode_modifier.staticrounding
4451 || !t->opcode_modifier.sae)))
4453 i.error = unsupported_rc_sae;
4456 /* If the instruction has several immediate operands and one of
4457 them is rounding, the rounding operand should be the last
4458 immediate operand. */
4459 if (i.imm_operands > 1
4460 && i.rounding->operand != (int) (i.imm_operands - 1))
4462 i.error = rc_sae_operand_not_last_imm;
4467 /* Check vector Disp8 operand. */
4468 if (t->opcode_modifier.disp8memshift)
4471 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4473 i.memshift = t->opcode_modifier.disp8memshift;
4475 for (op = 0; op < i.operands; op++)
4476 if (operand_type_check (i.types[op], disp)
4477 && i.op[op].disps->X_op == O_constant)
4479 offsetT value = i.op[op].disps->X_add_number;
4480 int vec_disp8_ok = fits_in_vec_disp8 (value);
4481 if (t->operand_types [op].bitfield.vec_disp8)
4484 i.types[op].bitfield.vec_disp8 = 1;
4487 /* Vector insn can only have Vec_Disp8/Disp32 in
4488 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4490 i.types[op].bitfield.disp8 = 0;
4491 if (flag_code != CODE_16BIT)
4492 i.types[op].bitfield.disp16 = 0;
4495 else if (flag_code != CODE_16BIT)
4497 /* One form of this instruction supports vector Disp8.
4498 Try vector Disp8 if we need to use Disp32. */
4499 if (vec_disp8_ok && !fits_in_signed_byte (value))
4501 i.error = try_vector_disp8;
4513 /* Check if operands are valid for the instruction. Update VEX
4517 VEX_check_operands (const insn_template *t)
4519 /* VREX is only valid with EVEX prefix. */
4520 if (i.need_vrex && !t->opcode_modifier.evex)
4522 i.error = invalid_register_operand;
4526 if (!t->opcode_modifier.vex)
4529 /* Only check VEX_Imm4, which must be the first operand. */
4530 if (t->operand_types[0].bitfield.vec_imm4)
4532 if (i.op[0].imms->X_op != O_constant
4533 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4539 /* Turn off Imm8 so that update_imm won't complain. */
4540 i.types[0] = vec_imm4;
4546 static const insn_template *
4547 match_template (void)
4549 /* Points to template once we've found it. */
4550 const insn_template *t;
4551 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4552 i386_operand_type overlap4;
4553 unsigned int found_reverse_match;
4554 i386_opcode_modifier suffix_check;
4555 i386_operand_type operand_types [MAX_OPERANDS];
4556 int addr_prefix_disp;
4558 unsigned int found_cpu_match;
4559 unsigned int check_register;
4560 enum i386_error specific_error = 0;
4562 #if MAX_OPERANDS != 5
4563 # error "MAX_OPERANDS must be 5."
4566 found_reverse_match = 0;
4567 addr_prefix_disp = -1;
4569 memset (&suffix_check, 0, sizeof (suffix_check));
4570 if (i.suffix == BYTE_MNEM_SUFFIX)
4571 suffix_check.no_bsuf = 1;
4572 else if (i.suffix == WORD_MNEM_SUFFIX)
4573 suffix_check.no_wsuf = 1;
4574 else if (i.suffix == SHORT_MNEM_SUFFIX)
4575 suffix_check.no_ssuf = 1;
4576 else if (i.suffix == LONG_MNEM_SUFFIX)
4577 suffix_check.no_lsuf = 1;
4578 else if (i.suffix == QWORD_MNEM_SUFFIX)
4579 suffix_check.no_qsuf = 1;
4580 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4581 suffix_check.no_ldsuf = 1;
4583 /* Must have right number of operands. */
4584 i.error = number_of_operands_mismatch;
4586 for (t = current_templates->start; t < current_templates->end; t++)
4588 addr_prefix_disp = -1;
4590 if (i.operands != t->operands)
4593 /* Check processor support. */
4594 i.error = unsupported;
4595 found_cpu_match = (cpu_flags_match (t)
4596 == CPU_FLAGS_PERFECT_MATCH);
4597 if (!found_cpu_match)
4600 /* Check old gcc support. */
4601 i.error = old_gcc_only;
4602 if (!old_gcc && t->opcode_modifier.oldgcc)
4605 /* Check AT&T mnemonic. */
4606 i.error = unsupported_with_intel_mnemonic;
4607 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4610 /* Check AT&T/Intel syntax. */
4611 i.error = unsupported_syntax;
4612 if ((intel_syntax && t->opcode_modifier.attsyntax)
4613 || (!intel_syntax && t->opcode_modifier.intelsyntax))
4616 /* Check the suffix, except for some instructions in intel mode. */
4617 i.error = invalid_instruction_suffix;
4618 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4619 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4620 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4621 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4622 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4623 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4624 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4627 if (!operand_size_match (t))
4630 for (j = 0; j < MAX_OPERANDS; j++)
4631 operand_types[j] = t->operand_types[j];
4633 /* In general, don't allow 64-bit operands in 32-bit mode. */
4634 if (i.suffix == QWORD_MNEM_SUFFIX
4635 && flag_code != CODE_64BIT
4637 ? (!t->opcode_modifier.ignoresize
4638 && !intel_float_operand (t->name))
4639 : intel_float_operand (t->name) != 2)
4640 && ((!operand_types[0].bitfield.regmmx
4641 && !operand_types[0].bitfield.regxmm
4642 && !operand_types[0].bitfield.regymm
4643 && !operand_types[0].bitfield.regzmm)
4644 || (!operand_types[t->operands > 1].bitfield.regmmx
4645 && operand_types[t->operands > 1].bitfield.regxmm
4646 && operand_types[t->operands > 1].bitfield.regymm
4647 && operand_types[t->operands > 1].bitfield.regzmm))
4648 && (t->base_opcode != 0x0fc7
4649 || t->extension_opcode != 1 /* cmpxchg8b */))
4652 /* In general, don't allow 32-bit operands on pre-386. */
4653 else if (i.suffix == LONG_MNEM_SUFFIX
4654 && !cpu_arch_flags.bitfield.cpui386
4656 ? (!t->opcode_modifier.ignoresize
4657 && !intel_float_operand (t->name))
4658 : intel_float_operand (t->name) != 2)
4659 && ((!operand_types[0].bitfield.regmmx
4660 && !operand_types[0].bitfield.regxmm)
4661 || (!operand_types[t->operands > 1].bitfield.regmmx
4662 && operand_types[t->operands > 1].bitfield.regxmm)))
4665 /* Do not verify operands when there are none. */
4669 /* We've found a match; break out of loop. */
4673 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4674 into Disp32/Disp16/Disp32 operand. */
4675 if (i.prefix[ADDR_PREFIX] != 0)
4677 /* There should be only one Disp operand. */
4681 for (j = 0; j < MAX_OPERANDS; j++)
4683 if (operand_types[j].bitfield.disp16)
4685 addr_prefix_disp = j;
4686 operand_types[j].bitfield.disp32 = 1;
4687 operand_types[j].bitfield.disp16 = 0;
4693 for (j = 0; j < MAX_OPERANDS; j++)
4695 if (operand_types[j].bitfield.disp32)
4697 addr_prefix_disp = j;
4698 operand_types[j].bitfield.disp32 = 0;
4699 operand_types[j].bitfield.disp16 = 1;
4705 for (j = 0; j < MAX_OPERANDS; j++)
4707 if (operand_types[j].bitfield.disp64)
4709 addr_prefix_disp = j;
4710 operand_types[j].bitfield.disp64 = 0;
4711 operand_types[j].bitfield.disp32 = 1;
4719 /* We check register size if needed. */
4720 check_register = t->opcode_modifier.checkregsize;
4721 overlap0 = operand_type_and (i.types[0], operand_types[0]);
4722 switch (t->operands)
4725 if (!operand_type_match (overlap0, i.types[0]))
4729 /* xchg %eax, %eax is a special case. It is an aliase for nop
4730 only in 32bit mode and we can use opcode 0x90. In 64bit
4731 mode, we can't use 0x90 for xchg %eax, %eax since it should
4732 zero-extend %eax to %rax. */
4733 if (flag_code == CODE_64BIT
4734 && t->base_opcode == 0x90
4735 && operand_type_equal (&i.types [0], &acc32)
4736 && operand_type_equal (&i.types [1], &acc32))
4740 /* If we swap operand in encoding, we either match
4741 the next one or reverse direction of operands. */
4742 if (t->opcode_modifier.s)
4744 else if (t->opcode_modifier.d)
4749 /* If we swap operand in encoding, we match the next one. */
4750 if (i.swap_operand && t->opcode_modifier.s)
4754 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4755 if (!operand_type_match (overlap0, i.types[0])
4756 || !operand_type_match (overlap1, i.types[1])
4758 && !operand_type_register_match (overlap0, i.types[0],
4760 overlap1, i.types[1],
4763 /* Check if other direction is valid ... */
4764 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4768 /* Try reversing direction of operands. */
4769 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4770 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4771 if (!operand_type_match (overlap0, i.types[0])
4772 || !operand_type_match (overlap1, i.types[1])
4774 && !operand_type_register_match (overlap0,
4781 /* Does not match either direction. */
4784 /* found_reverse_match holds which of D or FloatDR
4786 if (t->opcode_modifier.d)
4787 found_reverse_match = Opcode_D;
4788 else if (t->opcode_modifier.floatd)
4789 found_reverse_match = Opcode_FloatD;
4791 found_reverse_match = 0;
4792 if (t->opcode_modifier.floatr)
4793 found_reverse_match |= Opcode_FloatR;
4797 /* Found a forward 2 operand match here. */
4798 switch (t->operands)
4801 overlap4 = operand_type_and (i.types[4],
4804 overlap3 = operand_type_and (i.types[3],
4807 overlap2 = operand_type_and (i.types[2],
4812 switch (t->operands)
4815 if (!operand_type_match (overlap4, i.types[4])
4816 || !operand_type_register_match (overlap3,
4824 if (!operand_type_match (overlap3, i.types[3])
4826 && !operand_type_register_match (overlap2,
4834 /* Here we make use of the fact that there are no
4835 reverse match 3 operand instructions, and all 3
4836 operand instructions only need to be checked for
4837 register consistency between operands 2 and 3. */
4838 if (!operand_type_match (overlap2, i.types[2])
4840 && !operand_type_register_match (overlap1,
4850 /* Found either forward/reverse 2, 3 or 4 operand match here:
4851 slip through to break. */
4853 if (!found_cpu_match)
4855 found_reverse_match = 0;
4859 /* Check if vector and VEX operands are valid. */
4860 if (check_VecOperands (t) || VEX_check_operands (t))
4862 specific_error = i.error;
4866 /* We've found a match; break out of loop. */
4870 if (t == current_templates->end)
4872 /* We found no match. */
4873 const char *err_msg;
4874 switch (specific_error ? specific_error : i.error)
4878 case operand_size_mismatch:
4879 err_msg = _("operand size mismatch");
4881 case operand_type_mismatch:
4882 err_msg = _("operand type mismatch");
4884 case register_type_mismatch:
4885 err_msg = _("register type mismatch");
4887 case number_of_operands_mismatch:
4888 err_msg = _("number of operands mismatch");
4890 case invalid_instruction_suffix:
4891 err_msg = _("invalid instruction suffix");
4894 err_msg = _("constant doesn't fit in 4 bits");
4897 err_msg = _("only supported with old gcc");
4899 case unsupported_with_intel_mnemonic:
4900 err_msg = _("unsupported with Intel mnemonic");
4902 case unsupported_syntax:
4903 err_msg = _("unsupported syntax");
4906 as_bad (_("unsupported instruction `%s'"),
4907 current_templates->start->name);
4909 case invalid_vsib_address:
4910 err_msg = _("invalid VSIB address");
4912 case invalid_vector_register_set:
4913 err_msg = _("mask, index, and destination registers must be distinct");
4915 case unsupported_vector_index_register:
4916 err_msg = _("unsupported vector index register");
4918 case unsupported_broadcast:
4919 err_msg = _("unsupported broadcast");
4921 case broadcast_not_on_src_operand:
4922 err_msg = _("broadcast not on source memory operand");
4924 case broadcast_needed:
4925 err_msg = _("broadcast is needed for operand of such type");
4927 case unsupported_masking:
4928 err_msg = _("unsupported masking");
4930 case mask_not_on_destination:
4931 err_msg = _("mask not on destination operand");
4933 case no_default_mask:
4934 err_msg = _("default mask isn't allowed");
4936 case unsupported_rc_sae:
4937 err_msg = _("unsupported static rounding/sae");
4939 case rc_sae_operand_not_last_imm:
4941 err_msg = _("RC/SAE operand must precede immediate operands");
4943 err_msg = _("RC/SAE operand must follow immediate operands");
4945 case invalid_register_operand:
4946 err_msg = _("invalid register operand");
4949 as_bad (_("%s for `%s'"), err_msg,
4950 current_templates->start->name);
4954 if (!quiet_warnings)
4957 && (i.types[0].bitfield.jumpabsolute
4958 != operand_types[0].bitfield.jumpabsolute))
4960 as_warn (_("indirect %s without `*'"), t->name);
4963 if (t->opcode_modifier.isprefix
4964 && t->opcode_modifier.ignoresize)
4966 /* Warn them that a data or address size prefix doesn't
4967 affect assembly of the next line of code. */
4968 as_warn (_("stand-alone `%s' prefix"), t->name);
4972 /* Copy the template we found. */
4975 if (addr_prefix_disp != -1)
4976 i.tm.operand_types[addr_prefix_disp]
4977 = operand_types[addr_prefix_disp];
4979 if (found_reverse_match)
4981 /* If we found a reverse match we must alter the opcode
4982 direction bit. found_reverse_match holds bits to change
4983 (different for int & float insns). */
4985 i.tm.base_opcode ^= found_reverse_match;
4987 i.tm.operand_types[0] = operand_types[1];
4988 i.tm.operand_types[1] = operand_types[0];
4997 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4998 if (i.tm.operand_types[mem_op].bitfield.esseg)
5000 if (i.seg[0] != NULL && i.seg[0] != &es)
5002 as_bad (_("`%s' operand %d must use `%ses' segment"),
5008 /* There's only ever one segment override allowed per instruction.
5009 This instruction possibly has a legal segment override on the
5010 second operand, so copy the segment to where non-string
5011 instructions store it, allowing common code. */
5012 i.seg[0] = i.seg[1];
5014 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5016 if (i.seg[1] != NULL && i.seg[1] != &es)
5018 as_bad (_("`%s' operand %d must use `%ses' segment"),
5029 process_suffix (void)
5031 /* If matched instruction specifies an explicit instruction mnemonic
5033 if (i.tm.opcode_modifier.size16)
5034 i.suffix = WORD_MNEM_SUFFIX;
5035 else if (i.tm.opcode_modifier.size32)
5036 i.suffix = LONG_MNEM_SUFFIX;
5037 else if (i.tm.opcode_modifier.size64)
5038 i.suffix = QWORD_MNEM_SUFFIX;
5039 else if (i.reg_operands)
5041 /* If there's no instruction mnemonic suffix we try to invent one
5042 based on register operands. */
5045 /* We take i.suffix from the last register operand specified,
5046 Destination register type is more significant than source
5047 register type. crc32 in SSE4.2 prefers source register
5049 if (i.tm.base_opcode == 0xf20f38f1)
5051 if (i.types[0].bitfield.reg16)
5052 i.suffix = WORD_MNEM_SUFFIX;
5053 else if (i.types[0].bitfield.reg32)
5054 i.suffix = LONG_MNEM_SUFFIX;
5055 else if (i.types[0].bitfield.reg64)
5056 i.suffix = QWORD_MNEM_SUFFIX;
5058 else if (i.tm.base_opcode == 0xf20f38f0)
5060 if (i.types[0].bitfield.reg8)
5061 i.suffix = BYTE_MNEM_SUFFIX;
5068 if (i.tm.base_opcode == 0xf20f38f1
5069 || i.tm.base_opcode == 0xf20f38f0)
5071 /* We have to know the operand size for crc32. */
5072 as_bad (_("ambiguous memory operand size for `%s`"),
5077 for (op = i.operands; --op >= 0;)
5078 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5080 if (i.types[op].bitfield.reg8)
5082 i.suffix = BYTE_MNEM_SUFFIX;
5085 else if (i.types[op].bitfield.reg16)
5087 i.suffix = WORD_MNEM_SUFFIX;
5090 else if (i.types[op].bitfield.reg32)
5092 i.suffix = LONG_MNEM_SUFFIX;
5095 else if (i.types[op].bitfield.reg64)
5097 i.suffix = QWORD_MNEM_SUFFIX;
5103 else if (i.suffix == BYTE_MNEM_SUFFIX)
5106 && i.tm.opcode_modifier.ignoresize
5107 && i.tm.opcode_modifier.no_bsuf)
5109 else if (!check_byte_reg ())
5112 else if (i.suffix == LONG_MNEM_SUFFIX)
5115 && i.tm.opcode_modifier.ignoresize
5116 && i.tm.opcode_modifier.no_lsuf)
5118 else if (!check_long_reg ())
5121 else if (i.suffix == QWORD_MNEM_SUFFIX)
5124 && i.tm.opcode_modifier.ignoresize
5125 && i.tm.opcode_modifier.no_qsuf)
5127 else if (!check_qword_reg ())
5130 else if (i.suffix == WORD_MNEM_SUFFIX)
5133 && i.tm.opcode_modifier.ignoresize
5134 && i.tm.opcode_modifier.no_wsuf)
5136 else if (!check_word_reg ())
5139 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5140 || i.suffix == YMMWORD_MNEM_SUFFIX
5141 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5143 /* Skip if the instruction has x/y/z suffix. match_template
5144 should check if it is a valid suffix. */
5146 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5147 /* Do nothing if the instruction is going to ignore the prefix. */
5152 else if (i.tm.opcode_modifier.defaultsize
5154 /* exclude fldenv/frstor/fsave/fstenv */
5155 && i.tm.opcode_modifier.no_ssuf)
5157 i.suffix = stackop_size;
5159 else if (intel_syntax
5161 && (i.tm.operand_types[0].bitfield.jumpabsolute
5162 || i.tm.opcode_modifier.jumpbyte
5163 || i.tm.opcode_modifier.jumpintersegment
5164 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5165 && i.tm.extension_opcode <= 3)))
5170 if (!i.tm.opcode_modifier.no_qsuf)
5172 i.suffix = QWORD_MNEM_SUFFIX;
5176 if (!i.tm.opcode_modifier.no_lsuf)
5177 i.suffix = LONG_MNEM_SUFFIX;
5180 if (!i.tm.opcode_modifier.no_wsuf)
5181 i.suffix = WORD_MNEM_SUFFIX;
5190 if (i.tm.opcode_modifier.w)
5192 as_bad (_("no instruction mnemonic suffix given and "
5193 "no register operands; can't size instruction"));
5199 unsigned int suffixes;
5201 suffixes = !i.tm.opcode_modifier.no_bsuf;
5202 if (!i.tm.opcode_modifier.no_wsuf)
5204 if (!i.tm.opcode_modifier.no_lsuf)
5206 if (!i.tm.opcode_modifier.no_ldsuf)
5208 if (!i.tm.opcode_modifier.no_ssuf)
5210 if (!i.tm.opcode_modifier.no_qsuf)
5213 /* There are more than suffix matches. */
5214 if (i.tm.opcode_modifier.w
5215 || ((suffixes & (suffixes - 1))
5216 && !i.tm.opcode_modifier.defaultsize
5217 && !i.tm.opcode_modifier.ignoresize))
5219 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5225 /* Change the opcode based on the operand size given by i.suffix;
5226 We don't need to change things for byte insns. */
5229 && i.suffix != BYTE_MNEM_SUFFIX
5230 && i.suffix != XMMWORD_MNEM_SUFFIX
5231 && i.suffix != YMMWORD_MNEM_SUFFIX
5232 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5234 /* It's not a byte, select word/dword operation. */
5235 if (i.tm.opcode_modifier.w)
5237 if (i.tm.opcode_modifier.shortform)
5238 i.tm.base_opcode |= 8;
5240 i.tm.base_opcode |= 1;
5243 /* Now select between word & dword operations via the operand
5244 size prefix, except for instructions that will ignore this
5246 if (i.tm.opcode_modifier.addrprefixop0)
5248 /* The address size override prefix changes the size of the
5250 if ((flag_code == CODE_32BIT
5251 && i.op->regs[0].reg_type.bitfield.reg16)
5252 || (flag_code != CODE_32BIT
5253 && i.op->regs[0].reg_type.bitfield.reg32))
5254 if (!add_prefix (ADDR_PREFIX_OPCODE))
5257 else if (i.suffix != QWORD_MNEM_SUFFIX
5258 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5259 && !i.tm.opcode_modifier.ignoresize
5260 && !i.tm.opcode_modifier.floatmf
5261 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5262 || (flag_code == CODE_64BIT
5263 && i.tm.opcode_modifier.jumpbyte)))
5265 unsigned int prefix = DATA_PREFIX_OPCODE;
5267 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5268 prefix = ADDR_PREFIX_OPCODE;
5270 if (!add_prefix (prefix))
5274 /* Set mode64 for an operand. */
5275 if (i.suffix == QWORD_MNEM_SUFFIX
5276 && flag_code == CODE_64BIT
5277 && !i.tm.opcode_modifier.norex64)
5279 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5280 need rex64. cmpxchg8b is also a special case. */
5281 if (! (i.operands == 2
5282 && i.tm.base_opcode == 0x90
5283 && i.tm.extension_opcode == None
5284 && operand_type_equal (&i.types [0], &acc64)
5285 && operand_type_equal (&i.types [1], &acc64))
5286 && ! (i.operands == 1
5287 && i.tm.base_opcode == 0xfc7
5288 && i.tm.extension_opcode == 1
5289 && !operand_type_check (i.types [0], reg)
5290 && operand_type_check (i.types [0], anymem)))
5294 /* Size floating point instruction. */
5295 if (i.suffix == LONG_MNEM_SUFFIX)
5296 if (i.tm.opcode_modifier.floatmf)
5297 i.tm.base_opcode ^= 4;
5304 check_byte_reg (void)
5308 for (op = i.operands; --op >= 0;)
5310 /* If this is an eight bit register, it's OK. If it's the 16 or
5311 32 bit version of an eight bit register, we will just use the
5312 low portion, and that's OK too. */
5313 if (i.types[op].bitfield.reg8)
5316 /* I/O port address operands are OK too. */
5317 if (i.tm.operand_types[op].bitfield.inoutportreg)
5320 /* crc32 doesn't generate this warning. */
5321 if (i.tm.base_opcode == 0xf20f38f0)
5324 if ((i.types[op].bitfield.reg16
5325 || i.types[op].bitfield.reg32
5326 || i.types[op].bitfield.reg64)
5327 && i.op[op].regs->reg_num < 4
5328 /* Prohibit these changes in 64bit mode, since the lowering
5329 would be more complicated. */
5330 && flag_code != CODE_64BIT)
5332 #if REGISTER_WARNINGS
5333 if (!quiet_warnings)
5334 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5336 (i.op[op].regs + (i.types[op].bitfield.reg16
5337 ? REGNAM_AL - REGNAM_AX
5338 : REGNAM_AL - REGNAM_EAX))->reg_name,
5340 i.op[op].regs->reg_name,
5345 /* Any other register is bad. */
5346 if (i.types[op].bitfield.reg16
5347 || i.types[op].bitfield.reg32
5348 || i.types[op].bitfield.reg64
5349 || i.types[op].bitfield.regmmx
5350 || i.types[op].bitfield.regxmm
5351 || i.types[op].bitfield.regymm
5352 || i.types[op].bitfield.regzmm
5353 || i.types[op].bitfield.sreg2
5354 || i.types[op].bitfield.sreg3
5355 || i.types[op].bitfield.control
5356 || i.types[op].bitfield.debug
5357 || i.types[op].bitfield.test
5358 || i.types[op].bitfield.floatreg
5359 || i.types[op].bitfield.floatacc)
5361 as_bad (_("`%s%s' not allowed with `%s%c'"),
5363 i.op[op].regs->reg_name,
5373 check_long_reg (void)
5377 for (op = i.operands; --op >= 0;)
5378 /* Reject eight bit registers, except where the template requires
5379 them. (eg. movzb) */
5380 if (i.types[op].bitfield.reg8
5381 && (i.tm.operand_types[op].bitfield.reg16
5382 || i.tm.operand_types[op].bitfield.reg32
5383 || i.tm.operand_types[op].bitfield.acc))
5385 as_bad (_("`%s%s' not allowed with `%s%c'"),
5387 i.op[op].regs->reg_name,
5392 /* Warn if the e prefix on a general reg is missing. */
5393 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5394 && i.types[op].bitfield.reg16
5395 && (i.tm.operand_types[op].bitfield.reg32
5396 || i.tm.operand_types[op].bitfield.acc))
5398 /* Prohibit these changes in the 64bit mode, since the
5399 lowering is more complicated. */
5400 if (flag_code == CODE_64BIT)
5402 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5403 register_prefix, i.op[op].regs->reg_name,
5407 #if REGISTER_WARNINGS
5408 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5410 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5411 register_prefix, i.op[op].regs->reg_name, i.suffix);
5414 /* Warn if the r prefix on a general reg is present. */
5415 else if (i.types[op].bitfield.reg64
5416 && (i.tm.operand_types[op].bitfield.reg32
5417 || i.tm.operand_types[op].bitfield.acc))
5420 && i.tm.opcode_modifier.toqword
5421 && !i.types[0].bitfield.regxmm)
5423 /* Convert to QWORD. We want REX byte. */
5424 i.suffix = QWORD_MNEM_SUFFIX;
5428 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5429 register_prefix, i.op[op].regs->reg_name,
5438 check_qword_reg (void)
5442 for (op = i.operands; --op >= 0; )
5443 /* Reject eight bit registers, except where the template requires
5444 them. (eg. movzb) */
5445 if (i.types[op].bitfield.reg8
5446 && (i.tm.operand_types[op].bitfield.reg16
5447 || i.tm.operand_types[op].bitfield.reg32
5448 || i.tm.operand_types[op].bitfield.acc))
5450 as_bad (_("`%s%s' not allowed with `%s%c'"),
5452 i.op[op].regs->reg_name,
5457 /* Warn if the r prefix on a general reg is missing. */
5458 else if ((i.types[op].bitfield.reg16
5459 || i.types[op].bitfield.reg32)
5460 && (i.tm.operand_types[op].bitfield.reg32
5461 || i.tm.operand_types[op].bitfield.acc))
5463 /* Prohibit these changes in the 64bit mode, since the
5464 lowering is more complicated. */
5466 && i.tm.opcode_modifier.todword
5467 && !i.types[0].bitfield.regxmm)
5469 /* Convert to DWORD. We don't want REX byte. */
5470 i.suffix = LONG_MNEM_SUFFIX;
5474 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5475 register_prefix, i.op[op].regs->reg_name,
5484 check_word_reg (void)
5487 for (op = i.operands; --op >= 0;)
5488 /* Reject eight bit registers, except where the template requires
5489 them. (eg. movzb) */
5490 if (i.types[op].bitfield.reg8
5491 && (i.tm.operand_types[op].bitfield.reg16
5492 || i.tm.operand_types[op].bitfield.reg32
5493 || i.tm.operand_types[op].bitfield.acc))
5495 as_bad (_("`%s%s' not allowed with `%s%c'"),
5497 i.op[op].regs->reg_name,
5502 /* Warn if the e or r prefix on a general reg is present. */
5503 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5504 && (i.types[op].bitfield.reg32
5505 || i.types[op].bitfield.reg64)
5506 && (i.tm.operand_types[op].bitfield.reg16
5507 || i.tm.operand_types[op].bitfield.acc))
5509 /* Prohibit these changes in the 64bit mode, since the
5510 lowering is more complicated. */
5511 if (flag_code == CODE_64BIT)
5513 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5514 register_prefix, i.op[op].regs->reg_name,
5518 #if REGISTER_WARNINGS
5519 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5521 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5522 register_prefix, i.op[op].regs->reg_name, i.suffix);
5529 update_imm (unsigned int j)
5531 i386_operand_type overlap = i.types[j];
5532 if ((overlap.bitfield.imm8
5533 || overlap.bitfield.imm8s
5534 || overlap.bitfield.imm16
5535 || overlap.bitfield.imm32
5536 || overlap.bitfield.imm32s
5537 || overlap.bitfield.imm64)
5538 && !operand_type_equal (&overlap, &imm8)
5539 && !operand_type_equal (&overlap, &imm8s)
5540 && !operand_type_equal (&overlap, &imm16)
5541 && !operand_type_equal (&overlap, &imm32)
5542 && !operand_type_equal (&overlap, &imm32s)
5543 && !operand_type_equal (&overlap, &imm64))
5547 i386_operand_type temp;
5549 operand_type_set (&temp, 0);
5550 if (i.suffix == BYTE_MNEM_SUFFIX)
5552 temp.bitfield.imm8 = overlap.bitfield.imm8;
5553 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5555 else if (i.suffix == WORD_MNEM_SUFFIX)
5556 temp.bitfield.imm16 = overlap.bitfield.imm16;
5557 else if (i.suffix == QWORD_MNEM_SUFFIX)
5559 temp.bitfield.imm64 = overlap.bitfield.imm64;
5560 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5563 temp.bitfield.imm32 = overlap.bitfield.imm32;
5566 else if (operand_type_equal (&overlap, &imm16_32_32s)
5567 || operand_type_equal (&overlap, &imm16_32)
5568 || operand_type_equal (&overlap, &imm16_32s))
5570 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5575 if (!operand_type_equal (&overlap, &imm8)
5576 && !operand_type_equal (&overlap, &imm8s)
5577 && !operand_type_equal (&overlap, &imm16)
5578 && !operand_type_equal (&overlap, &imm32)
5579 && !operand_type_equal (&overlap, &imm32s)
5580 && !operand_type_equal (&overlap, &imm64))
5582 as_bad (_("no instruction mnemonic suffix given; "
5583 "can't determine immediate size"));
5587 i.types[j] = overlap;
5597 /* Update the first 2 immediate operands. */
5598 n = i.operands > 2 ? 2 : i.operands;
5601 for (j = 0; j < n; j++)
5602 if (update_imm (j) == 0)
5605 /* The 3rd operand can't be immediate operand. */
5606 gas_assert (operand_type_check (i.types[2], imm) == 0);
5613 bad_implicit_operand (int xmm)
5615 const char *ireg = xmm ? "xmm0" : "ymm0";
5618 as_bad (_("the last operand of `%s' must be `%s%s'"),
5619 i.tm.name, register_prefix, ireg);
5621 as_bad (_("the first operand of `%s' must be `%s%s'"),
5622 i.tm.name, register_prefix, ireg);
5627 process_operands (void)
5629 /* Default segment register this instruction will use for memory
5630 accesses. 0 means unknown. This is only for optimizing out
5631 unnecessary segment overrides. */
5632 const seg_entry *default_seg = 0;
5634 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5636 unsigned int dupl = i.operands;
5637 unsigned int dest = dupl - 1;
5640 /* The destination must be an xmm register. */
5641 gas_assert (i.reg_operands
5642 && MAX_OPERANDS > dupl
5643 && operand_type_equal (&i.types[dest], ®xmm));
5645 if (i.tm.opcode_modifier.firstxmm0)
5647 /* The first operand is implicit and must be xmm0. */
5648 gas_assert (operand_type_equal (&i.types[0], ®xmm));
5649 if (register_number (i.op[0].regs) != 0)
5650 return bad_implicit_operand (1);
5652 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5654 /* Keep xmm0 for instructions with VEX prefix and 3
5660 /* We remove the first xmm0 and keep the number of
5661 operands unchanged, which in fact duplicates the
5663 for (j = 1; j < i.operands; j++)
5665 i.op[j - 1] = i.op[j];
5666 i.types[j - 1] = i.types[j];
5667 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5671 else if (i.tm.opcode_modifier.implicit1stxmm0)
5673 gas_assert ((MAX_OPERANDS - 1) > dupl
5674 && (i.tm.opcode_modifier.vexsources
5677 /* Add the implicit xmm0 for instructions with VEX prefix
5679 for (j = i.operands; j > 0; j--)
5681 i.op[j] = i.op[j - 1];
5682 i.types[j] = i.types[j - 1];
5683 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5686 = (const reg_entry *) hash_find (reg_hash, "xmm0");
5687 i.types[0] = regxmm;
5688 i.tm.operand_types[0] = regxmm;
5691 i.reg_operands += 2;
5696 i.op[dupl] = i.op[dest];
5697 i.types[dupl] = i.types[dest];
5698 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5707 i.op[dupl] = i.op[dest];
5708 i.types[dupl] = i.types[dest];
5709 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5712 if (i.tm.opcode_modifier.immext)
5715 else if (i.tm.opcode_modifier.firstxmm0)
5719 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5720 gas_assert (i.reg_operands
5721 && (operand_type_equal (&i.types[0], ®xmm)
5722 || operand_type_equal (&i.types[0], ®ymm)
5723 || operand_type_equal (&i.types[0], ®zmm)));
5724 if (register_number (i.op[0].regs) != 0)
5725 return bad_implicit_operand (i.types[0].bitfield.regxmm);
5727 for (j = 1; j < i.operands; j++)
5729 i.op[j - 1] = i.op[j];
5730 i.types[j - 1] = i.types[j];
5732 /* We need to adjust fields in i.tm since they are used by
5733 build_modrm_byte. */
5734 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5741 else if (i.tm.opcode_modifier.regkludge)
5743 /* The imul $imm, %reg instruction is converted into
5744 imul $imm, %reg, %reg, and the clr %reg instruction
5745 is converted into xor %reg, %reg. */
5747 unsigned int first_reg_op;
5749 if (operand_type_check (i.types[0], reg))
5753 /* Pretend we saw the extra register operand. */
5754 gas_assert (i.reg_operands == 1
5755 && i.op[first_reg_op + 1].regs == 0);
5756 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5757 i.types[first_reg_op + 1] = i.types[first_reg_op];
5762 if (i.tm.opcode_modifier.shortform)
5764 if (i.types[0].bitfield.sreg2
5765 || i.types[0].bitfield.sreg3)
5767 if (i.tm.base_opcode == POP_SEG_SHORT
5768 && i.op[0].regs->reg_num == 1)
5770 as_bad (_("you can't `pop %scs'"), register_prefix);
5773 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5774 if ((i.op[0].regs->reg_flags & RegRex) != 0)
5779 /* The register or float register operand is in operand
5783 if (i.types[0].bitfield.floatreg
5784 || operand_type_check (i.types[0], reg))
5788 /* Register goes in low 3 bits of opcode. */
5789 i.tm.base_opcode |= i.op[op].regs->reg_num;
5790 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5792 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5794 /* Warn about some common errors, but press on regardless.
5795 The first case can be generated by gcc (<= 2.8.1). */
5796 if (i.operands == 2)
5798 /* Reversed arguments on faddp, fsubp, etc. */
5799 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5800 register_prefix, i.op[!intel_syntax].regs->reg_name,
5801 register_prefix, i.op[intel_syntax].regs->reg_name);
5805 /* Extraneous `l' suffix on fp insn. */
5806 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5807 register_prefix, i.op[0].regs->reg_name);
5812 else if (i.tm.opcode_modifier.modrm)
5814 /* The opcode is completed (modulo i.tm.extension_opcode which
5815 must be put into the modrm byte). Now, we make the modrm and
5816 index base bytes based on all the info we've collected. */
5818 default_seg = build_modrm_byte ();
5820 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5824 else if (i.tm.opcode_modifier.isstring)
5826 /* For the string instructions that allow a segment override
5827 on one of their operands, the default segment is ds. */
5831 if (i.tm.base_opcode == 0x8d /* lea */
5834 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5836 /* If a segment was explicitly specified, and the specified segment
5837 is not the default, use an opcode prefix to select it. If we
5838 never figured out what the default segment is, then default_seg
5839 will be zero at this point, and the specified segment prefix will
5841 if ((i.seg[0]) && (i.seg[0] != default_seg))
5843 if (!add_prefix (i.seg[0]->seg_prefix))
5849 static const seg_entry *
5850 build_modrm_byte (void)
5852 const seg_entry *default_seg = 0;
5853 unsigned int source, dest;
5856 /* The first operand of instructions with VEX prefix and 3 sources
5857 must be VEX_Imm4. */
5858 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5861 unsigned int nds, reg_slot;
5864 if (i.tm.opcode_modifier.veximmext
5865 && i.tm.opcode_modifier.immext)
5867 dest = i.operands - 2;
5868 gas_assert (dest == 3);
5871 dest = i.operands - 1;
5874 /* There are 2 kinds of instructions:
5875 1. 5 operands: 4 register operands or 3 register operands
5876 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5877 VexW0 or VexW1. The destination must be either XMM, YMM or
5879 2. 4 operands: 4 register operands or 3 register operands
5880 plus 1 memory operand, VexXDS, and VexImmExt */
5881 gas_assert ((i.reg_operands == 4
5882 || (i.reg_operands == 3 && i.mem_operands == 1))
5883 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5884 && (i.tm.opcode_modifier.veximmext
5885 || (i.imm_operands == 1
5886 && i.types[0].bitfield.vec_imm4
5887 && (i.tm.opcode_modifier.vexw == VEXW0
5888 || i.tm.opcode_modifier.vexw == VEXW1)
5889 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5890 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)
5891 || operand_type_equal (&i.tm.operand_types[dest], ®zmm)))));
5893 if (i.imm_operands == 0)
5895 /* When there is no immediate operand, generate an 8bit
5896 immediate operand to encode the first operand. */
5897 exp = &im_expressions[i.imm_operands++];
5898 i.op[i.operands].imms = exp;
5899 i.types[i.operands] = imm8;
5901 /* If VexW1 is set, the first operand is the source and
5902 the second operand is encoded in the immediate operand. */
5903 if (i.tm.opcode_modifier.vexw == VEXW1)
5914 /* FMA swaps REG and NDS. */
5915 if (i.tm.cpu_flags.bitfield.cpufma)
5923 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5925 || operand_type_equal (&i.tm.operand_types[reg_slot],
5927 || operand_type_equal (&i.tm.operand_types[reg_slot],
5929 exp->X_op = O_constant;
5930 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
5931 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5935 unsigned int imm_slot;
5937 if (i.tm.opcode_modifier.vexw == VEXW0)
5939 /* If VexW0 is set, the third operand is the source and
5940 the second operand is encoded in the immediate
5947 /* VexW1 is set, the second operand is the source and
5948 the third operand is encoded in the immediate
5954 if (i.tm.opcode_modifier.immext)
5956 /* When ImmExt is set, the immdiate byte is the last
5958 imm_slot = i.operands - 1;
5966 /* Turn on Imm8 so that output_imm will generate it. */
5967 i.types[imm_slot].bitfield.imm8 = 1;
5970 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5972 || operand_type_equal (&i.tm.operand_types[reg_slot],
5974 || operand_type_equal (&i.tm.operand_types[reg_slot],
5976 i.op[imm_slot].imms->X_add_number
5977 |= register_number (i.op[reg_slot].regs) << 4;
5978 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5981 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
5982 || operand_type_equal (&i.tm.operand_types[nds],
5984 || operand_type_equal (&i.tm.operand_types[nds],
5986 i.vex.register_specifier = i.op[nds].regs;
5991 /* i.reg_operands MUST be the number of real register operands;
5992 implicit registers do not count. If there are 3 register
5993 operands, it must be a instruction with VexNDS. For a
5994 instruction with VexNDD, the destination register is encoded
5995 in VEX prefix. If there are 4 register operands, it must be
5996 a instruction with VEX prefix and 3 sources. */
5997 if (i.mem_operands == 0
5998 && ((i.reg_operands == 2
5999 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6000 || (i.reg_operands == 3
6001 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6002 || (i.reg_operands == 4 && vex_3_sources)))
6010 /* When there are 3 operands, one of them may be immediate,
6011 which may be the first or the last operand. Otherwise,
6012 the first operand must be shift count register (cl) or it
6013 is an instruction with VexNDS. */
6014 gas_assert (i.imm_operands == 1
6015 || (i.imm_operands == 0
6016 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6017 || i.types[0].bitfield.shiftcount)));
6018 if (operand_type_check (i.types[0], imm)
6019 || i.types[0].bitfield.shiftcount)
6025 /* When there are 4 operands, the first two must be 8bit
6026 immediate operands. The source operand will be the 3rd
6029 For instructions with VexNDS, if the first operand
6030 an imm8, the source operand is the 2nd one. If the last
6031 operand is imm8, the source operand is the first one. */
6032 gas_assert ((i.imm_operands == 2
6033 && i.types[0].bitfield.imm8
6034 && i.types[1].bitfield.imm8)
6035 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6036 && i.imm_operands == 1
6037 && (i.types[0].bitfield.imm8
6038 || i.types[i.operands - 1].bitfield.imm8
6040 if (i.imm_operands == 2)
6044 if (i.types[0].bitfield.imm8)
6051 if (i.tm.opcode_modifier.evex)
6053 /* For EVEX instructions, when there are 5 operands, the
6054 first one must be immediate operand. If the second one
6055 is immediate operand, the source operand is the 3th
6056 one. If the last one is immediate operand, the source
6057 operand is the 2nd one. */
6058 gas_assert (i.imm_operands == 2
6059 && i.tm.opcode_modifier.sae
6060 && operand_type_check (i.types[0], imm));
6061 if (operand_type_check (i.types[1], imm))
6063 else if (operand_type_check (i.types[4], imm))
6077 /* RC/SAE operand could be between DEST and SRC. That happens
6078 when one operand is GPR and the other one is XMM/YMM/ZMM
6080 if (i.rounding && i.rounding->operand == (int) dest)
6083 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6085 /* For instructions with VexNDS, the register-only source
6086 operand must be 32/64bit integer, XMM, YMM or ZMM
6087 register. It is encoded in VEX prefix. We need to
6088 clear RegMem bit before calling operand_type_equal. */
6090 i386_operand_type op;
6093 /* Check register-only source operand when two source
6094 operands are swapped. */
6095 if (!i.tm.operand_types[source].bitfield.baseindex
6096 && i.tm.operand_types[dest].bitfield.baseindex)
6104 op = i.tm.operand_types[vvvv];
6105 op.bitfield.regmem = 0;
6106 if ((dest + 1) >= i.operands
6107 || (!op.bitfield.reg32
6108 && op.bitfield.reg64
6109 && !operand_type_equal (&op, ®xmm)
6110 && !operand_type_equal (&op, ®ymm)
6111 && !operand_type_equal (&op, ®zmm)
6112 && !operand_type_equal (&op, ®mask)))
6114 i.vex.register_specifier = i.op[vvvv].regs;
6120 /* One of the register operands will be encoded in the i.tm.reg
6121 field, the other in the combined i.tm.mode and i.tm.regmem
6122 fields. If no form of this instruction supports a memory
6123 destination operand, then we assume the source operand may
6124 sometimes be a memory operand and so we need to store the
6125 destination in the i.rm.reg field. */
6126 if (!i.tm.operand_types[dest].bitfield.regmem
6127 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6129 i.rm.reg = i.op[dest].regs->reg_num;
6130 i.rm.regmem = i.op[source].regs->reg_num;
6131 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6133 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6135 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6137 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6142 i.rm.reg = i.op[source].regs->reg_num;
6143 i.rm.regmem = i.op[dest].regs->reg_num;
6144 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6146 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6148 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6150 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6153 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6155 if (!i.types[0].bitfield.control
6156 && !i.types[1].bitfield.control)
6158 i.rex &= ~(REX_R | REX_B);
6159 add_prefix (LOCK_PREFIX_OPCODE);
6163 { /* If it's not 2 reg operands... */
6168 unsigned int fake_zero_displacement = 0;
6171 for (op = 0; op < i.operands; op++)
6172 if (operand_type_check (i.types[op], anymem))
6174 gas_assert (op < i.operands);
6176 if (i.tm.opcode_modifier.vecsib)
6178 if (i.index_reg->reg_num == RegEiz
6179 || i.index_reg->reg_num == RegRiz)
6182 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6185 i.sib.base = NO_BASE_REGISTER;
6186 i.sib.scale = i.log2_scale_factor;
6187 /* No Vec_Disp8 if there is no base. */
6188 i.types[op].bitfield.vec_disp8 = 0;
6189 i.types[op].bitfield.disp8 = 0;
6190 i.types[op].bitfield.disp16 = 0;
6191 i.types[op].bitfield.disp64 = 0;
6192 if (flag_code != CODE_64BIT)
6194 /* Must be 32 bit */
6195 i.types[op].bitfield.disp32 = 1;
6196 i.types[op].bitfield.disp32s = 0;
6200 i.types[op].bitfield.disp32 = 0;
6201 i.types[op].bitfield.disp32s = 1;
6204 i.sib.index = i.index_reg->reg_num;
6205 if ((i.index_reg->reg_flags & RegRex) != 0)
6207 if ((i.index_reg->reg_flags & RegVRex) != 0)
6213 if (i.base_reg == 0)
6216 if (!i.disp_operands)
6218 fake_zero_displacement = 1;
6219 /* Instructions with VSIB byte need 32bit displacement
6220 if there is no base register. */
6221 if (i.tm.opcode_modifier.vecsib)
6222 i.types[op].bitfield.disp32 = 1;
6224 if (i.index_reg == 0)
6226 gas_assert (!i.tm.opcode_modifier.vecsib);
6227 /* Operand is just <disp> */
6228 if (flag_code == CODE_64BIT)
6230 /* 64bit mode overwrites the 32bit absolute
6231 addressing by RIP relative addressing and
6232 absolute addressing is encoded by one of the
6233 redundant SIB forms. */
6234 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6235 i.sib.base = NO_BASE_REGISTER;
6236 i.sib.index = NO_INDEX_REGISTER;
6237 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6238 ? disp32s : disp32);
6240 else if ((flag_code == CODE_16BIT)
6241 ^ (i.prefix[ADDR_PREFIX] != 0))
6243 i.rm.regmem = NO_BASE_REGISTER_16;
6244 i.types[op] = disp16;
6248 i.rm.regmem = NO_BASE_REGISTER;
6249 i.types[op] = disp32;
6252 else if (!i.tm.opcode_modifier.vecsib)
6254 /* !i.base_reg && i.index_reg */
6255 if (i.index_reg->reg_num == RegEiz
6256 || i.index_reg->reg_num == RegRiz)
6257 i.sib.index = NO_INDEX_REGISTER;
6259 i.sib.index = i.index_reg->reg_num;
6260 i.sib.base = NO_BASE_REGISTER;
6261 i.sib.scale = i.log2_scale_factor;
6262 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6263 /* No Vec_Disp8 if there is no base. */
6264 i.types[op].bitfield.vec_disp8 = 0;
6265 i.types[op].bitfield.disp8 = 0;
6266 i.types[op].bitfield.disp16 = 0;
6267 i.types[op].bitfield.disp64 = 0;
6268 if (flag_code != CODE_64BIT)
6270 /* Must be 32 bit */
6271 i.types[op].bitfield.disp32 = 1;
6272 i.types[op].bitfield.disp32s = 0;
6276 i.types[op].bitfield.disp32 = 0;
6277 i.types[op].bitfield.disp32s = 1;
6279 if ((i.index_reg->reg_flags & RegRex) != 0)
6283 /* RIP addressing for 64bit mode. */
6284 else if (i.base_reg->reg_num == RegRip ||
6285 i.base_reg->reg_num == RegEip)
6287 gas_assert (!i.tm.opcode_modifier.vecsib);
6288 i.rm.regmem = NO_BASE_REGISTER;
6289 i.types[op].bitfield.disp8 = 0;
6290 i.types[op].bitfield.disp16 = 0;
6291 i.types[op].bitfield.disp32 = 0;
6292 i.types[op].bitfield.disp32s = 1;
6293 i.types[op].bitfield.disp64 = 0;
6294 i.types[op].bitfield.vec_disp8 = 0;
6295 i.flags[op] |= Operand_PCrel;
6296 if (! i.disp_operands)
6297 fake_zero_displacement = 1;
6299 else if (i.base_reg->reg_type.bitfield.reg16)
6301 gas_assert (!i.tm.opcode_modifier.vecsib);
6302 switch (i.base_reg->reg_num)
6305 if (i.index_reg == 0)
6307 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6308 i.rm.regmem = i.index_reg->reg_num - 6;
6312 if (i.index_reg == 0)
6315 if (operand_type_check (i.types[op], disp) == 0)
6317 /* fake (%bp) into 0(%bp) */
6318 if (i.tm.operand_types[op].bitfield.vec_disp8)
6319 i.types[op].bitfield.vec_disp8 = 1;
6321 i.types[op].bitfield.disp8 = 1;
6322 fake_zero_displacement = 1;
6325 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6326 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6328 default: /* (%si) -> 4 or (%di) -> 5 */
6329 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6331 i.rm.mode = mode_from_disp_size (i.types[op]);
6333 else /* i.base_reg and 32/64 bit mode */
6335 if (flag_code == CODE_64BIT
6336 && operand_type_check (i.types[op], disp))
6338 i386_operand_type temp;
6339 operand_type_set (&temp, 0);
6340 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6341 temp.bitfield.vec_disp8
6342 = i.types[op].bitfield.vec_disp8;
6344 if (i.prefix[ADDR_PREFIX] == 0)
6345 i.types[op].bitfield.disp32s = 1;
6347 i.types[op].bitfield.disp32 = 1;
6350 if (!i.tm.opcode_modifier.vecsib)
6351 i.rm.regmem = i.base_reg->reg_num;
6352 if ((i.base_reg->reg_flags & RegRex) != 0)
6354 i.sib.base = i.base_reg->reg_num;
6355 /* x86-64 ignores REX prefix bit here to avoid decoder
6357 if (!(i.base_reg->reg_flags & RegRex)
6358 && (i.base_reg->reg_num == EBP_REG_NUM
6359 || i.base_reg->reg_num == ESP_REG_NUM))
6361 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6363 fake_zero_displacement = 1;
6364 if (i.tm.operand_types [op].bitfield.vec_disp8)
6365 i.types[op].bitfield.vec_disp8 = 1;
6367 i.types[op].bitfield.disp8 = 1;
6369 i.sib.scale = i.log2_scale_factor;
6370 if (i.index_reg == 0)
6372 gas_assert (!i.tm.opcode_modifier.vecsib);
6373 /* <disp>(%esp) becomes two byte modrm with no index
6374 register. We've already stored the code for esp
6375 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6376 Any base register besides %esp will not use the
6377 extra modrm byte. */
6378 i.sib.index = NO_INDEX_REGISTER;
6380 else if (!i.tm.opcode_modifier.vecsib)
6382 if (i.index_reg->reg_num == RegEiz
6383 || i.index_reg->reg_num == RegRiz)
6384 i.sib.index = NO_INDEX_REGISTER;
6386 i.sib.index = i.index_reg->reg_num;
6387 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6388 if ((i.index_reg->reg_flags & RegRex) != 0)
6393 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6394 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6398 if (!fake_zero_displacement
6402 fake_zero_displacement = 1;
6403 if (i.disp_encoding == disp_encoding_8bit)
6404 i.types[op].bitfield.disp8 = 1;
6406 i.types[op].bitfield.disp32 = 1;
6408 i.rm.mode = mode_from_disp_size (i.types[op]);
6412 if (fake_zero_displacement)
6414 /* Fakes a zero displacement assuming that i.types[op]
6415 holds the correct displacement size. */
6418 gas_assert (i.op[op].disps == 0);
6419 exp = &disp_expressions[i.disp_operands++];
6420 i.op[op].disps = exp;
6421 exp->X_op = O_constant;
6422 exp->X_add_number = 0;
6423 exp->X_add_symbol = (symbolS *) 0;
6424 exp->X_op_symbol = (symbolS *) 0;
6432 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6434 if (operand_type_check (i.types[0], imm))
6435 i.vex.register_specifier = NULL;
6438 /* VEX.vvvv encodes one of the sources when the first
6439 operand is not an immediate. */
6440 if (i.tm.opcode_modifier.vexw == VEXW0)
6441 i.vex.register_specifier = i.op[0].regs;
6443 i.vex.register_specifier = i.op[1].regs;
6446 /* Destination is a XMM register encoded in the ModRM.reg
6448 i.rm.reg = i.op[2].regs->reg_num;
6449 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6452 /* ModRM.rm and VEX.B encodes the other source. */
6453 if (!i.mem_operands)
6457 if (i.tm.opcode_modifier.vexw == VEXW0)
6458 i.rm.regmem = i.op[1].regs->reg_num;
6460 i.rm.regmem = i.op[0].regs->reg_num;
6462 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6466 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6468 i.vex.register_specifier = i.op[2].regs;
6469 if (!i.mem_operands)
6472 i.rm.regmem = i.op[1].regs->reg_num;
6473 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6477 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6478 (if any) based on i.tm.extension_opcode. Again, we must be
6479 careful to make sure that segment/control/debug/test/MMX
6480 registers are coded into the i.rm.reg field. */
6481 else if (i.reg_operands)
6484 unsigned int vex_reg = ~0;
6486 for (op = 0; op < i.operands; op++)
6487 if (i.types[op].bitfield.reg8
6488 || i.types[op].bitfield.reg16
6489 || i.types[op].bitfield.reg32
6490 || i.types[op].bitfield.reg64
6491 || i.types[op].bitfield.regmmx
6492 || i.types[op].bitfield.regxmm
6493 || i.types[op].bitfield.regymm
6494 || i.types[op].bitfield.regbnd
6495 || i.types[op].bitfield.regzmm
6496 || i.types[op].bitfield.regmask
6497 || i.types[op].bitfield.sreg2
6498 || i.types[op].bitfield.sreg3
6499 || i.types[op].bitfield.control
6500 || i.types[op].bitfield.debug
6501 || i.types[op].bitfield.test)
6506 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6508 /* For instructions with VexNDS, the register-only
6509 source operand is encoded in VEX prefix. */
6510 gas_assert (mem != (unsigned int) ~0);
6515 gas_assert (op < i.operands);
6519 /* Check register-only source operand when two source
6520 operands are swapped. */
6521 if (!i.tm.operand_types[op].bitfield.baseindex
6522 && i.tm.operand_types[op + 1].bitfield.baseindex)
6526 gas_assert (mem == (vex_reg + 1)
6527 && op < i.operands);
6532 gas_assert (vex_reg < i.operands);
6536 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6538 /* For instructions with VexNDD, the register destination
6539 is encoded in VEX prefix. */
6540 if (i.mem_operands == 0)
6542 /* There is no memory operand. */
6543 gas_assert ((op + 2) == i.operands);
6548 /* There are only 2 operands. */
6549 gas_assert (op < 2 && i.operands == 2);
6554 gas_assert (op < i.operands);
6556 if (vex_reg != (unsigned int) ~0)
6558 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6560 if (type->bitfield.reg32 != 1
6561 && type->bitfield.reg64 != 1
6562 && !operand_type_equal (type, ®xmm)
6563 && !operand_type_equal (type, ®ymm)
6564 && !operand_type_equal (type, ®zmm)
6565 && !operand_type_equal (type, ®mask))
6568 i.vex.register_specifier = i.op[vex_reg].regs;
6571 /* Don't set OP operand twice. */
6574 /* If there is an extension opcode to put here, the
6575 register number must be put into the regmem field. */
6576 if (i.tm.extension_opcode != None)
6578 i.rm.regmem = i.op[op].regs->reg_num;
6579 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6581 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6586 i.rm.reg = i.op[op].regs->reg_num;
6587 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6589 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6594 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6595 must set it to 3 to indicate this is a register operand
6596 in the regmem field. */
6597 if (!i.mem_operands)
6601 /* Fill in i.rm.reg field with extension opcode (if any). */
6602 if (i.tm.extension_opcode != None)
6603 i.rm.reg = i.tm.extension_opcode;
6609 output_branch (void)
6615 relax_substateT subtype;
6619 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6620 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6623 if (i.prefix[DATA_PREFIX] != 0)
6629 /* Pentium4 branch hints. */
6630 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6631 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6636 if (i.prefix[REX_PREFIX] != 0)
6642 /* BND prefixed jump. */
6643 if (i.prefix[BND_PREFIX] != 0)
6645 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6649 if (i.prefixes != 0 && !intel_syntax)
6650 as_warn (_("skipping prefixes on this instruction"));
6652 /* It's always a symbol; End frag & setup for relax.
6653 Make sure there is enough room in this frag for the largest
6654 instruction we may generate in md_convert_frag. This is 2
6655 bytes for the opcode and room for the prefix and largest
6657 frag_grow (prefix + 2 + 4);
6658 /* Prefix and 1 opcode byte go in fr_fix. */
6659 p = frag_more (prefix + 1);
6660 if (i.prefix[DATA_PREFIX] != 0)
6661 *p++ = DATA_PREFIX_OPCODE;
6662 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6663 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6664 *p++ = i.prefix[SEG_PREFIX];
6665 if (i.prefix[REX_PREFIX] != 0)
6666 *p++ = i.prefix[REX_PREFIX];
6667 *p = i.tm.base_opcode;
6669 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6670 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6671 else if (cpu_arch_flags.bitfield.cpui386)
6672 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6674 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6677 sym = i.op[0].disps->X_add_symbol;
6678 off = i.op[0].disps->X_add_number;
6680 if (i.op[0].disps->X_op != O_constant
6681 && i.op[0].disps->X_op != O_symbol)
6683 /* Handle complex expressions. */
6684 sym = make_expr_symbol (i.op[0].disps);
6688 /* 1 possible extra opcode + 4 byte displacement go in var part.
6689 Pass reloc in fr_var. */
6690 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6700 if (i.tm.opcode_modifier.jumpbyte)
6702 /* This is a loop or jecxz type instruction. */
6704 if (i.prefix[ADDR_PREFIX] != 0)
6706 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6709 /* Pentium4 branch hints. */
6710 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6711 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6713 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6722 if (flag_code == CODE_16BIT)
6725 if (i.prefix[DATA_PREFIX] != 0)
6727 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6737 if (i.prefix[REX_PREFIX] != 0)
6739 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6743 /* BND prefixed jump. */
6744 if (i.prefix[BND_PREFIX] != 0)
6746 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6750 if (i.prefixes != 0 && !intel_syntax)
6751 as_warn (_("skipping prefixes on this instruction"));
6753 p = frag_more (i.tm.opcode_length + size);
6754 switch (i.tm.opcode_length)
6757 *p++ = i.tm.base_opcode >> 8;
6759 *p++ = i.tm.base_opcode;
6765 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6766 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6768 /* All jumps handled here are signed, but don't use a signed limit
6769 check for 32 and 16 bit jumps as we want to allow wrap around at
6770 4G and 64k respectively. */
6772 fixP->fx_signed = 1;
6776 output_interseg_jump (void)
6784 if (flag_code == CODE_16BIT)
6788 if (i.prefix[DATA_PREFIX] != 0)
6794 if (i.prefix[REX_PREFIX] != 0)
6804 if (i.prefixes != 0 && !intel_syntax)
6805 as_warn (_("skipping prefixes on this instruction"));
6807 /* 1 opcode; 2 segment; offset */
6808 p = frag_more (prefix + 1 + 2 + size);
6810 if (i.prefix[DATA_PREFIX] != 0)
6811 *p++ = DATA_PREFIX_OPCODE;
6813 if (i.prefix[REX_PREFIX] != 0)
6814 *p++ = i.prefix[REX_PREFIX];
6816 *p++ = i.tm.base_opcode;
6817 if (i.op[1].imms->X_op == O_constant)
6819 offsetT n = i.op[1].imms->X_add_number;
6822 && !fits_in_unsigned_word (n)
6823 && !fits_in_signed_word (n))
6825 as_bad (_("16-bit jump out of range"));
6828 md_number_to_chars (p, n, size);
6831 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6832 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6833 if (i.op[0].imms->X_op != O_constant)
6834 as_bad (_("can't handle non absolute segment in `%s'"),
6836 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6842 fragS *insn_start_frag;
6843 offsetT insn_start_off;
6845 /* Tie dwarf2 debug info to the address at the start of the insn.
6846 We can't do this after the insn has been output as the current
6847 frag may have been closed off. eg. by frag_var. */
6848 dwarf2_emit_insn (0);
6850 insn_start_frag = frag_now;
6851 insn_start_off = frag_now_fix ();
6854 if (i.tm.opcode_modifier.jump)
6856 else if (i.tm.opcode_modifier.jumpbyte
6857 || i.tm.opcode_modifier.jumpdword)
6859 else if (i.tm.opcode_modifier.jumpintersegment)
6860 output_interseg_jump ();
6863 /* Output normal instructions here. */
6867 unsigned int prefix;
6869 /* Some processors fail on LOCK prefix. This options makes
6870 assembler ignore LOCK prefix and serves as a workaround. */
6871 if (omit_lock_prefix)
6873 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6875 i.prefix[LOCK_PREFIX] = 0;
6878 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6879 don't need the explicit prefix. */
6880 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
6882 switch (i.tm.opcode_length)
6885 if (i.tm.base_opcode & 0xff000000)
6887 prefix = (i.tm.base_opcode >> 24) & 0xff;
6892 if ((i.tm.base_opcode & 0xff0000) != 0)
6894 prefix = (i.tm.base_opcode >> 16) & 0xff;
6895 if (i.tm.cpu_flags.bitfield.cpupadlock)
6898 if (prefix != REPE_PREFIX_OPCODE
6899 || (i.prefix[REP_PREFIX]
6900 != REPE_PREFIX_OPCODE))
6901 add_prefix (prefix);
6904 add_prefix (prefix);
6913 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6914 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6915 R_X86_64_GOTTPOFF relocation so that linker can safely
6916 perform IE->LE optimization. */
6917 if (x86_elf_abi == X86_64_X32_ABI
6919 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6920 && i.prefix[REX_PREFIX] == 0)
6921 add_prefix (REX_OPCODE);
6924 /* The prefix bytes. */
6925 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6927 FRAG_APPEND_1_CHAR (*q);
6931 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6936 /* REX byte is encoded in VEX prefix. */
6940 FRAG_APPEND_1_CHAR (*q);
6943 /* There should be no other prefixes for instructions
6948 /* For EVEX instructions i.vrex should become 0 after
6949 build_evex_prefix. For VEX instructions upper 16 registers
6950 aren't available, so VREX should be 0. */
6953 /* Now the VEX prefix. */
6954 p = frag_more (i.vex.length);
6955 for (j = 0; j < i.vex.length; j++)
6956 p[j] = i.vex.bytes[j];
6959 /* Now the opcode; be careful about word order here! */
6960 if (i.tm.opcode_length == 1)
6962 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6966 switch (i.tm.opcode_length)
6970 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6971 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6975 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6985 /* Put out high byte first: can't use md_number_to_chars! */
6986 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6987 *p = i.tm.base_opcode & 0xff;
6990 /* Now the modrm byte and sib byte (if present). */
6991 if (i.tm.opcode_modifier.modrm)
6993 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6996 /* If i.rm.regmem == ESP (4)
6997 && i.rm.mode != (Register mode)
6999 ==> need second modrm byte. */
7000 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7002 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7003 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7005 | i.sib.scale << 6));
7008 if (i.disp_operands)
7009 output_disp (insn_start_frag, insn_start_off);
7012 output_imm (insn_start_frag, insn_start_off);
7018 pi ("" /*line*/, &i);
7020 #endif /* DEBUG386 */
7023 /* Return the size of the displacement operand N. */
7026 disp_size (unsigned int n)
7030 /* Vec_Disp8 has to be 8bit. */
7031 if (i.types[n].bitfield.vec_disp8)
7033 else if (i.types[n].bitfield.disp64)
7035 else if (i.types[n].bitfield.disp8)
7037 else if (i.types[n].bitfield.disp16)
7042 /* Return the size of the immediate operand N. */
7045 imm_size (unsigned int n)
7048 if (i.types[n].bitfield.imm64)
7050 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7052 else if (i.types[n].bitfield.imm16)
7058 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7063 for (n = 0; n < i.operands; n++)
7065 if (i.types[n].bitfield.vec_disp8
7066 || operand_type_check (i.types[n], disp))
7068 if (i.op[n].disps->X_op == O_constant)
7070 int size = disp_size (n);
7071 offsetT val = i.op[n].disps->X_add_number;
7073 if (i.types[n].bitfield.vec_disp8)
7075 val = offset_in_range (val, size);
7076 p = frag_more (size);
7077 md_number_to_chars (p, val, size);
7081 enum bfd_reloc_code_real reloc_type;
7082 int size = disp_size (n);
7083 int sign = i.types[n].bitfield.disp32s;
7084 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7086 /* We can't have 8 bit displacement here. */
7087 gas_assert (!i.types[n].bitfield.disp8);
7089 /* The PC relative address is computed relative
7090 to the instruction boundary, so in case immediate
7091 fields follows, we need to adjust the value. */
7092 if (pcrel && i.imm_operands)
7097 for (n1 = 0; n1 < i.operands; n1++)
7098 if (operand_type_check (i.types[n1], imm))
7100 /* Only one immediate is allowed for PC
7101 relative address. */
7102 gas_assert (sz == 0);
7104 i.op[n].disps->X_add_number -= sz;
7106 /* We should find the immediate. */
7107 gas_assert (sz != 0);
7110 p = frag_more (size);
7111 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7113 && GOT_symbol == i.op[n].disps->X_add_symbol
7114 && (((reloc_type == BFD_RELOC_32
7115 || reloc_type == BFD_RELOC_X86_64_32S
7116 || (reloc_type == BFD_RELOC_64
7118 && (i.op[n].disps->X_op == O_symbol
7119 || (i.op[n].disps->X_op == O_add
7120 && ((symbol_get_value_expression
7121 (i.op[n].disps->X_op_symbol)->X_op)
7123 || reloc_type == BFD_RELOC_32_PCREL))
7127 if (insn_start_frag == frag_now)
7128 add = (p - frag_now->fr_literal) - insn_start_off;
7133 add = insn_start_frag->fr_fix - insn_start_off;
7134 for (fr = insn_start_frag->fr_next;
7135 fr && fr != frag_now; fr = fr->fr_next)
7137 add += p - frag_now->fr_literal;
7142 reloc_type = BFD_RELOC_386_GOTPC;
7143 i.op[n].imms->X_add_number += add;
7145 else if (reloc_type == BFD_RELOC_64)
7146 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7148 /* Don't do the adjustment for x86-64, as there
7149 the pcrel addressing is relative to the _next_
7150 insn, and that is taken care of in other code. */
7151 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7153 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7154 i.op[n].disps, pcrel, reloc_type);
7161 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7166 for (n = 0; n < i.operands; n++)
7168 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7169 if (i.rounding && (int) n == i.rounding->operand)
7172 if (operand_type_check (i.types[n], imm))
7174 if (i.op[n].imms->X_op == O_constant)
7176 int size = imm_size (n);
7179 val = offset_in_range (i.op[n].imms->X_add_number,
7181 p = frag_more (size);
7182 md_number_to_chars (p, val, size);
7186 /* Not absolute_section.
7187 Need a 32-bit fixup (don't support 8bit
7188 non-absolute imms). Try to support other
7190 enum bfd_reloc_code_real reloc_type;
7191 int size = imm_size (n);
7194 if (i.types[n].bitfield.imm32s
7195 && (i.suffix == QWORD_MNEM_SUFFIX
7196 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7201 p = frag_more (size);
7202 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7204 /* This is tough to explain. We end up with this one if we
7205 * have operands that look like
7206 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7207 * obtain the absolute address of the GOT, and it is strongly
7208 * preferable from a performance point of view to avoid using
7209 * a runtime relocation for this. The actual sequence of
7210 * instructions often look something like:
7215 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7217 * The call and pop essentially return the absolute address
7218 * of the label .L66 and store it in %ebx. The linker itself
7219 * will ultimately change the first operand of the addl so
7220 * that %ebx points to the GOT, but to keep things simple, the
7221 * .o file must have this operand set so that it generates not
7222 * the absolute address of .L66, but the absolute address of
7223 * itself. This allows the linker itself simply treat a GOTPC
7224 * relocation as asking for a pcrel offset to the GOT to be
7225 * added in, and the addend of the relocation is stored in the
7226 * operand field for the instruction itself.
7228 * Our job here is to fix the operand so that it would add
7229 * the correct offset so that %ebx would point to itself. The
7230 * thing that is tricky is that .-.L66 will point to the
7231 * beginning of the instruction, so we need to further modify
7232 * the operand so that it will point to itself. There are
7233 * other cases where you have something like:
7235 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7237 * and here no correction would be required. Internally in
7238 * the assembler we treat operands of this form as not being
7239 * pcrel since the '.' is explicitly mentioned, and I wonder
7240 * whether it would simplify matters to do it this way. Who
7241 * knows. In earlier versions of the PIC patches, the
7242 * pcrel_adjust field was used to store the correction, but
7243 * since the expression is not pcrel, I felt it would be
7244 * confusing to do it this way. */
7246 if ((reloc_type == BFD_RELOC_32
7247 || reloc_type == BFD_RELOC_X86_64_32S
7248 || reloc_type == BFD_RELOC_64)
7250 && GOT_symbol == i.op[n].imms->X_add_symbol
7251 && (i.op[n].imms->X_op == O_symbol
7252 || (i.op[n].imms->X_op == O_add
7253 && ((symbol_get_value_expression
7254 (i.op[n].imms->X_op_symbol)->X_op)
7259 if (insn_start_frag == frag_now)
7260 add = (p - frag_now->fr_literal) - insn_start_off;
7265 add = insn_start_frag->fr_fix - insn_start_off;
7266 for (fr = insn_start_frag->fr_next;
7267 fr && fr != frag_now; fr = fr->fr_next)
7269 add += p - frag_now->fr_literal;
7273 reloc_type = BFD_RELOC_386_GOTPC;
7275 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7277 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7278 i.op[n].imms->X_add_number += add;
7280 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7281 i.op[n].imms, 0, reloc_type);
7287 /* x86_cons_fix_new is called via the expression parsing code when a
7288 reloc is needed. We use this hook to get the correct .got reloc. */
7289 static int cons_sign = -1;
7292 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7293 expressionS *exp, bfd_reloc_code_real_type r)
7295 r = reloc (len, 0, cons_sign, r);
7298 if (exp->X_op == O_secrel)
7300 exp->X_op = O_symbol;
7301 r = BFD_RELOC_32_SECREL;
7305 fix_new_exp (frag, off, len, exp, 0, r);
7308 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7309 purpose of the `.dc.a' internal pseudo-op. */
7312 x86_address_bytes (void)
7314 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7316 return stdoutput->arch_info->bits_per_address / 8;
7319 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7321 # define lex_got(reloc, adjust, types) NULL
7323 /* Parse operands of the form
7324 <symbol>@GOTOFF+<nnn>
7325 and similar .plt or .got references.
7327 If we find one, set up the correct relocation in RELOC and copy the
7328 input string, minus the `@GOTOFF' into a malloc'd buffer for
7329 parsing by the calling routine. Return this buffer, and if ADJUST
7330 is non-null set it to the length of the string we removed from the
7331 input line. Otherwise return NULL. */
7333 lex_got (enum bfd_reloc_code_real *rel,
7335 i386_operand_type *types)
7337 /* Some of the relocations depend on the size of what field is to
7338 be relocated. But in our callers i386_immediate and i386_displacement
7339 we don't yet know the operand size (this will be set by insn
7340 matching). Hence we record the word32 relocation here,
7341 and adjust the reloc according to the real size in reloc(). */
7342 static const struct {
7345 const enum bfd_reloc_code_real rel[2];
7346 const i386_operand_type types64;
7348 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7349 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7351 OPERAND_TYPE_IMM32_64 },
7353 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7354 BFD_RELOC_X86_64_PLTOFF64 },
7355 OPERAND_TYPE_IMM64 },
7356 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7357 BFD_RELOC_X86_64_PLT32 },
7358 OPERAND_TYPE_IMM32_32S_DISP32 },
7359 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7360 BFD_RELOC_X86_64_GOTPLT64 },
7361 OPERAND_TYPE_IMM64_DISP64 },
7362 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7363 BFD_RELOC_X86_64_GOTOFF64 },
7364 OPERAND_TYPE_IMM64_DISP64 },
7365 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7366 BFD_RELOC_X86_64_GOTPCREL },
7367 OPERAND_TYPE_IMM32_32S_DISP32 },
7368 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7369 BFD_RELOC_X86_64_TLSGD },
7370 OPERAND_TYPE_IMM32_32S_DISP32 },
7371 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7372 _dummy_first_bfd_reloc_code_real },
7373 OPERAND_TYPE_NONE },
7374 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7375 BFD_RELOC_X86_64_TLSLD },
7376 OPERAND_TYPE_IMM32_32S_DISP32 },
7377 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7378 BFD_RELOC_X86_64_GOTTPOFF },
7379 OPERAND_TYPE_IMM32_32S_DISP32 },
7380 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7381 BFD_RELOC_X86_64_TPOFF32 },
7382 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7383 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7384 _dummy_first_bfd_reloc_code_real },
7385 OPERAND_TYPE_NONE },
7386 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7387 BFD_RELOC_X86_64_DTPOFF32 },
7388 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7389 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7390 _dummy_first_bfd_reloc_code_real },
7391 OPERAND_TYPE_NONE },
7392 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7393 _dummy_first_bfd_reloc_code_real },
7394 OPERAND_TYPE_NONE },
7395 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7396 BFD_RELOC_X86_64_GOT32 },
7397 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7398 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7399 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7400 OPERAND_TYPE_IMM32_32S_DISP32 },
7401 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7402 BFD_RELOC_X86_64_TLSDESC_CALL },
7403 OPERAND_TYPE_IMM32_32S_DISP32 },
7408 #if defined (OBJ_MAYBE_ELF)
7413 for (cp = input_line_pointer; *cp != '@'; cp++)
7414 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7417 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7419 int len = gotrel[j].len;
7420 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7422 if (gotrel[j].rel[object_64bit] != 0)
7425 char *tmpbuf, *past_reloc;
7427 *rel = gotrel[j].rel[object_64bit];
7431 if (flag_code != CODE_64BIT)
7433 types->bitfield.imm32 = 1;
7434 types->bitfield.disp32 = 1;
7437 *types = gotrel[j].types64;
7440 if (j != 0 && GOT_symbol == NULL)
7441 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7443 /* The length of the first part of our input line. */
7444 first = cp - input_line_pointer;
7446 /* The second part goes from after the reloc token until
7447 (and including) an end_of_line char or comma. */
7448 past_reloc = cp + 1 + len;
7450 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7452 second = cp + 1 - past_reloc;
7454 /* Allocate and copy string. The trailing NUL shouldn't
7455 be necessary, but be safe. */
7456 tmpbuf = (char *) xmalloc (first + second + 2);
7457 memcpy (tmpbuf, input_line_pointer, first);
7458 if (second != 0 && *past_reloc != ' ')
7459 /* Replace the relocation token with ' ', so that
7460 errors like foo@GOTOFF1 will be detected. */
7461 tmpbuf[first++] = ' ';
7463 /* Increment length by 1 if the relocation token is
7468 memcpy (tmpbuf + first, past_reloc, second);
7469 tmpbuf[first + second] = '\0';
7473 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7474 gotrel[j].str, 1 << (5 + object_64bit));
7479 /* Might be a symbol version string. Don't as_bad here. */
7488 /* Parse operands of the form
7489 <symbol>@SECREL32+<nnn>
7491 If we find one, set up the correct relocation in RELOC and copy the
7492 input string, minus the `@SECREL32' into a malloc'd buffer for
7493 parsing by the calling routine. Return this buffer, and if ADJUST
7494 is non-null set it to the length of the string we removed from the
7495 input line. Otherwise return NULL.
7497 This function is copied from the ELF version above adjusted for PE targets. */
7500 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7501 int *adjust ATTRIBUTE_UNUSED,
7502 i386_operand_type *types)
7508 const enum bfd_reloc_code_real rel[2];
7509 const i386_operand_type types64;
7513 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7514 BFD_RELOC_32_SECREL },
7515 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7521 for (cp = input_line_pointer; *cp != '@'; cp++)
7522 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7525 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7527 int len = gotrel[j].len;
7529 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7531 if (gotrel[j].rel[object_64bit] != 0)
7534 char *tmpbuf, *past_reloc;
7536 *rel = gotrel[j].rel[object_64bit];
7542 if (flag_code != CODE_64BIT)
7544 types->bitfield.imm32 = 1;
7545 types->bitfield.disp32 = 1;
7548 *types = gotrel[j].types64;
7551 /* The length of the first part of our input line. */
7552 first = cp - input_line_pointer;
7554 /* The second part goes from after the reloc token until
7555 (and including) an end_of_line char or comma. */
7556 past_reloc = cp + 1 + len;
7558 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7560 second = cp + 1 - past_reloc;
7562 /* Allocate and copy string. The trailing NUL shouldn't
7563 be necessary, but be safe. */
7564 tmpbuf = (char *) xmalloc (first + second + 2);
7565 memcpy (tmpbuf, input_line_pointer, first);
7566 if (second != 0 && *past_reloc != ' ')
7567 /* Replace the relocation token with ' ', so that
7568 errors like foo@SECLREL321 will be detected. */
7569 tmpbuf[first++] = ' ';
7570 memcpy (tmpbuf + first, past_reloc, second);
7571 tmpbuf[first + second] = '\0';
7575 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7576 gotrel[j].str, 1 << (5 + object_64bit));
7581 /* Might be a symbol version string. Don't as_bad here. */
7587 bfd_reloc_code_real_type
7588 x86_cons (expressionS *exp, int size)
7590 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7592 intel_syntax = -intel_syntax;
7595 if (size == 4 || (object_64bit && size == 8))
7597 /* Handle @GOTOFF and the like in an expression. */
7599 char *gotfree_input_line;
7602 save = input_line_pointer;
7603 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
7604 if (gotfree_input_line)
7605 input_line_pointer = gotfree_input_line;
7609 if (gotfree_input_line)
7611 /* expression () has merrily parsed up to the end of line,
7612 or a comma - in the wrong buffer. Transfer how far
7613 input_line_pointer has moved to the right buffer. */
7614 input_line_pointer = (save
7615 + (input_line_pointer - gotfree_input_line)
7617 free (gotfree_input_line);
7618 if (exp->X_op == O_constant
7619 || exp->X_op == O_absent
7620 || exp->X_op == O_illegal
7621 || exp->X_op == O_register
7622 || exp->X_op == O_big)
7624 char c = *input_line_pointer;
7625 *input_line_pointer = 0;
7626 as_bad (_("missing or invalid expression `%s'"), save);
7627 *input_line_pointer = c;
7634 intel_syntax = -intel_syntax;
7637 i386_intel_simplify (exp);
7643 signed_cons (int size)
7645 if (flag_code == CODE_64BIT)
7653 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
7660 if (exp.X_op == O_symbol)
7661 exp.X_op = O_secrel;
7663 emit_expr (&exp, 4);
7665 while (*input_line_pointer++ == ',');
7667 input_line_pointer--;
7668 demand_empty_rest_of_line ();
7672 /* Handle Vector operations. */
7675 check_VecOperations (char *op_string, char *op_end)
7677 const reg_entry *mask;
7682 && (op_end == NULL || op_string < op_end))
7685 if (*op_string == '{')
7689 /* Check broadcasts. */
7690 if (strncmp (op_string, "1to", 3) == 0)
7695 goto duplicated_vec_op;
7698 if (*op_string == '8')
7699 bcst_type = BROADCAST_1TO8;
7700 else if (*op_string == '4')
7701 bcst_type = BROADCAST_1TO4;
7702 else if (*op_string == '2')
7703 bcst_type = BROADCAST_1TO2;
7704 else if (*op_string == '1'
7705 && *(op_string+1) == '6')
7707 bcst_type = BROADCAST_1TO16;
7712 as_bad (_("Unsupported broadcast: `%s'"), saved);
7717 broadcast_op.type = bcst_type;
7718 broadcast_op.operand = this_operand;
7719 i.broadcast = &broadcast_op;
7721 /* Check masking operation. */
7722 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7724 /* k0 can't be used for write mask. */
7725 if (mask->reg_num == 0)
7727 as_bad (_("`%s' can't be used for write mask"),
7734 mask_op.mask = mask;
7735 mask_op.zeroing = 0;
7736 mask_op.operand = this_operand;
7742 goto duplicated_vec_op;
7744 i.mask->mask = mask;
7746 /* Only "{z}" is allowed here. No need to check
7747 zeroing mask explicitly. */
7748 if (i.mask->operand != this_operand)
7750 as_bad (_("invalid write mask `%s'"), saved);
7757 /* Check zeroing-flag for masking operation. */
7758 else if (*op_string == 'z')
7762 mask_op.mask = NULL;
7763 mask_op.zeroing = 1;
7764 mask_op.operand = this_operand;
7769 if (i.mask->zeroing)
7772 as_bad (_("duplicated `%s'"), saved);
7776 i.mask->zeroing = 1;
7778 /* Only "{%k}" is allowed here. No need to check mask
7779 register explicitly. */
7780 if (i.mask->operand != this_operand)
7782 as_bad (_("invalid zeroing-masking `%s'"),
7791 goto unknown_vec_op;
7793 if (*op_string != '}')
7795 as_bad (_("missing `}' in `%s'"), saved);
7802 /* We don't know this one. */
7803 as_bad (_("unknown vector operation: `%s'"), saved);
7811 i386_immediate (char *imm_start)
7813 char *save_input_line_pointer;
7814 char *gotfree_input_line;
7817 i386_operand_type types;
7819 operand_type_set (&types, ~0);
7821 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7823 as_bad (_("at most %d immediate operands are allowed"),
7824 MAX_IMMEDIATE_OPERANDS);
7828 exp = &im_expressions[i.imm_operands++];
7829 i.op[this_operand].imms = exp;
7831 if (is_space_char (*imm_start))
7834 save_input_line_pointer = input_line_pointer;
7835 input_line_pointer = imm_start;
7837 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
7838 if (gotfree_input_line)
7839 input_line_pointer = gotfree_input_line;
7841 exp_seg = expression (exp);
7845 /* Handle vector operations. */
7846 if (*input_line_pointer == '{')
7848 input_line_pointer = check_VecOperations (input_line_pointer,
7850 if (input_line_pointer == NULL)
7854 if (*input_line_pointer)
7855 as_bad (_("junk `%s' after expression"), input_line_pointer);
7857 input_line_pointer = save_input_line_pointer;
7858 if (gotfree_input_line)
7860 free (gotfree_input_line);
7862 if (exp->X_op == O_constant || exp->X_op == O_register)
7863 exp->X_op = O_illegal;
7866 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7870 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7871 i386_operand_type types, const char *imm_start)
7873 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
7876 as_bad (_("missing or invalid immediate expression `%s'"),
7880 else if (exp->X_op == O_constant)
7882 /* Size it properly later. */
7883 i.types[this_operand].bitfield.imm64 = 1;
7884 /* If not 64bit, sign extend val. */
7885 if (flag_code != CODE_64BIT
7886 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7888 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
7890 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7891 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
7892 && exp_seg != absolute_section
7893 && exp_seg != text_section
7894 && exp_seg != data_section
7895 && exp_seg != bss_section
7896 && exp_seg != undefined_section
7897 && !bfd_is_com_section (exp_seg))
7899 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
7903 else if (!intel_syntax && exp_seg == reg_section)
7906 as_bad (_("illegal immediate register operand %s"), imm_start);
7911 /* This is an address. The size of the address will be
7912 determined later, depending on destination register,
7913 suffix, or the default for the section. */
7914 i.types[this_operand].bitfield.imm8 = 1;
7915 i.types[this_operand].bitfield.imm16 = 1;
7916 i.types[this_operand].bitfield.imm32 = 1;
7917 i.types[this_operand].bitfield.imm32s = 1;
7918 i.types[this_operand].bitfield.imm64 = 1;
7919 i.types[this_operand] = operand_type_and (i.types[this_operand],
7927 i386_scale (char *scale)
7930 char *save = input_line_pointer;
7932 input_line_pointer = scale;
7933 val = get_absolute_expression ();
7938 i.log2_scale_factor = 0;
7941 i.log2_scale_factor = 1;
7944 i.log2_scale_factor = 2;
7947 i.log2_scale_factor = 3;
7951 char sep = *input_line_pointer;
7953 *input_line_pointer = '\0';
7954 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7956 *input_line_pointer = sep;
7957 input_line_pointer = save;
7961 if (i.log2_scale_factor != 0 && i.index_reg == 0)
7963 as_warn (_("scale factor of %d without an index register"),
7964 1 << i.log2_scale_factor);
7965 i.log2_scale_factor = 0;
7967 scale = input_line_pointer;
7968 input_line_pointer = save;
7973 i386_displacement (char *disp_start, char *disp_end)
7977 char *save_input_line_pointer;
7978 char *gotfree_input_line;
7980 i386_operand_type bigdisp, types = anydisp;
7983 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7985 as_bad (_("at most %d displacement operands are allowed"),
7986 MAX_MEMORY_OPERANDS);
7990 operand_type_set (&bigdisp, 0);
7991 if ((i.types[this_operand].bitfield.jumpabsolute)
7992 || (!current_templates->start->opcode_modifier.jump
7993 && !current_templates->start->opcode_modifier.jumpdword))
7995 bigdisp.bitfield.disp32 = 1;
7996 override = (i.prefix[ADDR_PREFIX] != 0);
7997 if (flag_code == CODE_64BIT)
8001 bigdisp.bitfield.disp32s = 1;
8002 bigdisp.bitfield.disp64 = 1;
8005 else if ((flag_code == CODE_16BIT) ^ override)
8007 bigdisp.bitfield.disp32 = 0;
8008 bigdisp.bitfield.disp16 = 1;
8013 /* For PC-relative branches, the width of the displacement
8014 is dependent upon data size, not address size. */
8015 override = (i.prefix[DATA_PREFIX] != 0);
8016 if (flag_code == CODE_64BIT)
8018 if (override || i.suffix == WORD_MNEM_SUFFIX)
8019 bigdisp.bitfield.disp16 = 1;
8022 bigdisp.bitfield.disp32 = 1;
8023 bigdisp.bitfield.disp32s = 1;
8029 override = (i.suffix == (flag_code != CODE_16BIT
8031 : LONG_MNEM_SUFFIX));
8032 bigdisp.bitfield.disp32 = 1;
8033 if ((flag_code == CODE_16BIT) ^ override)
8035 bigdisp.bitfield.disp32 = 0;
8036 bigdisp.bitfield.disp16 = 1;
8040 i.types[this_operand] = operand_type_or (i.types[this_operand],
8043 exp = &disp_expressions[i.disp_operands];
8044 i.op[this_operand].disps = exp;
8046 save_input_line_pointer = input_line_pointer;
8047 input_line_pointer = disp_start;
8048 END_STRING_AND_SAVE (disp_end);
8050 #ifndef GCC_ASM_O_HACK
8051 #define GCC_ASM_O_HACK 0
8054 END_STRING_AND_SAVE (disp_end + 1);
8055 if (i.types[this_operand].bitfield.baseIndex
8056 && displacement_string_end[-1] == '+')
8058 /* This hack is to avoid a warning when using the "o"
8059 constraint within gcc asm statements.
8062 #define _set_tssldt_desc(n,addr,limit,type) \
8063 __asm__ __volatile__ ( \
8065 "movw %w1,2+%0\n\t" \
8067 "movb %b1,4+%0\n\t" \
8068 "movb %4,5+%0\n\t" \
8069 "movb $0,6+%0\n\t" \
8070 "movb %h1,7+%0\n\t" \
8072 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8074 This works great except that the output assembler ends
8075 up looking a bit weird if it turns out that there is
8076 no offset. You end up producing code that looks like:
8089 So here we provide the missing zero. */
8091 *displacement_string_end = '0';
8094 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8095 if (gotfree_input_line)
8096 input_line_pointer = gotfree_input_line;
8098 exp_seg = expression (exp);
8101 if (*input_line_pointer)
8102 as_bad (_("junk `%s' after expression"), input_line_pointer);
8104 RESTORE_END_STRING (disp_end + 1);
8106 input_line_pointer = save_input_line_pointer;
8107 if (gotfree_input_line)
8109 free (gotfree_input_line);
8111 if (exp->X_op == O_constant || exp->X_op == O_register)
8112 exp->X_op = O_illegal;
8115 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8117 RESTORE_END_STRING (disp_end);
8123 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8124 i386_operand_type types, const char *disp_start)
8126 i386_operand_type bigdisp;
8129 /* We do this to make sure that the section symbol is in
8130 the symbol table. We will ultimately change the relocation
8131 to be relative to the beginning of the section. */
8132 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8133 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8134 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8136 if (exp->X_op != O_symbol)
8139 if (S_IS_LOCAL (exp->X_add_symbol)
8140 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8141 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8142 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8143 exp->X_op = O_subtract;
8144 exp->X_op_symbol = GOT_symbol;
8145 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8146 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8147 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8148 i.reloc[this_operand] = BFD_RELOC_64;
8150 i.reloc[this_operand] = BFD_RELOC_32;
8153 else if (exp->X_op == O_absent
8154 || exp->X_op == O_illegal
8155 || exp->X_op == O_big)
8158 as_bad (_("missing or invalid displacement expression `%s'"),
8163 else if (flag_code == CODE_64BIT
8164 && !i.prefix[ADDR_PREFIX]
8165 && exp->X_op == O_constant)
8167 /* Since displacement is signed extended to 64bit, don't allow
8168 disp32 and turn off disp32s if they are out of range. */
8169 i.types[this_operand].bitfield.disp32 = 0;
8170 if (!fits_in_signed_long (exp->X_add_number))
8172 i.types[this_operand].bitfield.disp32s = 0;
8173 if (i.types[this_operand].bitfield.baseindex)
8175 as_bad (_("0x%lx out range of signed 32bit displacement"),
8176 (long) exp->X_add_number);
8182 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8183 else if (exp->X_op != O_constant
8184 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8185 && exp_seg != absolute_section
8186 && exp_seg != text_section
8187 && exp_seg != data_section
8188 && exp_seg != bss_section
8189 && exp_seg != undefined_section
8190 && !bfd_is_com_section (exp_seg))
8192 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8197 /* Check if this is a displacement only operand. */
8198 bigdisp = i.types[this_operand];
8199 bigdisp.bitfield.disp8 = 0;
8200 bigdisp.bitfield.disp16 = 0;
8201 bigdisp.bitfield.disp32 = 0;
8202 bigdisp.bitfield.disp32s = 0;
8203 bigdisp.bitfield.disp64 = 0;
8204 if (operand_type_all_zero (&bigdisp))
8205 i.types[this_operand] = operand_type_and (i.types[this_operand],
8211 /* Make sure the memory operand we've been dealt is valid.
8212 Return 1 on success, 0 on a failure. */
8215 i386_index_check (const char *operand_string)
8217 const char *kind = "base/index";
8218 enum flag_code addr_mode;
8220 if (i.prefix[ADDR_PREFIX])
8221 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8224 addr_mode = flag_code;
8226 #if INFER_ADDR_PREFIX
8227 if (i.mem_operands == 0)
8229 /* Infer address prefix from the first memory operand. */
8230 const reg_entry *addr_reg = i.base_reg;
8232 if (addr_reg == NULL)
8233 addr_reg = i.index_reg;
8237 if (addr_reg->reg_num == RegEip
8238 || addr_reg->reg_num == RegEiz
8239 || addr_reg->reg_type.bitfield.reg32)
8240 addr_mode = CODE_32BIT;
8241 else if (flag_code != CODE_64BIT
8242 && addr_reg->reg_type.bitfield.reg16)
8243 addr_mode = CODE_16BIT;
8245 if (addr_mode != flag_code)
8247 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8249 /* Change the size of any displacement too. At most one
8250 of Disp16 or Disp32 is set.
8251 FIXME. There doesn't seem to be any real need for
8252 separate Disp16 and Disp32 flags. The same goes for
8253 Imm16 and Imm32. Removing them would probably clean
8254 up the code quite a lot. */
8255 if (flag_code != CODE_64BIT
8256 && (i.types[this_operand].bitfield.disp16
8257 || i.types[this_operand].bitfield.disp32))
8258 i.types[this_operand]
8259 = operand_type_xor (i.types[this_operand], disp16_32);
8266 if (current_templates->start->opcode_modifier.isstring
8267 && !current_templates->start->opcode_modifier.immext
8268 && (current_templates->end[-1].opcode_modifier.isstring
8271 /* Memory operands of string insns are special in that they only allow
8272 a single register (rDI, rSI, or rBX) as their memory address. */
8273 const reg_entry *expected_reg;
8274 static const char *di_si[][2] =
8280 static const char *bx[] = { "ebx", "bx", "rbx" };
8282 kind = "string address";
8284 if (current_templates->start->opcode_modifier.w)
8286 i386_operand_type type = current_templates->end[-1].operand_types[0];
8288 if (!type.bitfield.baseindex
8289 || ((!i.mem_operands != !intel_syntax)
8290 && current_templates->end[-1].operand_types[1]
8291 .bitfield.baseindex))
8292 type = current_templates->end[-1].operand_types[1];
8293 expected_reg = hash_find (reg_hash,
8294 di_si[addr_mode][type.bitfield.esseg]);
8298 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8300 if (i.base_reg != expected_reg
8302 || operand_type_check (i.types[this_operand], disp))
8304 /* The second memory operand must have the same size as
8308 && !((addr_mode == CODE_64BIT
8309 && i.base_reg->reg_type.bitfield.reg64)
8310 || (addr_mode == CODE_32BIT
8311 ? i.base_reg->reg_type.bitfield.reg32
8312 : i.base_reg->reg_type.bitfield.reg16)))
8315 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8317 intel_syntax ? '[' : '(',
8319 expected_reg->reg_name,
8320 intel_syntax ? ']' : ')');
8327 as_bad (_("`%s' is not a valid %s expression"),
8328 operand_string, kind);
8333 if (addr_mode != CODE_16BIT)
8335 /* 32-bit/64-bit checks. */
8337 && (addr_mode == CODE_64BIT
8338 ? !i.base_reg->reg_type.bitfield.reg64
8339 : !i.base_reg->reg_type.bitfield.reg32)
8341 || (i.base_reg->reg_num
8342 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8344 && !i.index_reg->reg_type.bitfield.regxmm
8345 && !i.index_reg->reg_type.bitfield.regymm
8346 && !i.index_reg->reg_type.bitfield.regzmm
8347 && ((addr_mode == CODE_64BIT
8348 ? !(i.index_reg->reg_type.bitfield.reg64
8349 || i.index_reg->reg_num == RegRiz)
8350 : !(i.index_reg->reg_type.bitfield.reg32
8351 || i.index_reg->reg_num == RegEiz))
8352 || !i.index_reg->reg_type.bitfield.baseindex)))
8357 /* 16-bit checks. */
8359 && (!i.base_reg->reg_type.bitfield.reg16
8360 || !i.base_reg->reg_type.bitfield.baseindex))
8362 && (!i.index_reg->reg_type.bitfield.reg16
8363 || !i.index_reg->reg_type.bitfield.baseindex
8365 && i.base_reg->reg_num < 6
8366 && i.index_reg->reg_num >= 6
8367 && i.log2_scale_factor == 0))))
8374 /* Handle vector immediates. */
8377 RC_SAE_immediate (const char *imm_start)
8379 unsigned int match_found, j;
8380 const char *pstr = imm_start;
8388 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8390 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8394 rc_op.type = RC_NamesTable[j].type;
8395 rc_op.operand = this_operand;
8396 i.rounding = &rc_op;
8400 as_bad (_("duplicated `%s'"), imm_start);
8403 pstr += RC_NamesTable[j].len;
8413 as_bad (_("Missing '}': '%s'"), imm_start);
8416 /* RC/SAE immediate string should contain nothing more. */;
8419 as_bad (_("Junk after '}': '%s'"), imm_start);
8423 exp = &im_expressions[i.imm_operands++];
8424 i.op[this_operand].imms = exp;
8426 exp->X_op = O_constant;
8427 exp->X_add_number = 0;
8428 exp->X_add_symbol = (symbolS *) 0;
8429 exp->X_op_symbol = (symbolS *) 0;
8431 i.types[this_operand].bitfield.imm8 = 1;
8435 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8439 i386_att_operand (char *operand_string)
8443 char *op_string = operand_string;
8445 if (is_space_char (*op_string))
8448 /* We check for an absolute prefix (differentiating,
8449 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8450 if (*op_string == ABSOLUTE_PREFIX)
8453 if (is_space_char (*op_string))
8455 i.types[this_operand].bitfield.jumpabsolute = 1;
8458 /* Check if operand is a register. */
8459 if ((r = parse_register (op_string, &end_op)) != NULL)
8461 i386_operand_type temp;
8463 /* Check for a segment override by searching for ':' after a
8464 segment register. */
8466 if (is_space_char (*op_string))
8468 if (*op_string == ':'
8469 && (r->reg_type.bitfield.sreg2
8470 || r->reg_type.bitfield.sreg3))
8475 i.seg[i.mem_operands] = &es;
8478 i.seg[i.mem_operands] = &cs;
8481 i.seg[i.mem_operands] = &ss;
8484 i.seg[i.mem_operands] = &ds;
8487 i.seg[i.mem_operands] = &fs;
8490 i.seg[i.mem_operands] = &gs;
8494 /* Skip the ':' and whitespace. */
8496 if (is_space_char (*op_string))
8499 if (!is_digit_char (*op_string)
8500 && !is_identifier_char (*op_string)
8501 && *op_string != '('
8502 && *op_string != ABSOLUTE_PREFIX)
8504 as_bad (_("bad memory operand `%s'"), op_string);
8507 /* Handle case of %es:*foo. */
8508 if (*op_string == ABSOLUTE_PREFIX)
8511 if (is_space_char (*op_string))
8513 i.types[this_operand].bitfield.jumpabsolute = 1;
8515 goto do_memory_reference;
8518 /* Handle vector operations. */
8519 if (*op_string == '{')
8521 op_string = check_VecOperations (op_string, NULL);
8522 if (op_string == NULL)
8528 as_bad (_("junk `%s' after register"), op_string);
8532 temp.bitfield.baseindex = 0;
8533 i.types[this_operand] = operand_type_or (i.types[this_operand],
8535 i.types[this_operand].bitfield.unspecified = 0;
8536 i.op[this_operand].regs = r;
8539 else if (*op_string == REGISTER_PREFIX)
8541 as_bad (_("bad register name `%s'"), op_string);
8544 else if (*op_string == IMMEDIATE_PREFIX)
8547 if (i.types[this_operand].bitfield.jumpabsolute)
8549 as_bad (_("immediate operand illegal with absolute jump"));
8552 if (!i386_immediate (op_string))
8555 else if (RC_SAE_immediate (operand_string))
8557 /* If it is a RC or SAE immediate, do nothing. */
8560 else if (is_digit_char (*op_string)
8561 || is_identifier_char (*op_string)
8562 || *op_string == '(')
8564 /* This is a memory reference of some sort. */
8567 /* Start and end of displacement string expression (if found). */
8568 char *displacement_string_start;
8569 char *displacement_string_end;
8572 do_memory_reference:
8573 if ((i.mem_operands == 1
8574 && !current_templates->start->opcode_modifier.isstring)
8575 || i.mem_operands == 2)
8577 as_bad (_("too many memory references for `%s'"),
8578 current_templates->start->name);
8582 /* Check for base index form. We detect the base index form by
8583 looking for an ')' at the end of the operand, searching
8584 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8586 base_string = op_string + strlen (op_string);
8588 /* Handle vector operations. */
8589 vop_start = strchr (op_string, '{');
8590 if (vop_start && vop_start < base_string)
8592 if (check_VecOperations (vop_start, base_string) == NULL)
8594 base_string = vop_start;
8598 if (is_space_char (*base_string))
8601 /* If we only have a displacement, set-up for it to be parsed later. */
8602 displacement_string_start = op_string;
8603 displacement_string_end = base_string + 1;
8605 if (*base_string == ')')
8608 unsigned int parens_balanced = 1;
8609 /* We've already checked that the number of left & right ()'s are
8610 equal, so this loop will not be infinite. */
8614 if (*base_string == ')')
8616 if (*base_string == '(')
8619 while (parens_balanced);
8621 temp_string = base_string;
8623 /* Skip past '(' and whitespace. */
8625 if (is_space_char (*base_string))
8628 if (*base_string == ','
8629 || ((i.base_reg = parse_register (base_string, &end_op))
8632 displacement_string_end = temp_string;
8634 i.types[this_operand].bitfield.baseindex = 1;
8638 base_string = end_op;
8639 if (is_space_char (*base_string))
8643 /* There may be an index reg or scale factor here. */
8644 if (*base_string == ',')
8647 if (is_space_char (*base_string))
8650 if ((i.index_reg = parse_register (base_string, &end_op))
8653 base_string = end_op;
8654 if (is_space_char (*base_string))
8656 if (*base_string == ',')
8659 if (is_space_char (*base_string))
8662 else if (*base_string != ')')
8664 as_bad (_("expecting `,' or `)' "
8665 "after index register in `%s'"),
8670 else if (*base_string == REGISTER_PREFIX)
8672 end_op = strchr (base_string, ',');
8675 as_bad (_("bad register name `%s'"), base_string);
8679 /* Check for scale factor. */
8680 if (*base_string != ')')
8682 char *end_scale = i386_scale (base_string);
8687 base_string = end_scale;
8688 if (is_space_char (*base_string))
8690 if (*base_string != ')')
8692 as_bad (_("expecting `)' "
8693 "after scale factor in `%s'"),
8698 else if (!i.index_reg)
8700 as_bad (_("expecting index register or scale factor "
8701 "after `,'; got '%c'"),
8706 else if (*base_string != ')')
8708 as_bad (_("expecting `,' or `)' "
8709 "after base register in `%s'"),
8714 else if (*base_string == REGISTER_PREFIX)
8716 end_op = strchr (base_string, ',');
8719 as_bad (_("bad register name `%s'"), base_string);
8724 /* If there's an expression beginning the operand, parse it,
8725 assuming displacement_string_start and
8726 displacement_string_end are meaningful. */
8727 if (displacement_string_start != displacement_string_end)
8729 if (!i386_displacement (displacement_string_start,
8730 displacement_string_end))
8734 /* Special case for (%dx) while doing input/output op. */
8736 && operand_type_equal (&i.base_reg->reg_type,
8737 ®16_inoutportreg)
8739 && i.log2_scale_factor == 0
8740 && i.seg[i.mem_operands] == 0
8741 && !operand_type_check (i.types[this_operand], disp))
8743 i.types[this_operand] = inoutportreg;
8747 if (i386_index_check (operand_string) == 0)
8749 i.types[this_operand].bitfield.mem = 1;
8754 /* It's not a memory operand; argh! */
8755 as_bad (_("invalid char %s beginning operand %d `%s'"),
8756 output_invalid (*op_string),
8761 return 1; /* Normal return. */
8764 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8765 that an rs_machine_dependent frag may reach. */
8768 i386_frag_max_var (fragS *frag)
8770 /* The only relaxable frags are for jumps.
8771 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8772 gas_assert (frag->fr_type == rs_machine_dependent);
8773 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8776 /* md_estimate_size_before_relax()
8778 Called just before relax() for rs_machine_dependent frags. The x86
8779 assembler uses these frags to handle variable size jump
8782 Any symbol that is now undefined will not become defined.
8783 Return the correct fr_subtype in the frag.
8784 Return the initial "guess for variable size of frag" to caller.
8785 The guess is actually the growth beyond the fixed part. Whatever
8786 we do to grow the fixed or variable part contributes to our
8790 md_estimate_size_before_relax (fragS *fragP, segT segment)
8792 /* We've already got fragP->fr_subtype right; all we have to do is
8793 check for un-relaxable symbols. On an ELF system, we can't relax
8794 an externally visible symbol, because it may be overridden by a
8796 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
8797 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8799 && (S_IS_EXTERNAL (fragP->fr_symbol)
8800 || S_IS_WEAK (fragP->fr_symbol)
8801 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8802 & BSF_GNU_INDIRECT_FUNCTION))))
8804 #if defined (OBJ_COFF) && defined (TE_PE)
8805 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
8806 && S_IS_WEAK (fragP->fr_symbol))
8810 /* Symbol is undefined in this segment, or we need to keep a
8811 reloc so that weak symbols can be overridden. */
8812 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
8813 enum bfd_reloc_code_real reloc_type;
8814 unsigned char *opcode;
8817 if (fragP->fr_var != NO_RELOC)
8818 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
8820 reloc_type = BFD_RELOC_16_PCREL;
8822 reloc_type = BFD_RELOC_32_PCREL;
8824 old_fr_fix = fragP->fr_fix;
8825 opcode = (unsigned char *) fragP->fr_opcode;
8827 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
8830 /* Make jmp (0xeb) a (d)word displacement jump. */
8832 fragP->fr_fix += size;
8833 fix_new (fragP, old_fr_fix, size,
8835 fragP->fr_offset, 1,
8841 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
8843 /* Negate the condition, and branch past an
8844 unconditional jump. */
8847 /* Insert an unconditional jump. */
8849 /* We added two extra opcode bytes, and have a two byte
8851 fragP->fr_fix += 2 + 2;
8852 fix_new (fragP, old_fr_fix + 2, 2,
8854 fragP->fr_offset, 1,
8861 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8866 fixP = fix_new (fragP, old_fr_fix, 1,
8868 fragP->fr_offset, 1,
8870 fixP->fx_signed = 1;
8874 /* This changes the byte-displacement jump 0x7N
8875 to the (d)word-displacement jump 0x0f,0x8N. */
8876 opcode[1] = opcode[0] + 0x10;
8877 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8878 /* We've added an opcode byte. */
8879 fragP->fr_fix += 1 + size;
8880 fix_new (fragP, old_fr_fix + 1, size,
8882 fragP->fr_offset, 1,
8887 BAD_CASE (fragP->fr_subtype);
8891 return fragP->fr_fix - old_fr_fix;
8894 /* Guess size depending on current relax state. Initially the relax
8895 state will correspond to a short jump and we return 1, because
8896 the variable part of the frag (the branch offset) is one byte
8897 long. However, we can relax a section more than once and in that
8898 case we must either set fr_subtype back to the unrelaxed state,
8899 or return the value for the appropriate branch. */
8900 return md_relax_table[fragP->fr_subtype].rlx_length;
8903 /* Called after relax() is finished.
8905 In: Address of frag.
8906 fr_type == rs_machine_dependent.
8907 fr_subtype is what the address relaxed to.
8909 Out: Any fixSs and constants are set up.
8910 Caller will turn frag into a ".space 0". */
8913 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8916 unsigned char *opcode;
8917 unsigned char *where_to_put_displacement = NULL;
8918 offsetT target_address;
8919 offsetT opcode_address;
8920 unsigned int extension = 0;
8921 offsetT displacement_from_opcode_start;
8923 opcode = (unsigned char *) fragP->fr_opcode;
8925 /* Address we want to reach in file space. */
8926 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
8928 /* Address opcode resides at in file space. */
8929 opcode_address = fragP->fr_address + fragP->fr_fix;
8931 /* Displacement from opcode start to fill into instruction. */
8932 displacement_from_opcode_start = target_address - opcode_address;
8934 if ((fragP->fr_subtype & BIG) == 0)
8936 /* Don't have to change opcode. */
8937 extension = 1; /* 1 opcode + 1 displacement */
8938 where_to_put_displacement = &opcode[1];
8942 if (no_cond_jump_promotion
8943 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
8944 as_warn_where (fragP->fr_file, fragP->fr_line,
8945 _("long jump required"));
8947 switch (fragP->fr_subtype)
8949 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8950 extension = 4; /* 1 opcode + 4 displacement */
8952 where_to_put_displacement = &opcode[1];
8955 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8956 extension = 2; /* 1 opcode + 2 displacement */
8958 where_to_put_displacement = &opcode[1];
8961 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8962 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8963 extension = 5; /* 2 opcode + 4 displacement */
8964 opcode[1] = opcode[0] + 0x10;
8965 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8966 where_to_put_displacement = &opcode[2];
8969 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8970 extension = 3; /* 2 opcode + 2 displacement */
8971 opcode[1] = opcode[0] + 0x10;
8972 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8973 where_to_put_displacement = &opcode[2];
8976 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8981 where_to_put_displacement = &opcode[3];
8985 BAD_CASE (fragP->fr_subtype);
8990 /* If size if less then four we are sure that the operand fits,
8991 but if it's 4, then it could be that the displacement is larger
8993 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8995 && ((addressT) (displacement_from_opcode_start - extension
8996 + ((addressT) 1 << 31))
8997 > (((addressT) 2 << 31) - 1)))
8999 as_bad_where (fragP->fr_file, fragP->fr_line,
9000 _("jump target out of range"));
9001 /* Make us emit 0. */
9002 displacement_from_opcode_start = extension;
9004 /* Now put displacement after opcode. */
9005 md_number_to_chars ((char *) where_to_put_displacement,
9006 (valueT) (displacement_from_opcode_start - extension),
9007 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9008 fragP->fr_fix += extension;
9011 /* Apply a fixup (fixP) to segment data, once it has been determined
9012 by our caller that we have all the info we need to fix it up.
9014 Parameter valP is the pointer to the value of the bits.
9016 On the 386, immediates, displacements, and data pointers are all in
9017 the same (little-endian) format, so we don't need to care about which
9021 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9023 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9024 valueT value = *valP;
9026 #if !defined (TE_Mach)
9029 switch (fixP->fx_r_type)
9035 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9038 case BFD_RELOC_X86_64_32S:
9039 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9042 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9045 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9050 if (fixP->fx_addsy != NULL
9051 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9052 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9053 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9054 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9055 && !use_rela_relocations)
9057 /* This is a hack. There should be a better way to handle this.
9058 This covers for the fact that bfd_install_relocation will
9059 subtract the current location (for partial_inplace, PC relative
9060 relocations); see more below. */
9064 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9067 value += fixP->fx_where + fixP->fx_frag->fr_address;
9069 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9072 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9075 || (symbol_section_p (fixP->fx_addsy)
9076 && sym_seg != absolute_section))
9077 && !generic_force_reloc (fixP))
9079 /* Yes, we add the values in twice. This is because
9080 bfd_install_relocation subtracts them out again. I think
9081 bfd_install_relocation is broken, but I don't dare change
9083 value += fixP->fx_where + fixP->fx_frag->fr_address;
9087 #if defined (OBJ_COFF) && defined (TE_PE)
9088 /* For some reason, the PE format does not store a
9089 section address offset for a PC relative symbol. */
9090 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9091 || S_IS_WEAK (fixP->fx_addsy))
9092 value += md_pcrel_from (fixP);
9095 #if defined (OBJ_COFF) && defined (TE_PE)
9096 if (fixP->fx_addsy != NULL
9097 && S_IS_WEAK (fixP->fx_addsy)
9098 /* PR 16858: Do not modify weak function references. */
9099 && ! fixP->fx_pcrel)
9101 #if !defined (TE_PEP)
9102 /* For x86 PE weak function symbols are neither PC-relative
9103 nor do they set S_IS_FUNCTION. So the only reliable way
9104 to detect them is to check the flags of their containing
9106 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9107 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9111 value -= S_GET_VALUE (fixP->fx_addsy);
9115 /* Fix a few things - the dynamic linker expects certain values here,
9116 and we must not disappoint it. */
9117 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9118 if (IS_ELF && fixP->fx_addsy)
9119 switch (fixP->fx_r_type)
9121 case BFD_RELOC_386_PLT32:
9122 case BFD_RELOC_X86_64_PLT32:
9123 /* Make the jump instruction point to the address of the operand. At
9124 runtime we merely add the offset to the actual PLT entry. */
9128 case BFD_RELOC_386_TLS_GD:
9129 case BFD_RELOC_386_TLS_LDM:
9130 case BFD_RELOC_386_TLS_IE_32:
9131 case BFD_RELOC_386_TLS_IE:
9132 case BFD_RELOC_386_TLS_GOTIE:
9133 case BFD_RELOC_386_TLS_GOTDESC:
9134 case BFD_RELOC_X86_64_TLSGD:
9135 case BFD_RELOC_X86_64_TLSLD:
9136 case BFD_RELOC_X86_64_GOTTPOFF:
9137 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9138 value = 0; /* Fully resolved at runtime. No addend. */
9140 case BFD_RELOC_386_TLS_LE:
9141 case BFD_RELOC_386_TLS_LDO_32:
9142 case BFD_RELOC_386_TLS_LE_32:
9143 case BFD_RELOC_X86_64_DTPOFF32:
9144 case BFD_RELOC_X86_64_DTPOFF64:
9145 case BFD_RELOC_X86_64_TPOFF32:
9146 case BFD_RELOC_X86_64_TPOFF64:
9147 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9150 case BFD_RELOC_386_TLS_DESC_CALL:
9151 case BFD_RELOC_X86_64_TLSDESC_CALL:
9152 value = 0; /* Fully resolved at runtime. No addend. */
9153 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9157 case BFD_RELOC_386_GOT32:
9158 case BFD_RELOC_X86_64_GOT32:
9159 value = 0; /* Fully resolved at runtime. No addend. */
9162 case BFD_RELOC_VTABLE_INHERIT:
9163 case BFD_RELOC_VTABLE_ENTRY:
9170 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9172 #endif /* !defined (TE_Mach) */
9174 /* Are we finished with this relocation now? */
9175 if (fixP->fx_addsy == NULL)
9177 #if defined (OBJ_COFF) && defined (TE_PE)
9178 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9181 /* Remember value for tc_gen_reloc. */
9182 fixP->fx_addnumber = value;
9183 /* Clear out the frag for now. */
9187 else if (use_rela_relocations)
9189 fixP->fx_no_overflow = 1;
9190 /* Remember value for tc_gen_reloc. */
9191 fixP->fx_addnumber = value;
9195 md_number_to_chars (p, value, fixP->fx_size);
9199 md_atof (int type, char *litP, int *sizeP)
9201 /* This outputs the LITTLENUMs in REVERSE order;
9202 in accord with the bigendian 386. */
9203 return ieee_md_atof (type, litP, sizeP, FALSE);
9206 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9209 output_invalid (int c)
9212 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9215 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9216 "(0x%x)", (unsigned char) c);
9217 return output_invalid_buf;
9220 /* REG_STRING starts *before* REGISTER_PREFIX. */
9222 static const reg_entry *
9223 parse_real_register (char *reg_string, char **end_op)
9225 char *s = reg_string;
9227 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9230 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9231 if (*s == REGISTER_PREFIX)
9234 if (is_space_char (*s))
9238 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9240 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9241 return (const reg_entry *) NULL;
9245 /* For naked regs, make sure that we are not dealing with an identifier.
9246 This prevents confusing an identifier like `eax_var' with register
9248 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9249 return (const reg_entry *) NULL;
9253 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9255 /* Handle floating point regs, allowing spaces in the (i) part. */
9256 if (r == i386_regtab /* %st is first entry of table */)
9258 if (is_space_char (*s))
9263 if (is_space_char (*s))
9265 if (*s >= '0' && *s <= '7')
9269 if (is_space_char (*s))
9274 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9279 /* We have "%st(" then garbage. */
9280 return (const reg_entry *) NULL;
9284 if (r == NULL || allow_pseudo_reg)
9287 if (operand_type_all_zero (&r->reg_type))
9288 return (const reg_entry *) NULL;
9290 if ((r->reg_type.bitfield.reg32
9291 || r->reg_type.bitfield.sreg3
9292 || r->reg_type.bitfield.control
9293 || r->reg_type.bitfield.debug
9294 || r->reg_type.bitfield.test)
9295 && !cpu_arch_flags.bitfield.cpui386)
9296 return (const reg_entry *) NULL;
9298 if (r->reg_type.bitfield.floatreg
9299 && !cpu_arch_flags.bitfield.cpu8087
9300 && !cpu_arch_flags.bitfield.cpu287
9301 && !cpu_arch_flags.bitfield.cpu387)
9302 return (const reg_entry *) NULL;
9304 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9305 return (const reg_entry *) NULL;
9307 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9308 return (const reg_entry *) NULL;
9310 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9311 return (const reg_entry *) NULL;
9313 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9314 && !cpu_arch_flags.bitfield.cpuavx512f)
9315 return (const reg_entry *) NULL;
9317 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9318 if (!allow_index_reg
9319 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9320 return (const reg_entry *) NULL;
9322 /* Upper 16 vector register is only available with VREX in 64bit
9324 if ((r->reg_flags & RegVRex))
9326 if (!cpu_arch_flags.bitfield.cpuvrex
9327 || flag_code != CODE_64BIT)
9328 return (const reg_entry *) NULL;
9333 if (((r->reg_flags & (RegRex64 | RegRex))
9334 || r->reg_type.bitfield.reg64)
9335 && (!cpu_arch_flags.bitfield.cpulm
9336 || !operand_type_equal (&r->reg_type, &control))
9337 && flag_code != CODE_64BIT)
9338 return (const reg_entry *) NULL;
9340 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9341 return (const reg_entry *) NULL;
9346 /* REG_STRING starts *before* REGISTER_PREFIX. */
9348 static const reg_entry *
9349 parse_register (char *reg_string, char **end_op)
9353 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9354 r = parse_real_register (reg_string, end_op);
9359 char *save = input_line_pointer;
9363 input_line_pointer = reg_string;
9364 c = get_symbol_end ();
9365 symbolP = symbol_find (reg_string);
9366 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9368 const expressionS *e = symbol_get_value_expression (symbolP);
9370 know (e->X_op == O_register);
9371 know (e->X_add_number >= 0
9372 && (valueT) e->X_add_number < i386_regtab_size);
9373 r = i386_regtab + e->X_add_number;
9374 if ((r->reg_flags & RegVRex))
9376 *end_op = input_line_pointer;
9378 *input_line_pointer = c;
9379 input_line_pointer = save;
9385 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9388 char *end = input_line_pointer;
9391 r = parse_register (name, &input_line_pointer);
9392 if (r && end <= input_line_pointer)
9394 *nextcharP = *input_line_pointer;
9395 *input_line_pointer = 0;
9396 e->X_op = O_register;
9397 e->X_add_number = r - i386_regtab;
9400 input_line_pointer = end;
9402 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9406 md_operand (expressionS *e)
9411 switch (*input_line_pointer)
9413 case REGISTER_PREFIX:
9414 r = parse_real_register (input_line_pointer, &end);
9417 e->X_op = O_register;
9418 e->X_add_number = r - i386_regtab;
9419 input_line_pointer = end;
9424 gas_assert (intel_syntax);
9425 end = input_line_pointer++;
9427 if (*input_line_pointer == ']')
9429 ++input_line_pointer;
9430 e->X_op_symbol = make_expr_symbol (e);
9431 e->X_add_symbol = NULL;
9432 e->X_add_number = 0;
9438 input_line_pointer = end;
9445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9446 const char *md_shortopts = "kVQ:sqn";
9448 const char *md_shortopts = "qn";
9451 #define OPTION_32 (OPTION_MD_BASE + 0)
9452 #define OPTION_64 (OPTION_MD_BASE + 1)
9453 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9454 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9455 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9456 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9457 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9458 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9459 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9460 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9461 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9462 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9463 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9464 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9465 #define OPTION_X32 (OPTION_MD_BASE + 14)
9466 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9467 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9468 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9469 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9470 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9471 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9473 struct option md_longopts[] =
9475 {"32", no_argument, NULL, OPTION_32},
9476 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9477 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9478 {"64", no_argument, NULL, OPTION_64},
9480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9481 {"x32", no_argument, NULL, OPTION_X32},
9483 {"divide", no_argument, NULL, OPTION_DIVIDE},
9484 {"march", required_argument, NULL, OPTION_MARCH},
9485 {"mtune", required_argument, NULL, OPTION_MTUNE},
9486 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9487 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9488 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9489 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9490 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9491 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9492 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9493 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9494 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9495 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9496 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9497 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9498 # if defined (TE_PE) || defined (TE_PEP)
9499 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9501 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
9502 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
9503 {NULL, no_argument, NULL, 0}
9505 size_t md_longopts_size = sizeof (md_longopts);
9508 md_parse_option (int c, char *arg)
9516 optimize_align_code = 0;
9523 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9524 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9525 should be emitted or not. FIXME: Not implemented. */
9529 /* -V: SVR4 argument to print version ID. */
9531 print_version_id ();
9534 /* -k: Ignore for FreeBSD compatibility. */
9539 /* -s: On i386 Solaris, this tells the native assembler to use
9540 .stab instead of .stab.excl. We always use .stab anyhow. */
9543 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9544 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9547 const char **list, **l;
9549 list = bfd_target_list ();
9550 for (l = list; *l != NULL; l++)
9551 if (CONST_STRNEQ (*l, "elf64-x86-64")
9552 || strcmp (*l, "coff-x86-64") == 0
9553 || strcmp (*l, "pe-x86-64") == 0
9554 || strcmp (*l, "pei-x86-64") == 0
9555 || strcmp (*l, "mach-o-x86-64") == 0)
9557 default_arch = "x86_64";
9561 as_fatal (_("no compiled in support for x86_64"));
9567 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9571 const char **list, **l;
9573 list = bfd_target_list ();
9574 for (l = list; *l != NULL; l++)
9575 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9577 default_arch = "x86_64:32";
9581 as_fatal (_("no compiled in support for 32bit x86_64"));
9585 as_fatal (_("32bit x86_64 is only supported for ELF"));
9590 default_arch = "i386";
9594 #ifdef SVR4_COMMENT_CHARS
9599 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9601 for (s = i386_comment_chars; *s != '\0'; s++)
9605 i386_comment_chars = n;
9611 arch = xstrdup (arg);
9615 as_fatal (_("invalid -march= option: `%s'"), arg);
9616 next = strchr (arch, '+');
9619 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9621 if (strcmp (arch, cpu_arch [j].name) == 0)
9624 if (! cpu_arch[j].flags.bitfield.cpui386)
9627 cpu_arch_name = cpu_arch[j].name;
9628 cpu_sub_arch_name = NULL;
9629 cpu_arch_flags = cpu_arch[j].flags;
9630 cpu_arch_isa = cpu_arch[j].type;
9631 cpu_arch_isa_flags = cpu_arch[j].flags;
9632 if (!cpu_arch_tune_set)
9634 cpu_arch_tune = cpu_arch_isa;
9635 cpu_arch_tune_flags = cpu_arch_isa_flags;
9639 else if (*cpu_arch [j].name == '.'
9640 && strcmp (arch, cpu_arch [j].name + 1) == 0)
9642 /* ISA entension. */
9643 i386_cpu_flags flags;
9645 if (!cpu_arch[j].negated)
9646 flags = cpu_flags_or (cpu_arch_flags,
9649 flags = cpu_flags_and_not (cpu_arch_flags,
9651 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9653 if (cpu_sub_arch_name)
9655 char *name = cpu_sub_arch_name;
9656 cpu_sub_arch_name = concat (name,
9658 (const char *) NULL);
9662 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
9663 cpu_arch_flags = flags;
9664 cpu_arch_isa_flags = flags;
9670 if (j >= ARRAY_SIZE (cpu_arch))
9671 as_fatal (_("invalid -march= option: `%s'"), arg);
9675 while (next != NULL );
9680 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9681 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9683 if (strcmp (arg, cpu_arch [j].name) == 0)
9685 cpu_arch_tune_set = 1;
9686 cpu_arch_tune = cpu_arch [j].type;
9687 cpu_arch_tune_flags = cpu_arch[j].flags;
9691 if (j >= ARRAY_SIZE (cpu_arch))
9692 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9695 case OPTION_MMNEMONIC:
9696 if (strcasecmp (arg, "att") == 0)
9698 else if (strcasecmp (arg, "intel") == 0)
9701 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
9704 case OPTION_MSYNTAX:
9705 if (strcasecmp (arg, "att") == 0)
9707 else if (strcasecmp (arg, "intel") == 0)
9710 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
9713 case OPTION_MINDEX_REG:
9714 allow_index_reg = 1;
9717 case OPTION_MNAKED_REG:
9718 allow_naked_reg = 1;
9721 case OPTION_MOLD_GCC:
9725 case OPTION_MSSE2AVX:
9729 case OPTION_MSSE_CHECK:
9730 if (strcasecmp (arg, "error") == 0)
9731 sse_check = check_error;
9732 else if (strcasecmp (arg, "warning") == 0)
9733 sse_check = check_warning;
9734 else if (strcasecmp (arg, "none") == 0)
9735 sse_check = check_none;
9737 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
9740 case OPTION_MOPERAND_CHECK:
9741 if (strcasecmp (arg, "error") == 0)
9742 operand_check = check_error;
9743 else if (strcasecmp (arg, "warning") == 0)
9744 operand_check = check_warning;
9745 else if (strcasecmp (arg, "none") == 0)
9746 operand_check = check_none;
9748 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9751 case OPTION_MAVXSCALAR:
9752 if (strcasecmp (arg, "128") == 0)
9754 else if (strcasecmp (arg, "256") == 0)
9757 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
9760 case OPTION_MADD_BND_PREFIX:
9764 case OPTION_MEVEXLIG:
9765 if (strcmp (arg, "128") == 0)
9767 else if (strcmp (arg, "256") == 0)
9769 else if (strcmp (arg, "512") == 0)
9772 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9775 case OPTION_MEVEXRCIG:
9776 if (strcmp (arg, "rne") == 0)
9778 else if (strcmp (arg, "rd") == 0)
9780 else if (strcmp (arg, "ru") == 0)
9782 else if (strcmp (arg, "rz") == 0)
9785 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9788 case OPTION_MEVEXWIG:
9789 if (strcmp (arg, "0") == 0)
9791 else if (strcmp (arg, "1") == 0)
9794 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9797 # if defined (TE_PE) || defined (TE_PEP)
9798 case OPTION_MBIG_OBJ:
9803 case OPTION_OMIT_LOCK_PREFIX:
9804 if (strcasecmp (arg, "yes") == 0)
9805 omit_lock_prefix = 1;
9806 else if (strcasecmp (arg, "no") == 0)
9807 omit_lock_prefix = 0;
9809 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9818 #define MESSAGE_TEMPLATE \
9822 show_arch (FILE *stream, int ext, int check)
9824 static char message[] = MESSAGE_TEMPLATE;
9825 char *start = message + 27;
9827 int size = sizeof (MESSAGE_TEMPLATE);
9834 left = size - (start - message);
9835 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9837 /* Should it be skipped? */
9838 if (cpu_arch [j].skip)
9841 name = cpu_arch [j].name;
9842 len = cpu_arch [j].len;
9845 /* It is an extension. Skip if we aren't asked to show it. */
9856 /* It is an processor. Skip if we show only extension. */
9859 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9861 /* It is an impossible processor - skip. */
9865 /* Reserve 2 spaces for ", " or ",\0" */
9868 /* Check if there is any room. */
9876 p = mempcpy (p, name, len);
9880 /* Output the current message now and start a new one. */
9883 fprintf (stream, "%s\n", message);
9885 left = size - (start - message) - len - 2;
9887 gas_assert (left >= 0);
9889 p = mempcpy (p, name, len);
9894 fprintf (stream, "%s\n", message);
9898 md_show_usage (FILE *stream)
9900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9901 fprintf (stream, _("\
9903 -V print assembler version number\n\
9906 fprintf (stream, _("\
9907 -n Do not optimize code alignment\n\
9908 -q quieten some warnings\n"));
9909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9910 fprintf (stream, _("\
9913 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9914 || defined (TE_PE) || defined (TE_PEP))
9915 fprintf (stream, _("\
9916 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9918 #ifdef SVR4_COMMENT_CHARS
9919 fprintf (stream, _("\
9920 --divide do not treat `/' as a comment character\n"));
9922 fprintf (stream, _("\
9923 --divide ignored\n"));
9925 fprintf (stream, _("\
9926 -march=CPU[,+EXTENSION...]\n\
9927 generate code for CPU and EXTENSION, CPU is one of:\n"));
9928 show_arch (stream, 0, 1);
9929 fprintf (stream, _("\
9930 EXTENSION is combination of:\n"));
9931 show_arch (stream, 1, 0);
9932 fprintf (stream, _("\
9933 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9934 show_arch (stream, 0, 0);
9935 fprintf (stream, _("\
9936 -msse2avx encode SSE instructions with VEX prefix\n"));
9937 fprintf (stream, _("\
9938 -msse-check=[none|error|warning]\n\
9939 check SSE instructions\n"));
9940 fprintf (stream, _("\
9941 -moperand-check=[none|error|warning]\n\
9942 check operand combinations for validity\n"));
9943 fprintf (stream, _("\
9944 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9946 fprintf (stream, _("\
9947 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9949 fprintf (stream, _("\
9950 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9951 for EVEX.W bit ignored instructions\n"));
9952 fprintf (stream, _("\
9953 -mevexrcig=[rne|rd|ru|rz]\n\
9954 encode EVEX instructions with specific EVEX.RC value\n\
9955 for SAE-only ignored instructions\n"));
9956 fprintf (stream, _("\
9957 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9958 fprintf (stream, _("\
9959 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9960 fprintf (stream, _("\
9961 -mindex-reg support pseudo index registers\n"));
9962 fprintf (stream, _("\
9963 -mnaked-reg don't require `%%' prefix for registers\n"));
9964 fprintf (stream, _("\
9965 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9966 fprintf (stream, _("\
9967 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9968 # if defined (TE_PE) || defined (TE_PEP)
9969 fprintf (stream, _("\
9970 -mbig-obj generate big object files\n"));
9972 fprintf (stream, _("\
9973 -momit-lock-prefix=[no|yes]\n\
9974 strip all lock prefixes\n"));
9977 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9978 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9979 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9981 /* Pick the target format to use. */
9984 i386_target_format (void)
9986 if (!strncmp (default_arch, "x86_64", 6))
9988 update_code_flag (CODE_64BIT, 1);
9989 if (default_arch[6] == '\0')
9990 x86_elf_abi = X86_64_ABI;
9992 x86_elf_abi = X86_64_X32_ABI;
9994 else if (!strcmp (default_arch, "i386"))
9995 update_code_flag (CODE_32BIT, 1);
9997 as_fatal (_("unknown architecture"));
9999 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10000 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10001 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10002 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10004 switch (OUTPUT_FLAVOR)
10006 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10007 case bfd_target_aout_flavour:
10008 return AOUT_TARGET_FORMAT;
10010 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10011 # if defined (TE_PE) || defined (TE_PEP)
10012 case bfd_target_coff_flavour:
10013 if (flag_code == CODE_64BIT)
10014 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10017 # elif defined (TE_GO32)
10018 case bfd_target_coff_flavour:
10019 return "coff-go32";
10021 case bfd_target_coff_flavour:
10022 return "coff-i386";
10025 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10026 case bfd_target_elf_flavour:
10028 const char *format;
10030 switch (x86_elf_abi)
10033 format = ELF_TARGET_FORMAT;
10036 use_rela_relocations = 1;
10038 format = ELF_TARGET_FORMAT64;
10040 case X86_64_X32_ABI:
10041 use_rela_relocations = 1;
10043 disallow_64bit_reloc = 1;
10044 format = ELF_TARGET_FORMAT32;
10047 if (cpu_arch_isa == PROCESSOR_L1OM)
10049 if (x86_elf_abi != X86_64_ABI)
10050 as_fatal (_("Intel L1OM is 64bit only"));
10051 return ELF_TARGET_L1OM_FORMAT;
10053 if (cpu_arch_isa == PROCESSOR_K1OM)
10055 if (x86_elf_abi != X86_64_ABI)
10056 as_fatal (_("Intel K1OM is 64bit only"));
10057 return ELF_TARGET_K1OM_FORMAT;
10063 #if defined (OBJ_MACH_O)
10064 case bfd_target_mach_o_flavour:
10065 if (flag_code == CODE_64BIT)
10067 use_rela_relocations = 1;
10069 return "mach-o-x86-64";
10072 return "mach-o-i386";
10080 #endif /* OBJ_MAYBE_ more than one */
10082 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10084 i386_elf_emit_arch_note (void)
10086 if (IS_ELF && cpu_arch_name != NULL)
10089 asection *seg = now_seg;
10090 subsegT subseg = now_subseg;
10091 Elf_Internal_Note i_note;
10092 Elf_External_Note e_note;
10093 asection *note_secp;
10096 /* Create the .note section. */
10097 note_secp = subseg_new (".note", 0);
10098 bfd_set_section_flags (stdoutput,
10100 SEC_HAS_CONTENTS | SEC_READONLY);
10102 /* Process the arch string. */
10103 len = strlen (cpu_arch_name);
10105 i_note.namesz = len + 1;
10107 i_note.type = NT_ARCH;
10108 p = frag_more (sizeof (e_note.namesz));
10109 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10110 p = frag_more (sizeof (e_note.descsz));
10111 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10112 p = frag_more (sizeof (e_note.type));
10113 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10114 p = frag_more (len + 1);
10115 strcpy (p, cpu_arch_name);
10117 frag_align (2, 0, 0);
10119 subseg_set (seg, subseg);
10125 md_undefined_symbol (char *name)
10127 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10128 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10129 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10130 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10134 if (symbol_find (name))
10135 as_bad (_("GOT already in symbol table"));
10136 GOT_symbol = symbol_new (name, undefined_section,
10137 (valueT) 0, &zero_address_frag);
10144 /* Round up a section size to the appropriate boundary. */
10147 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10149 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10150 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10152 /* For a.out, force the section size to be aligned. If we don't do
10153 this, BFD will align it for us, but it will not write out the
10154 final bytes of the section. This may be a bug in BFD, but it is
10155 easier to fix it here since that is how the other a.out targets
10159 align = bfd_get_section_alignment (stdoutput, segment);
10160 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10167 /* On the i386, PC-relative offsets are relative to the start of the
10168 next instruction. That is, the address of the offset, plus its
10169 size, since the offset is always the last part of the insn. */
10172 md_pcrel_from (fixS *fixP)
10174 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10180 s_bss (int ignore ATTRIBUTE_UNUSED)
10184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10186 obj_elf_section_change_hook ();
10188 temp = get_absolute_expression ();
10189 subseg_set (bss_section, (subsegT) temp);
10190 demand_empty_rest_of_line ();
10196 i386_validate_fix (fixS *fixp)
10198 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10200 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10204 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10209 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10211 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10213 fixp->fx_subsy = 0;
10218 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10221 bfd_reloc_code_real_type code;
10223 switch (fixp->fx_r_type)
10225 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10226 case BFD_RELOC_SIZE32:
10227 case BFD_RELOC_SIZE64:
10228 if (S_IS_DEFINED (fixp->fx_addsy)
10229 && !S_IS_EXTERNAL (fixp->fx_addsy))
10231 /* Resolve size relocation against local symbol to size of
10232 the symbol plus addend. */
10233 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10234 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10235 && !fits_in_unsigned_long (value))
10236 as_bad_where (fixp->fx_file, fixp->fx_line,
10237 _("symbol size computation overflow"));
10238 fixp->fx_addsy = NULL;
10239 fixp->fx_subsy = NULL;
10240 md_apply_fix (fixp, (valueT *) &value, NULL);
10245 case BFD_RELOC_X86_64_PLT32:
10246 case BFD_RELOC_X86_64_GOT32:
10247 case BFD_RELOC_X86_64_GOTPCREL:
10248 case BFD_RELOC_386_PLT32:
10249 case BFD_RELOC_386_GOT32:
10250 case BFD_RELOC_386_GOTOFF:
10251 case BFD_RELOC_386_GOTPC:
10252 case BFD_RELOC_386_TLS_GD:
10253 case BFD_RELOC_386_TLS_LDM:
10254 case BFD_RELOC_386_TLS_LDO_32:
10255 case BFD_RELOC_386_TLS_IE_32:
10256 case BFD_RELOC_386_TLS_IE:
10257 case BFD_RELOC_386_TLS_GOTIE:
10258 case BFD_RELOC_386_TLS_LE_32:
10259 case BFD_RELOC_386_TLS_LE:
10260 case BFD_RELOC_386_TLS_GOTDESC:
10261 case BFD_RELOC_386_TLS_DESC_CALL:
10262 case BFD_RELOC_X86_64_TLSGD:
10263 case BFD_RELOC_X86_64_TLSLD:
10264 case BFD_RELOC_X86_64_DTPOFF32:
10265 case BFD_RELOC_X86_64_DTPOFF64:
10266 case BFD_RELOC_X86_64_GOTTPOFF:
10267 case BFD_RELOC_X86_64_TPOFF32:
10268 case BFD_RELOC_X86_64_TPOFF64:
10269 case BFD_RELOC_X86_64_GOTOFF64:
10270 case BFD_RELOC_X86_64_GOTPC32:
10271 case BFD_RELOC_X86_64_GOT64:
10272 case BFD_RELOC_X86_64_GOTPCREL64:
10273 case BFD_RELOC_X86_64_GOTPC64:
10274 case BFD_RELOC_X86_64_GOTPLT64:
10275 case BFD_RELOC_X86_64_PLTOFF64:
10276 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10277 case BFD_RELOC_X86_64_TLSDESC_CALL:
10278 case BFD_RELOC_RVA:
10279 case BFD_RELOC_VTABLE_ENTRY:
10280 case BFD_RELOC_VTABLE_INHERIT:
10282 case BFD_RELOC_32_SECREL:
10284 code = fixp->fx_r_type;
10286 case BFD_RELOC_X86_64_32S:
10287 if (!fixp->fx_pcrel)
10289 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10290 code = fixp->fx_r_type;
10294 if (fixp->fx_pcrel)
10296 switch (fixp->fx_size)
10299 as_bad_where (fixp->fx_file, fixp->fx_line,
10300 _("can not do %d byte pc-relative relocation"),
10302 code = BFD_RELOC_32_PCREL;
10304 case 1: code = BFD_RELOC_8_PCREL; break;
10305 case 2: code = BFD_RELOC_16_PCREL; break;
10306 case 4: code = BFD_RELOC_32_PCREL; break;
10308 case 8: code = BFD_RELOC_64_PCREL; break;
10314 switch (fixp->fx_size)
10317 as_bad_where (fixp->fx_file, fixp->fx_line,
10318 _("can not do %d byte relocation"),
10320 code = BFD_RELOC_32;
10322 case 1: code = BFD_RELOC_8; break;
10323 case 2: code = BFD_RELOC_16; break;
10324 case 4: code = BFD_RELOC_32; break;
10326 case 8: code = BFD_RELOC_64; break;
10333 if ((code == BFD_RELOC_32
10334 || code == BFD_RELOC_32_PCREL
10335 || code == BFD_RELOC_X86_64_32S)
10337 && fixp->fx_addsy == GOT_symbol)
10340 code = BFD_RELOC_386_GOTPC;
10342 code = BFD_RELOC_X86_64_GOTPC32;
10344 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10346 && fixp->fx_addsy == GOT_symbol)
10348 code = BFD_RELOC_X86_64_GOTPC64;
10351 rel = (arelent *) xmalloc (sizeof (arelent));
10352 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10353 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10355 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10357 if (!use_rela_relocations)
10359 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10360 vtable entry to be used in the relocation's section offset. */
10361 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10362 rel->address = fixp->fx_offset;
10363 #if defined (OBJ_COFF) && defined (TE_PE)
10364 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10365 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10370 /* Use the rela in 64bit mode. */
10373 if (disallow_64bit_reloc)
10376 case BFD_RELOC_X86_64_DTPOFF64:
10377 case BFD_RELOC_X86_64_TPOFF64:
10378 case BFD_RELOC_64_PCREL:
10379 case BFD_RELOC_X86_64_GOTOFF64:
10380 case BFD_RELOC_X86_64_GOT64:
10381 case BFD_RELOC_X86_64_GOTPCREL64:
10382 case BFD_RELOC_X86_64_GOTPC64:
10383 case BFD_RELOC_X86_64_GOTPLT64:
10384 case BFD_RELOC_X86_64_PLTOFF64:
10385 as_bad_where (fixp->fx_file, fixp->fx_line,
10386 _("cannot represent relocation type %s in x32 mode"),
10387 bfd_get_reloc_code_name (code));
10393 if (!fixp->fx_pcrel)
10394 rel->addend = fixp->fx_offset;
10398 case BFD_RELOC_X86_64_PLT32:
10399 case BFD_RELOC_X86_64_GOT32:
10400 case BFD_RELOC_X86_64_GOTPCREL:
10401 case BFD_RELOC_X86_64_TLSGD:
10402 case BFD_RELOC_X86_64_TLSLD:
10403 case BFD_RELOC_X86_64_GOTTPOFF:
10404 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10405 case BFD_RELOC_X86_64_TLSDESC_CALL:
10406 rel->addend = fixp->fx_offset - fixp->fx_size;
10409 rel->addend = (section->vma
10411 + fixp->fx_addnumber
10412 + md_pcrel_from (fixp));
10417 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10418 if (rel->howto == NULL)
10420 as_bad_where (fixp->fx_file, fixp->fx_line,
10421 _("cannot represent relocation type %s"),
10422 bfd_get_reloc_code_name (code));
10423 /* Set howto to a garbage value so that we can keep going. */
10424 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
10425 gas_assert (rel->howto != NULL);
10431 #include "tc-i386-intel.c"
10434 tc_x86_parse_to_dw2regnum (expressionS *exp)
10436 int saved_naked_reg;
10437 char saved_register_dot;
10439 saved_naked_reg = allow_naked_reg;
10440 allow_naked_reg = 1;
10441 saved_register_dot = register_chars['.'];
10442 register_chars['.'] = '.';
10443 allow_pseudo_reg = 1;
10444 expression_and_evaluate (exp);
10445 allow_pseudo_reg = 0;
10446 register_chars['.'] = saved_register_dot;
10447 allow_naked_reg = saved_naked_reg;
10449 if (exp->X_op == O_register && exp->X_add_number >= 0)
10451 if ((addressT) exp->X_add_number < i386_regtab_size)
10453 exp->X_op = O_constant;
10454 exp->X_add_number = i386_regtab[exp->X_add_number]
10455 .dw2_regnum[flag_code >> 1];
10458 exp->X_op = O_illegal;
10463 tc_x86_frame_initial_instructions (void)
10465 static unsigned int sp_regno[2];
10467 if (!sp_regno[flag_code >> 1])
10469 char *saved_input = input_line_pointer;
10470 char sp[][4] = {"esp", "rsp"};
10473 input_line_pointer = sp[flag_code >> 1];
10474 tc_x86_parse_to_dw2regnum (&exp);
10475 gas_assert (exp.X_op == O_constant);
10476 sp_regno[flag_code >> 1] = exp.X_add_number;
10477 input_line_pointer = saved_input;
10480 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10481 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
10485 x86_dwarf2_addr_size (void)
10487 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10488 if (x86_elf_abi == X86_64_X32_ABI)
10491 return bfd_arch_bits_per_address (stdoutput) / 8;
10495 i386_elf_section_type (const char *str, size_t len)
10497 if (flag_code == CODE_64BIT
10498 && len == sizeof ("unwind") - 1
10499 && strncmp (str, "unwind", 6) == 0)
10500 return SHT_X86_64_UNWIND;
10507 i386_solaris_fix_up_eh_frame (segT sec)
10509 if (flag_code == CODE_64BIT)
10510 elf_section_type (sec) = SHT_X86_64_UNWIND;
10516 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10520 exp.X_op = O_secrel;
10521 exp.X_add_symbol = symbol;
10522 exp.X_add_number = 0;
10523 emit_expr (&exp, size);
10527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10528 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10531 x86_64_section_letter (int letter, char **ptr_msg)
10533 if (flag_code == CODE_64BIT)
10536 return SHF_X86_64_LARGE;
10538 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10541 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
10546 x86_64_section_word (char *str, size_t len)
10548 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10549 return SHF_X86_64_LARGE;
10555 handle_large_common (int small ATTRIBUTE_UNUSED)
10557 if (flag_code != CODE_64BIT)
10559 s_comm_internal (0, elf_common_parse);
10560 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10564 static segT lbss_section;
10565 asection *saved_com_section_ptr = elf_com_section_ptr;
10566 asection *saved_bss_section = bss_section;
10568 if (lbss_section == NULL)
10570 flagword applicable;
10571 segT seg = now_seg;
10572 subsegT subseg = now_subseg;
10574 /* The .lbss section is for local .largecomm symbols. */
10575 lbss_section = subseg_new (".lbss", 0);
10576 applicable = bfd_applicable_section_flags (stdoutput);
10577 bfd_set_section_flags (stdoutput, lbss_section,
10578 applicable & SEC_ALLOC);
10579 seg_info (lbss_section)->bss = 1;
10581 subseg_set (seg, subseg);
10584 elf_com_section_ptr = &_bfd_elf_large_com_section;
10585 bss_section = lbss_section;
10587 s_comm_internal (0, elf_common_parse);
10589 elf_com_section_ptr = saved_com_section_ptr;
10590 bss_section = saved_bss_section;
10593 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */