2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.49 2005/12/31 14:07:59 sephe Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Xircom X3201 (www.xircom.com)
50 * Conexant LANfinity (www.conexant.com)
52 * Datasheets for the 21143 are available at developer.intel.com.
53 * Datasheets for the clone parts can be found at their respective sites.
54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
55 * The PNIC II is essentially a Macronix 98715A chip; the only difference
56 * worth noting is that its multicast hash table is only 128 bits wide
59 * Written by Bill Paul <wpaul@ee.columbia.edu>
60 * Electrical Engineering Department
61 * Columbia University, New York City
65 * The Intel 21143 is the successor to the DEC 21140. It is basically
66 * the same as the 21140 but with a few new features. The 21143 supports
67 * three kinds of media attachments:
69 * o MII port, for 10Mbps and 100Mbps support and NWAY
70 * autonegotiation provided by an external PHY.
71 * o SYM port, for symbol mode 100Mbps support.
75 * The 100Mbps SYM port and 10baseT port can be used together in
76 * combination with the internal NWAY support to create a 10/100
77 * autosensing configuration.
79 * Note that not all tulip workalikes are handled in this driver: we only
80 * deal with those which are relatively well behaved. The Winbond is
81 * handled separately due to its different register offsets and the
82 * special handling needed for its various bugs. The PNIC is handled
83 * here, but I'm not thrilled about it.
85 * All of the workalike chips use some form of MII transceiver support
86 * with the exception of the Macronix chips, which also have a SYM port.
87 * The ASIX AX88140A is also documented to have a SYM port, but all
88 * the cards I've seen use an MII transceiver, probably because the
89 * AX88140A doesn't support internal NWAY.
92 #include "opt_polling.h"
94 #include <sys/param.h>
95 #include <sys/systm.h>
96 #include <sys/sockio.h>
98 #include <sys/malloc.h>
99 #include <sys/kernel.h>
100 #include <sys/socket.h>
101 #include <sys/sysctl.h>
102 #include <sys/thread2.h>
105 #include <net/ifq_var.h>
106 #include <net/if_arp.h>
107 #include <net/ethernet.h>
108 #include <net/if_dl.h>
109 #include <net/if_media.h>
110 #include <net/if_types.h>
111 #include <net/vlan/if_vlan_var.h>
115 #include <vm/vm.h> /* for vtophys */
116 #include <vm/pmap.h> /* for vtophys */
117 #include <machine/bus_pio.h>
118 #include <machine/bus_memio.h>
119 #include <machine/bus.h>
120 #include <machine/resource.h>
122 #include <sys/rman.h>
124 #include "../mii_layer/mii.h"
125 #include "../mii_layer/miivar.h"
127 #include <bus/pci/pcireg.h>
128 #include <bus/pci/pcivar.h>
130 #define DC_USEIOSPACE
132 #include "if_dcreg.h"
134 /* "controller miibus0" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
138 * Various supported device vendors/types and their names.
140 static const struct dc_type dc_devs[] = {
141 { DC_VENDORID_DEC, DC_DEVICEID_21143,
142 "Intel 21143 10/100BaseTX" },
143 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
144 "Davicom DM9009 10/100BaseTX" },
145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
146 "Davicom DM9100 10/100BaseTX" },
147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
148 "Davicom DM9102 10/100BaseTX" },
149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
150 "Davicom DM9102A 10/100BaseTX" },
151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
152 "ADMtek AL981 10/100BaseTX" },
153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
154 "ADMtek AN985 10/100BaseTX" },
155 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
156 "ADMtek ADM9511 10/100BaseTX" },
157 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
158 "ADMtek ADM9513 10/100BaseTX" },
159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
160 "ASIX AX88140A 10/100BaseTX" },
161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
162 "ASIX AX88141 10/100BaseTX" },
163 { DC_VENDORID_MX, DC_DEVICEID_98713,
164 "Macronix 98713 10/100BaseTX" },
165 { DC_VENDORID_MX, DC_DEVICEID_98713,
166 "Macronix 98713A 10/100BaseTX" },
167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
168 "Compex RL100-TX 10/100BaseTX" },
169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
170 "Compex RL100-TX 10/100BaseTX" },
171 { DC_VENDORID_MX, DC_DEVICEID_987x5,
172 "Macronix 98715/98715A 10/100BaseTX" },
173 { DC_VENDORID_MX, DC_DEVICEID_987x5,
174 "Macronix 98715AEC-C 10/100BaseTX" },
175 { DC_VENDORID_MX, DC_DEVICEID_987x5,
176 "Macronix 98725 10/100BaseTX" },
177 { DC_VENDORID_MX, DC_DEVICEID_98727,
178 "Macronix 98727/98732 10/100BaseTX" },
179 { DC_VENDORID_LO, DC_DEVICEID_82C115,
180 "LC82C115 PNIC II 10/100BaseTX" },
181 { DC_VENDORID_LO, DC_DEVICEID_82C168,
182 "82c168 PNIC 10/100BaseTX" },
183 { DC_VENDORID_LO, DC_DEVICEID_82C168,
184 "82c169 PNIC 10/100BaseTX" },
185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
186 "Accton EN1217 10/100BaseTX" },
187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
188 "Accton EN2242 MiniPCI 10/100BaseTX" },
189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
190 "Xircom X3201 10/100BaseTX" },
191 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
192 "Conexant LANfinity MiniPCI 10/100BaseTX" },
193 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
194 "3Com OfficeConnect 10/100B" },
198 static int dc_probe (device_t);
199 static int dc_attach (device_t);
200 static int dc_detach (device_t);
201 static int dc_suspend (device_t);
202 static int dc_resume (device_t);
203 static void dc_acpi (device_t);
204 static const struct dc_type *dc_devtype (device_t);
205 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
206 static int dc_encap (struct dc_softc *, struct mbuf *,
208 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
209 static int dc_rx_resync (struct dc_softc *);
210 static void dc_rxeof (struct dc_softc *);
211 static void dc_txeof (struct dc_softc *);
212 static void dc_tick (void *);
213 static void dc_tx_underrun (struct dc_softc *);
214 static void dc_intr (void *);
215 static void dc_start (struct ifnet *);
216 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
218 #ifdef DEVICE_POLLING
219 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd,
222 static void dc_init (void *);
223 static void dc_stop (struct dc_softc *);
224 static void dc_watchdog (struct ifnet *);
225 static void dc_shutdown (device_t);
226 static int dc_ifmedia_upd (struct ifnet *);
227 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
229 static void dc_delay (struct dc_softc *);
230 static void dc_eeprom_idle (struct dc_softc *);
231 static void dc_eeprom_putbyte (struct dc_softc *, int);
232 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
233 static void dc_eeprom_getword_pnic
234 (struct dc_softc *, int, u_int16_t *);
235 static void dc_eeprom_getword_xircom
236 (struct dc_softc *, int, u_int16_t *);
237 static void dc_eeprom_width (struct dc_softc *);
238 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
241 static void dc_mii_writebit (struct dc_softc *, int);
242 static int dc_mii_readbit (struct dc_softc *);
243 static void dc_mii_sync (struct dc_softc *);
244 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
245 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
246 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
247 static int dc_miibus_readreg (device_t, int, int);
248 static int dc_miibus_writereg (device_t, int, int, int);
249 static void dc_miibus_statchg (device_t);
250 static void dc_miibus_mediainit (device_t);
252 static u_int32_t dc_crc_mask (struct dc_softc *);
253 static void dc_setcfg (struct dc_softc *, int);
254 static void dc_setfilt_21143 (struct dc_softc *);
255 static void dc_setfilt_asix (struct dc_softc *);
256 static void dc_setfilt_admtek (struct dc_softc *);
257 static void dc_setfilt_xircom (struct dc_softc *);
259 static void dc_setfilt (struct dc_softc *);
261 static void dc_reset (struct dc_softc *);
262 static int dc_list_rx_init (struct dc_softc *);
263 static int dc_list_tx_init (struct dc_softc *);
265 static void dc_read_srom (struct dc_softc *, int);
266 static void dc_parse_21143_srom (struct dc_softc *);
267 static void dc_decode_leaf_sia (struct dc_softc *,
268 struct dc_eblock_sia *);
269 static void dc_decode_leaf_mii (struct dc_softc *,
270 struct dc_eblock_mii *);
271 static void dc_decode_leaf_sym (struct dc_softc *,
272 struct dc_eblock_sym *);
273 static void dc_apply_fixup (struct dc_softc *, int);
274 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *);
277 #define DC_RES SYS_RES_IOPORT
278 #define DC_RID DC_PCI_CFBIO
280 #define DC_RES SYS_RES_MEMORY
281 #define DC_RID DC_PCI_CFBMA
284 static device_method_t dc_methods[] = {
285 /* Device interface */
286 DEVMETHOD(device_probe, dc_probe),
287 DEVMETHOD(device_attach, dc_attach),
288 DEVMETHOD(device_detach, dc_detach),
289 DEVMETHOD(device_suspend, dc_suspend),
290 DEVMETHOD(device_resume, dc_resume),
291 DEVMETHOD(device_shutdown, dc_shutdown),
294 DEVMETHOD(bus_print_child, bus_generic_print_child),
295 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
298 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
299 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
300 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
301 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
306 static driver_t dc_driver = {
309 sizeof(struct dc_softc)
312 static devclass_t dc_devclass;
315 static int dc_quick=1;
316 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
317 &dc_quick,0,"do not mdevget in dc driver");
320 DECLARE_DUMMY_MODULE(if_dc);
321 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0);
322 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
323 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
325 #define DC_SETBIT(sc, reg, x) \
326 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
328 #define DC_CLRBIT(sc, reg, x) \
329 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
331 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
332 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
335 dc_delay(struct dc_softc *sc)
339 for (idx = (300 / 33) + 1; idx > 0; idx--)
340 CSR_READ_4(sc, DC_BUSCTL);
344 dc_eeprom_width(struct dc_softc *sc)
348 /* Force EEPROM to idle state. */
351 /* Enter EEPROM access mode. */
352 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
354 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
356 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
358 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
363 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
367 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
373 for (i = 1; i <= 12; i++) {
374 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
376 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
385 /* Turn off EEPROM access mode. */
393 /* Enter EEPROM access mode. */
394 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
396 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
403 /* Turn off EEPROM access mode. */
408 dc_eeprom_idle(struct dc_softc *sc)
412 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
414 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
418 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
421 for (i = 0; i < 25; i++) {
422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
424 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
432 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
438 * Send a read command and address to the EEPROM, check for ACK.
441 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
445 d = DC_EECMD_READ >> 6;
448 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
452 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
454 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
459 * Feed in each bit and strobe the clock.
461 for (i = sc->dc_romwidth; i--;) {
462 if (addr & (1 << i)) {
463 SIO_SET(DC_SIO_EE_DATAIN);
465 SIO_CLR(DC_SIO_EE_DATAIN);
468 SIO_SET(DC_SIO_EE_CLK);
470 SIO_CLR(DC_SIO_EE_CLK);
478 * Read a word of data stored in the EEPROM at address 'addr.'
479 * The PNIC 82c168/82c169 has its own non-standard way to read
483 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
488 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
490 for (i = 0; i < DC_TIMEOUT; i++) {
492 r = CSR_READ_4(sc, DC_SIO);
493 if (!(r & DC_PN_SIOCTL_BUSY)) {
494 *dest = (u_int16_t)(r & 0xFFFF);
503 * Read a word of data stored in the EEPROM at address 'addr.'
504 * The Xircom X3201 has its own non-standard way to read
508 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
510 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
513 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
514 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff;
516 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
517 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8;
519 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
523 * Read a word of data stored in the EEPROM at address 'addr.'
526 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
531 /* Force EEPROM to idle state. */
534 /* Enter EEPROM access mode. */
535 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
537 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
539 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
541 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
545 * Send address of word we want to read.
547 dc_eeprom_putbyte(sc, addr);
550 * Start reading bits from EEPROM.
552 for (i = 0x8000; i; i >>= 1) {
553 SIO_SET(DC_SIO_EE_CLK);
555 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
558 SIO_CLR(DC_SIO_EE_CLK);
562 /* Turn off EEPROM access mode. */
571 * Read a sequence of words from the EEPROM.
574 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap)
577 u_int16_t word = 0, *ptr;
579 for (i = 0; i < cnt; i++) {
581 dc_eeprom_getword_pnic(sc, off + i, &word);
582 else if (DC_IS_XIRCOM(sc))
583 dc_eeprom_getword_xircom(sc, off + i, &word);
585 dc_eeprom_getword(sc, off + i, &word);
586 ptr = (u_int16_t *)(dest + (i * 2));
597 * The following two routines are taken from the Macronix 98713
598 * Application Notes pp.19-21.
601 * Write a bit to the MII bus.
604 dc_mii_writebit(struct dc_softc *sc, int bit)
607 CSR_WRITE_4(sc, DC_SIO,
608 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
610 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
612 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
613 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
619 * Read a bit from the MII bus.
622 dc_mii_readbit(struct dc_softc *sc)
624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
625 CSR_READ_4(sc, DC_SIO);
626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
628 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
635 * Sync the PHYs by setting data bit and strobing the clock 32 times.
638 dc_mii_sync(struct dc_softc *sc)
642 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
644 for (i = 0; i < 32; i++)
645 dc_mii_writebit(sc, 1);
651 * Clock a series of bits through the MII.
654 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
658 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
659 dc_mii_writebit(sc, bits & i);
663 * Read an PHY register through the MII.
666 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
671 * Set up frame for RX.
673 frame->mii_stdelim = DC_MII_STARTDELIM;
674 frame->mii_opcode = DC_MII_READOP;
675 frame->mii_turnaround = 0;
684 * Send command/address info.
686 dc_mii_send(sc, frame->mii_stdelim, 2);
687 dc_mii_send(sc, frame->mii_opcode, 2);
688 dc_mii_send(sc, frame->mii_phyaddr, 5);
689 dc_mii_send(sc, frame->mii_regaddr, 5);
693 dc_mii_writebit(sc, 1);
694 dc_mii_writebit(sc, 0);
698 ack = dc_mii_readbit(sc);
701 * Now try reading data bits. If the ack failed, we still
702 * need to clock through 16 cycles to keep the PHY(s) in sync.
705 for(i = 0; i < 16; i++) {
711 for (i = 0x8000; i; i >>= 1) {
713 if (dc_mii_readbit(sc))
714 frame->mii_data |= i;
720 dc_mii_writebit(sc, 0);
721 dc_mii_writebit(sc, 0);
729 * Write to a PHY register through the MII.
732 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
735 * Set up frame for TX.
738 frame->mii_stdelim = DC_MII_STARTDELIM;
739 frame->mii_opcode = DC_MII_WRITEOP;
740 frame->mii_turnaround = DC_MII_TURNAROUND;
747 dc_mii_send(sc, frame->mii_stdelim, 2);
748 dc_mii_send(sc, frame->mii_opcode, 2);
749 dc_mii_send(sc, frame->mii_phyaddr, 5);
750 dc_mii_send(sc, frame->mii_regaddr, 5);
751 dc_mii_send(sc, frame->mii_turnaround, 2);
752 dc_mii_send(sc, frame->mii_data, 16);
755 dc_mii_writebit(sc, 0);
756 dc_mii_writebit(sc, 0);
762 dc_miibus_readreg(device_t dev, int phy, int reg)
764 struct dc_mii_frame frame;
766 int i, rval, phy_reg = 0;
768 sc = device_get_softc(dev);
769 bzero((char *)&frame, sizeof(frame));
772 * Note: both the AL981 and AN985 have internal PHYs,
773 * however the AL981 provides direct access to the PHY
774 * registers while the AN985 uses a serial MII interface.
775 * The AN985's MII interface is also buggy in that you
776 * can read from any MII address (0 to 31), but only address 1
777 * behaves normally. To deal with both cases, we pretend
778 * that the PHY is at MII address 1.
780 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
784 * Note: the ukphy probes of the RS7112 report a PHY at
785 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
786 * so we only respond to correct one.
788 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
791 if (sc->dc_pmode != DC_PMODE_MII) {
792 if (phy == (MII_NPHY - 1)) {
796 * Fake something to make the probe
797 * code think there's a PHY here.
799 return(BMSR_MEDIAMASK);
803 return(DC_VENDORID_LO);
804 return(DC_VENDORID_DEC);
808 return(DC_DEVICEID_82C168);
809 return(DC_DEVICEID_21143);
819 if (DC_IS_PNIC(sc)) {
820 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
821 (phy << 23) | (reg << 18));
822 for (i = 0; i < DC_TIMEOUT; i++) {
824 rval = CSR_READ_4(sc, DC_PN_MII);
825 if (!(rval & DC_PN_MII_BUSY)) {
827 return(rval == 0xFFFF ? 0 : rval);
833 if (DC_IS_COMET(sc)) {
836 phy_reg = DC_AL_BMCR;
839 phy_reg = DC_AL_BMSR;
842 phy_reg = DC_AL_VENID;
845 phy_reg = DC_AL_DEVID;
848 phy_reg = DC_AL_ANAR;
851 phy_reg = DC_AL_LPAR;
854 phy_reg = DC_AL_ANER;
857 if_printf(&sc->arpcom.ac_if,
858 "phy_read: bad phy register %x\n", reg);
863 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
870 frame.mii_phyaddr = phy;
871 frame.mii_regaddr = reg;
872 if (sc->dc_type == DC_TYPE_98713) {
873 phy_reg = CSR_READ_4(sc, DC_NETCFG);
874 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
876 dc_mii_readreg(sc, &frame);
877 if (sc->dc_type == DC_TYPE_98713)
878 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
880 return(frame.mii_data);
884 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
887 struct dc_mii_frame frame;
890 sc = device_get_softc(dev);
891 bzero((char *)&frame, sizeof(frame));
893 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
896 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
899 if (DC_IS_PNIC(sc)) {
900 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
901 (phy << 23) | (reg << 10) | data);
902 for (i = 0; i < DC_TIMEOUT; i++) {
903 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
909 if (DC_IS_COMET(sc)) {
912 phy_reg = DC_AL_BMCR;
915 phy_reg = DC_AL_BMSR;
918 phy_reg = DC_AL_VENID;
921 phy_reg = DC_AL_DEVID;
924 phy_reg = DC_AL_ANAR;
927 phy_reg = DC_AL_LPAR;
930 phy_reg = DC_AL_ANER;
933 if_printf(&sc->arpcom.ac_if,
934 "phy_write: bad phy register %x\n", reg);
939 CSR_WRITE_4(sc, phy_reg, data);
943 frame.mii_phyaddr = phy;
944 frame.mii_regaddr = reg;
945 frame.mii_data = data;
947 if (sc->dc_type == DC_TYPE_98713) {
948 phy_reg = CSR_READ_4(sc, DC_NETCFG);
949 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
951 dc_mii_writereg(sc, &frame);
952 if (sc->dc_type == DC_TYPE_98713)
953 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
959 dc_miibus_statchg(device_t dev)
962 struct mii_data *mii;
965 sc = device_get_softc(dev);
966 if (DC_IS_ADMTEK(sc))
969 mii = device_get_softc(sc->dc_miibus);
970 ifm = &mii->mii_media;
971 if (DC_IS_DAVICOM(sc) &&
972 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
973 dc_setcfg(sc, ifm->ifm_media);
974 sc->dc_if_media = ifm->ifm_media;
976 dc_setcfg(sc, mii->mii_media_active);
977 sc->dc_if_media = mii->mii_media_active;
984 * Special support for DM9102A cards with HomePNA PHYs. Note:
985 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
986 * to be impossible to talk to the management interface of the DM9801
987 * PHY (its MDIO pin is not connected to anything). Consequently,
988 * the driver has to just 'know' about the additional mode and deal
989 * with it itself. *sigh*
992 dc_miibus_mediainit(device_t dev)
995 struct mii_data *mii;
999 rev = pci_get_revid(dev);
1001 sc = device_get_softc(dev);
1002 mii = device_get_softc(sc->dc_miibus);
1003 ifm = &mii->mii_media;
1005 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1006 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1011 #define DC_BITS_512 9
1012 #define DC_BITS_128 7
1013 #define DC_BITS_64 6
1016 dc_crc_mask(struct dc_softc *sc)
1019 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1020 * chips is only 128 bits wide.
1022 if (sc->dc_flags & DC_128BIT_HASH)
1023 return ((1 << DC_BITS_128) - 1);
1025 /* The hash table on the MX98715BEC is only 64 bits wide. */
1026 if (sc->dc_flags & DC_64BIT_HASH)
1027 return ((1 << DC_BITS_64) - 1);
1029 return ((1 << DC_BITS_512) - 1);
1033 * 21143-style RX filter setup routine. Filter programming is done by
1034 * downloading a special setup frame into the TX engine. 21143, Macronix,
1035 * PNIC, PNIC II and Davicom chips are programmed this way.
1037 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1038 * address (our node address) and a 512-bit hash filter for multicast
1039 * frames. We also sneak the broadcast address into the hash filter since
1043 dc_setfilt_21143(struct dc_softc *sc)
1045 struct dc_desc *sframe;
1046 u_int32_t h, crc_mask, *sp;
1047 struct ifmultiaddr *ifma;
1051 ifp = &sc->arpcom.ac_if;
1053 i = sc->dc_cdata.dc_tx_prod;
1054 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1055 sc->dc_cdata.dc_tx_cnt++;
1056 sframe = &sc->dc_ldata->dc_tx_list[i];
1057 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1058 bzero((char *)sp, DC_SFRAME_LEN);
1060 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1061 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1062 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1064 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1066 /* If we want promiscuous mode, set the allframes bit. */
1067 if (ifp->if_flags & IFF_PROMISC)
1068 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1070 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1072 if (ifp->if_flags & IFF_ALLMULTI)
1073 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1075 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1077 crc_mask = dc_crc_mask(sc);
1078 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1079 if (ifma->ifma_addr->sa_family != AF_LINK)
1082 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1083 ETHER_ADDR_LEN) & crc_mask;
1084 sp[h >> 4] |= 1 << (h & 0xF);
1087 if (ifp->if_flags & IFF_BROADCAST) {
1088 h = ether_crc32_le(ifp->if_broadcastaddr,
1089 ETHER_ADDR_LEN) & crc_mask;
1090 sp[h >> 4] |= 1 << (h & 0xF);
1093 /* Set our MAC address */
1094 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1095 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1096 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1098 sframe->dc_status = DC_TXSTAT_OWN;
1099 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1102 * The PNIC takes an exceedingly long time to process its
1103 * setup frame; wait 10ms after posting the setup frame
1104 * before proceeding, just so it has time to swallow its
1115 dc_setfilt_admtek(struct dc_softc *sc)
1120 u_int32_t hashes[2] = { 0, 0 };
1121 struct ifmultiaddr *ifma;
1123 ifp = &sc->arpcom.ac_if;
1125 /* Init our MAC address */
1126 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1127 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1129 /* If we want promiscuous mode, set the allframes bit. */
1130 if (ifp->if_flags & IFF_PROMISC)
1131 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1133 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1135 if (ifp->if_flags & IFF_ALLMULTI)
1136 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1138 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1140 /* first, zot all the existing hash bits */
1141 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1142 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1145 * If we're already in promisc or allmulti mode, we
1146 * don't have to bother programming the multicast filter.
1148 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1151 /* now program new ones */
1152 if (DC_IS_CENTAUR(sc))
1153 crc_mask = dc_crc_mask(sc);
1156 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1157 if (ifma->ifma_addr->sa_family != AF_LINK)
1159 if (DC_IS_CENTAUR(sc)) {
1161 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1162 ETHER_ADDR_LEN) & crc_mask;
1165 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1167 h = (h >> 26) & crc_mask;
1170 hashes[0] |= (1 << h);
1172 hashes[1] |= (1 << (h - 32));
1175 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1176 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1182 dc_setfilt_asix(struct dc_softc *sc)
1186 u_int32_t hashes[2] = { 0, 0 };
1187 struct ifmultiaddr *ifma;
1189 ifp = &sc->arpcom.ac_if;
1191 /* Init our MAC address */
1192 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1193 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1194 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1195 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1196 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1197 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1199 /* If we want promiscuous mode, set the allframes bit. */
1200 if (ifp->if_flags & IFF_PROMISC)
1201 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1203 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1205 if (ifp->if_flags & IFF_ALLMULTI)
1206 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1208 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1211 * The ASIX chip has a special bit to enable reception
1212 * of broadcast frames.
1214 if (ifp->if_flags & IFF_BROADCAST)
1215 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1217 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1219 /* first, zot all the existing hash bits */
1220 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1221 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1226 * If we're already in promisc or allmulti mode, we
1227 * don't have to bother programming the multicast filter.
1229 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1232 /* now program new ones */
1233 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1234 if (ifma->ifma_addr->sa_family != AF_LINK)
1237 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1239 h = (h >> 26) & 0x3f;
1241 hashes[0] |= (1 << h);
1243 hashes[1] |= (1 << (h - 32));
1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1255 dc_setfilt_xircom(struct dc_softc *sc)
1257 struct dc_desc *sframe;
1259 struct ifmultiaddr *ifma;
1263 ifp = &sc->arpcom.ac_if;
1264 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1266 i = sc->dc_cdata.dc_tx_prod;
1267 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1268 sc->dc_cdata.dc_tx_cnt++;
1269 sframe = &sc->dc_ldata->dc_tx_list[i];
1270 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1271 bzero(sp, DC_SFRAME_LEN);
1273 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1274 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1275 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1277 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1279 /* If we want promiscuous mode, set the allframes bit. */
1280 if (ifp->if_flags & IFF_PROMISC)
1281 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1283 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1285 if (ifp->if_flags & IFF_ALLMULTI)
1286 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1288 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1290 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1291 if (ifma->ifma_addr->sa_family != AF_LINK)
1293 h = dc_mchash_xircom(sc,
1294 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1295 sp[h >> 4] |= 1 << (h & 0xF);
1298 if (ifp->if_flags & IFF_BROADCAST) {
1299 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr);
1300 sp[h >> 4] |= 1 << (h & 0xF);
1303 /* Set our MAC address */
1304 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1305 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1306 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1308 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1309 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1310 ifp->if_flags |= IFF_RUNNING;
1311 sframe->dc_status = DC_TXSTAT_OWN;
1312 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1323 dc_setfilt(struct dc_softc *sc)
1325 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1326 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1327 dc_setfilt_21143(sc);
1330 dc_setfilt_asix(sc);
1332 if (DC_IS_ADMTEK(sc))
1333 dc_setfilt_admtek(sc);
1335 if (DC_IS_XIRCOM(sc))
1336 dc_setfilt_xircom(sc);
1340 * In order to fiddle with the
1341 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1342 * first have to put the transmit and/or receive logic in the idle state.
1345 dc_setcfg(struct dc_softc *sc, int media)
1350 if (IFM_SUBTYPE(media) == IFM_NONE)
1353 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1355 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1357 for (i = 0; i < DC_TIMEOUT; i++) {
1358 isr = CSR_READ_4(sc, DC_ISR);
1359 if ((isr & DC_ISR_TX_IDLE) &&
1360 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1361 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1366 if (i == DC_TIMEOUT) {
1367 if_printf(&sc->arpcom.ac_if,
1368 "failed to force tx and rx to idle state\n");
1372 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1373 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1374 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1375 if (sc->dc_pmode == DC_PMODE_MII) {
1378 if (DC_IS_INTEL(sc)) {
1379 /* there's a write enable bit here that reads as 1 */
1380 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1381 watchdogreg &= ~DC_WDOG_CTLWREN;
1382 watchdogreg |= DC_WDOG_JABBERDIS;
1383 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1385 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1387 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1388 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1389 if (sc->dc_type == DC_TYPE_98713)
1390 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1391 DC_NETCFG_SCRAMBLER));
1392 if (!DC_IS_DAVICOM(sc))
1393 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1394 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1395 if (DC_IS_INTEL(sc))
1396 dc_apply_fixup(sc, IFM_AUTO);
1398 if (DC_IS_PNIC(sc)) {
1399 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1400 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1401 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1404 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1406 if (DC_IS_INTEL(sc))
1408 (media & IFM_GMASK) == IFM_FDX ?
1409 IFM_100_TX|IFM_FDX : IFM_100_TX);
1413 if (IFM_SUBTYPE(media) == IFM_10_T) {
1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1415 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1416 if (sc->dc_pmode == DC_PMODE_MII) {
1419 /* there's a write enable bit here that reads as 1 */
1420 if (DC_IS_INTEL(sc)) {
1421 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1422 watchdogreg &= ~DC_WDOG_CTLWREN;
1423 watchdogreg |= DC_WDOG_JABBERDIS;
1424 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1426 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1428 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1429 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1430 if (sc->dc_type == DC_TYPE_98713)
1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1432 if (!DC_IS_DAVICOM(sc))
1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1434 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1435 if (DC_IS_INTEL(sc))
1436 dc_apply_fixup(sc, IFM_AUTO);
1438 if (DC_IS_PNIC(sc)) {
1439 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1440 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1441 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1443 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1445 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1446 if (DC_IS_INTEL(sc)) {
1447 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1448 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1449 if ((media & IFM_GMASK) == IFM_FDX)
1450 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1452 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1453 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1454 DC_CLRBIT(sc, DC_10BTCTRL,
1455 DC_TCTL_AUTONEGENBL);
1457 (media & IFM_GMASK) == IFM_FDX ?
1458 IFM_10_T|IFM_FDX : IFM_10_T);
1465 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1466 * PHY and we want HomePNA mode, set the portsel bit to turn
1467 * on the external MII port.
1469 if (DC_IS_DAVICOM(sc)) {
1470 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1471 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1478 if ((media & IFM_GMASK) == IFM_FDX) {
1479 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1480 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1481 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1483 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1484 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1485 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1495 dc_reset(struct dc_softc *sc)
1499 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1501 for (i = 0; i < DC_TIMEOUT; i++) {
1503 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1507 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) ||
1508 DC_IS_CONEXANT(sc)) {
1510 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1514 if (i == DC_TIMEOUT)
1515 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1517 /* Wait a little while for the chip to get its brains in order. */
1520 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1521 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1522 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1525 * Bring the SIA out of reset. In some cases, it looks
1526 * like failing to unreset the SIA soon enough gets it
1527 * into a state where it will never come out of reset
1528 * until we reset the whole chip again.
1530 if (DC_IS_INTEL(sc)) {
1531 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1532 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1533 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1539 static const struct dc_type *
1540 dc_devtype(device_t dev)
1542 const struct dc_type *t;
1547 while(t->dc_name != NULL) {
1548 if ((pci_get_vendor(dev) == t->dc_vid) &&
1549 (pci_get_device(dev) == t->dc_did)) {
1550 /* Check the PCI revision */
1551 rev = pci_get_revid(dev);
1552 if (t->dc_did == DC_DEVICEID_98713 &&
1553 rev >= DC_REVISION_98713A)
1555 if (t->dc_did == DC_DEVICEID_98713_CP &&
1556 rev >= DC_REVISION_98713A)
1558 if (t->dc_did == DC_DEVICEID_987x5 &&
1559 rev >= DC_REVISION_98715AEC_C)
1561 if (t->dc_did == DC_DEVICEID_987x5 &&
1562 rev >= DC_REVISION_98725)
1564 if (t->dc_did == DC_DEVICEID_AX88140A &&
1565 rev >= DC_REVISION_88141)
1567 if (t->dc_did == DC_DEVICEID_82C168 &&
1568 rev >= DC_REVISION_82C169)
1570 if (t->dc_did == DC_DEVICEID_DM9102 &&
1571 rev >= DC_REVISION_DM9102A)
1582 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1583 * IDs against our list and return a device name if we find a match.
1584 * We do a little bit of extra work to identify the exact type of
1585 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1586 * but different revision IDs. The same is true for 98715/98715A
1587 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1588 * cases, the exact chip revision affects driver behavior.
1591 dc_probe(device_t dev)
1593 const struct dc_type *t;
1595 t = dc_devtype(dev);
1597 struct dc_softc *sc = device_get_softc(dev);
1599 /* Need this info to decide on a chip type. */
1601 device_set_desc(dev, t->dc_name);
1609 dc_acpi(device_t dev)
1611 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1612 uint32_t iobase, membase, irq;
1613 struct dc_softc *sc;
1615 /* Save important PCI config data. */
1616 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1617 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1618 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1620 sc = device_get_softc(dev);
1621 /* Reset the power state. */
1622 if_printf(&sc->arpcom.ac_if,
1623 "chip is in D%d power mode "
1624 "-- setting to D0\n", pci_get_powerstate(dev));
1625 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1627 /* Restore PCI config data. */
1628 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1629 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1630 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1635 dc_apply_fixup(struct dc_softc *sc, int media)
1637 struct dc_mediainfo *m;
1645 if (m->dc_media == media)
1653 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1654 reg = (p[0] | (p[1] << 8)) << 16;
1655 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1658 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1659 reg = (p[0] | (p[1] << 8)) << 16;
1660 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1667 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1669 struct dc_mediainfo *m;
1671 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1672 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){
1673 case DC_SIA_CODE_10BT:
1674 m->dc_media = IFM_10_T;
1677 case DC_SIA_CODE_10BT_FDX:
1678 m->dc_media = IFM_10_T|IFM_FDX;
1681 case DC_SIA_CODE_10B2:
1682 m->dc_media = IFM_10_2;
1685 case DC_SIA_CODE_10B5:
1686 m->dc_media = IFM_10_5;
1689 if (l->dc_sia_code & DC_SIA_CODE_EXT){
1692 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1696 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1699 m->dc_next = sc->dc_mi;
1702 sc->dc_pmode = DC_PMODE_SIA;
1708 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1710 struct dc_mediainfo *m;
1712 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1713 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1714 m->dc_media = IFM_100_TX;
1716 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1717 m->dc_media = IFM_100_TX|IFM_FDX;
1720 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1722 m->dc_next = sc->dc_mi;
1725 sc->dc_pmode = DC_PMODE_SYM;
1731 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1734 struct dc_mediainfo *m;
1736 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1737 /* We abuse IFM_AUTO to represent MII. */
1738 m->dc_media = IFM_AUTO;
1739 m->dc_gp_len = l->dc_gpr_len;
1742 p += sizeof(struct dc_eblock_mii);
1744 p += 2 * l->dc_gpr_len;
1745 m->dc_reset_len = *p;
1747 m->dc_reset_ptr = p;
1749 m->dc_next = sc->dc_mi;
1756 dc_read_srom(struct dc_softc *sc, int bits)
1761 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1762 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1766 dc_parse_21143_srom(struct dc_softc *sc)
1768 struct dc_leaf_hdr *lhdr;
1769 struct dc_eblock_hdr *hdr;
1775 loff = sc->dc_srom[27];
1776 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1779 ptr += sizeof(struct dc_leaf_hdr) - 1;
1781 * Look if we got a MII media block.
1783 for (i = 0; i < lhdr->dc_mcnt; i++) {
1784 hdr = (struct dc_eblock_hdr *)ptr;
1785 if (hdr->dc_type == DC_EBLOCK_MII)
1788 ptr += (hdr->dc_len & 0x7F);
1793 * Do the same thing again. Only use SIA and SYM media
1794 * blocks if no MII media block is available.
1797 ptr += sizeof(struct dc_leaf_hdr) - 1;
1798 for (i = 0; i < lhdr->dc_mcnt; i++) {
1799 hdr = (struct dc_eblock_hdr *)ptr;
1800 switch(hdr->dc_type) {
1802 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1806 dc_decode_leaf_sia(sc,
1807 (struct dc_eblock_sia *)hdr);
1811 dc_decode_leaf_sym(sc,
1812 (struct dc_eblock_sym *)hdr);
1815 /* Don't care. Yet. */
1818 ptr += (hdr->dc_len & 0x7F);
1826 * Attach the interface. Allocate softc structures, do ifmedia
1827 * setup and ethernet/BPF attach.
1830 dc_attach(device_t dev)
1833 u_char eaddr[ETHER_ADDR_LEN];
1835 struct dc_softc *sc;
1838 int error = 0, rid, mac_offset;
1841 sc = device_get_softc(dev);
1842 callout_init(&sc->dc_stat_timer);
1844 ifp = &sc->arpcom.ac_if;
1845 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1848 * Handle power management nonsense.
1853 * Map control/status registers.
1855 pci_enable_busmaster(dev);
1858 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1860 if (sc->dc_res == NULL) {
1861 device_printf(dev, "couldn't map ports/memory\n");
1866 sc->dc_btag = rman_get_bustag(sc->dc_res);
1867 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1869 /* Allocate interrupt */
1871 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1872 RF_SHAREABLE | RF_ACTIVE);
1874 if (sc->dc_irq == NULL) {
1875 device_printf(dev, "couldn't map interrupt\n");
1880 revision = pci_get_revid(dev);
1882 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1883 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1884 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1885 dc_eeprom_width(sc);
1887 switch(sc->dc_info->dc_did) {
1888 case DC_DEVICEID_21143:
1889 sc->dc_type = DC_TYPE_21143;
1890 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1891 sc->dc_flags |= DC_REDUCED_MII_POLL;
1892 /* Save EEPROM contents so we can parse them later. */
1893 dc_read_srom(sc, sc->dc_romwidth);
1895 case DC_DEVICEID_DM9009:
1896 case DC_DEVICEID_DM9100:
1897 case DC_DEVICEID_DM9102:
1898 sc->dc_type = DC_TYPE_DM9102;
1899 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1900 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1901 sc->dc_flags |= DC_TX_ALIGN;
1902 sc->dc_pmode = DC_PMODE_MII;
1903 /* Increase the latency timer value. */
1904 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1905 command &= 0xFFFF00FF;
1906 command |= 0x00008000;
1907 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1909 case DC_DEVICEID_AL981:
1910 sc->dc_type = DC_TYPE_AL981;
1911 sc->dc_flags |= DC_TX_USE_TX_INTR;
1912 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1913 sc->dc_pmode = DC_PMODE_MII;
1914 dc_read_srom(sc, sc->dc_romwidth);
1916 case DC_DEVICEID_AN985:
1917 case DC_DEVICEID_ADM9511:
1918 case DC_DEVICEID_ADM9513:
1919 case DC_DEVICEID_EN2242:
1920 case DC_DEVICEID_3CSOHOB:
1921 sc->dc_type = DC_TYPE_AN985;
1922 sc->dc_flags |= DC_64BIT_HASH;
1923 sc->dc_flags |= DC_TX_USE_TX_INTR;
1924 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1925 sc->dc_pmode = DC_PMODE_MII;
1927 case DC_DEVICEID_98713:
1928 case DC_DEVICEID_98713_CP:
1929 if (revision < DC_REVISION_98713A) {
1930 sc->dc_type = DC_TYPE_98713;
1932 if (revision >= DC_REVISION_98713A) {
1933 sc->dc_type = DC_TYPE_98713A;
1934 sc->dc_flags |= DC_21143_NWAY;
1936 sc->dc_flags |= DC_REDUCED_MII_POLL;
1937 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1939 case DC_DEVICEID_987x5:
1940 case DC_DEVICEID_EN1217:
1942 * Macronix MX98715AEC-C/D/E parts have only a
1943 * 128-bit hash table. We need to deal with these
1944 * in the same manner as the PNIC II so that we
1945 * get the right number of bits out of the
1948 if (revision >= DC_REVISION_98715AEC_C &&
1949 revision < DC_REVISION_98725)
1950 sc->dc_flags |= DC_128BIT_HASH;
1951 sc->dc_type = DC_TYPE_987x5;
1952 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1953 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1955 case DC_DEVICEID_98727:
1956 sc->dc_type = DC_TYPE_987x5;
1957 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1958 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1960 case DC_DEVICEID_82C115:
1961 sc->dc_type = DC_TYPE_PNICII;
1962 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1963 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1965 case DC_DEVICEID_82C168:
1966 sc->dc_type = DC_TYPE_PNIC;
1967 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1968 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1969 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1970 if (revision < DC_REVISION_82C169)
1971 sc->dc_pmode = DC_PMODE_SYM;
1973 case DC_DEVICEID_AX88140A:
1974 sc->dc_type = DC_TYPE_ASIX;
1975 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1976 sc->dc_flags |= DC_REDUCED_MII_POLL;
1977 sc->dc_pmode = DC_PMODE_MII;
1979 case DC_DEVICEID_RS7112:
1980 sc->dc_type = DC_TYPE_CONEXANT;
1981 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1982 sc->dc_flags |= DC_REDUCED_MII_POLL;
1983 sc->dc_pmode = DC_PMODE_MII;
1984 dc_read_srom(sc, sc->dc_romwidth);
1986 case DC_DEVICEID_X3201:
1987 sc->dc_type = DC_TYPE_XIRCOM;
1988 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1991 * We don't actually need to coalesce, but we're doing
1992 * it to obtain a double word aligned buffer.
1993 * The DC_TX_COALESCE flag is required.
1995 sc->dc_pmode = DC_PMODE_MII;
1998 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
2002 /* Save the cache line size. */
2003 if (DC_IS_DAVICOM(sc))
2004 sc->dc_cachesize = 0;
2006 sc->dc_cachesize = pci_read_config(dev,
2007 DC_PCI_CFLT, 4) & 0xFF;
2009 /* Reset the adapter. */
2012 /* Take 21143 out of snooze mode */
2013 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2014 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2015 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2016 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2020 * Try to learn something about the supported media.
2021 * We know that ASIX and ADMtek and Davicom devices
2022 * will *always* be using MII media, so that's a no-brainer.
2023 * The tricky ones are the Macronix/PNIC II and the
2026 if (DC_IS_INTEL(sc))
2027 dc_parse_21143_srom(sc);
2028 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2029 if (sc->dc_type == DC_TYPE_98713)
2030 sc->dc_pmode = DC_PMODE_MII;
2032 sc->dc_pmode = DC_PMODE_SYM;
2033 } else if (!sc->dc_pmode)
2034 sc->dc_pmode = DC_PMODE_MII;
2037 * Get station address from the EEPROM.
2039 switch(sc->dc_type) {
2041 case DC_TYPE_98713A:
2043 case DC_TYPE_PNICII:
2044 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2045 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2046 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2049 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2051 case DC_TYPE_DM9102:
2054 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2058 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);
2059 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);
2061 case DC_TYPE_CONEXANT:
2062 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2064 case DC_TYPE_XIRCOM:
2065 /* The MAC comes from the CIS */
2066 mac = pci_get_ether(dev);
2068 device_printf(dev, "No station address in CIS!\n");
2071 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2074 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2078 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2079 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
2081 if (sc->dc_ldata == NULL) {
2082 device_printf(dev, "no memory for list buffers!\n");
2087 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2090 ifp->if_mtu = ETHERMTU;
2091 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2092 ifp->if_ioctl = dc_ioctl;
2093 ifp->if_start = dc_start;
2094 #ifdef DEVICE_POLLING
2095 ifp->if_poll = dc_poll;
2097 ifp->if_watchdog = dc_watchdog;
2098 ifp->if_init = dc_init;
2099 ifp->if_baudrate = 10000000;
2100 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2101 ifq_set_ready(&ifp->if_snd);
2104 * Do MII setup. If this is a 21143, check for a PHY on the
2105 * MII bus after applying any necessary fixups to twiddle the
2106 * GPIO bits. If we don't end up finding a PHY, restore the
2107 * old selection (SIA only or SIA/SYM) and attach the dcphy
2110 if (DC_IS_INTEL(sc)) {
2111 dc_apply_fixup(sc, IFM_AUTO);
2113 sc->dc_pmode = DC_PMODE_MII;
2117 * Setup General Purpose port mode and data so the tulip can talk
2118 * to the MII. This needs to be done before mii_phy_probe so that
2119 * we can actually see them.
2121 if (DC_IS_XIRCOM(sc)) {
2122 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2123 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2125 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2126 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2130 error = mii_phy_probe(dev, &sc->dc_miibus,
2131 dc_ifmedia_upd, dc_ifmedia_sts);
2133 if (error && DC_IS_INTEL(sc)) {
2135 if (sc->dc_pmode != DC_PMODE_SIA)
2136 sc->dc_pmode = DC_PMODE_SYM;
2137 sc->dc_flags |= DC_21143_NWAY;
2138 mii_phy_probe(dev, &sc->dc_miibus,
2139 dc_ifmedia_upd, dc_ifmedia_sts);
2141 * For non-MII cards, we need to have the 21143
2142 * drive the LEDs. Except there are some systems
2143 * like the NEC VersaPro NoteBook PC which have no
2144 * LEDs, and twiddling these bits has adverse effects
2145 * on them. (I.e. you suddenly can't get a link.)
2147 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2148 sc->dc_flags |= DC_TULIP_LEDS;
2153 device_printf(dev, "MII without any PHY!\n");
2159 * Call MI attach routine.
2161 ether_ifattach(ifp, eaddr, NULL);
2163 if (DC_IS_ADMTEK(sc)) {
2165 * Set automatic TX underrun recovery for the ADMtek chips
2167 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2171 * Tell the upper layer(s) we support long frames.
2173 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2175 error = bus_setup_intr(dev, sc->dc_irq, INTR_NETSAFE,
2176 dc_intr, sc, &sc->dc_intrhand,
2177 ifp->if_serializer);
2179 ether_ifdetach(ifp);
2180 device_printf(dev, "couldn't set up irq\n");
2192 dc_detach(device_t dev)
2194 struct dc_softc *sc = device_get_softc(dev);
2195 struct ifnet *ifp = &sc->arpcom.ac_if;
2196 struct dc_mediainfo *m;
2198 if (device_is_attached(dev)) {
2199 lwkt_serialize_enter(ifp->if_serializer);
2201 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2202 lwkt_serialize_exit(ifp->if_serializer);
2204 ether_ifdetach(ifp);
2208 device_delete_child(dev, sc->dc_miibus);
2209 bus_generic_detach(dev);
2212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2214 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2217 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2218 if (sc->dc_pnic_rx_buf != NULL)
2219 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2221 while (sc->dc_mi != NULL) {
2222 m = sc->dc_mi->dc_next;
2223 free(sc->dc_mi, M_DEVBUF);
2228 free(sc->dc_srom, M_DEVBUF);
2234 * Initialize the transmit descriptors.
2237 dc_list_tx_init(struct dc_softc *sc)
2239 struct dc_chain_data *cd;
2240 struct dc_list_data *ld;
2245 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2246 if (i == (DC_TX_LIST_CNT - 1)) {
2247 ld->dc_tx_list[i].dc_next =
2248 vtophys(&ld->dc_tx_list[0]);
2250 ld->dc_tx_list[i].dc_next =
2251 vtophys(&ld->dc_tx_list[i + 1]);
2253 cd->dc_tx_chain[i] = NULL;
2254 ld->dc_tx_list[i].dc_data = 0;
2255 ld->dc_tx_list[i].dc_ctl = 0;
2258 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2265 * Initialize the RX descriptors and allocate mbufs for them. Note that
2266 * we arrange the descriptors in a closed ring, so that the last descriptor
2267 * points back to the first.
2270 dc_list_rx_init(struct dc_softc *sc)
2272 struct dc_chain_data *cd;
2273 struct dc_list_data *ld;
2279 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2280 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2282 if (i == (DC_RX_LIST_CNT - 1)) {
2283 ld->dc_rx_list[i].dc_next =
2284 vtophys(&ld->dc_rx_list[0]);
2286 ld->dc_rx_list[i].dc_next =
2287 vtophys(&ld->dc_rx_list[i + 1]);
2297 * Initialize an RX descriptor and attach an MBUF cluster.
2300 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
2302 struct mbuf *m_new = NULL;
2305 c = &sc->dc_ldata->dc_rx_list[i];
2308 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2311 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2314 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2315 m_new->m_data = m_new->m_ext.ext_buf;
2318 m_adj(m_new, sizeof(u_int64_t));
2321 * If this is a PNIC chip, zero the buffer. This is part
2322 * of the workaround for the receive bug in the 82c168 and
2325 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2326 bzero((char *)mtod(m_new, char *), m_new->m_len);
2328 sc->dc_cdata.dc_rx_chain[i] = m_new;
2329 c->dc_data = vtophys(mtod(m_new, caddr_t));
2330 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2331 c->dc_status = DC_RXSTAT_OWN;
2338 * The PNIC chip has a terrible bug in it that manifests itself during
2339 * periods of heavy activity. The exact mode of failure if difficult to
2340 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2341 * will happen on slow machines. The bug is that sometimes instead of
2342 * uploading one complete frame during reception, it uploads what looks
2343 * like the entire contents of its FIFO memory. The frame we want is at
2344 * the end of the whole mess, but we never know exactly how much data has
2345 * been uploaded, so salvaging the frame is hard.
2347 * There is only one way to do it reliably, and it's disgusting.
2348 * Here's what we know:
2350 * - We know there will always be somewhere between one and three extra
2351 * descriptors uploaded.
2353 * - We know the desired received frame will always be at the end of the
2354 * total data upload.
2356 * - We know the size of the desired received frame because it will be
2357 * provided in the length field of the status word in the last descriptor.
2359 * Here's what we do:
2361 * - When we allocate buffers for the receive ring, we bzero() them.
2362 * This means that we know that the buffer contents should be all
2363 * zeros, except for data uploaded by the chip.
2365 * - We also force the PNIC chip to upload frames that include the
2366 * ethernet CRC at the end.
2368 * - We gather all of the bogus frame data into a single buffer.
2370 * - We then position a pointer at the end of this buffer and scan
2371 * backwards until we encounter the first non-zero byte of data.
2372 * This is the end of the received frame. We know we will encounter
2373 * some data at the end of the frame because the CRC will always be
2374 * there, so even if the sender transmits a packet of all zeros,
2375 * we won't be fooled.
2377 * - We know the size of the actual received frame, so we subtract
2378 * that value from the current pointer location. This brings us
2379 * to the start of the actual received packet.
2381 * - We copy this into an mbuf and pass it on, along with the actual
2384 * The performance hit is tremendous, but it beats dropping frames all
2388 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2390 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2392 struct dc_desc *cur_rx;
2393 struct dc_desc *c = NULL;
2394 struct mbuf *m = NULL;
2397 u_int32_t rxstat = 0;
2399 i = sc->dc_pnic_rx_bug_save;
2400 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2401 ptr = sc->dc_pnic_rx_buf;
2402 bzero(ptr, DC_RXLEN * 5);
2404 /* Copy all the bytes from the bogus buffers. */
2406 c = &sc->dc_ldata->dc_rx_list[i];
2407 rxstat = c->dc_status;
2408 m = sc->dc_cdata.dc_rx_chain[i];
2409 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2411 /* If this is the last buffer, break out. */
2412 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2414 dc_newbuf(sc, i, m);
2415 DC_INC(i, DC_RX_LIST_CNT);
2418 /* Find the length of the actual receive frame. */
2419 total_len = DC_RXBYTES(rxstat);
2421 /* Scan backwards until we hit a non-zero byte. */
2426 if ((uintptr_t)(ptr) & 0x3)
2429 /* Now find the start of the frame. */
2431 if (ptr < sc->dc_pnic_rx_buf)
2432 ptr = sc->dc_pnic_rx_buf;
2435 * Now copy the salvaged frame to the last mbuf and fake up
2436 * the status word to make it look like a successful
2439 dc_newbuf(sc, i, m);
2440 bcopy(ptr, mtod(m, char *), total_len);
2441 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2447 * This routine searches the RX ring for dirty descriptors in the
2448 * event that the rxeof routine falls out of sync with the chip's
2449 * current descriptor pointer. This may happen sometimes as a result
2450 * of a "no RX buffer available" condition that happens when the chip
2451 * consumes all of the RX buffers before the driver has a chance to
2452 * process the RX ring. This routine may need to be called more than
2453 * once to bring the driver back in sync with the chip, however we
2454 * should still be getting RX DONE interrupts to drive the search
2455 * for new packets in the RX ring, so we should catch up eventually.
2458 dc_rx_resync(struct dc_softc *sc)
2461 struct dc_desc *cur_rx;
2463 pos = sc->dc_cdata.dc_rx_prod;
2465 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2466 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2467 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2469 DC_INC(pos, DC_RX_LIST_CNT);
2472 /* If the ring really is empty, then just return. */
2473 if (i == DC_RX_LIST_CNT)
2476 /* We've fallen behing the chip: catch it. */
2477 sc->dc_cdata.dc_rx_prod = pos;
2483 * A frame has been uploaded: pass the resulting mbuf chain up to
2484 * the higher level protocols.
2487 dc_rxeof(struct dc_softc *sc)
2491 struct dc_desc *cur_rx;
2492 int i, total_len = 0;
2495 ifp = &sc->arpcom.ac_if;
2496 i = sc->dc_cdata.dc_rx_prod;
2498 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2500 #ifdef DEVICE_POLLING
2501 if (ifp->if_flags & IFF_POLLING) {
2502 if (sc->rxcycles <= 0)
2506 #endif /* DEVICE_POLLING */
2507 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2508 rxstat = cur_rx->dc_status;
2509 m = sc->dc_cdata.dc_rx_chain[i];
2510 total_len = DC_RXBYTES(rxstat);
2512 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2513 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2514 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2515 sc->dc_pnic_rx_bug_save = i;
2516 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2517 DC_INC(i, DC_RX_LIST_CNT);
2520 dc_pnic_rx_bug_war(sc, i);
2521 rxstat = cur_rx->dc_status;
2522 total_len = DC_RXBYTES(rxstat);
2526 sc->dc_cdata.dc_rx_chain[i] = NULL;
2529 * If an error occurs, update stats, clear the
2530 * status word and leave the mbuf cluster in place:
2531 * it should simply get re-used next time this descriptor
2532 * comes up in the ring. However, don't report long
2533 * frames as errors since they could be vlans
2535 if ((rxstat & DC_RXSTAT_RXERR)){
2536 if (!(rxstat & DC_RXSTAT_GIANT) ||
2537 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2538 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2539 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2541 if (rxstat & DC_RXSTAT_COLLSEEN)
2542 ifp->if_collisions++;
2543 dc_newbuf(sc, i, m);
2544 if (rxstat & DC_RXSTAT_CRCERR) {
2545 DC_INC(i, DC_RX_LIST_CNT);
2554 /* No errors; receive the packet. */
2555 total_len -= ETHER_CRC_LEN;
2559 * On the x86 we do not have alignment problems, so try to
2560 * allocate a new buffer for the receive ring, and pass up
2561 * the one where the packet is already, saving the expensive
2562 * copy done in m_devget().
2563 * If we are on an architecture with alignment problems, or
2564 * if the allocation fails, then use m_devget and leave the
2565 * existing buffer in the receive ring.
2567 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2568 m->m_pkthdr.rcvif = ifp;
2569 m->m_pkthdr.len = m->m_len = total_len;
2570 DC_INC(i, DC_RX_LIST_CNT);
2576 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2577 total_len + ETHER_ALIGN, 0, ifp, NULL);
2578 dc_newbuf(sc, i, m);
2579 DC_INC(i, DC_RX_LIST_CNT);
2584 m_adj(m0, ETHER_ALIGN);
2589 ifp->if_input(ifp, m);
2592 sc->dc_cdata.dc_rx_prod = i;
2596 * A frame was downloaded to the chip. It's safe for us to clean up
2601 dc_txeof(struct dc_softc *sc)
2603 struct dc_desc *cur_tx = NULL;
2607 ifp = &sc->arpcom.ac_if;
2610 * Go through our tx list and free mbufs for those
2611 * frames that have been transmitted.
2613 idx = sc->dc_cdata.dc_tx_cons;
2614 while(idx != sc->dc_cdata.dc_tx_prod) {
2617 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2618 txstat = cur_tx->dc_status;
2620 if (txstat & DC_TXSTAT_OWN)
2623 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2624 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2625 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2627 * Yes, the PNIC is so brain damaged
2628 * that it will sometimes generate a TX
2629 * underrun error while DMAing the RX
2630 * filter setup frame. If we detect this,
2631 * we have to send the setup frame again,
2632 * or else the filter won't be programmed
2635 if (DC_IS_PNIC(sc)) {
2636 if (txstat & DC_TXSTAT_ERRSUM)
2639 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2641 sc->dc_cdata.dc_tx_cnt--;
2642 DC_INC(idx, DC_TX_LIST_CNT);
2646 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2648 * XXX: Why does my Xircom taunt me so?
2649 * For some reason Conexant chips like
2650 * setting the CARRLOST flag even when
2651 * the carrier is there. In CURRENT we
2652 * have the same problem for Xircom
2655 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2656 sc->dc_pmode == DC_PMODE_MII &&
2657 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2658 DC_TXSTAT_NOCARRIER)))
2659 txstat &= ~DC_TXSTAT_ERRSUM;
2661 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2662 sc->dc_pmode == DC_PMODE_MII &&
2663 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2664 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2665 txstat &= ~DC_TXSTAT_ERRSUM;
2668 if (txstat & DC_TXSTAT_ERRSUM) {
2670 if (txstat & DC_TXSTAT_EXCESSCOLL)
2671 ifp->if_collisions++;
2672 if (txstat & DC_TXSTAT_LATECOLL)
2673 ifp->if_collisions++;
2674 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2680 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2683 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2684 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2685 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2688 sc->dc_cdata.dc_tx_cnt--;
2689 DC_INC(idx, DC_TX_LIST_CNT);
2692 if (idx != sc->dc_cdata.dc_tx_cons) {
2693 /* some buffers have been freed */
2694 sc->dc_cdata.dc_tx_cons = idx;
2695 ifp->if_flags &= ~IFF_OACTIVE;
2697 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2705 struct dc_softc *sc = xsc;
2706 struct ifnet *ifp = &sc->arpcom.ac_if;
2707 struct mii_data *mii;
2710 lwkt_serialize_enter(ifp->if_serializer);
2712 mii = device_get_softc(sc->dc_miibus);
2714 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2715 if (sc->dc_flags & DC_21143_NWAY) {
2716 r = CSR_READ_4(sc, DC_10BTSTAT);
2717 if (IFM_SUBTYPE(mii->mii_media_active) ==
2718 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2722 if (IFM_SUBTYPE(mii->mii_media_active) ==
2723 IFM_10_T && (r & DC_TSTAT_LS10)) {
2727 if (sc->dc_link == 0)
2730 r = CSR_READ_4(sc, DC_ISR);
2731 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2732 sc->dc_cdata.dc_tx_cnt == 0) {
2734 if (!(mii->mii_media_status & IFM_ACTIVE))
2743 * When the init routine completes, we expect to be able to send
2744 * packets right away, and in fact the network code will send a
2745 * gratuitous ARP the moment the init routine marks the interface
2746 * as running. However, even though the MAC may have been initialized,
2747 * there may be a delay of a few seconds before the PHY completes
2748 * autonegotiation and the link is brought up. Any transmissions
2749 * made during that delay will be lost. Dealing with this is tricky:
2750 * we can't just pause in the init routine while waiting for the
2751 * PHY to come ready since that would bring the whole system to
2752 * a screeching halt for several seconds.
2754 * What we do here is prevent the TX start routine from sending
2755 * any packets until a link has been established. After the
2756 * interface has been initialized, the tick routine will poll
2757 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2758 * that time, packets will stay in the send queue, and once the
2759 * link comes up, they will be flushed out to the wire.
2763 if (mii->mii_media_status & IFM_ACTIVE &&
2764 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2766 if (!ifq_is_empty(&ifp->if_snd))
2771 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2772 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2774 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2776 lwkt_serialize_exit(ifp->if_serializer);
2780 * A transmit underrun has occurred. Back off the transmit threshold,
2781 * or switch to store and forward mode if we have to.
2784 dc_tx_underrun(struct dc_softc *sc)
2789 if (DC_IS_DAVICOM(sc))
2792 if (DC_IS_INTEL(sc)) {
2794 * The real 21143 requires that the transmitter be idle
2795 * in order to change the transmit threshold or store
2796 * and forward state.
2798 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2800 for (i = 0; i < DC_TIMEOUT; i++) {
2801 isr = CSR_READ_4(sc, DC_ISR);
2802 if (isr & DC_ISR_TX_IDLE)
2806 if (i == DC_TIMEOUT) {
2807 if_printf(&sc->arpcom.ac_if,
2808 "failed to force tx to idle state\n");
2813 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2814 sc->dc_txthresh += DC_TXTHRESH_INC;
2815 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2816 printf("using store and forward mode\n");
2817 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2819 printf("increasing TX threshold\n");
2820 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2821 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2824 if (DC_IS_INTEL(sc))
2825 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2830 #ifdef DEVICE_POLLING
2833 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2835 struct dc_softc *sc = ifp->if_softc;
2840 /* Disable interrupts */
2841 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2843 case POLL_DEREGISTER:
2844 /* Re-enable interrupts. */
2845 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2848 sc->rxcycles = count;
2851 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2854 case POLL_AND_CHECK_STATUS:
2855 sc->rxcycles = count;
2858 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2860 status = CSR_READ_4(sc, DC_ISR);
2861 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2862 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2866 /* ack what we have */
2867 CSR_WRITE_4(sc, DC_ISR, status);
2869 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2870 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2871 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2873 if (dc_rx_resync(sc))
2876 /* restart transmit unit if necessary */
2877 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2878 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2880 if (status & DC_ISR_TX_UNDERRUN)
2883 if (status & DC_ISR_BUS_ERR) {
2884 if_printf(ifp, "dc_poll: bus error\n");
2891 #endif /* DEVICE_POLLING */
2896 struct dc_softc *sc;
2902 if (sc->suspended) {
2906 ifp = &sc->arpcom.ac_if;
2908 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2911 /* Suppress unwanted interrupts */
2912 if (!(ifp->if_flags & IFF_UP)) {
2913 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2918 /* Disable interrupts. */
2919 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2921 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
2922 status != 0xFFFFFFFF) {
2924 CSR_WRITE_4(sc, DC_ISR, status);
2926 if (status & DC_ISR_RX_OK) {
2928 curpkts = ifp->if_ipackets;
2930 if (curpkts == ifp->if_ipackets) {
2931 while(dc_rx_resync(sc))
2936 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2939 if (status & DC_ISR_TX_IDLE) {
2941 if (sc->dc_cdata.dc_tx_cnt) {
2942 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2943 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2947 if (status & DC_ISR_TX_UNDERRUN)
2950 if ((status & DC_ISR_RX_WATDOGTIMEO)
2951 || (status & DC_ISR_RX_NOBUF)) {
2953 curpkts = ifp->if_ipackets;
2955 if (curpkts == ifp->if_ipackets) {
2956 while(dc_rx_resync(sc))
2961 if (status & DC_ISR_BUS_ERR) {
2967 /* Re-enable interrupts. */
2968 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2970 if (!ifq_is_empty(&ifp->if_snd))
2977 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2978 * pointers to the fragment pointers.
2981 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
2983 struct dc_desc *f = NULL;
2985 int frag, cur, cnt = 0;
2988 * Start packing the mbufs in this chain into
2989 * the fragment pointers. Stop when we run out
2990 * of fragments or hit the end of the mbuf chain.
2993 cur = frag = *txidx;
2995 for (m = m_head; m != NULL; m = m->m_next) {
2996 if (m->m_len != 0) {
2997 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2998 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2999 frag == (DC_TX_LIST_CNT - 1))
3002 if ((DC_TX_LIST_CNT -
3003 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3006 f = &sc->dc_ldata->dc_tx_list[frag];
3007 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
3010 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
3012 f->dc_status = DC_TXSTAT_OWN;
3013 f->dc_data = vtophys(mtod(m, vm_offset_t));
3015 DC_INC(frag, DC_TX_LIST_CNT);
3023 sc->dc_cdata.dc_tx_cnt += cnt;
3024 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3025 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3026 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3027 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3028 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3029 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3030 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3031 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3032 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3039 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3040 * to the mbuf data regions directly in the transmit lists. We also save a
3041 * copy of the pointers since the transmit list fragment pointers are
3042 * physical addresses.
3046 dc_start(struct ifnet *ifp)
3048 struct dc_softc *sc;
3049 struct mbuf *m_head;
3050 struct mbuf *m_defragged;
3051 int idx, need_trans;
3058 if (ifp->if_flags & IFF_OACTIVE)
3061 idx = sc->dc_cdata.dc_tx_prod;
3064 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3066 m_head = ifq_poll(&ifp->if_snd);
3070 if (sc->dc_flags & DC_TX_COALESCE &&
3071 (m_head->m_next != NULL ||
3072 sc->dc_flags & DC_TX_ALIGN)){
3074 * Check first if coalescing allows us to queue
3075 * the packet. We don't want to loose it if
3076 * the TX queue is full.
3078 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3079 idx != sc->dc_cdata.dc_tx_prod &&
3080 idx == (DC_TX_LIST_CNT - 1)) {
3081 ifp->if_flags |= IFF_OACTIVE;
3084 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3085 ifp->if_flags |= IFF_OACTIVE;
3089 /* only coalesce if have >1 mbufs */
3090 m_defragged = m_defrag_nofree(m_head, MB_DONTWAIT);
3091 if (m_defragged == NULL) {
3092 ifp->if_flags |= IFF_OACTIVE;
3097 if (dc_encap(sc, (m_defragged ? m_defragged : m_head), &idx)) {
3100 * Throw away the original packet if the
3101 * defragged packet could not be encapsulated,
3102 * as well as the defragged packet.
3104 ifq_dequeue(&ifp->if_snd, m_head);
3106 m_freem(m_defragged);
3108 ifp->if_flags |= IFF_OACTIVE;
3112 ifq_dequeue(&ifp->if_snd, m_head);
3117 * If there's a BPF listener, bounce a copy of this frame
3120 BPF_MTAP(ifp, (m_defragged ? m_defragged : m_head));
3123 * If we defragged the packet, m_head is not the one we
3124 * encapsulated so we can throw it away.
3129 if (sc->dc_flags & DC_TX_ONE) {
3130 ifp->if_flags |= IFF_OACTIVE;
3139 sc->dc_cdata.dc_tx_prod = idx;
3140 if (!(sc->dc_flags & DC_TX_POLL))
3141 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3144 * Set a timeout in case the chip goes out to lunch.
3152 struct dc_softc *sc = xsc;
3153 struct ifnet *ifp = &sc->arpcom.ac_if;
3154 struct mii_data *mii;
3156 mii = device_get_softc(sc->dc_miibus);
3159 * Cancel pending I/O and free all RX/TX buffers.
3165 * Set cache alignment and burst length.
3167 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3168 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3170 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3172 * Evenly share the bus between receive and transmit process.
3174 if (DC_IS_INTEL(sc))
3175 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3176 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3177 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3179 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3181 if (sc->dc_flags & DC_TX_POLL)
3182 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3183 switch(sc->dc_cachesize) {
3185 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3188 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3191 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3195 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3199 if (sc->dc_flags & DC_TX_STORENFWD)
3200 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3202 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3203 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3205 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3206 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3210 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3211 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3213 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3215 * The app notes for the 98713 and 98715A say that
3216 * in order to have the chips operate properly, a magic
3217 * number must be written to CSR16. Macronix does not
3218 * document the meaning of these bits so there's no way
3219 * to know exactly what they do. The 98713 has a magic
3220 * number all its own; the rest all use a different one.
3222 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3223 if (sc->dc_type == DC_TYPE_98713)
3224 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3226 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3229 if (DC_IS_XIRCOM(sc)) {
3231 * Setup General Purpose Port mode and data so the tulip
3232 * can talk to the MII.
3234 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3235 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3237 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3238 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3242 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3243 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3245 /* Init circular RX list. */
3246 if (dc_list_rx_init(sc) == ENOBUFS) {
3247 if_printf(ifp, "initialization failed: no "
3248 "memory for rx buffers\n");
3254 * Init tx descriptors.
3256 dc_list_tx_init(sc);
3259 * Load the address of the RX list.
3261 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3262 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3265 * Enable interrupts.
3267 #ifdef DEVICE_POLLING
3269 * ... but only if we are not polling, and make sure they are off in
3270 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3273 if (ifp->if_flags & IFF_POLLING)
3274 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3277 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3278 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3280 /* Enable transmitter. */
3281 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3284 * If this is an Intel 21143 and we're not using the
3285 * MII port, program the LED control pins so we get
3286 * link and activity indications.
3288 if (sc->dc_flags & DC_TULIP_LEDS) {
3289 CSR_WRITE_4(sc, DC_WATCHDOG,
3290 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3291 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3295 * Load the RX/multicast filter. We do this sort of late
3296 * because the filter programming scheme on the 21143 and
3297 * some clones requires DMAing a setup frame via the TX
3298 * engine, and we need the transmitter enabled for that.
3302 /* Enable receiver. */
3303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3304 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3307 dc_setcfg(sc, sc->dc_if_media);
3309 ifp->if_flags |= IFF_RUNNING;
3310 ifp->if_flags &= ~IFF_OACTIVE;
3312 /* Don't start the ticker if this is a homePNA link. */
3313 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3316 if (sc->dc_flags & DC_21143_NWAY)
3317 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3319 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3326 * Set media options.
3329 dc_ifmedia_upd(struct ifnet *ifp)
3331 struct dc_softc *sc;
3332 struct mii_data *mii;
3333 struct ifmedia *ifm;
3336 mii = device_get_softc(sc->dc_miibus);
3338 ifm = &mii->mii_media;
3340 if (DC_IS_DAVICOM(sc) &&
3341 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3342 dc_setcfg(sc, ifm->ifm_media);
3350 * Report current media status.
3353 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3355 struct dc_softc *sc;
3356 struct mii_data *mii;
3357 struct ifmedia *ifm;
3360 mii = device_get_softc(sc->dc_miibus);
3362 ifm = &mii->mii_media;
3363 if (DC_IS_DAVICOM(sc)) {
3364 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3365 ifmr->ifm_active = ifm->ifm_media;
3366 ifmr->ifm_status = 0;
3370 ifmr->ifm_active = mii->mii_media_active;
3371 ifmr->ifm_status = mii->mii_media_status;
3377 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3379 struct dc_softc *sc = ifp->if_softc;
3380 struct ifreq *ifr = (struct ifreq *) data;
3381 struct mii_data *mii;
3386 if (ifp->if_flags & IFF_UP) {
3387 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3388 (IFF_PROMISC | IFF_ALLMULTI);
3389 if (ifp->if_flags & IFF_RUNNING) {
3393 sc->dc_txthresh = 0;
3397 if (ifp->if_flags & IFF_RUNNING)
3400 sc->dc_if_flags = ifp->if_flags;
3410 mii = device_get_softc(sc->dc_miibus);
3411 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3414 error = ether_ioctl(ifp, command, data);
3422 dc_watchdog(struct ifnet *ifp)
3424 struct dc_softc *sc;
3429 if_printf(ifp, "watchdog timeout\n");
3435 if (!ifq_is_empty(&ifp->if_snd))
3442 * Stop the adapter and free any mbufs allocated to the
3446 dc_stop(struct dc_softc *sc)
3451 ifp = &sc->arpcom.ac_if;
3454 callout_stop(&sc->dc_stat_timer);
3456 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3458 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3459 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3460 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3461 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3465 * Free data in the RX lists.
3467 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3468 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3469 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3470 sc->dc_cdata.dc_rx_chain[i] = NULL;
3473 bzero((char *)&sc->dc_ldata->dc_rx_list,
3474 sizeof(sc->dc_ldata->dc_rx_list));
3477 * Free the TX list buffers.
3479 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3480 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3481 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3483 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3484 DC_TXCTL_LASTFRAG)) {
3485 sc->dc_cdata.dc_tx_chain[i] = NULL;
3488 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3489 sc->dc_cdata.dc_tx_chain[i] = NULL;
3493 bzero((char *)&sc->dc_ldata->dc_tx_list,
3494 sizeof(sc->dc_ldata->dc_tx_list));
3500 * Stop all chip I/O so that the kernel's probe routines don't
3501 * get confused by errant DMAs when rebooting.
3504 dc_shutdown(device_t dev)
3506 struct dc_softc *sc;
3509 sc = device_get_softc(dev);
3510 ifp = &sc->arpcom.ac_if;
3511 lwkt_serialize_enter(ifp->if_serializer);
3515 lwkt_serialize_exit(ifp->if_serializer);
3519 * Device suspend routine. Stop the interface and save some PCI
3520 * settings in case the BIOS doesn't restore them properly on
3524 dc_suspend(device_t dev)
3526 struct dc_softc *sc = device_get_softc(dev);
3527 struct ifnet *ifp = &sc->arpcom.ac_if;
3529 lwkt_serialize_enter(ifp->if_serializer);
3532 for (i = 0; i < 5; i++)
3533 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3534 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3535 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3536 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3537 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3541 lwkt_serialize_exit(ifp->if_serializer);
3546 * Device resume routine. Restore some PCI settings in case the BIOS
3547 * doesn't, re-enable busmastering, and restart the interface if
3551 dc_resume(device_t dev)
3553 struct dc_softc *sc = device_get_softc(dev);
3554 struct ifnet *ifp = &sc->arpcom.ac_if;
3557 lwkt_serialize_enter(ifp->if_serializer);
3560 /* better way to do this? */
3561 for (i = 0; i < 5; i++)
3562 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3563 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3564 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3565 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3566 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3568 /* reenable busmastering */
3569 pci_enable_busmaster(dev);
3570 pci_enable_io(dev, DC_RES);
3572 /* reinitialize interface if necessary */
3573 if (ifp->if_flags & IFF_UP)
3577 lwkt_serialize_exit(ifp->if_serializer);
3583 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr)
3587 /* Compute CRC for the address value. */
3588 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
3590 if ((crc & 0x180) == 0x180)
3591 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
3593 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4));