sys/dev/netif/sr/if_sr.c

   1 /*
   2  * Copyright (c) 1996 - 2001 John Hay.
   3  * Copyright (c) 1996 SDL Communications, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
  31  * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.17 2005/11/28 17:13:44 dillon Exp $
  32  */
  33
  34 /*
  35  * Programming assumptions and other issues.
  36  *
  37  * Only a 16K window will be used.
  38  *
  39  * The descriptors of a DMA channel will fit in a 16K memory window.
  40  *
  41  * The buffers of a transmit DMA channel will fit in a 16K memory window.
  42  *
  43  * When interface is going up, handshaking is set and it is only cleared
  44  * when the interface is down'ed.
  45  *
  46  * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
  47  * internal/external clock, etc.....
  48  *
  49  */
  50
  51 #include "opt_netgraph.h"
  52 #ifdef NETGRAPH
  53 #include "if_sr.h"
  54 #endif  /* NETGRAPH */
  55
  56 #include <sys/param.h>
  57 #include <sys/systm.h>
  58 #include <sys/kernel.h>
  59 #include <sys/malloc.h>
  60 #include <sys/mbuf.h>
  61 #include <sys/sockio.h>
  62 #include <sys/socket.h>
  63 #include <sys/thread2.h>
  64 #include <sys/bus.h>
  65 #include <machine/bus.h>
  66 #include <machine/resource.h>
  67 #include <machine/bus_pio.h>
  68 #include <machine/bus_memio.h>
  69 #include <sys/rman.h>
  70
  71 #include <net/if.h>
  72 #ifdef NETGRAPH
  73 #include <sys/syslog.h>
  74 #else /* NETGRAPH */
  75 #include <net/sppp/if_sppp.h>
  76
  77 #include <net/bpf.h>
  78 #endif  /* NETGRAPH */
  79
  80 #include <machine/md_var.h>
  81
  82 #include "../ic_layer/hd64570.h"
  83 #include "if_srregs.h"
  84
  85 #ifdef NETGRAPH
  86 #include <netgraph/ng_message.h>
  87 #include <netgraph/netgraph.h>
  88 #endif /* NETGRAPH */
  89 /* #define USE_MODEMCK */
  90
  91 #ifndef BUGGY
  92 #define BUGGY           0
  93 #endif
  94
  95 #ifndef NETGRAPH
  96 #define PPP_HEADER_LEN  4
  97 #endif /* NETGRAPH */
  98
  99 static int      next_sc_unit = 0;
 100 #ifndef NETGRAPH
 101 #ifdef USE_MODEMCK
 102 static int      sr_watcher = 0;
 103 #endif
 104 #endif /* NETGRAPH */
 105
 106 /*
 107  * Define the software interface for the card... There is one for
 108  * every channel (port).
 109  */
 110 struct sr_softc {
 111 #ifndef NETGRAPH
 112         struct  sppp ifsppp;    /* PPP service w/in system */
 113 #endif /* NETGRAPH */
 114         struct  sr_hardc *hc;   /* card-level information */
 115
 116         int     unit;           /* With regard to all sr devices */
 117         int     subunit;        /* With regard to this card */
 118
 119         struct  buf_block {
 120                 u_int   txdesc; /* DPRAM offset */
 121                 u_int   txstart;/* DPRAM offset */
 122                 u_int   txend;  /* DPRAM offset */
 123                 u_int   txtail; /* # of 1st free gran */
 124                 u_int   txmax;  /* # of free grans */
 125                 u_int   txeda;  /* err descr addr */
 126         } block[SR_TX_BLOCKS];
 127
 128         char    xmit_busy;      /* Transmitter is busy */
 129         char    txb_inuse;      /* # of tx grans in use */
 130         u_int   txb_new;        /* ndx to new buffer */
 131         u_int   txb_next_tx;    /* ndx to next gran rdy tx */
 132
 133         u_int   rxdesc;         /* DPRAM offset */
 134         u_int   rxstart;        /* DPRAM offset */
 135         u_int   rxend;          /* DPRAM offset */
 136         u_int   rxhind;         /* ndx to the hd of rx bufrs */
 137         u_int   rxmax;          /* # of avail grans */
 138
 139         u_int   clk_cfg;        /* Clock configuration */
 140
 141         int     scachan;        /* channel # on card */
 142 #ifdef NETGRAPH
 143         int     running;        /* something is attached so we are running */
 144         int     dcd;            /* do we have dcd? */
 145         /* ---netgraph bits --- */
 146         char            nodename[NG_NODELEN + 1]; /* store our node name */
 147         int             datahooks;      /* number of data hooks attached */
 148         node_p          node;           /* netgraph node */
 149         hook_p          hook;           /* data hook */
 150         hook_p          debug_hook;
 151         struct ifqueue  xmitq_hipri;    /* hi-priority transmit queue */
 152         struct ifqueue  xmitq;          /* transmit queue */
 153         int             flags;          /* state */
 154 #define SCF_RUNNING     0x01            /* board is active */
 155 #define SCF_OACTIVE     0x02            /* output is active */
 156         int             out_dog;        /* watchdog cycles output count-down */
 157         struct callout  sr_timer;       /* timeout(9) handle */
 158         u_long          inbytes, outbytes;      /* stats */
 159         u_long          lastinbytes, lastoutbytes; /* a second ago */
 160         u_long          inrate, outrate;        /* highest rate seen */
 161         u_long          inlast;         /* last input N secs ago */
 162         u_long          out_deficit;    /* output since last input */
 163         u_long          oerrors, ierrors[6];
 164         u_long          opackets, ipackets;
 165 #endif /* NETGRAPH */
 166 };
 167
 168 #ifdef NETGRAPH
 169 #define DOG_HOLDOFF     6       /* dog holds off for 6 secs */
 170 #define QUITE_A_WHILE   300     /* 5 MINUTES */
 171 #define LOTS_OF_PACKETS 100
 172 #endif /* NETGRAPH */
 173
 174 /*
 175  * Baud Rate table for Sync Mode.
 176  * Each entry consists of 3 elements:
 177  * Baud Rate (x100) , TMC, BR
 178  *
 179  * Baud Rate = FCLK / TMC / 2^BR
 180  * Baud table for Crystal freq. of 9.8304 Mhz
 181  */
 182 #ifdef N2_TEST_SPEED
 183 struct rate_line {
 184         int     target;         /* target rate/100 */
 185         int     tmc_reg;        /* TMC register value */
 186         int     br_reg;         /* BR (BaudRateClk) selector */
 187 } n2_rates[] = {
 188         /* Baudx100     TMC             BR */
 189         { 3,            128,            8 },
 190         { 6,            128,            7 },
 191         { 12,           128,            6 },
 192         { 24,           128,            5 },
 193         { 48,           128,            4 },
 194         { 96,           128,            3 },
 195         { 192,          128,            2 },
 196         { 384,          128,            1 },
 197         { 560,          88,             1 },
 198         { 640,          77,             1 },
 199         { 1280,         38,             1 },
 200         { 2560,         19,             1 },
 201         { 5120,         10,             1 },
 202         { 10000,        5,              1 },
 203         { 15000,        3,              1 },
 204         { 25000,        2,              1 },
 205         { 50000,        1,              1 },
 206         { 0,            0,              0 }
 207 };
 208
 209 int     sr_test_speed[] = {
 210         N2_TEST_SPEED,
 211         N2_TEST_SPEED
 212 };
 213
 214 int     etc0vals[] = {
 215         SR_MCR_ETC0,            /* ISA channel 0 */
 216         SR_MCR_ETC1,            /* ISA channel 1 */
 217         SR_FECR_ETC0,           /* PCI channel 0 */
 218         SR_FECR_ETC1            /* PCI channel 1 */
 219 };
 220 #endif
 221
 222 devclass_t sr_devclass;
 223 #ifndef NETGRAPH
 224 DECLARE_DUMMY_MODULE(if_sr);
 225 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
 226 #else
 227 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
 228 #endif
 229
 230 static void     srintr(void *arg);
 231 static void     sr_xmit(struct sr_softc *sc);
 232 #ifndef NETGRAPH
 233 static void     srstart(struct ifnet *ifp);
 234 static int      srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
 235                         struct ucred *);
 236 static void     srwatchdog(struct ifnet *ifp);
 237 #else
 238 static void     srstart(struct sr_softc *sc);
 239 static void     srwatchdog(struct sr_softc *sc);
 240 #endif /* NETGRAPH */
 241 static int      sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
 242 static void     sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
 243 static void     sr_eat_packet(struct sr_softc *sc, int single);
 244 static void     sr_get_packets(struct sr_softc *sc);
 245
 246 static void     sr_up(struct sr_softc *sc);
 247 static void     sr_down(struct sr_softc *sc);
 248 static void     src_init(struct sr_hardc *hc);
 249 static void     sr_init_sca(struct sr_hardc *hc);
 250 static void     sr_init_msci(struct sr_softc *sc);
 251 static void     sr_init_rx_dmac(struct sr_softc *sc);
 252 static void     sr_init_tx_dmac(struct sr_softc *sc);
 253 static void     sr_dmac_intr(struct sr_hardc *hc, u_char isr);
 254 static void     sr_msci_intr(struct sr_hardc *hc, u_char isr);
 255 static void     sr_timer_intr(struct sr_hardc *hc, u_char isr);
 256 #ifndef NETGRAPH
 257 #ifdef USE_MODEMCK
 258 static void     sr_modemck(void *x);
 259 #endif
 260 #else
 261 static void     sr_modemck(struct sr_softc *x);
 262 #endif /* NETGRAPH */
 263
 264 #ifdef NETGRAPH
 265 static  void    ngsr_watchdog_frame(void * arg);
 266 static  void    ngsr_init(void* ignored);
 267
 268 static ng_constructor_t ngsr_constructor;
 269 static ng_rcvmsg_t      ngsr_rcvmsg;
 270 static ng_shutdown_t    ngsr_rmnode;
 271 static ng_newhook_t     ngsr_newhook;
 272 /*static ng_findhook_t  ngsr_findhook; */
 273 static ng_connect_t     ngsr_connect;
 274 static ng_rcvdata_t     ngsr_rcvdata;
 275 static ng_disconnect_t  ngsr_disconnect;
 276
 277 static struct ng_type typestruct = {
 278         NG_VERSION,
 279         NG_SR_NODE_TYPE,
 280         NULL,
 281         ngsr_constructor,
 282         ngsr_rcvmsg,
 283         ngsr_rmnode,
 284         ngsr_newhook,
 285         NULL,
 286         ngsr_connect,
 287         ngsr_rcvdata,
 288         ngsr_rcvdata,
 289         ngsr_disconnect,
 290         NULL
 291 };
 292
 293 static int      ngsr_done_init = 0;
 294 #endif /* NETGRAPH */
 295
 296 /*
 297  * Register the ports on the adapter.
 298  * Fill in the info for each port.
 299 #ifndef NETGRAPH
 300  * Attach each port to sppp and bpf.
 301 #endif
 302  */
 303 int
 304 sr_attach(device_t device)
 305 {
 306         int intf_sw, pndx;
 307         u_int32_t flags;
 308         u_int fecr, *fecrp;
 309         struct sr_hardc *hc;
 310         struct sr_softc *sc;
 311 #ifndef NETGRAPH
 312         struct ifnet *ifp;
 313 #endif /* NETGRAPH */
 314         int unit;               /* index: channel w/in card */
 315
 316         hc = (struct sr_hardc *)device_get_softc(device);
 317         MALLOC(sc, struct sr_softc *,
 318                 hc->numports * sizeof(struct sr_softc),
 319                 M_DEVBUF, M_WAITOK | M_ZERO);
 320         if (sc == NULL)
 321                 goto errexit;
 322         hc->sc = sc;
 323
 324         /*
 325          * Get the TX clock direction and configuration. The default is a
 326          * single external clock which is used by RX and TX.
 327          */
 328         switch(hc->cardtype) {
 329         case SR_CRD_N2:
 330                 flags = device_get_flags(device);
 331 #ifdef N2_TEST_SPEED
 332                 if (sr_test_speed[0] > 0)
 333                         hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 334                 else
 335 #endif
 336                 if (flags & SR_FLAGS_0_CLK_MSK)
 337                         hc->sc[0].clk_cfg =
 338                             (flags & SR_FLAGS_0_CLK_MSK)
 339                             >> SR_FLAGS_CLK_SHFT;
 340
 341                 if (hc->numports == 2)
 342 #ifdef N2_TEST_SPEED
 343                         if (sr_test_speed[1] > 0)
 344                                 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 345                         else
 346 #endif
 347                         if (flags & SR_FLAGS_1_CLK_MSK)
 348                                 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
 349                                     >> (SR_FLAGS_CLK_SHFT +
 350                                     SR_FLAGS_CLK_CHAN_SHFT);
 351                 break;
 352         case SR_CRD_N2PCI:
 353                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
 354                 fecr = *fecrp;
 355                 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
 356                         switch (pndx) {
 357                         case 1:
 358                                 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
 359                                 break;
 360                         case 0:
 361                         default:
 362                                 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
 363                         }
 364
 365 #ifdef N2_TEST_SPEED
 366                         if (sr_test_speed[pndx] > 0)
 367                                 sc->clk_cfg = SR_FLAGS_INT_CLK;
 368                         else
 369 #endif
 370                                 switch (intf_sw) {
 371                                 default:
 372                                 case SR_FE_ID_RS232:
 373                                 case SR_FE_ID_HSSI:
 374                                 case SR_FE_ID_RS422:
 375                                 case SR_FE_ID_TEST:
 376                                         break;
 377
 378                                 case SR_FE_ID_V35:
 379                                         sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
 380                                         break;
 381
 382                                 case SR_FE_ID_X21:
 383                                         sc->clk_cfg = SR_FLAGS_EXT_CLK;
 384                                         break;
 385                                 }
 386                 }
 387                 sc = hc->sc;
 388                 break;
 389         }
 390
 391         /*
 392          * Report Card configuration information before we start configuring
 393          * each channel on the card...
 394          */
 395         printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
 396                hc->cunit, hc->memsize / 1024, hc->mempages,
 397                (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
 398
 399         src_init(hc);
 400         sr_init_sca(hc);
 401
 402         if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
 403                            0, srintr, hc,
 404                            &hc->intr_cookie, NULL) != 0)
 405                 goto errexit;
 406
 407         /*
 408          * Now configure each port on the card.
 409          */
 410         for (unit = 0; unit < hc->numports; sc++, unit++) {
 411                 sc->hc = hc;
 412                 sc->subunit = unit;
 413                 sc->unit = next_sc_unit;
 414                 next_sc_unit++;
 415                 sc->scachan = unit % NCHAN;
 416
 417                 sr_init_rx_dmac(sc);
 418                 sr_init_tx_dmac(sc);
 419                 sr_init_msci(sc);
 420
 421                 printf("sr%d: Adapter %d, port %d.\n",
 422                        sc->unit, hc->cunit, sc->subunit);
 423
 424 #ifndef NETGRAPH
 425                 ifp = &sc->ifsppp.pp_if;
 426                 ifp->if_softc = sc;
 427                 if_initname(ifp, "sr", sc->unit);
 428                 ifp->if_mtu = PP_MTU;
 429                 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
 430                 ifp->if_ioctl = srioctl;
 431                 ifp->if_start = srstart;
 432                 ifp->if_watchdog = srwatchdog;
 433
 434                 sc->ifsppp.pp_flags = PP_KEEPALIVE;
 435                 sppp_attach((struct ifnet *)&sc->ifsppp);
 436                 if_attach(ifp, NULL);
 437
 438                 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
 439 #else   /* NETGRAPH */
 440                 /*
 441                  * we have found a node, make sure our 'type' is availabe.
 442                  */
 443                 if (ngsr_done_init == 0) ngsr_init(NULL);
 444                 if (ng_make_node_common(&typestruct, &sc->node) != 0)
 445                         goto errexit;
 446                 sc->node->private = sc;
 447                 callout_init(&sc->sr_timer);
 448                 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
 449                 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
 450                 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
 451                 if (ng_name_node(sc->node, sc->nodename)) {
 452                         ng_rmnode(sc->node);
 453                         ng_unref(sc->node);
 454                         return (0);
 455                 }
 456                 sc->running = 0;
 457 #endif  /* NETGRAPH */
 458         }
 459
 460         if (hc->mempages)
 461                 SRC_SET_OFF(hc->iobase);
 462
 463         return (0);
 464
 465 errexit:
 466         sr_deallocate_resources(device);
 467         return (ENXIO);
 468 }
 469
 470 int
 471 sr_detach(device_t device)
 472 {
 473         device_t parent = device_get_parent(device);
 474         struct sr_hardc *hc = device_get_softc(device);
 475
 476         if (hc->intr_cookie != NULL) {
 477                 if (BUS_TEARDOWN_INTR(parent, device,
 478                         hc->res_irq, hc->intr_cookie) != 0) {
 479                                 printf("intr teardown failed.. continuing\n");
 480                 }
 481                 hc->intr_cookie = NULL;
 482         }
 483
 484         /* XXX Stop the DMA. */
 485
 486         /*
 487          * deallocate any system resources we may have
 488          * allocated on behalf of this driver.
 489          */
 490         FREE(hc->sc, M_DEVBUF);
 491         hc->sc = NULL;
 492         hc->mem_start = NULL;
 493         return (sr_deallocate_resources(device));
 494 }
 495
 496 int
 497 sr_allocate_ioport(device_t device, int rid, u_long size)
 498 {
 499         struct sr_hardc *hc = device_get_softc(device);
 500
 501         hc->rid_ioport = rid;
 502         hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
 503                         &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
 504         if (hc->res_ioport == NULL) {
 505                 goto errexit;
 506         }
 507         return (0);
 508
 509 errexit:
 510         sr_deallocate_resources(device);
 511         return (ENXIO);
 512 }
 513
 514 int
 515 sr_allocate_irq(device_t device, int rid, u_long size)
 516 {
 517         struct sr_hardc *hc = device_get_softc(device);
 518
 519         hc->rid_irq = rid;
 520         hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
 521             &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
 522         if (hc->res_irq == NULL) {
 523                 goto errexit;
 524         }
 525         return (0);
 526
 527 errexit:
 528         sr_deallocate_resources(device);
 529         return (ENXIO);
 530 }
 531
 532 int
 533 sr_allocate_memory(device_t device, int rid, u_long size)
 534 {
 535         struct sr_hardc *hc = device_get_softc(device);
 536
 537         hc->rid_memory = rid;
 538         hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 539                         &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
 540         if (hc->res_memory == NULL) {
 541                 goto errexit;
 542         }
 543         return (0);
 544
 545 errexit:
 546         sr_deallocate_resources(device);
 547         return (ENXIO);
 548 }
 549
 550 int
 551 sr_allocate_plx_memory(device_t device, int rid, u_long size)
 552 {
 553         struct sr_hardc *hc = device_get_softc(device);
 554
 555         hc->rid_plx_memory = rid;
 556         hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 557                         &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
 558         if (hc->res_plx_memory == NULL) {
 559                 goto errexit;
 560         }
 561         return (0);
 562
 563 errexit:
 564         sr_deallocate_resources(device);
 565         return (ENXIO);
 566 }
 567
 568 int
 569 sr_deallocate_resources(device_t device)
 570 {
 571         struct sr_hardc *hc = device_get_softc(device);
 572
 573         if (hc->res_irq != 0) {
 574                 bus_deactivate_resource(device, SYS_RES_IRQ,
 575                         hc->rid_irq, hc->res_irq);
 576                 bus_release_resource(device, SYS_RES_IRQ,
 577                         hc->rid_irq, hc->res_irq);
 578                 hc->res_irq = 0;
 579         }
 580         if (hc->res_ioport != 0) {
 581                 bus_deactivate_resource(device, SYS_RES_IOPORT,
 582                         hc->rid_ioport, hc->res_ioport);
 583                 bus_release_resource(device, SYS_RES_IOPORT,
 584                         hc->rid_ioport, hc->res_ioport);
 585                 hc->res_ioport = 0;
 586         }
 587         if (hc->res_memory != 0) {
 588                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 589                         hc->rid_memory, hc->res_memory);
 590                 bus_release_resource(device, SYS_RES_MEMORY,
 591                         hc->rid_memory, hc->res_memory);
 592                 hc->res_memory = 0;
 593         }
 594         if (hc->res_plx_memory != 0) {
 595                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 596                         hc->rid_plx_memory, hc->res_plx_memory);
 597                 bus_release_resource(device, SYS_RES_MEMORY,
 598                         hc->rid_plx_memory, hc->res_plx_memory);
 599                 hc->res_plx_memory = 0;
 600         }
 601         return (0);
 602 }
 603
 604 /*
 605  * N2 Interrupt Service Routine
 606  *
 607  * First figure out which SCA gave the interrupt.
 608  * Process it.
 609  * See if there is other interrupts pending.
 610  * Repeat until there no interrupts remain.
 611  */
 612 static void
 613 srintr(void *arg)
 614 {
 615         struct sr_hardc *hc = (struct sr_hardc *)arg;
 616         sca_regs *sca = hc->sca;        /* MSCI register tree */
 617         u_char  isr0, isr1, isr2;       /* interrupt statii captured */
 618
 619 #if BUGGY > 1
 620         printf("sr: srintr_hc(hc=%08x)\n", hc);
 621 #endif
 622
 623         /*
 624          * Since multiple interfaces may share this interrupt, we must loop
 625          * until no interrupts are still pending service.
 626          */
 627         while (1) {
 628                 /*
 629                  * Read all three interrupt status registers from the N2
 630                  * card...
 631                  */
 632                 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
 633                 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
 634                 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
 635
 636                 /*
 637                  * If all three registers returned 0, we've finished
 638                  * processing interrupts from this device, so we can quit
 639                  * this loop...
 640                  */
 641                 if ((isr0 | isr1 | isr2) == 0)
 642                         break;
 643
 644 #if BUGGY > 2
 645                 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
 646 #ifndef NETGRAPH
 647                         unit, isr0, isr1, isr2);
 648 #else
 649                         hc->cunit, isr0, isr1, isr2);
 650 #endif /* NETGRAPH */
 651 #endif
 652
 653                 /*
 654                  * Now we can dispatch the interrupts. Since we don't expect
 655                  * either MSCI or timer interrupts, we'll test for DMA
 656                  * interrupts first...
 657                  */
 658                 if (isr1)       /* DMA-initiated interrupt */
 659                         sr_dmac_intr(hc, isr1);
 660
 661                 if (isr0)       /* serial part IRQ? */
 662                         sr_msci_intr(hc, isr0);
 663
 664                 if (isr2)       /* timer-initiated interrupt */
 665                         sr_timer_intr(hc, isr2);
 666         }
 667 }
 668
 669 /*
 670  * This will only start the transmitter. It is assumed that the data
 671  * is already there.
 672  * It is normally called from srstart() or sr_dmac_intr().
 673  */
 674 static void
 675 sr_xmit(struct sr_softc *sc)
 676 {
 677         u_short cda_value;      /* starting descriptor */
 678         u_short eda_value;      /* ending descriptor */
 679         struct sr_hardc *hc;
 680 #ifndef NETGRAPH
 681         struct ifnet *ifp;      /* O/S Network Services */
 682 #endif /* NETGRAPH */
 683         dmac_channel *dmac;     /* DMA channel registers */
 684
 685 #if BUGGY > 0
 686         printf("sr: sr_xmit( sc=%08x)\n", sc);
 687 #endif
 688
 689         hc = sc->hc;
 690 #ifndef NETGRAPH
 691         ifp = &sc->ifsppp.pp_if;
 692 #endif /* NETGRAPH */
 693         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
 694
 695         /*
 696          * Get the starting and ending addresses of the chain to be
 697          * transmitted and pass these on to the DMA engine on-chip.
 698          */
 699         cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
 700         cda_value &= 0x00ffff;
 701         eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
 702         eda_value &= 0x00ffff;
 703
 704         SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
 705         SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
 706
 707         /*
 708          * Now we'll let the DMA status register know about this change
 709          */
 710         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
 711
 712         sc->xmit_busy = 1;      /* mark transmitter busy */
 713
 714 #if BUGGY > 2
 715         printf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
 716                sc->unit, cda_value, eda_value,
 717                sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
 718 #endif
 719
 720         sc->txb_next_tx++;      /* update next transmit seq# */
 721
 722         if (sc->txb_next_tx == SR_TX_BLOCKS)    /* handle wrap... */
 723                 sc->txb_next_tx = 0;
 724
 725 #ifndef NETGRAPH
 726         /*
 727          * Finally, we'll set a timout (which will start srwatchdog())
 728          * within the O/S network services layer...
 729          */
 730         ifp->if_timer = 2;      /* Value in seconds. */
 731 #else
 732         /*
 733          * Don't time out for a while.
 734          */
 735         sc->out_dog = DOG_HOLDOFF;      /* give ourself some breathing space*/
 736 #endif /* NETGRAPH */
 737 }
 738
 739 /*
 740  * This function will be called from the upper level when a user add a
 741  * packet to be send, and from the interrupt handler after a finished
 742  * transmit.
 743  *
 744  * This function only place the data in the oncard buffers. It does not
 745  * start the transmition. sr_xmit() does that.
 746  *
 747  * Transmitter idle state is indicated by the IFF_OACTIVE flag.
 748  * The function that clears that should ensure that the transmitter
 749  * and its DMA is in a "good" idle state.
 750  */
 751 #ifndef NETGRAPH
 752 static void
 753 srstart(struct ifnet *ifp)
 754 {
 755         struct sr_softc *sc;    /* channel control structure */
 756 #else
 757 static void
 758 srstart(struct sr_softc *sc)
 759 {
 760 #endif /* NETGRAPH */
 761         struct sr_hardc *hc;    /* card control/config block */
 762         int len;                /* total length of a packet */
 763         int pkts;               /* packets placed in DPRAM */
 764         int tlen;               /* working length of pkt */
 765         u_int i;
 766         struct mbuf *mtx;       /* message buffer from O/S */
 767         u_char *txdata;         /* buffer address in DPRAM */
 768         sca_descriptor *txdesc; /* working descriptor pointr */
 769         struct buf_block *blkp;
 770
 771 #ifndef NETGRAPH
 772 #if BUGGY > 0
 773         printf("sr: srstart( ifp=%08x)\n", ifp);
 774 #endif
 775         sc = ifp->if_softc;
 776         if ((ifp->if_flags & IFF_RUNNING) == 0)
 777                 return;
 778 #endif /* NETGRAPH */
 779         hc = sc->hc;
 780         /*
 781          * It is OK to set the memory window outside the loop because all tx
 782          * buffers and descriptors are assumed to be in the same 16K window.
 783          */
 784         if (hc->mempages) {
 785                 SRC_SET_ON(hc->iobase);
 786                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
 787         }
 788
 789         /*
 790          * Loop to place packets into DPRAM.
 791          *
 792          * We stay in this loop until there is nothing in
 793          * the TX queue left or the tx buffers are full.
 794          */
 795 top_srstart:
 796
 797         /*
 798          * See if we have space for more packets.
 799          */
 800         if (sc->txb_inuse == SR_TX_BLOCKS) {    /* out of space? */
 801 #ifndef NETGRAPH
 802                 ifp->if_flags |= IFF_OACTIVE;   /* yes, mark active */
 803 #else
 804                 /*ifp->if_flags |= IFF_OACTIVE;*/       /* yes, mark active */
 805 #endif /* NETGRAPH */
 806
 807                 if (hc->mempages)
 808                         SRC_SET_OFF(hc->iobase);
 809
 810 #if BUGGY > 9
 811                 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
 812                        sc->unit, sc->txb_inuse);
 813 #endif
 814                 return;
 815         }
 816         /*
 817          * OK, the card can take more traffic.  Let's see if there's any
 818          * pending from the system...
 819          *
 820          * NOTE:
 821          * The architecture of the networking interface doesn't
 822          * actually call us like 'write()', providing an address.  We get
 823          * started, a lot like a disk strategy routine, and we actually call
 824          * back out to the system to get traffic to send...
 825          *
 826          * NOTE:
 827          * If we were gonna run through another layer, we would use a
 828          * dispatch table to select the service we're getting a packet
 829          * from...
 830          */
 831 #ifndef NETGRAPH
 832         mtx = sppp_dequeue(ifp);
 833 #else /* NETGRAPH */
 834         IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 835         if (mtx == NULL) {
 836                 IF_DEQUEUE(&sc->xmitq, mtx);
 837         }
 838 #endif /* NETGRAPH */
 839         if (!mtx) {
 840                 if (hc->mempages)
 841                         SRC_SET_OFF(hc->iobase);
 842                 return;
 843         }
 844         /*
 845          * OK, we got a packet from the network services of the O/S. Now we
 846          * can move it into the DPRAM (under control of the descriptors) and
 847          * fire it off...
 848          */
 849         pkts = 0;
 850         i = 0;                  /* counts # of granules used */
 851
 852         blkp = &sc->block[sc->txb_new]; /* address of free granule */
 853         txdesc = (sca_descriptor *)
 854             (hc->mem_start + (blkp->txdesc & hc->winmsk));
 855
 856         txdata = (u_char *)(hc->mem_start
 857                             + (blkp->txstart & hc->winmsk));
 858
 859         /*
 860          * Now we'll try to install as many packets as possible into the
 861          * card's DP RAM buffers.
 862          */
 863         for (;;) {              /* perform actual copy of packet */
 864                 len = mtx->m_pkthdr.len;        /* length of message */
 865
 866 #if BUGGY > 1
 867                 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
 868                            sc->unit, mtx, len);
 869 #endif
 870
 871 #ifndef NETGRAPH
 872                 BPF_MTAP(ifp, mtx);
 873 #else   /* NETGRAPH */
 874                 sc->outbytes += len;
 875 #endif  /* NETGRAPH */
 876
 877                 /*
 878                  * We can perform a straight copy because the tranmit
 879                  * buffers won't wrap.
 880                  */
 881                 m_copydata(mtx, 0, len, txdata);
 882
 883                 /*
 884                  * Now we know how big the message is gonna be.  We must now
 885                  * construct the descriptors to drive this message out...
 886                  */
 887                 tlen = len;
 888                 while (tlen > SR_BUF_SIZ) {     /* loop for full granules */
 889                         txdesc->stat = 0;       /* reset bits */
 890                         txdesc->len = SR_BUF_SIZ;       /* size of granule */
 891                         tlen -= SR_BUF_SIZ;
 892
 893                         txdesc++;       /* move to next dscr */
 894                         txdata += SR_BUF_SIZ;   /* adjust data addr */
 895                         i++;
 896                 }
 897
 898                 /*
 899                  * This section handles the setting of the final piece of a
 900                  * message.
 901                  */
 902                 txdesc->stat = SCA_DESC_EOM;
 903                 txdesc->len = tlen;
 904                 pkts++;
 905
 906                 /*
 907                  * prepare for subsequent packets (if any)
 908                  */
 909                 txdesc++;
 910                 txdata += SR_BUF_SIZ;   /* next mem granule */
 911                 i++;            /* count of granules */
 912
 913                 /*
 914                  * OK, we've now placed the message into the DPRAM where it
 915                  * can be transmitted.  We'll now release the message memory
 916                  * and update the statistics...
 917                  */
 918                 m_freem(mtx);
 919 #ifndef NETGRAPH
 920                 ++sc->ifsppp.pp_if.if_opackets;
 921 #else   /* NETGRAPH */
 922                 sc->opackets++;
 923 #endif /* NETGRAPH */
 924
 925                 /*
 926                  * Check if we have space for another packet. XXX This is
 927                  * hardcoded.  A packet can't be larger than 3 buffers (3 x
 928                  * 512).
 929                  */
 930                 if ((i + 3) >= blkp->txmax) {   /* enough remains? */
 931 #if BUGGY > 9
 932                         printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
 933                                sc->unit, i, pkts);
 934 #endif
 935                         break;
 936                 }
 937                 /*
 938                  * We'll pull the next message to be sent (if any)
 939                  */
 940 #ifndef NETGRAPH
 941                 mtx = sppp_dequeue(ifp);
 942 #else /* NETGRAPH */
 943                 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 944                 if (mtx == NULL) {
 945                         IF_DEQUEUE(&sc->xmitq, mtx);
 946                 }
 947 #endif /* NETGRAPH */
 948                 if (!mtx) {     /* no message?  We're done! */
 949 #if BUGGY > 9
 950                         printf("sr%d.srstart: pending=0, pkts=%d\n",
 951                                sc->unit, pkts);
 952 #endif
 953                         break;
 954                 }
 955         }
 956
 957         blkp->txtail = i;       /* record next free granule */
 958
 959         /*
 960          * Mark the last descriptor, so that the SCA know where to stop.
 961          */
 962         txdesc--;               /* back up to last descriptor in list */
 963         txdesc->stat |= SCA_DESC_EOT;   /* mark as end of list */
 964
 965         /*
 966          * Now we'll reset the transmit granule's descriptor address so we
 967          * can record this in the structure and fire it off w/ the DMA
 968          * processor of the serial chip...
 969          */
 970         txdesc = (sca_descriptor *)blkp->txdesc;
 971         blkp->txeda = (u_short)((u_int)&txdesc[i]);
 972
 973         sc->txb_inuse++;        /* update inuse status */
 974         sc->txb_new++;          /* new traffic wuz added */
 975
 976         if (sc->txb_new == SR_TX_BLOCKS)
 977                 sc->txb_new = 0;
 978
 979         /*
 980          * If the tranmitter wasn't marked as "busy" we will force it to be
 981          * started...
 982          */
 983         if (sc->xmit_busy == 0) {
 984                 sr_xmit(sc);
 985 #if BUGGY > 9
 986                 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
 987 #endif
 988         }
 989         goto top_srstart;
 990 }
 991
 992 #ifndef NETGRAPH
 993 /*
 994  * Handle ioctl's at the device level, though we *will* call up
 995  * a layer...
 996  */
 997 #if BUGGY > 2
 998 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
 999 #endif
1000
1001 static int
1002 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1003 {
1004         int error, was_up, should_be_up;
1005         struct sr_softc *sc = ifp->if_softc;
1006
1007 #if BUGGY > 0
1008         printf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1009                ifp->if_xname, ifp, cmd, data);
1010 #endif
1011
1012         was_up = ifp->if_flags & IFF_RUNNING;
1013
1014         error = sppp_ioctl(ifp, cmd, data);
1015
1016 #if BUGGY > 1
1017         printf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1018               ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1019 #endif
1020
1021         if (error)
1022                 return error;
1023
1024         if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1025 #if BUGGY > 2
1026                 if (bug_splats[sc->unit]++ < 2) {
1027                         printf("sr(%d).if_addrlist = %08x\n",
1028                                sc->unit, ifp->if_addrlist);
1029                         printf("sr(%d).if_bpf = %08x\n",
1030                                sc->unit, ifp->if_bpf);
1031                         printf("sr(%d).if_init = %08x\n",
1032                                sc->unit, ifp->if_init);
1033                         printf("sr(%d).if_output = %08x\n",
1034                                sc->unit, ifp->if_output);
1035                         printf("sr(%d).if_start = %08x\n",
1036                                sc->unit, ifp->if_start);
1037                         printf("sr(%d).if_done = %08x\n",
1038                                sc->unit, ifp->if_done);
1039                         printf("sr(%d).if_ioctl = %08x\n",
1040                                sc->unit, ifp->if_ioctl);
1041                         printf("sr(%d).if_reset = %08x\n",
1042                                sc->unit, ifp->if_reset);
1043                         printf("sr(%d).if_watchdog = %08x\n",
1044                                sc->unit, ifp->if_watchdog);
1045                 }
1046 #endif
1047                 return 0;
1048         }
1049
1050         crit_enter();
1051
1052         should_be_up = ifp->if_flags & IFF_RUNNING;
1053
1054         if (!was_up && should_be_up) {
1055                 /*
1056                  * Interface should be up -- start it.
1057                  */
1058                 sr_up(sc);
1059                 srstart(ifp);
1060
1061                 /*
1062                  * XXX Clear the IFF_UP flag so that the link will only go
1063                  * up after sppp lcp and ipcp negotiation.
1064                  */
1065                 /* ifp->if_flags &= ~IFF_UP; */
1066         } else if (was_up && !should_be_up) {
1067                 /*
1068                  * Interface should be down -- stop it.
1069                  */
1070                 sr_down(sc);
1071                 sppp_flush(ifp);
1072         }
1073
1074         crit_exit();
1075
1076         return 0;
1077 }
1078 #endif /* NETGRAPH */
1079
1080 /*
1081  * This is to catch lost tx interrupts.
1082  */
1083 static void
1084 #ifndef NETGRAPH
1085 srwatchdog(struct ifnet *ifp)
1086 #else
1087 srwatchdog(struct sr_softc *sc)
1088 #endif /* NETGRAPH */
1089 {
1090         int     got_st0, got_st1, got_st3, got_dsr;
1091 #ifndef NETGRAPH
1092         struct sr_softc *sc = ifp->if_softc;
1093 #endif /* NETGRAPH */
1094         struct sr_hardc *hc = sc->hc;
1095         msci_channel *msci = &hc->sca->msci[sc->scachan];
1096         dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1097
1098 #if BUGGY > 0
1099 #ifndef NETGRAPH
1100         printf("srwatchdog(unit=%d)\n", unit);
1101 #else
1102         printf("srwatchdog(unit=%d)\n", sc->unit);
1103 #endif /* NETGRAPH */
1104 #endif
1105
1106 #ifndef NETGRAPH
1107         if (!(ifp->if_flags & IFF_RUNNING))
1108                 return;
1109
1110         ifp->if_oerrors++;      /* update output error count */
1111 #else   /* NETGRAPH */
1112         sc->oerrors++;  /* update output error count */
1113 #endif /* NETGRAPH */
1114
1115         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1116         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1117         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1118         got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1119
1120 #ifndef NETGRAPH
1121 #if     0
1122         if (ifp->if_flags & IFF_DEBUG)
1123 #endif
1124                 printf("sr%d: transmit failed, "
1125 #else   /* NETGRAPH */
1126         printf("sr%d: transmit failed, "
1127 #endif /* NETGRAPH */
1128                        "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1129                        sc->unit,
1130                        got_st0, got_st1, got_st3, got_dsr);
1131
1132         if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1133                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1134                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1135                 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1136         }
1137         sc->xmit_busy = 0;
1138 #ifndef NETGRAPH
1139         ifp->if_flags &= ~IFF_OACTIVE;
1140 #else
1141         /*ifp->if_flags &= ~IFF_OACTIVE; */
1142 #endif /* NETGRAPH */
1143
1144         if (sc->txb_inuse && --sc->txb_inuse)
1145                 sr_xmit(sc);
1146
1147 #ifndef NETGRAPH
1148         srstart(ifp);   /* restart transmitter */
1149 #else
1150         srstart(sc);    /* restart transmitter */
1151 #endif /* NETGRAPH */
1152 }
1153
1154 static void
1155 sr_up(struct sr_softc *sc)
1156 {
1157         u_int *fecrp;
1158         struct sr_hardc *hc = sc->hc;
1159         sca_regs *sca = hc->sca;
1160         msci_channel *msci = &sca->msci[sc->scachan];
1161
1162 #if BUGGY > 0
1163         printf("sr_up(sc=%08x)\n", sc);
1164 #endif
1165
1166         /*
1167          * Enable transmitter and receiver. Raise DTR and RTS. Enable
1168          * interrupts.
1169          *
1170          * XXX What about using AUTO mode in msci->md0 ???
1171          */
1172         SRC_PUT8(hc->sca_base, msci->ctl,
1173                  SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1174
1175         if (sc->scachan == 0)
1176                 switch (hc->cardtype) {
1177                 case SR_CRD_N2:
1178                         outb(hc->iobase + SR_MCR,
1179                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1180                         break;
1181                 case SR_CRD_N2PCI:
1182                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1183                         *fecrp &= ~SR_FECR_DTR0;
1184                         break;
1185                 }
1186         else
1187                 switch (hc->cardtype) {
1188                 case SR_CRD_N2:
1189                         outb(hc->iobase + SR_MCR,
1190                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1191                         break;
1192                 case SR_CRD_N2PCI:
1193                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1194                         *fecrp &= ~SR_FECR_DTR1;
1195                         break;
1196                 }
1197
1198         if (sc->scachan == 0) {
1199                 SRC_PUT8(hc->sca_base, sca->ier0,
1200                          SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1201                 SRC_PUT8(hc->sca_base, sca->ier1,
1202                          SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1203         } else {
1204                 SRC_PUT8(hc->sca_base, sca->ier0,
1205                          SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1206                 SRC_PUT8(hc->sca_base, sca->ier1,
1207                          SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1208         }
1209
1210         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1211         inb(hc->iobase);        /* XXX slow it down a bit. */
1212         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1213
1214 #ifndef NETGRAPH
1215 #ifdef USE_MODEMCK
1216         if (sr_watcher == 0)
1217                 sr_modemck(NULL);
1218 #endif
1219 #else   /* NETGRAPH */
1220         callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
1221         sc->running = 1;
1222 #endif /* NETGRAPH */
1223 }
1224
1225 static void
1226 sr_down(struct sr_softc *sc)
1227 {
1228         u_int *fecrp;
1229         struct sr_hardc *hc = sc->hc;
1230         sca_regs *sca = hc->sca;
1231         msci_channel *msci = &sca->msci[sc->scachan];
1232
1233 #if BUGGY > 0
1234         printf("sr_down(sc=%08x)\n", sc);
1235 #endif
1236 #ifdef NETGRAPH
1237         callout_stop(&sc->sr_timer);
1238         sc->running = 0;
1239 #endif /* NETGRAPH */
1240
1241         /*
1242          * Disable transmitter and receiver. Lower DTR and RTS. Disable
1243          * interrupts.
1244          */
1245         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1246         inb(hc->iobase);        /* XXX slow it down a bit. */
1247         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1248
1249         SRC_PUT8(hc->sca_base, msci->ctl,
1250                  SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1251
1252         if (sc->scachan == 0)
1253                 switch (hc->cardtype) {
1254                 case SR_CRD_N2:
1255                         outb(hc->iobase + SR_MCR,
1256                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1257                         break;
1258                 case SR_CRD_N2PCI:
1259                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1260                         *fecrp |= SR_FECR_DTR0;
1261                         break;
1262                 }
1263         else
1264                 switch (hc->cardtype) {
1265                 case SR_CRD_N2:
1266                         outb(hc->iobase + SR_MCR,
1267                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1268                         break;
1269                 case SR_CRD_N2PCI:
1270                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1271                         *fecrp |= SR_FECR_DTR1;
1272                         break;
1273                 }
1274
1275         if (sc->scachan == 0) {
1276                 SRC_PUT8(hc->sca_base, sca->ier0,
1277                          SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1278                 SRC_PUT8(hc->sca_base, sca->ier1,
1279                          SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1280         } else {
1281                 SRC_PUT8(hc->sca_base, sca->ier0,
1282                          SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1283                 SRC_PUT8(hc->sca_base, sca->ier1,
1284                          SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1285         }
1286 }
1287
1288 /*
1289  * Initialize the card, allocate memory for the sr_softc structures
1290  * and fill in the pointers.
1291  */
1292 static void
1293 src_init(struct sr_hardc *hc)
1294 {
1295         struct sr_softc *sc = hc->sc;
1296         int x;
1297         u_int chanmem;
1298         u_int bufmem;
1299         u_int next;
1300         u_int descneeded;
1301
1302 #if BUGGY > 0
1303         printf("src_init(hc=%08x)\n", hc);
1304 #endif
1305
1306         chanmem = hc->memsize / hc->numports;
1307         next = 0;
1308
1309         for (x = 0; x < hc->numports; x++, sc++) {
1310                 int blk;
1311
1312                 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1313                         sc->block[blk].txdesc = next;
1314                         bufmem = (16 * 1024) / SR_TX_BLOCKS;
1315                         descneeded = bufmem / SR_BUF_SIZ;
1316
1317                         sc->block[blk].txstart = sc->block[blk].txdesc
1318                             + ((((descneeded * sizeof(sca_descriptor))
1319                                  / SR_BUF_SIZ) + 1)
1320                                * SR_BUF_SIZ);
1321
1322                         sc->block[blk].txend = next + bufmem;
1323                         sc->block[blk].txmax =
1324                             (sc->block[blk].txend - sc->block[blk].txstart)
1325                             / SR_BUF_SIZ;
1326                         next += bufmem;
1327
1328 #if BUGGY > 2
1329                         printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1330                                sc->unit, blk,
1331                                sc->block[blk].txdesc, sc->block[blk].txstart);
1332 #endif
1333                 }
1334
1335                 sc->rxdesc = next;
1336                 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1337                 descneeded = bufmem / SR_BUF_SIZ;
1338                 sc->rxstart = sc->rxdesc +
1339                     ((((descneeded * sizeof(sca_descriptor)) /
1340                        SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1341                 sc->rxend = next + bufmem;
1342                 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1343                 next += bufmem;
1344         }
1345 }
1346
1347 /*
1348  * The things done here are channel independent.
1349  *
1350  * Configure the sca waitstates.
1351  * Configure the global interrupt registers.
1352  * Enable master dma enable.
1353  */
1354 static void
1355 sr_init_sca(struct sr_hardc *hc)
1356 {
1357         sca_regs *sca = hc->sca;
1358
1359 #if BUGGY > 0
1360         printf("sr_init_sca(hc=%08x)\n", hc);
1361 #endif
1362
1363         /*
1364          * Do the wait registers. Set everything to 0 wait states.
1365          */
1366         SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1367         SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1368         SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1369         SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1370         SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1371
1372         /*
1373          * Configure the interrupt registers. Most are cleared until the
1374          * interface is configured.
1375          */
1376         SRC_PUT8(hc->sca_base, sca->ier0, 0x00);        /* MSCI interrupts. */
1377         SRC_PUT8(hc->sca_base, sca->ier1, 0x00);        /* DMAC interrupts */
1378         SRC_PUT8(hc->sca_base, sca->ier2, 0x00);        /* TIMER interrupts. */
1379         SRC_PUT8(hc->sca_base, sca->itcr, 0x00);        /* Use ivr and no intr
1380                                                          * ack */
1381         SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1382         SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1383
1384         /*
1385          * Configure the timers. XXX Later
1386          */
1387
1388         /*
1389          * Set the DMA channel priority to rotate between all four channels.
1390          *
1391          * Enable all dma channels.
1392          */
1393         SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1394         SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1395 }
1396
1397 /*
1398  * Configure the msci
1399  *
1400  * NOTE: The serial port configuration is hardcoded at the moment.
1401  */
1402 static void
1403 sr_init_msci(struct sr_softc *sc)
1404 {
1405         int portndx;            /* on-board port number */
1406         u_int mcr_v;            /* contents of modem control */
1407         u_int *fecrp;           /* pointer for PCI's MCR i/o */
1408         struct sr_hardc *hc = sc->hc;
1409         msci_channel *msci = &hc->sca->msci[sc->scachan];
1410 #ifdef N2_TEST_SPEED
1411         int br_v;               /* contents for BR divisor */
1412         int etcndx;             /* index into ETC table */
1413         int fifo_v, gotspeed;   /* final tabled speed found */
1414         int tmc_v;              /* timer control register */
1415         int wanted;             /* speed (bitrate) wanted... */
1416         struct rate_line *rtp;
1417 #endif
1418
1419         portndx = sc->scachan;
1420
1421 #if BUGGY > 0
1422         printf("sr: sr_init_msci( sc=%08x)\n", sc);
1423 #endif
1424
1425         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1426         SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1427                  SCA_MD0_CRC_CCITT |
1428                  SCA_MD0_CRC_ENABLE |
1429                  SCA_MD0_MODE_HDLC);
1430         SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1431         SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1432
1433         /*
1434          * According to the manual I should give a reset after changing the
1435          * mode registers.
1436          */
1437         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1438         SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1439                  SCA_CTL_UDRNC |
1440                  SCA_CTL_RTS);
1441
1442         /*
1443          * XXX Later we will have to support different clock settings.
1444          */
1445         switch (sc->clk_cfg) {
1446         default:
1447 #if BUGGY > 0
1448                 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1449                        portndx, sc->clk_cfg);
1450 #endif
1451                 /* FALLTHROUGH */
1452         case SR_FLAGS_EXT_CLK:
1453                 /*
1454                  * For now all interfaces are programmed to use the RX clock
1455                  * for the TX clock.
1456                  */
1457
1458 #if BUGGY > 0
1459                 printf("sr%d: External Clock Selected.\n", portndx);
1460 #endif
1461
1462                 SRC_PUT8(hc->sca_base, msci->rxs,
1463                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1464                 SRC_PUT8(hc->sca_base, msci->txs,
1465                          SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1466                 break;
1467
1468         case SR_FLAGS_EXT_SEP_CLK:
1469 #if BUGGY > 0
1470                 printf("sr%d: Split Clocking Selected.\n", portndx);
1471 #endif
1472
1473                 SRC_PUT8(hc->sca_base, msci->rxs,
1474                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1475                 SRC_PUT8(hc->sca_base, msci->txs,
1476                          SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1477                 break;
1478
1479         case SR_FLAGS_INT_CLK:
1480 #if BUGGY > 0
1481                 printf("sr%d: Internal Clocking selected.\n", portndx);
1482 #endif
1483
1484                 /*
1485                  * XXX I do need some code to set the baud rate here!
1486                  */
1487 #ifdef N2_TEST_SPEED
1488                 switch (hc->cardtype) {
1489                 case SR_CRD_N2PCI:
1490                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1491                         mcr_v = *fecrp;
1492                         etcndx = 2;
1493                         break;
1494                 case SR_CRD_N2:
1495                 default:
1496                         mcr_v = inb(hc->iobase + SR_MCR);
1497                         etcndx = 0;
1498                 }
1499
1500                 fifo_v = 0x10;  /* stolen from Linux version */
1501
1502                 /*
1503                  * search for appropriate speed in table, don't calc it:
1504                  */
1505                 wanted = sr_test_speed[portndx];
1506                 rtp = &n2_rates[0];     /* point to first table item */
1507
1508                 while ((rtp->target > 0)        /* search table for speed */
1509                        &&(rtp->target != wanted))
1510                         rtp++;
1511
1512                 /*
1513                  * We've searched the table for a matching speed.  If we've
1514                  * found the correct rate line, we'll get the pre-calc'd
1515                  * values for the TMC and baud rate divisor for subsequent
1516                  * use...
1517                  */
1518                 if (rtp->target > 0) {  /* use table-provided values */
1519                         gotspeed = wanted;
1520                         tmc_v = rtp->tmc_reg;
1521                         br_v = rtp->br_reg;
1522                 } else {        /* otherwise assume 1MBit comm rate */
1523                         gotspeed = 10000;
1524                         tmc_v = 5;
1525                         br_v = 1;
1526                 }
1527
1528                 /*
1529                  * Now we mask in the enable clock output for the MCR:
1530                  */
1531                 mcr_v |= etc0vals[etcndx + portndx];
1532
1533                 /*
1534                  * Now we'll program the registers with these speed- related
1535                  * contents...
1536                  */
1537                 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1538                 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1539                 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1540                 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1541
1542                 switch (hc->cardtype) {
1543                 case SR_CRD_N2PCI:
1544                         *fecrp = mcr_v;
1545                         break;
1546                 case SR_CRD_N2:
1547                 default:
1548                         outb(hc->iobase + SR_MCR, mcr_v);
1549                 }
1550
1551 #if BUGGY > 0
1552                 if (wanted != gotspeed)
1553                         printf("sr%d: Speed wanted=%d, found=%d\n",
1554                                wanted, gotspeed);
1555
1556                 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1557                        portndx, gotspeed, tmc_v, br_v);
1558 #endif
1559 #else
1560                 SRC_PUT8(hc->sca_base, msci->rxs,
1561                          SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1562                 SRC_PUT8(hc->sca_base, msci->txs,
1563                          SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1564
1565                 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1566
1567                 if (portndx == 0)
1568                         switch (hc->cardtype) {
1569                         case SR_CRD_N2PCI:
1570                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1571                                 *fecrp |= SR_FECR_ETC0;
1572                                 break;
1573                         case SR_CRD_N2:
1574                         default:
1575                                 mcr_v = inb(hc->iobase + SR_MCR);
1576                                 mcr_v |= SR_MCR_ETC0;
1577                                 outb(hc->iobase + SR_MCR, mcr_v);
1578                         }
1579                 else
1580                         switch (hc->cardtype) {
1581                         case SR_CRD_N2:
1582                                 mcr_v = inb(hc->iobase + SR_MCR);
1583                                 mcr_v |= SR_MCR_ETC1;
1584                                 outb(hc->iobase + SR_MCR, mcr_v);
1585                                 break;
1586                         case SR_CRD_N2PCI:
1587                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1588                                 *fecrp |= SR_FECR_ETC1;
1589                                 break;
1590                         }
1591 #endif
1592         }
1593
1594         /*
1595          * XXX Disable all interrupts for now. I think if you are using the
1596          * dmac you don't use these interrupts.
1597          */
1598         SRC_PUT8(hc->sca_base, msci->ie0, 0);
1599         SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1600         SRC_PUT8(hc->sca_base, msci->ie2, 0);
1601         SRC_PUT8(hc->sca_base, msci->fie, 0);
1602
1603         SRC_PUT8(hc->sca_base, msci->sa0, 0);
1604         SRC_PUT8(hc->sca_base, msci->sa1, 0);
1605
1606         SRC_PUT8(hc->sca_base, msci->idl, 0x7E);        /* set flags value */
1607
1608         SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1609         SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1610         SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1611 }
1612
1613 /*
1614  * Configure the rx dma controller.
1615  */
1616 static void
1617 sr_init_rx_dmac(struct sr_softc *sc)
1618 {
1619         struct sr_hardc *hc;
1620         dmac_channel *dmac;
1621         sca_descriptor *rxd;
1622         u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1623
1624 #if BUGGY > 0
1625         printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1626 #endif
1627
1628         hc = sc->hc;
1629         dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1630
1631         if (hc->mempages)
1632                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1633
1634         /*
1635          * This phase initializes the contents of the descriptor table
1636          * needed to construct a circular buffer...
1637          */
1638         rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1639         rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1640
1641         for (rxbuf = sc->rxstart;
1642              rxbuf < sc->rxend;
1643              rxbuf += SR_BUF_SIZ, rxd++) {
1644                 /*
1645                  * construct the circular chain...
1646                  */
1647                 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1648                 rxd->cp = (u_short)(rxda & 0xffff);
1649
1650                 /*
1651                  * set the on-card buffer address...
1652                  */
1653                 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1654                 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1655
1656                 rxd->len = 0;   /* bytes resident w/in granule */
1657                 rxd->stat = 0xff;       /* The sca write here when finished */
1658         }
1659
1660         /*
1661          * heal the chain so that the last entry points to the first...
1662          */
1663         rxd--;
1664         rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1665
1666         /*
1667          * reset the reception handler's index...
1668          */
1669         sc->rxhind = 0;
1670
1671         /*
1672          * We'll now configure the receiver's DMA logic...
1673          */
1674         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA transfer */
1675         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1676
1677         /* XXX maybe also SCA_DMR_CNTE */
1678         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1679         SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1680
1681         cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1682         sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1683
1684         SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1685         SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1686
1687         rxd = (sca_descriptor *)sc->rxstart;
1688
1689         SRC_PUT16(hc->sca_base, dmac->eda,
1690                   (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1691
1692         SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1693
1694
1695         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);  /* Enable DMA */
1696 }
1697
1698 /*
1699  * Configure the TX DMA descriptors.
1700  * Initialize the needed values and chain the descriptors.
1701  */
1702 static void
1703 sr_init_tx_dmac(struct sr_softc *sc)
1704 {
1705         int blk;
1706         u_int txbuf, txda, txda_d;
1707         struct sr_hardc *hc;
1708         sca_descriptor *txd;
1709         dmac_channel *dmac;
1710         struct buf_block *blkp;
1711         u_int x;
1712         u_int sarb_v;
1713
1714 #if BUGGY > 0
1715         printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1716 #endif
1717
1718         hc = sc->hc;
1719         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1720
1721         if (hc->mempages)
1722                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1723
1724         /*
1725          * Initialize the array of descriptors for transmission
1726          */
1727         for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1728                 blkp = &sc->block[blk];
1729                 txd = (sca_descriptor *)(hc->mem_start
1730                                          + (blkp->txdesc & hc->winmsk));
1731                 txda_d = (u_int) hc->mem_start
1732                     - (blkp->txdesc & ~hc->winmsk);
1733
1734                 x = 0;
1735                 txbuf = blkp->txstart;
1736                 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1737                         txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1738                         txd->cp = (u_short)(txda & 0xffff);
1739
1740                         txd->bp = (u_short)((txbuf + hc->mem_pstart)
1741                                             & 0xffff);
1742                         txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1743                                             & 0xff);
1744                         txd->len = 0;
1745                         txd->stat = 0;
1746                         x++;
1747                 }
1748
1749                 txd--;
1750                 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1751                                     & 0xffff);
1752
1753                 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1754         }
1755
1756         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA */
1757         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1758         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1759         SRC_PUT8(hc->sca_base, dmac->dir,
1760                  SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1761
1762         sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1763         sarb_v &= 0x00ff;
1764
1765         SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1766 }
1767
1768 /*
1769  * Look through the descriptors to see if there is a complete packet
1770  * available. Stop if we get to where the sca is busy.
1771  *
1772  * Return the length and status of the packet.
1773  * Return nonzero if there is a packet available.
1774  *
1775  * NOTE:
1776  * It seems that we get the interrupt a bit early. The updateing of
1777  * descriptor values is not always completed when this is called.
1778  */
1779 static int
1780 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1781 {
1782         int granules;   /* count of granules in pkt */
1783         int wki, wko;
1784         struct sr_hardc *hc;
1785         sca_descriptor *rxdesc; /* current descriptor */
1786         sca_descriptor *endp;   /* ending descriptor */
1787         sca_descriptor *cda;    /* starting descriptor */
1788
1789         hc = sc->hc;            /* get card's information */
1790
1791         /*
1792          * set up starting descriptor by pulling that info from the DMA half
1793          * of the HD chip...
1794          */
1795         wki = DMAC_RXCH(sc->scachan);
1796         wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1797
1798         cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1799
1800 #if BUGGY > 1
1801         printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1802                wki, wko, cda);
1803 #endif
1804
1805         /*
1806          * open the appropriate memory window and set our expectations...
1807          */
1808         if (hc->mempages) {
1809                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1810                 SRC_SET_ON(hc->iobase);
1811         }
1812         rxdesc = (sca_descriptor *)
1813             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1814         endp = rxdesc;
1815         rxdesc = &rxdesc[sc->rxhind];
1816         endp = &endp[sc->rxmax];
1817
1818         *len = 0;               /* reset result total length */
1819         granules = 0;           /* reset count of granules */
1820
1821         /*
1822          * This loop will scan descriptors, but it *will* puke up if we wrap
1823          * around to our starting point...
1824          */
1825         while (rxdesc != cda) {
1826                 *len += rxdesc->len;    /* increment result length */
1827                 granules++;
1828
1829                 /*
1830                  * If we hit a valid packet's completion we'll know we've
1831                  * got a live one, and that we can deliver the packet.
1832                  * Since we're only allowed to report a packet available,
1833                  * somebody else does that...
1834                  */
1835                 if (rxdesc->stat & SCA_DESC_EOM) {      /* End Of Message */
1836                         *rxstat = rxdesc->stat; /* return closing */
1837 #if BUGGY > 0
1838                         printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1839                                sc->unit, *len, *rxstat, granules);
1840 #endif
1841                         return 1;       /* indicate success */
1842                 }
1843                 /*
1844                  * OK, this packet take up multiple granules.  Move on to
1845                  * the next descriptor so we can consider it...
1846                  */
1847                 rxdesc++;
1848
1849                 if (rxdesc == endp)     /* recognize & act on wrap point */
1850                         rxdesc = (sca_descriptor *)
1851                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1852         }
1853
1854         /*
1855          * Nothing found in the DPRAM.  Let the caller know...
1856          */
1857         *len = 0;
1858         *rxstat = 0;
1859
1860         return 0;
1861 }
1862
1863 /*
1864  * Copy a packet from the on card memory into a provided mbuf.
1865  * Take into account that buffers wrap and that a packet may
1866  * be larger than a buffer.
1867  */
1868 static void
1869 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1870 {
1871         struct sr_hardc *hc;
1872         sca_descriptor *rxdesc;
1873         u_int rxdata;
1874         u_int rxmax;
1875         u_int off = 0;
1876         u_int tlen;
1877
1878 #if BUGGY > 0
1879         printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1880                m, sc, len);
1881 #endif
1882
1883         hc = sc->hc;
1884
1885         rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1886         rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1887
1888         rxdesc = (sca_descriptor *)
1889             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1890         rxdesc = &rxdesc[sc->rxhind];
1891
1892         /*
1893          * Using the count of bytes in the received packet, we decrement it
1894          * for each granule (controller by an SCA descriptor) to control the
1895          * looping...
1896          */
1897         while (len) {
1898                 /*
1899                  * tlen gets the length of *this* granule... ...which is
1900                  * then copied to the target buffer.
1901                  */
1902                 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1903
1904                 if (hc->mempages)
1905                         SRC_SET_MEM(hc->iobase, rxdata);
1906
1907                 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1908                       mtod(m, caddr_t) +off,
1909                       tlen);
1910
1911                 off += tlen;
1912                 len -= tlen;
1913
1914                 /*
1915                  * now, return to the descriptor's window in DPRAM and reset
1916                  * the descriptor we've just suctioned...
1917                  */
1918                 if (hc->mempages)
1919                         SRC_SET_MEM(hc->iobase, sc->rxdesc);
1920
1921                 rxdesc->len = 0;
1922                 rxdesc->stat = 0xff;
1923
1924                 /*
1925                  * Move on to the next granule.  If we've any remaining
1926                  * bytes to process we'll just continue in our loop...
1927                  */
1928                 rxdata += SR_BUF_SIZ;
1929                 rxdesc++;
1930
1931                 if (rxdata == rxmax) {  /* handle the wrap point */
1932                         rxdata = sc->rxstart;
1933                         rxdesc = (sca_descriptor *)
1934                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1935                 }
1936         }
1937 }
1938
1939 /*
1940  * If single is set, just eat a packet. Otherwise eat everything up to
1941  * where cda points. Update pointers to point to the next packet.
1942  *
1943  * This handles "flushing" of a packet as received...
1944  *
1945  * If the "single" parameter is zero, all pending reeceive traffic will
1946  * be flushed out of existence.  A non-zero value will only drop the
1947  * *next* (currently) pending packet...
1948  */
1949 static void
1950 sr_eat_packet(struct sr_softc *sc, int single)
1951 {
1952         struct sr_hardc *hc;
1953         sca_descriptor *rxdesc; /* current descriptor being eval'd */
1954         sca_descriptor *endp;   /* last descriptor in chain */
1955         sca_descriptor *cda;    /* current start point */
1956         u_int loopcnt = 0;      /* count of packets flushed ??? */
1957         u_char stat;            /* captured status byte from descr */
1958
1959         hc = sc->hc;
1960         cda = (sca_descriptor *)(hc->mem_start +
1961                                  (SRC_GET16(hc->sca_base,
1962                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1963                                   hc->winmsk));
1964
1965         /*
1966          * loop until desc->stat == (0xff || EOM) Clear the status and
1967          * length in the descriptor. Increment the descriptor.
1968          */
1969         if (hc->mempages)
1970                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1971
1972         rxdesc = (sca_descriptor *)
1973             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1974         endp = rxdesc;
1975         rxdesc = &rxdesc[sc->rxhind];
1976         endp = &endp[sc->rxmax];
1977
1978         /*
1979          * allow loop, but abort it if we wrap completely...
1980          */
1981         while (rxdesc != cda) {
1982                 loopcnt++;
1983
1984                 if (loopcnt > sc->rxmax) {
1985                         printf("sr%d: eat pkt %d loop, cda %x, "
1986                                "rxdesc %x, stat %x.\n",
1987                                sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1988                                rxdesc->stat);
1989                         break;
1990                 }
1991                 stat = rxdesc->stat;
1992
1993                 rxdesc->len = 0;
1994                 rxdesc->stat = 0xff;
1995
1996                 rxdesc++;
1997                 sc->rxhind++;
1998
1999                 if (rxdesc == endp) {
2000                         rxdesc = (sca_descriptor *)
2001                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
2002                         sc->rxhind = 0;
2003                 }
2004                 if (single && (stat == SCA_DESC_EOM))
2005                         break;
2006         }
2007
2008         /*
2009          * Update the eda to the previous descriptor.
2010          */
2011         rxdesc = (sca_descriptor *)sc->rxdesc;
2012         rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2013
2014         SRC_PUT16(hc->sca_base,
2015                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2016                   (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2017 }
2018
2019 /*
2020  * While there is packets available in the rx buffer, read them out
2021  * into mbufs and ship them off.
2022  */
2023 static void
2024 sr_get_packets(struct sr_softc *sc)
2025 {
2026         u_char rxstat;          /* acquired status byte */
2027         int i;
2028         int pkts;               /* count of packets found */
2029         int rxndx;              /* rcv buffer index */
2030         int tries;              /* settling time counter */
2031         u_int len;              /* length of pending packet */
2032         struct sr_hardc *hc;    /* card-level information */
2033         sca_descriptor *rxdesc; /* descriptor in memory */
2034 #ifndef NETGRAPH
2035         struct ifnet *ifp;      /* network intf ctl table */
2036 #endif /* NETGRAPH */
2037         struct mbuf *m = NULL;  /* message buffer */
2038
2039 #if BUGGY > 0
2040         printf("sr_get_packets(sc=%08x)\n", sc);
2041 #endif
2042
2043         hc = sc->hc;
2044 #ifndef NETGRAPH
2045         ifp = &sc->ifsppp.pp_if;
2046 #endif /* NETGRAPH */
2047
2048         if (hc->mempages) {
2049                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2050                 SRC_SET_ON(hc->iobase); /* enable shared memory */
2051         }
2052         pkts = 0;               /* reset count of found packets */
2053
2054         /*
2055          * for each complete packet in the receiving pool, process each
2056          * packet...
2057          */
2058         while (sr_packet_avail(sc, &len, &rxstat)) {    /* packet pending? */
2059                 /*
2060                  * I have seen situations where we got the interrupt but the
2061                  * status value wasn't deposited.  This code should allow
2062                  * the status byte's value to settle...
2063                  */
2064
2065                 tries = 5;
2066
2067                 while ((rxstat == 0x00ff)
2068                        && --tries)
2069                         sr_packet_avail(sc, &len, &rxstat);
2070
2071 #if BUGGY > 1
2072                 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2073                        len, rxstat);
2074 #endif
2075
2076                 pkts++;
2077 #ifdef NETGRAPH
2078                 sc->inbytes += len;
2079                 sc->inlast = 0;
2080 #endif /* NETGRAPH */
2081
2082                 /*
2083                  * OK, we've settled the incoming message status. We can now
2084                  * process it...
2085                  */
2086                 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2087 #if BUGGY > 1
2088                         printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2089                                sc->unit, rxstat, len);
2090 #endif
2091
2092                         MGETHDR(m, MB_DONTWAIT, MT_DATA);
2093                         if (m == NULL) {
2094                                 /*
2095                                  * eat (flush) packet if get mbuf fail!!
2096                                  */
2097                                 sr_eat_packet(sc, 1);
2098                                 continue;
2099                         }
2100                         /*
2101                          * construct control information for pass-off
2102                          */
2103 #ifndef NETGRAPH
2104                         m->m_pkthdr.rcvif = ifp;
2105 #else
2106                         m->m_pkthdr.rcvif = NULL;
2107 #endif /* NETGRAPH */
2108                         m->m_pkthdr.len = m->m_len = len;
2109                         if (len > MHLEN) {
2110                                 MCLGET(m, MB_DONTWAIT);
2111                                 if ((m->m_flags & M_EXT) == 0) {
2112                                         /*
2113                                          * We couldn't get a big enough
2114                                          * message packet, so we'll send the
2115                                          * packet to /dev/null...
2116                                          */
2117                                         m_freem(m);
2118                                         sr_eat_packet(sc, 1);
2119                                         continue;
2120                                 }
2121                         }
2122                         /*
2123                          * OK, we've got a good message buffer.  Now we can
2124                          * copy the received message into it
2125                          */
2126                         sr_copy_rxbuf(m, sc, len);      /* copy from DPRAM */
2127
2128 #ifndef NETGRAPH
2129                         BPF_MTAP(ifp, m);
2130
2131 #if BUGGY > 3
2132                         {
2133                                 u_char *bp;
2134
2135                                 bp = (u_char *)m;
2136                                 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2137                                        sc->unit,
2138                                        bp[0], bp[1], bp[2],
2139                                        bp[4], bp[5], bp[6]);
2140                         }
2141 #endif
2142                         sppp_input(ifp, m);
2143                         ifp->if_ipackets++;
2144
2145 #else   /* NETGRAPH */
2146 #if BUGGY > 3
2147                         {
2148                                 u_char *bp;
2149
2150                                 bp = mtod(m,u_char *);
2151                                 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2152                                        sc->unit,
2153                                        bp[0], bp[1], bp[2],
2154                                        bp[4], bp[5], bp[6]);
2155                                 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2156                                        bp[6], bp[7], bp[8],
2157                                        bp[9], bp[10], bp[11]);
2158                         }
2159 #endif
2160                         ng_queue_data(sc->hook, m, NULL);
2161                         sc->ipackets++;
2162 #endif /* NETGRAPH */
2163                         /*
2164                          * Update the eda to the previous descriptor.
2165                          */
2166                         i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2167                         sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2168
2169                         rxdesc = (sca_descriptor *)sc->rxdesc;
2170                         rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2171                         rxdesc = &rxdesc[rxndx];
2172
2173                         SRC_PUT16(hc->sca_base,
2174                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2175                                   (u_short)((u_int)(rxdesc + hc->mem_pstart)
2176                                              & 0xffff));
2177
2178                 } else {
2179                         int got_st3, got_cda, got_eda;
2180                         int tries = 5;
2181
2182                         while ((rxstat == 0xff) && --tries)
2183                                 sr_packet_avail(sc, &len, &rxstat);
2184
2185                         /*
2186                          * It look like we get an interrupt early
2187                          * sometimes and then the status is not
2188                          * filled in yet.
2189                          */
2190                         if (tries && (tries != 5))
2191                                 continue;
2192
2193                         /*
2194                          * This chunk of code handles the error packets.
2195                          * We'll log them for posterity...
2196                          */
2197                         sr_eat_packet(sc, 1);
2198
2199 #ifndef NETGRAPH
2200                         ifp->if_ierrors++;
2201 #else
2202                         sc->ierrors[0]++;
2203 #endif /* NETGRAPH */
2204
2205                         got_st3 = SRC_GET8(hc->sca_base,
2206                                   hc->sca->msci[sc->scachan].st3);
2207                         got_cda = SRC_GET16(hc->sca_base,
2208                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2209                         got_eda = SRC_GET16(hc->sca_base,
2210                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2211
2212 #if BUGGY > 0
2213                         printf("sr%d: Receive error chan %d, "
2214                                "stat %02x, msci st3 %02x,"
2215                                "rxhind %d, cda %04x, eda %04x.\n",
2216                                sc->unit, sc->scachan, rxstat,
2217                                got_st3, sc->rxhind, got_cda, got_eda);
2218 #endif
2219                 }
2220         }
2221
2222 #if BUGGY > 0
2223         printf("sr%d: sr_get_packets() found %d packet(s)\n",
2224                sc->unit, pkts);
2225 #endif
2226
2227         if (hc->mempages)
2228                 SRC_SET_OFF(hc->iobase);
2229 }
2230
2231 /*
2232  * All DMA interrupts come here.
2233  *
2234  * Each channel has two interrupts.
2235  * Interrupt A for errors and Interrupt B for normal stuff like end
2236  * of transmit or receive dmas.
2237  */
2238 static void
2239 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2240 {
2241         u_char dsr;             /* contents of DMA Stat Reg */
2242         u_char dotxstart;       /* enables for tranmit part */
2243         int mch;                /* channel being processed */
2244         struct sr_softc *sc;    /* channel's softc structure */
2245         sca_regs *sca = hc->sca;
2246         dmac_channel *dmac;     /* dma structure of chip */
2247
2248 #if BUGGY > 0
2249         printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2250 #endif
2251
2252         mch = 0;                /* assume chan0 on card */
2253         dotxstart = isr1;       /* copy for xmitter starts */
2254
2255         /*
2256          * Shortcut if there is no interrupts for dma channel 0 or 1.
2257          * Skip processing for channel 0 if no incoming hit
2258          */
2259         if ((isr1 & 0x0F) == 0) {
2260                 mch = 1;
2261                 isr1 >>= 4;
2262         }
2263         do {
2264                 sc = &hc->sc[mch];
2265
2266                 /*
2267                  * Transmit channel - DMA Status Register Evaluation
2268                  */
2269                 if (isr1 & 0x0C) {
2270                         dmac = &sca->dmac[DMAC_TXCH(mch)];
2271
2272                         /*
2273                          * get the DMA Status Register contents and write
2274                          * back to reset interrupt...
2275                          */
2276                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2277                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2278
2279                         /*
2280                          * Check for (& process) a Counter overflow
2281                          */
2282                         if (dsr & SCA_DSR_COF) {
2283                                 printf("sr%d: TX DMA Counter overflow, "
2284                                        "txpacket no %lu.\n",
2285 #ifndef NETGRAPH
2286                                        sc->unit, sc->ifsppp.pp_if.if_opackets);
2287                                 sc->ifsppp.pp_if.if_oerrors++;
2288 #else
2289                                        sc->unit, sc->opackets);
2290                                 sc->oerrors++;
2291 #endif /* NETGRAPH */
2292                         }
2293                         /*
2294                          * Check for (& process) a Buffer overflow
2295                          */
2296                         if (dsr & SCA_DSR_BOF) {
2297                                 printf("sr%d: TX DMA Buffer overflow, "
2298                                        "txpacket no %lu, dsr %02x, "
2299                                        "cda %04x, eda %04x.\n",
2300 #ifndef NETGRAPH
2301                                        sc->unit, sc->ifsppp.pp_if.if_opackets,
2302 #else
2303                                        sc->unit, sc->opackets,
2304 #endif /* NETGRAPH */
2305                                        dsr,
2306                                        SRC_GET16(hc->sca_base, dmac->cda),
2307                                        SRC_GET16(hc->sca_base, dmac->eda));
2308 #ifndef NETGRAPH
2309                                 sc->ifsppp.pp_if.if_oerrors++;
2310 #else
2311                                 sc->oerrors++;
2312 #endif /* NETGRAPH */
2313                         }
2314                         /*
2315                          * Check for (& process) an End of Transfer (OK)
2316                          */
2317                         if (dsr & SCA_DSR_EOT) {
2318                                 /*
2319                                  * This should be the most common case.
2320                                  *
2321                                  * Clear the IFF_OACTIVE flag.
2322                                  *
2323                                  * Call srstart to start a new transmit if
2324                                  * there is data to transmit.
2325                                  */
2326 #if BUGGY > 0
2327                                 printf("sr%d: TX Completed OK\n", sc->unit);
2328 #endif
2329                                 sc->xmit_busy = 0;
2330 #ifndef NETGRAPH
2331                                 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2332                                 sc->ifsppp.pp_if.if_timer = 0;
2333 #else
2334                                 /* XXX may need to mark tx inactive? */
2335                                 sc->out_deficit++;
2336                                 sc->out_dog = DOG_HOLDOFF;
2337 #endif /* NETGRAPH */
2338
2339                                 if (sc->txb_inuse && --sc->txb_inuse)
2340                                         sr_xmit(sc);
2341                         }
2342                 }
2343                 /*
2344                  * Receive channel processing of DMA Status Register
2345                  */
2346                 if (isr1 & 0x03) {
2347                         dmac = &sca->dmac[DMAC_RXCH(mch)];
2348
2349                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2350                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2351
2352                         /*
2353                          * End of frame processing (MSG OK?)
2354                          */
2355                         if (dsr & SCA_DSR_EOM) {
2356 #if BUGGY > 0
2357                                 int tt, ind;
2358
2359 #ifndef NETGRAPH
2360                                 tt = sc->ifsppp.pp_if.if_ipackets;
2361 #else   /* NETGRAPH */
2362                                 tt = sc->ipackets;
2363 #endif /* NETGRAPH */
2364                                 ind = sc->rxhind;
2365 #endif
2366
2367                                 sr_get_packets(sc);
2368 #if BUGGY > 0
2369 #ifndef NETGRAPH
2370                                 if (tt == sc->ifsppp.pp_if.if_ipackets)
2371 #else   /* NETGRAPH */
2372                                 if (tt == sc->ipackets)
2373 #endif /* NETGRAPH */
2374                                 {
2375                                         sca_descriptor *rxdesc;
2376                                         int i;
2377
2378                                         printf("SR: RXINTR isr1 %x, dsr %x, "
2379                                                "no data %d pkts, orxind %d.\n",
2380                                                dotxstart, dsr, tt, ind);
2381                                         printf("SR: rxdesc %x, rxstart %x, "
2382                                                "rxend %x, rxhind %d, "
2383                                                "rxmax %d.\n",
2384                                                sc->rxdesc, sc->rxstart,
2385                                                sc->rxend, sc->rxhind,
2386                                                sc->rxmax);
2387                                         printf("SR: cda %x, eda %x.\n",
2388                                             SRC_GET16(hc->sca_base, dmac->cda),
2389                                             SRC_GET16(hc->sca_base, dmac->eda));
2390
2391                                         if (hc->mempages) {
2392                                                 SRC_SET_ON(hc->iobase);
2393                                                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2394                                         }
2395                                         rxdesc = (sca_descriptor *)
2396                                                  (hc->mem_start +
2397                                                   (sc->rxdesc & hc->winmsk));
2398                                         rxdesc = &rxdesc[sc->rxhind];
2399
2400                                         for (i = 0; i < 3; i++, rxdesc++)
2401                                                 printf("SR: rxdesc->stat %x, "
2402                                                        "len %d.\n",
2403                                                        rxdesc->stat,
2404                                                        rxdesc->len);
2405
2406                                         if (hc->mempages)
2407                                                 SRC_SET_OFF(hc->iobase);
2408                                 }
2409 #endif /* BUGGY */
2410                         }
2411                         /*
2412                          * Check for Counter overflow
2413                          */
2414                         if (dsr & SCA_DSR_COF) {
2415                                 printf("sr%d: RX DMA Counter overflow, "
2416                                        "rxpkts %lu.\n",
2417 #ifndef NETGRAPH
2418                                        sc->unit, sc->ifsppp.pp_if.if_ipackets);
2419                                 sc->ifsppp.pp_if.if_ierrors++;
2420 #else   /* NETGRAPH */
2421                                        sc->unit, sc->ipackets);
2422                                 sc->ierrors[1]++;
2423 #endif /* NETGRAPH */
2424                         }
2425                         /*
2426                          * Check for Buffer overflow
2427                          */
2428                         if (dsr & SCA_DSR_BOF) {
2429                                 printf("sr%d: RX DMA Buffer overflow, "
2430                                        "rxpkts %lu, rxind %d, "
2431                                        "cda %x, eda %x, dsr %x.\n",
2432 #ifndef NETGRAPH
2433                                        sc->unit, sc->ifsppp.pp_if.if_ipackets,
2434 #else   /* NETGRAPH */
2435                                        sc->unit, sc->ipackets,
2436 #endif /* NETGRAPH */
2437                                        sc->rxhind,
2438                                        SRC_GET16(hc->sca_base, dmac->cda),
2439                                        SRC_GET16(hc->sca_base, dmac->eda),
2440                                        dsr);
2441
2442                                 /*
2443                                  * Make sure we eat as many as possible.
2444                                  * Then get the system running again.
2445                                  */
2446                                 if (hc->mempages)
2447                                         SRC_SET_ON(hc->iobase);
2448
2449                                 sr_eat_packet(sc, 0);
2450 #ifndef NETGRAPH
2451                                 sc->ifsppp.pp_if.if_ierrors++;
2452 #else   /* NETGRAPH */
2453                                 sc->ierrors[2]++;
2454 #endif /* NETGRAPH */
2455
2456                                 SRC_PUT8(hc->sca_base,
2457                                          sca->msci[mch].cmd,
2458                                          SCA_CMD_RXMSGREJ);
2459
2460                                 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2461
2462 #if BUGGY > 0
2463                                 printf("sr%d: RX DMA Buffer overflow, "
2464                                        "rxpkts %lu, rxind %d, "
2465                                        "cda %x, eda %x, dsr %x. After\n",
2466                                        sc->unit,
2467 #ifndef NETGRAPH
2468                                        sc->ipackets,
2469 #else   /* NETGRAPH */
2470                                        sc->ifsppp.pp_if.if_ipackets,
2471 #endif /* NETGRAPH */
2472                                        sc->rxhind,
2473                                        SRC_GET16(hc->sca_base, dmac->cda),
2474                                        SRC_GET16(hc->sca_base, dmac->eda),
2475                                        SRC_GET8(hc->sca_base, dmac->dsr));
2476 #endif
2477
2478                                 if (hc->mempages)
2479                                         SRC_SET_OFF(hc->iobase);
2480                         }
2481                         /*
2482                          * End of Transfer
2483                          */
2484                         if (dsr & SCA_DSR_EOT) {
2485                                 /*
2486                                  * If this happen, it means that we are
2487                                  * receiving faster than what the processor
2488                                  * can handle.
2489                                  *
2490                                  * XXX We should enable the dma again.
2491                                  */
2492                                 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2493                                        sc->unit,
2494 #ifndef NETGRAPH
2495                                        sc->ifsppp.pp_if.if_ipackets);
2496                                 sc->ifsppp.pp_if.if_ierrors++;
2497 #else
2498                                        sc->ipackets);
2499                                 sc->ierrors[3]++;
2500 #endif /* NETGRAPH */
2501                         }
2502                 }
2503                 isr1 >>= 4;     /* process next half of ISR */
2504                 mch++;          /* and move to next channel */
2505         } while ((mch < NCHAN) && isr1);        /* loop for each chn */
2506
2507         /*
2508          * Now that we have done all the urgent things, see if we can fill
2509          * the transmit buffers.
2510          */
2511         for (mch = 0; mch < NCHAN; mch++) {
2512                 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2513                         sc = &hc->sc[mch];
2514 #ifndef NETGRAPH
2515                         srstart(&sc->ifsppp.pp_if);
2516 #else
2517                         srstart(sc);
2518 #endif /* NETGRAPH */
2519                 }
2520                 dotxstart >>= 4;/* shift for next channel */
2521         }
2522 }
2523 #ifndef NETGRAPH
2524 #ifdef USE_MODEMCK
2525 /*
2526  * Perform timeout on an FR channel
2527  *
2528  * Establish a periodic check of open N2 ports;  If
2529  * a port is open/active, its DCD state is checked
2530  * and a loss of DCD is recognized (and eventually
2531  * processed).
2532  */
2533 static void
2534 sr_modemck(void *arg)
2535 {
2536         int card;               /* card index in table */
2537         int cards;              /* card list index */
2538         int mch;                /* channel on card */
2539         u_char dcd_v;           /* Data Carrier Detect */
2540         u_char got_st0;         /* contents of ST0 */
2541         u_char got_st1;         /* contents of ST1 */
2542         u_char got_st2;         /* contents of ST2 */
2543         u_char got_st3;         /* contents of ST3 */
2544         struct sr_hardc *hc;    /* card's configuration */
2545         struct sr_hardc *Card[16];/* up to 16 cards in system */
2546         struct sr_softc *sc;    /* channel's softc structure */
2547         struct ifnet *ifp;      /* interface control table */
2548         msci_channel *msci;     /* regs specific to channel */
2549
2550         crit_enter();
2551
2552 #if     0
2553         if (sr_opens == 0) {    /* count of "up" channels */
2554                 sr_watcher = 0; /* indicate no watcher */
2555
2556                 crit_exit();
2557
2558                 return;
2559         }
2560 #endif
2561
2562         sr_watcher = 1;         /* mark that we're online */
2563
2564         /*
2565          * Now we'll need a list of cards to process.  Since we can handle
2566          * both ISA and PCI cards (and I didn't think of making this logic
2567          * global YET) we'll generate a single table of card table
2568          * addresses.
2569          */
2570         cards = 0;
2571
2572         for (card = 0; card < NSR; card++) {
2573                 hc = &sr_hardc[card];
2574
2575                 if (hc->sc == (void *)0)
2576                         continue;
2577
2578                 Card[cards++] = hc;
2579         }
2580
2581         hc = sr_hardc_pci;
2582
2583         while (hc) {
2584                 Card[cards++] = hc;
2585                 hc = hc->next;
2586         }
2587
2588         /*
2589          * OK, we've got work we can do.  Let's do it... (Please note that
2590          * this code _only_ deals w/ ISA cards)
2591          */
2592         for (card = 0; card < cards; card++) {
2593                 hc = Card[card];/* get card table */
2594
2595                 for (mch = 0; mch < hc->numports; mch++) {
2596                         sc = &hc->sc[mch];
2597
2598                         ifp = &sc->ifsppp.pp_if;
2599
2600                         /*
2601                          * if this channel isn't "up", skip it
2602                          */
2603                         if ((ifp->if_flags & IFF_UP) == 0)
2604                                 continue;
2605
2606                         /*
2607                          * OK, now we can go looking at this channel's
2608                          * actual register contents...
2609                          */
2610                         msci = &hc->sca->msci[sc->scachan];
2611
2612                         /*
2613                          * OK, now we'll look into the actual status of this
2614                          * channel...
2615                          *
2616                          * I suck in more registers than strictly needed
2617                          */
2618                         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2619                         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2620                         got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2621                         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2622
2623                         /*
2624                          * We want to see if the DCD signal is up (DCD is
2625                          * true if zero)
2626                          */
2627                         dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2628
2629                         if (dcd_v == 0)
2630                                 printf("sr%d: DCD lost\n", sc->unit);
2631                 }
2632         }
2633
2634         /*
2635          * OK, now set up for the next modem signal checking pass...
2636          */
2637         timeout(sr_modemck, NULL, hz);
2638
2639         crit_exit();
2640 }
2641 #endif
2642 #else   /* NETGRAPH */
2643 /*
2644  * If a port is open/active, it's DCD state is checked
2645  * and a loss of DCD is recognized (and eventually processed?).
2646  */
2647 static void
2648 sr_modemck(struct sr_softc *sc )
2649 {
2650         u_char got_st3;                 /* contents of ST3 */
2651         struct sr_hardc *hc = sc->hc;   /* card's configuration */
2652         msci_channel *msci;             /* regs specific to channel */
2653
2654         crit_enter();
2655
2656         if (sc->running == 0) {
2657                 crit_exit();
2658                 return;
2659         }
2660
2661         /*
2662          * OK, now we can go looking at this channel's register contents...
2663          */
2664         msci = &hc->sca->msci[sc->scachan];
2665         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2666
2667         /*
2668          * We want to see if the DCD signal is up (DCD is true if zero)
2669          */
2670         sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2671
2672         crit_exit();
2673 }
2674
2675 #endif  /* NETGRAPH */
2676 static void
2677 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2678 {
2679         printf("src%d: SRINTR: MSCI\n", hc->cunit);
2680 }
2681
2682 static void
2683 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2684 {
2685         printf("src%d: SRINTR: TIMER\n", hc->cunit);
2686 }
2687
2688 #ifdef  NETGRAPH
2689 /*****************************************
2690  * Device timeout/watchdog routine.
2691  * called once per second.
2692  * checks to see that if activity was expected, that it hapenned.
2693  * At present we only look to see if expected output was completed.
2694  */
2695 static void
2696 ngsr_watchdog_frame(void * arg)
2697 {
2698         struct sr_softc * sc = arg;
2699         int     speed;
2700
2701         crit_enter();
2702
2703         if (sc->running == 0) {
2704                 crit_enter();
2705                 return; /* if we are not running let timeouts die */
2706         }
2707         /*
2708          * calculate the apparent throughputs
2709          *  XXX a real hack
2710          */
2711
2712         speed = sc->inbytes - sc->lastinbytes;
2713         sc->lastinbytes = sc->inbytes;
2714         if ( sc->inrate < speed )
2715                 sc->inrate = speed;
2716         speed = sc->outbytes - sc->lastoutbytes;
2717         sc->lastoutbytes = sc->outbytes;
2718         if ( sc->outrate < speed )
2719                 sc->outrate = speed;
2720         sc->inlast++;
2721
2722         crit_exit();
2723
2724         if ((sc->inlast > QUITE_A_WHILE)
2725         && (sc->out_deficit > LOTS_OF_PACKETS)) {
2726                 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2727
2728                 crit_enter();
2729
2730                 sr_down(sc);
2731                 sr_up(sc);
2732                 sc->inlast = sc->out_deficit = 0;
2733
2734                 crit_exit();
2735         } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2736                 if (sc->out_dog == 0) {
2737                         log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2738                                         sc->unit);
2739
2740                         crit_enter();
2741
2742                         srwatchdog(sc);
2743 #if 0
2744                         sr_down(sc);
2745                         sr_up(sc);
2746 #endif
2747
2748                         crit_exit();
2749
2750                         sc->inlast = sc->out_deficit = 0;
2751                 } else {
2752                         sc->out_dog--;
2753                 }
2754         }
2755         sr_modemck(sc);         /* update the DCD status */
2756         callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
2757 }
2758
2759 /***********************************************************************
2760  * This section contains the methods for the Netgraph interface
2761  ***********************************************************************/
2762 /*
2763  * It is not possible or allowable to create a node of this type.
2764  * If the hardware exists, it will already have created it.
2765  */
2766 static  int
2767 ngsr_constructor(node_p *nodep)
2768 {
2769         return (EINVAL);
2770 }
2771
2772 /*
2773  * give our ok for a hook to be added...
2774  * If we are not running this should kick the device into life.
2775  * The hook's private info points to our stash of info about that
2776  * channel.
2777  */
2778 static int
2779 ngsr_newhook(node_p node, hook_p hook, const char *name)
2780 {
2781         struct sr_softc *       sc = node->private;
2782
2783         /*
2784          * check if it's our friend the debug hook
2785          */
2786         if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2787                 hook->private = NULL; /* paranoid */
2788                 sc->debug_hook = hook;
2789                 return (0);
2790         }
2791
2792         /*
2793          * Check for raw mode hook.
2794          */
2795         if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2796                 return (EINVAL);
2797         }
2798         hook->private = sc;
2799         sc->hook = hook;
2800         sc->datahooks++;
2801         sr_up(sc);
2802         return (0);
2803 }
2804
2805 /*
2806  * incoming messages.
2807  * Just respond to the generic TEXT_STATUS message
2808  */
2809 static  int
2810 ngsr_rcvmsg(node_p node,
2811         struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2812 {
2813         struct sr_softc *       sc;
2814         int error = 0;
2815
2816         sc = node->private;
2817         switch (msg->header.typecookie) {
2818             case        NG_SR_COOKIE:
2819                 error = EINVAL;
2820                 break;
2821             case        NGM_GENERIC_COOKIE:
2822                 switch(msg->header.cmd) {
2823                     case NGM_TEXT_STATUS: {
2824                             char        *arg;
2825                             int pos = 0;
2826                             int resplen = sizeof(struct ng_mesg) + 512;
2827                             MALLOC(*resp, struct ng_mesg *, resplen,
2828                                         M_NETGRAPH, M_INTWAIT | M_ZERO);
2829                             if (*resp == NULL) {
2830                                 error = ENOMEM;
2831                                 break;
2832                             }
2833                             arg = (*resp)->data;
2834
2835                             /*
2836                              * Put in the throughput information.
2837                              */
2838                             pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2839                             "highest rate seen: %ld B/S in, %ld B/S out\n",
2840                             sc->inbytes, sc->outbytes,
2841                             sc->inrate, sc->outrate);
2842                             pos += sprintf(arg + pos,
2843                                 "%ld output errors\n",
2844                                 sc->oerrors);
2845                             pos += sprintf(arg + pos,
2846                                 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2847                                 sc->ierrors[0],
2848                                 sc->ierrors[1],
2849                                 sc->ierrors[2],
2850                                 sc->ierrors[3],
2851                                 sc->ierrors[4],
2852                                 sc->ierrors[5]);
2853
2854                             (*resp)->header.version = NG_VERSION;
2855                             (*resp)->header.arglen = strlen(arg) + 1;
2856                             (*resp)->header.token = msg->header.token;
2857                             (*resp)->header.typecookie = NG_SR_COOKIE;
2858                             (*resp)->header.cmd = msg->header.cmd;
2859                             strncpy((*resp)->header.cmdstr, "status",
2860                                         NG_CMDSTRLEN);
2861                         }
2862                         break;
2863                     default:
2864                         error = EINVAL;
2865                         break;
2866                     }
2867                 break;
2868             default:
2869                 error = EINVAL;
2870                 break;
2871         }
2872         free(msg, M_NETGRAPH);
2873         return (error);
2874 }
2875
2876 /*
2877  * get data from another node and transmit it to the correct channel
2878  */
2879 static  int
2880 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2881 {
2882         int error = 0;
2883         struct sr_softc * sc = hook->node->private;
2884         struct ifqueue  *xmitq_p;
2885
2886         /*
2887          * data doesn't come in from just anywhere (e.g control hook)
2888          */
2889         if ( hook->private == NULL) {
2890                 error = ENETDOWN;
2891                 goto bad;
2892         }
2893
2894         /*
2895          * Now queue the data for when it can be sent
2896          */
2897         if (meta && meta->priority > 0) {
2898                 xmitq_p = (&sc->xmitq_hipri);
2899         } else {
2900                 xmitq_p = (&sc->xmitq);
2901         }
2902
2903         crit_enter();
2904
2905         if (IF_QFULL(xmitq_p)) {
2906                 IF_DROP(xmitq_p);
2907
2908                 crit_exit();
2909
2910                 error = ENOBUFS;
2911                 goto bad;
2912         }
2913         IF_ENQUEUE(xmitq_p, m);
2914         srstart(sc);
2915
2916         crit_exit();
2917
2918         return (0);
2919
2920 bad:
2921         /*
2922          * It was an error case.
2923          * check if we need to free the mbuf, and then return the error
2924          */
2925         NG_FREE_DATA(m, meta);
2926         return (error);
2927 }
2928
2929 /*
2930  * do local shutdown processing..
2931  * this node will refuse to go away, unless the hardware says to..
2932  * don't unref the node, or remove our name. just clear our links up.
2933  */
2934 static  int
2935 ngsr_rmnode(node_p node)
2936 {
2937         struct sr_softc * sc = node->private;
2938
2939         sr_down(sc);
2940         ng_cutlinks(node);
2941         node->flags &= ~NG_INVALID; /* bounce back to life */
2942         return (0);
2943 }
2944
2945 /* already linked */
2946 static  int
2947 ngsr_connect(hook_p hook)
2948 {
2949         /* be really amiable and just say "YUP that's OK by me! " */
2950         return (0);
2951 }
2952
2953 /*
2954  * notify on hook disconnection (destruction)
2955  *
2956  * Invalidate the private data associated with this dlci.
2957  * For this type, removal of the last link resets tries to destroy the node.
2958  * As the device still exists, the shutdown method will not actually
2959  * destroy the node, but reset the device and leave it 'fresh' :)
2960  *
2961  * The node removal code will remove all references except that owned by the
2962  * driver.
2963  */
2964 static  int
2965 ngsr_disconnect(hook_p hook)
2966 {
2967         struct sr_softc * sc = hook->node->private;
2968         /*
2969          * If it's the data hook, then free resources etc.
2970          */
2971         if (hook->private) {
2972                 crit_enter();
2973
2974                 sc->datahooks--;
2975                 if (sc->datahooks == 0)
2976                         sr_down(sc);
2977
2978                 crit_exit();
2979         } else {
2980                 sc->debug_hook = NULL;
2981         }
2982         return (0);
2983 }
2984
2985 /*
2986  * called during bootup
2987  * or LKM loading to put this type into the list of known modules
2988  */
2989 static void
2990 ngsr_init(void *ignored)
2991 {
2992         if (ng_newtype(&typestruct))
2993                 printf("ngsr install failed\n");
2994         ngsr_done_init = 1;
2995 }
2996 #endif /* NETGRAPH */
2997
2998 /*
2999  ********************************* END ************************************
3000  */