2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.16 2005/02/21 18:40:37 joerg Exp $
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
48 * controller designed with flexibility and reducing CPU load in mind.
49 * The Starfire offers high and low priority buffer queues, a
50 * producer/consumer index mechanism and several different buffer
51 * queue and completion queue descriptor types. Any one of a number
52 * of different driver designs can be used, depending on system and
53 * OS requirements. This driver makes use of type0 transmit frame
54 * descriptors (since BSD fragments packets across an mbuf chain)
55 * and two RX buffer queues prioritized on size (one queue for small
56 * frames that will fit into a single mbuf, another with full size
57 * mbuf clusters for everything else). The producer/consumer indexes
58 * and completion queues are also used.
60 * One downside to the Starfire has to do with alignment: buffer
61 * queues must be aligned on 256-byte boundaries, and receive buffers
62 * must be aligned on longword boundaries. The receive buffer alignment
63 * causes problems on the Alpha platform, where the packet payload
64 * should be longword aligned. There is no simple way around this.
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/sockio.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/socket.h>
92 #include <net/ifq_var.h>
93 #include <net/if_arp.h>
94 #include <net/ethernet.h>
95 #include <net/if_dl.h>
96 #include <net/if_media.h>
100 #include <vm/vm.h> /* for vtophys */
101 #include <vm/pmap.h> /* for vtophys */
102 #include <machine/clock.h> /* for DELAY */
103 #include <machine/bus_pio.h>
104 #include <machine/bus_memio.h>
105 #include <machine/bus.h>
106 #include <machine/resource.h>
108 #include <sys/rman.h>
110 #include "../mii_layer/mii.h"
111 #include "../mii_layer/miivar.h"
113 /* "controller miibus0" required. See GENERIC if you get errors here. */
114 #include "miibus_if.h"
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
119 #define SF_USEIOSPACE
121 #include "if_sfreg.h"
123 static struct sf_type sf_devs[] = {
124 { AD_VENDORID, AD_DEVICEID_STARFIRE,
125 "Adaptec AIC-6915 10/100BaseTX" },
129 static int sf_probe (device_t);
130 static int sf_attach (device_t);
131 static int sf_detach (device_t);
132 static void sf_intr (void *);
133 static void sf_stats_update (void *);
134 static void sf_rxeof (struct sf_softc *);
135 static void sf_txeof (struct sf_softc *);
136 static int sf_encap (struct sf_softc *,
137 struct sf_tx_bufdesc_type0 *,
139 static void sf_start (struct ifnet *);
140 static int sf_ioctl (struct ifnet *, u_long, caddr_t,
142 static void sf_init (void *);
143 static void sf_stop (struct sf_softc *);
144 static void sf_watchdog (struct ifnet *);
145 static void sf_shutdown (device_t);
146 static int sf_ifmedia_upd (struct ifnet *);
147 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
148 static void sf_reset (struct sf_softc *);
149 static int sf_init_rx_ring (struct sf_softc *);
150 static void sf_init_tx_ring (struct sf_softc *);
151 static int sf_newbuf (struct sf_softc *,
152 struct sf_rx_bufdesc_type0 *,
154 static void sf_setmulti (struct sf_softc *);
155 static int sf_setperf (struct sf_softc *, int, caddr_t);
156 static int sf_sethash (struct sf_softc *, caddr_t, int);
158 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
161 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
162 static u_int32_t sf_calchash (caddr_t);
164 static int sf_miibus_readreg (device_t, int, int);
165 static int sf_miibus_writereg (device_t, int, int, int);
166 static void sf_miibus_statchg (device_t);
168 static u_int32_t csr_read_4 (struct sf_softc *, int);
169 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
170 static void sf_txthresh_adjust (struct sf_softc *);
173 #define SF_RES SYS_RES_IOPORT
174 #define SF_RID SF_PCI_LOIO
176 #define SF_RES SYS_RES_MEMORY
177 #define SF_RID SF_PCI_LOMEM
180 static device_method_t sf_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, sf_probe),
183 DEVMETHOD(device_attach, sf_attach),
184 DEVMETHOD(device_detach, sf_detach),
185 DEVMETHOD(device_shutdown, sf_shutdown),
188 DEVMETHOD(bus_print_child, bus_generic_print_child),
189 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
192 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
193 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
194 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
199 static driver_t sf_driver = {
202 sizeof(struct sf_softc),
205 static devclass_t sf_devclass;
207 DECLARE_DUMMY_MODULE(if_sf);
208 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
209 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
211 #define SF_SETBIT(sc, reg, x) \
212 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
214 #define SF_CLRBIT(sc, reg, x) \
215 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217 static u_int32_t csr_read_4(sc, reg)
224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
233 static u_int8_t sf_read_eeprom(sc, reg)
239 val = (csr_read_4(sc, SF_EEADDR_BASE +
240 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
245 static void csr_write_4(sc, reg, val)
251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
259 static u_int32_t sf_calchash(addr)
262 u_int32_t crc, carry;
266 /* Compute CRC for the address value. */
267 crc = 0xFFFFFFFF; /* initial value */
269 for (i = 0; i < 6; i++) {
271 for (j = 0; j < 8; j++) {
272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
276 crc = (crc ^ 0x04c11db6) | carry;
280 /* return the filter bit position */
281 return(crc >> 23 & 0x1FF);
285 * Copy the address 'mac' into the perfect RX filter entry at
286 * offset 'idx.' The perfect filter only has 16 entries so do
289 static int sf_setperf(sc, idx, mac)
296 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
302 p = (u_int16_t *)mac;
304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
305 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
307 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
308 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
309 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
315 * Set the bit in the 512-bit hash table that corresponds to the
316 * specified mac address 'mac.' If 'prio' is nonzero, update the
317 * priority hash table instead of the filter hash table.
319 static int sf_sethash(sc, mac, prio)
329 h = sf_calchash(mac);
332 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
333 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
335 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
336 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
344 * Set a VLAN tag in the receive filter.
346 static int sf_setvlan(sc, idx, vlan)
351 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
354 csr_write_4(sc, SF_RXFILT_HASH_BASE +
355 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
361 static int sf_miibus_readreg(dev, phy, reg)
369 sc = device_get_softc(dev);
371 for (i = 0; i < SF_TIMEOUT; i++) {
372 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
373 if (val & SF_MII_DATAVALID)
380 if ((val & 0x0000FFFF) == 0xFFFF)
383 return(val & 0x0000FFFF);
386 static int sf_miibus_writereg(dev, phy, reg, val)
394 sc = device_get_softc(dev);
396 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
398 for (i = 0; i < SF_TIMEOUT; i++) {
399 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
400 if (!(busy & SF_MII_BUSY))
407 static void sf_miibus_statchg(dev)
411 struct mii_data *mii;
413 sc = device_get_softc(dev);
414 mii = device_get_softc(sc->sf_miibus);
416 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
417 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
418 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
420 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
421 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
427 static void sf_setmulti(sc)
432 struct ifmultiaddr *ifma;
433 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
435 ifp = &sc->arpcom.ac_if;
437 /* First zot all the existing filters. */
438 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
439 sf_setperf(sc, i, (char *)&dummy);
440 for (i = SF_RXFILT_HASH_BASE;
441 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
442 csr_write_4(sc, i, 0);
443 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
445 /* Now program new ones. */
446 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
447 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
450 /* First find the tail of the list. */
451 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
452 ifma = ifma->ifma_link.le_next) {
453 if (ifma->ifma_link.le_next == NULL)
456 /* Now traverse the list backwards. */
457 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
458 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
459 if (ifma->ifma_addr->sa_family != AF_LINK)
462 * Program the first 15 multicast groups
463 * into the perfect filter. For all others,
464 * use the hash table.
466 if (i < SF_RXFILT_PERFECT_CNT) {
468 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
474 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
484 static int sf_ifmedia_upd(ifp)
488 struct mii_data *mii;
491 mii = device_get_softc(sc->sf_miibus);
493 if (mii->mii_instance) {
494 struct mii_softc *miisc;
495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
496 miisc = LIST_NEXT(miisc, mii_list))
497 mii_phy_reset(miisc);
505 * Report current media status.
507 static void sf_ifmedia_sts(ifp, ifmr)
509 struct ifmediareq *ifmr;
512 struct mii_data *mii;
515 mii = device_get_softc(sc->sf_miibus);
518 ifmr->ifm_active = mii->mii_media_active;
519 ifmr->ifm_status = mii->mii_media_status;
524 static int sf_ioctl(ifp, command, data, cr)
530 struct sf_softc *sc = ifp->if_softc;
531 struct ifreq *ifr = (struct ifreq *) data;
532 struct mii_data *mii;
541 error = ether_ioctl(ifp, command, data);
544 if (ifp->if_flags & IFF_UP) {
545 if (ifp->if_flags & IFF_RUNNING &&
546 ifp->if_flags & IFF_PROMISC &&
547 !(sc->sf_if_flags & IFF_PROMISC)) {
548 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
549 } else if (ifp->if_flags & IFF_RUNNING &&
550 !(ifp->if_flags & IFF_PROMISC) &&
551 sc->sf_if_flags & IFF_PROMISC) {
552 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
553 } else if (!(ifp->if_flags & IFF_RUNNING))
556 if (ifp->if_flags & IFF_RUNNING)
559 sc->sf_if_flags = ifp->if_flags;
569 mii = device_get_softc(sc->sf_miibus);
570 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
582 static void sf_reset(sc)
587 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
588 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
590 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
592 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
594 for (i = 0; i < SF_TIMEOUT; i++) {
596 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
601 printf("sf%d: reset never completed!\n", sc->sf_unit);
603 /* Wait a little while for the chip to get its brains in order. */
609 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
610 * IDs against our list and return a device name if we find a match.
611 * We also check the subsystem ID so that we can identify exactly which
612 * NIC has been found, if possible.
614 static int sf_probe(dev)
621 while(t->sf_name != NULL) {
622 if ((pci_get_vendor(dev) == t->sf_vid) &&
623 (pci_get_device(dev) == t->sf_did)) {
624 switch((pci_read_config(dev,
625 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
626 case AD_SUBSYSID_62011_REV0:
627 case AD_SUBSYSID_62011_REV1:
629 "Adaptec ANA-62011 10/100BaseTX");
632 case AD_SUBSYSID_62022:
634 "Adaptec ANA-62022 10/100BaseTX");
637 case AD_SUBSYSID_62044_REV0:
638 case AD_SUBSYSID_62044_REV1:
640 "Adaptec ANA-62044 10/100BaseTX");
643 case AD_SUBSYSID_62020:
645 "Adaptec ANA-62020 10/100BaseFX");
648 case AD_SUBSYSID_69011:
650 "Adaptec ANA-69011 10/100BaseTX");
654 device_set_desc(dev, t->sf_name);
666 * Attach the interface. Allocate softc structures, do ifmedia
667 * setup and ethernet/BPF attach.
669 static int sf_attach(dev)
676 int unit, rid, error = 0;
680 sc = device_get_softc(dev);
681 unit = device_get_unit(dev);
682 bzero(sc, sizeof(struct sf_softc));
685 * Handle power management nonsense.
687 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
688 if (command == 0x01) {
690 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
691 if (command & SF_PSTATE_MASK) {
692 u_int32_t iobase, membase, irq;
694 /* Save important PCI config data. */
695 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
696 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
697 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
699 /* Reset the power state. */
700 printf("sf%d: chip is in D%d power mode "
701 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
702 command &= 0xFFFFFFFC;
703 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
705 /* Restore PCI config data. */
706 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
707 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
708 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
713 * Map control/status registers.
715 command = pci_read_config(dev, PCIR_COMMAND, 4);
716 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
717 pci_write_config(dev, PCIR_COMMAND, command, 4);
718 command = pci_read_config(dev, PCIR_COMMAND, 4);
721 if (!(command & PCIM_CMD_PORTEN)) {
722 printf("sf%d: failed to enable I/O ports!\n", unit);
727 if (!(command & PCIM_CMD_MEMEN)) {
728 printf("sf%d: failed to enable memory mapping!\n", unit);
735 sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
736 0, ~0, 1, RF_ACTIVE);
738 if (sc->sf_res == NULL) {
739 printf ("sf%d: couldn't map ports\n", unit);
744 sc->sf_btag = rman_get_bustag(sc->sf_res);
745 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
747 /* Allocate interrupt */
749 sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
750 RF_SHAREABLE | RF_ACTIVE);
752 if (sc->sf_irq == NULL) {
753 printf("sf%d: couldn't map interrupt\n", unit);
754 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
759 error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
760 sf_intr, sc, &sc->sf_intrhand);
763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
764 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
765 printf("sf%d: couldn't set up irq\n", unit);
769 callout_init(&sc->sf_stat_timer);
771 /* Reset the adapter. */
775 * Get station address from the EEPROM.
777 for (i = 0; i < ETHER_ADDR_LEN; i++)
778 sc->arpcom.ac_enaddr[i] =
779 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
783 /* Allocate the descriptor queues. */
784 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
785 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
787 if (sc->sf_ldata == NULL) {
788 printf("sf%d: no memory for list buffers!\n", unit);
789 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
790 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
791 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
796 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
799 if (mii_phy_probe(dev, &sc->sf_miibus,
800 sf_ifmedia_upd, sf_ifmedia_sts)) {
801 printf("sf%d: MII without any phy!\n", sc->sf_unit);
802 contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF);
803 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
804 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
805 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
810 ifp = &sc->arpcom.ac_if;
812 if_initname(ifp, "sf", unit);
813 ifp->if_mtu = ETHERMTU;
814 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
815 ifp->if_ioctl = sf_ioctl;
816 ifp->if_start = sf_start;
817 ifp->if_watchdog = sf_watchdog;
818 ifp->if_init = sf_init;
819 ifp->if_baudrate = 10000000;
820 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
821 ifq_set_ready(&ifp->if_snd);
824 * Call MI attach routine.
826 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
833 static int sf_detach(dev)
842 sc = device_get_softc(dev);
843 ifp = &sc->arpcom.ac_if;
848 bus_generic_detach(dev);
849 device_delete_child(dev, sc->sf_miibus);
851 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
852 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
853 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
855 contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
862 static int sf_init_rx_ring(sc)
865 struct sf_list_data *ld;
870 bzero((char *)ld->sf_rx_dlist_big,
871 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
872 bzero((char *)ld->sf_rx_clist,
873 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
875 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
876 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
883 static void sf_init_tx_ring(sc)
886 struct sf_list_data *ld;
891 bzero((char *)ld->sf_tx_dlist,
892 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
893 bzero((char *)ld->sf_tx_clist,
894 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
896 for (i = 0; i < SF_TX_DLIST_CNT; i++)
897 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
898 for (i = 0; i < SF_TX_CLIST_CNT; i++)
899 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
901 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
907 static int sf_newbuf(sc, c, m)
909 struct sf_rx_bufdesc_type0 *c;
912 struct mbuf *m_new = NULL;
915 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
919 MCLGET(m_new, MB_DONTWAIT);
920 if (!(m_new->m_flags & M_EXT)) {
924 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
927 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
928 m_new->m_data = m_new->m_ext.ext_buf;
931 m_adj(m_new, sizeof(u_int64_t));
934 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
941 * The starfire is programmed to use 'normal' mode for packet reception,
942 * which means we use the consumer/producer model for both the buffer
943 * descriptor queue and the completion descriptor queue. The only problem
944 * with this is that it involves a lot of register accesses: we have to
945 * read the RX completion consumer and producer indexes and the RX buffer
946 * producer index, plus the RX completion consumer and RX buffer producer
947 * indexes have to be updated. It would have been easier if Adaptec had
948 * put each index in a separate register, especially given that the damn
949 * NIC has a 512K register space.
951 * In spite of all the lovely features that Adaptec crammed into the 6915,
952 * it is marred by one truly stupid design flaw, which is that receive
953 * buffer addresses must be aligned on a longword boundary. This forces
954 * the packet payload to be unaligned, which is suboptimal on the x86 and
955 * completely unuseable on the Alpha. Our only recourse is to copy received
956 * packets into properly aligned buffers before handing them off.
959 static void sf_rxeof(sc)
964 struct sf_rx_bufdesc_type0 *desc;
965 struct sf_rx_cmpdesc_type3 *cur_rx;
966 u_int32_t rxcons, rxprod;
967 int cmpprodidx, cmpconsidx, bufprodidx;
969 ifp = &sc->arpcom.ac_if;
971 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
972 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
973 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
974 cmpconsidx = SF_IDX_LO(rxcons);
975 bufprodidx = SF_IDX_LO(rxprod);
977 while (cmpconsidx != cmpprodidx) {
980 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
981 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
983 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
984 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
986 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
988 sf_newbuf(sc, desc, m);
992 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
993 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
994 sf_newbuf(sc, desc, m);
999 m_adj(m0, ETHER_ALIGN);
1004 (*ifp->if_input)(ifp, m);
1007 csr_write_4(sc, SF_CQ_CONSIDX,
1008 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
1009 csr_write_4(sc, SF_RXDQ_PTR_Q1,
1010 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
1016 * Read the transmit status from the completion queue and release
1017 * mbufs. Note that the buffer descriptor index in the completion
1018 * descriptor is an offset from the start of the transmit buffer
1019 * descriptor list in bytes. This is important because the manual
1020 * gives the impression that it should match the producer/consumer
1021 * index, which is the offset in 8 byte blocks.
1023 static void sf_txeof(sc)
1024 struct sf_softc *sc;
1026 int txcons, cmpprodidx, cmpconsidx;
1027 struct sf_tx_cmpdesc_type1 *cur_cmp;
1028 struct sf_tx_bufdesc_type0 *cur_tx;
1031 ifp = &sc->arpcom.ac_if;
1033 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1034 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1035 cmpconsidx = SF_IDX_HI(txcons);
1037 while (cmpconsidx != cmpprodidx) {
1038 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1039 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1041 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1044 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1045 sf_txthresh_adjust(sc);
1050 if (cur_tx->sf_mbuf != NULL) {
1051 m_freem(cur_tx->sf_mbuf);
1052 cur_tx->sf_mbuf = NULL;
1055 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1059 ifp->if_flags &= ~IFF_OACTIVE;
1061 csr_write_4(sc, SF_CQ_CONSIDX,
1062 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1063 ((cmpconsidx << 16) & 0xFFFF0000));
1068 static void sf_txthresh_adjust(sc)
1069 struct sf_softc *sc;
1074 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1075 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1076 if (txthresh < 0xFF) {
1078 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1081 printf("sf%d: tx underrun, increasing "
1082 "tx threshold to %d bytes\n",
1083 sc->sf_unit, txthresh * 4);
1085 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1091 static void sf_intr(arg)
1094 struct sf_softc *sc;
1099 ifp = &sc->arpcom.ac_if;
1101 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1104 /* Disable interrupts. */
1105 csr_write_4(sc, SF_IMR, 0x00000000);
1108 status = csr_read_4(sc, SF_ISR);
1110 csr_write_4(sc, SF_ISR, status);
1112 if (!(status & SF_INTRS))
1115 if (status & SF_ISR_RXDQ1_DMADONE)
1118 if (status & SF_ISR_TX_TXDONE ||
1119 status & SF_ISR_TX_DMADONE ||
1120 status & SF_ISR_TX_QUEUEDONE)
1123 if (status & SF_ISR_TX_LOFIFO)
1124 sf_txthresh_adjust(sc);
1126 if (status & SF_ISR_ABNORMALINTR) {
1127 if (status & SF_ISR_STATSOFLOW) {
1128 callout_stop(&sc->sf_stat_timer);
1129 sf_stats_update(sc);
1135 /* Re-enable interrupts. */
1136 csr_write_4(sc, SF_IMR, SF_INTRS);
1138 if (!ifq_is_empty(&ifp->if_snd))
1144 static void sf_init(xsc)
1147 struct sf_softc *sc;
1149 struct mii_data *mii;
1155 ifp = &sc->arpcom.ac_if;
1156 mii = device_get_softc(sc->sf_miibus);
1161 /* Init all the receive filter registers */
1162 for (i = SF_RXFILT_PERFECT_BASE;
1163 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1164 csr_write_4(sc, i, 0);
1166 /* Empty stats counter registers. */
1167 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1168 csr_write_4(sc, SF_STATS_BASE +
1169 (i + sizeof(u_int32_t)), 0);
1171 /* Init our MAC address */
1172 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1173 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1174 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1176 if (sf_init_rx_ring(sc) == ENOBUFS) {
1177 printf("sf%d: initialization failed: no "
1178 "memory for rx buffers\n", sc->sf_unit);
1183 sf_init_tx_ring(sc);
1185 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1187 /* If we want promiscuous mode, set the allframes bit. */
1188 if (ifp->if_flags & IFF_PROMISC) {
1189 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1191 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1194 if (ifp->if_flags & IFF_BROADCAST) {
1195 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1197 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1201 * Load the multicast filter.
1205 /* Init the completion queue indexes */
1206 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1207 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1209 /* Init the RX completion queue */
1210 csr_write_4(sc, SF_RXCQ_CTL_1,
1211 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1212 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1214 /* Init RX DMA control. */
1215 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1217 /* Init the RX buffer descriptor queue. */
1218 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1219 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1220 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1221 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1223 /* Init the TX completion queue */
1224 csr_write_4(sc, SF_TXCQ_CTL,
1225 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1227 /* Init the TX buffer descriptor queue. */
1228 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1229 vtophys(sc->sf_ldata->sf_tx_dlist));
1230 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1231 csr_write_4(sc, SF_TXDQ_CTL,
1232 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1233 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1235 /* Enable autopadding of short TX frames. */
1236 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1238 /* Enable interrupts. */
1239 csr_write_4(sc, SF_IMR, SF_INTRS);
1240 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1242 /* Enable the RX and TX engines. */
1243 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1244 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1246 /*mii_mediachg(mii);*/
1247 sf_ifmedia_upd(ifp);
1249 ifp->if_flags |= IFF_RUNNING;
1250 ifp->if_flags &= ~IFF_OACTIVE;
1252 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1259 static int sf_encap(sc, c, m_head)
1260 struct sf_softc *sc;
1261 struct sf_tx_bufdesc_type0 *c;
1262 struct mbuf *m_head;
1265 struct sf_frag *f = NULL;
1270 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1271 if (m->m_len != 0) {
1272 if (frag == SF_MAXFRAGS)
1274 f = &c->sf_frags[frag];
1276 f->sf_pktlen = m_head->m_pkthdr.len;
1277 f->sf_fraglen = m->m_len;
1278 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1284 struct mbuf *m_new = NULL;
1286 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1287 if (m_new == NULL) {
1288 printf("sf%d: no memory for tx list", sc->sf_unit);
1292 if (m_head->m_pkthdr.len > MHLEN) {
1293 MCLGET(m_new, MB_DONTWAIT);
1294 if (!(m_new->m_flags & M_EXT)) {
1296 printf("sf%d: no memory for tx list",
1301 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1302 mtod(m_new, caddr_t));
1303 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1306 f = &c->sf_frags[0];
1307 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1308 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1312 c->sf_mbuf = m_head;
1313 c->sf_id = SF_TX_BUFDESC_ID;
1314 c->sf_fragcnt = frag;
1322 static void sf_start(ifp)
1325 struct sf_softc *sc;
1326 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1327 struct mbuf *m_head = NULL;
1335 if (ifp->if_flags & IFF_OACTIVE)
1338 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1339 i = SF_IDX_HI(txprod) >> 4;
1341 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1342 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1344 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1345 i = SF_IDX_HI(txprod) >> 4;
1348 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1349 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1350 ifp->if_flags |= IFF_OACTIVE;
1354 m_head = ifq_poll(&ifp->if_snd);
1358 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1359 if (sf_encap(sc, cur_tx, m_head)) {
1360 ifp->if_flags |= IFF_OACTIVE;
1364 ifq_dequeue(&ifp->if_snd);
1365 BPF_MTAP(ifp, cur_tx->sf_mbuf);
1367 SF_INC(i, SF_TX_DLIST_CNT);
1370 * Don't get the TX DMA queue get too full.
1372 if (sc->sf_tx_cnt > 64)
1380 csr_write_4(sc, SF_TXDQ_PRODIDX,
1381 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1382 ((i << 20) & 0xFFFF0000));
1389 static void sf_stop(sc)
1390 struct sf_softc *sc;
1395 ifp = &sc->arpcom.ac_if;
1397 callout_stop(&sc->sf_stat_timer);
1399 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1400 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1401 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1402 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1403 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1404 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1405 csr_write_4(sc, SF_TXCQ_CTL, 0);
1406 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1407 csr_write_4(sc, SF_TXDQ_CTL, 0);
1412 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1413 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1414 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1415 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1419 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1420 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1421 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1422 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1426 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1432 * Note: it is important that this function not be interrupted. We
1433 * use a two-stage register access scheme: if we are interrupted in
1434 * between setting the indirect address register and reading from the
1435 * indirect data register, the contents of the address register could
1436 * be changed out from under us.
1438 static void sf_stats_update(xsc)
1441 struct sf_softc *sc;
1443 struct mii_data *mii;
1444 struct sf_stats stats;
1451 ifp = &sc->arpcom.ac_if;
1452 mii = device_get_softc(sc->sf_miibus);
1454 ptr = (u_int32_t *)&stats;
1455 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1456 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1457 (i + sizeof(u_int32_t)));
1459 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1460 csr_write_4(sc, SF_STATS_BASE +
1461 (i + sizeof(u_int32_t)), 0);
1463 ifp->if_collisions += stats.sf_tx_single_colls +
1464 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1469 if (mii->mii_media_status & IFM_ACTIVE &&
1470 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1472 if (!ifq_is_empty(&ifp->if_snd))
1476 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1483 static void sf_watchdog(ifp)
1486 struct sf_softc *sc;
1491 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1497 if (!ifq_is_empty(&ifp->if_snd))
1503 static void sf_shutdown(dev)
1506 struct sf_softc *sc;
1508 sc = device_get_softc(dev);