sys/dev/netif/sk/if_sk.c

   1 /*
   2  * Copyright (c) 1997, 1998, 1999, 2000
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
  33  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
  34  * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.58 2008/10/12 11:17:08 sephe Exp $
  35  */
  36
  37 /*
  38  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  39  *
  40  * Permission to use, copy, modify, and distribute this software for any
  41  * purpose with or without fee is hereby granted, provided that the above
  42  * copyright notice and this permission notice appear in all copies.
  43  *
  44  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  45  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  46  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  47  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  48  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  49  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  50  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  51  */
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71
  72 /*
  73  * The SysKonnect gigabit ethernet adapters consist of two main
  74  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  75  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  76  * components and a PHY while the GEnesis controller provides a PCI
  77  * interface with DMA support. Each card may have between 512K and
  78  * 2MB of SRAM on board depending on the configuration.
  79  *
  80  * The SysKonnect GEnesis controller can have either one or two XMAC
  81  * chips connected to it, allowing single or dual port NIC configurations.
  82  * SysKonnect has the distinction of being the only vendor on the market
  83  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  84  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  85  * XMAC registers. This driver takes advantage of these features to allow
  86  * both XMACs to operate as independent interfaces.
  87  */
  88
  89 #include <sys/param.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/in_cksum.h>
  93 #include <sys/kernel.h>
  94 #include <sys/interrupt.h>
  95 #include <sys/mbuf.h>
  96 #include <sys/malloc.h>
  97 #include <sys/queue.h>
  98 #include <sys/rman.h>
  99 #include <sys/serialize.h>
 100 #include <sys/socket.h>
 101 #include <sys/sockio.h>
 102 #include <sys/sysctl.h>
 103
 104 #include <net/bpf.h>
 105 #include <net/ethernet.h>
 106 #include <net/if.h>
 107 #include <net/if_arp.h>
 108 #include <net/if_dl.h>
 109 #include <net/if_media.h>
 110 #include <net/ifq_var.h>
 111 #include <net/vlan/if_vlan_var.h>
 112
 113 #include <netinet/ip.h>
 114 #include <netinet/udp.h>
 115
 116 #include <dev/netif/mii_layer/mii.h>
 117 #include <dev/netif/mii_layer/miivar.h>
 118 #include <dev/netif/mii_layer/brgphyreg.h>
 119
 120 #include <bus/pci/pcireg.h>
 121 #include <bus/pci/pcivar.h>
 122 #include <bus/pci/pcidevs.h>
 123
 124 #include <dev/netif/sk/if_skreg.h>
 125 #include <dev/netif/sk/yukonreg.h>
 126 #include <dev/netif/sk/xmaciireg.h>
 127 #include <dev/netif/sk/if_skvar.h>
 128
 129 #include "miibus_if.h"
 130
 131 #if 0
 132 #define SK_DEBUG
 133 #endif
 134
 135 #if 0
 136 #define SK_RXCSUM
 137 #endif
 138
 139 /* supported device vendors */
 140 static const struct skc_type {
 141         uint16_t        skc_vid;
 142         uint16_t        skc_did;
 143         const char      *skc_name;
 144 } skc_devs[] = {
 145         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940,
 146           "3Com 3C940" },
 147         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940B,
 148           "3Com 3C940B" },
 149
 150         { PCI_VENDOR_CNET,              PCI_PRODUCT_CNET_GIGACARD,
 151           "CNet GigaCard" },
 152
 153         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_A1,
 154           "D-Link DGE-530T A1" },
 155         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_B1,
 156           "D-Link DGE-530T B1" },
 157
 158         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1032,
 159           "Linksys EG1032 v2" },
 160         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1064,
 161           "Linksys EG1064" },
 162
 163         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON,
 164           "Marvell Yukon 88E8001/8003/8010" },
 165         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_BELKIN,
 166           "Belkin F5D5005" },
 167
 168         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
 169           "SysKonnect SK-NET" },
 170         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
 171           "SysKonnect SK9821 v2" },
 172
 173         { 0, 0, NULL }
 174 };
 175
 176 static int      skc_probe(device_t);
 177 static int      skc_attach(device_t);
 178 static int      skc_detach(device_t);
 179 static void     skc_shutdown(device_t);
 180 static int      skc_sysctl_imtime(SYSCTL_HANDLER_ARGS);
 181
 182 static int      sk_probe(device_t);
 183 static int      sk_attach(device_t);
 184 static int      sk_detach(device_t);
 185 static void     sk_tick(void *);
 186 static void     sk_yukon_tick(void *);
 187 static void     sk_intr(void *);
 188 static void     sk_intr_bcom(struct sk_if_softc *);
 189 static void     sk_intr_xmac(struct sk_if_softc *);
 190 static void     sk_intr_yukon(struct sk_if_softc *);
 191 static void     sk_rxeof(struct sk_if_softc *);
 192 static void     sk_txeof(struct sk_if_softc *);
 193 static int      sk_encap(struct sk_if_softc *, struct mbuf **, uint32_t *);
 194 static void     sk_start(struct ifnet *);
 195 static int      sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 196 static void     sk_init(void *);
 197 static void     sk_init_xmac(struct sk_if_softc *);
 198 static void     sk_init_yukon(struct sk_if_softc *);
 199 static void     sk_stop(struct sk_if_softc *);
 200 static void     sk_watchdog(struct ifnet *);
 201 static int      sk_ifmedia_upd(struct ifnet *);
 202 static void     sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 203 static void     sk_reset(struct sk_softc *);
 204 static int      sk_newbuf_jumbo(struct sk_if_softc *, int, int);
 205 static int      sk_newbuf_std(struct sk_if_softc *, int, int);
 206 static int      sk_jpool_alloc(device_t);
 207 static void     sk_jpool_free(struct sk_if_softc *);
 208 static struct sk_jpool_entry
 209                 *sk_jalloc(struct sk_if_softc *);
 210 static void     sk_jfree(void *);
 211 static void     sk_jref(void *);
 212 static int      sk_init_rx_ring(struct sk_if_softc *);
 213 static int      sk_init_tx_ring(struct sk_if_softc *);
 214
 215 static int      sk_miibus_readreg(device_t, int, int);
 216 static int      sk_miibus_writereg(device_t, int, int, int);
 217 static void     sk_miibus_statchg(device_t);
 218
 219 static int      sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 220 static int      sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
 221 static void     sk_xmac_miibus_statchg(struct sk_if_softc *);
 222
 223 static int      sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 224 static int      sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
 225 static void     sk_marv_miibus_statchg(struct sk_if_softc *);
 226
 227 static void     sk_setfilt(struct sk_if_softc *, caddr_t, int);
 228 static void     sk_setmulti(struct sk_if_softc *);
 229 static void     sk_setpromisc(struct sk_if_softc *);
 230
 231 #ifdef SK_RXCSUM
 232 static void     sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
 233                           const uint16_t);
 234 #endif
 235 static int      sk_dma_alloc(device_t);
 236 static void     sk_dma_free(device_t);
 237
 238 #ifdef SK_DEBUG
 239 #define DPRINTF(x)      if (skdebug) kprintf x
 240 #define DPRINTFN(n,x)   if (skdebug >= (n)) kprintf x
 241 static int      skdebug = 2;
 242
 243 static void     sk_dump_txdesc(struct sk_tx_desc *, int);
 244 static void     sk_dump_mbuf(struct mbuf *);
 245 static void     sk_dump_bytes(const char *, int);
 246 #else
 247 #define DPRINTF(x)
 248 #define DPRINTFN(n,x)
 249 #endif
 250
 251 /* Interrupt moderation time. */
 252 static int      skc_imtime = SK_IMTIME_DEFAULT;
 253 TUNABLE_INT("hw.skc.imtime", &skc_imtime);
 254
 255 /*
 256  * Note that we have newbus methods for both the GEnesis controller
 257  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 258  * the miibus code is a child of the XMACs. We need to do it this way
 259  * so that the miibus drivers can access the PHY registers on the
 260  * right PHY. It's not quite what I had in mind, but it's the only
 261  * design that achieves the desired effect.
 262  */
 263 static device_method_t skc_methods[] = {
 264         /* Device interface */
 265         DEVMETHOD(device_probe,         skc_probe),
 266         DEVMETHOD(device_attach,        skc_attach),
 267         DEVMETHOD(device_detach,        skc_detach),
 268         DEVMETHOD(device_shutdown,      skc_shutdown),
 269
 270         /* bus interface */
 271         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 272         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 273
 274         { 0, 0 }
 275 };
 276
 277 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
 278 static devclass_t skc_devclass;
 279
 280 static device_method_t sk_methods[] = {
 281         /* Device interface */
 282         DEVMETHOD(device_probe,         sk_probe),
 283         DEVMETHOD(device_attach,        sk_attach),
 284         DEVMETHOD(device_detach,        sk_detach),
 285         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 286
 287         /* bus interface */
 288         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 289         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 290
 291         /* MII interface */
 292         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 293         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 294         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 295
 296         { 0, 0 }
 297 };
 298
 299 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
 300 static devclass_t sk_devclass;
 301
 302 DECLARE_DUMMY_MODULE(if_sk);
 303 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
 304 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
 305 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
 306
 307 static __inline uint32_t
 308 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
 309 {
 310         return CSR_READ_4(sc, reg);
 311 }
 312
 313 static __inline uint16_t
 314 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
 315 {
 316         return CSR_READ_2(sc, reg);
 317 }
 318
 319 static __inline uint8_t
 320 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
 321 {
 322         return CSR_READ_1(sc, reg);
 323 }
 324
 325 static __inline void
 326 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
 327 {
 328         CSR_WRITE_4(sc, reg, x);
 329 }
 330
 331 static __inline void
 332 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
 333 {
 334         CSR_WRITE_2(sc, reg, x);
 335 }
 336
 337 static __inline void
 338 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
 339 {
 340         CSR_WRITE_1(sc, reg, x);
 341 }
 342
 343 static __inline int
 344 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
 345 {
 346         int ret;
 347
 348         if (sc_if->sk_use_jumbo)
 349                 ret = sk_newbuf_jumbo(sc_if, idx, wait);
 350         else
 351                 ret = sk_newbuf_std(sc_if, idx, wait);
 352         return ret;
 353 }
 354
 355 static int
 356 sk_miibus_readreg(device_t dev, int phy, int reg)
 357 {
 358         struct sk_if_softc *sc_if = device_get_softc(dev);
 359
 360         if (SK_IS_GENESIS(sc_if->sk_softc))
 361                 return sk_xmac_miibus_readreg(sc_if, phy, reg);
 362         else
 363                 return sk_marv_miibus_readreg(sc_if, phy, reg);
 364 }
 365
 366 static int
 367 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
 368 {
 369         struct sk_if_softc *sc_if = device_get_softc(dev);
 370
 371         if (SK_IS_GENESIS(sc_if->sk_softc))
 372                 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 373         else
 374                 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
 375 }
 376
 377 static void
 378 sk_miibus_statchg(device_t dev)
 379 {
 380         struct sk_if_softc *sc_if = device_get_softc(dev);
 381
 382         if (SK_IS_GENESIS(sc_if->sk_softc))
 383                 sk_xmac_miibus_statchg(sc_if);
 384         else
 385                 sk_marv_miibus_statchg(sc_if);
 386 }
 387
 388 static int
 389 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 390 {
 391         int i;
 392
 393         DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
 394
 395         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
 396                 return(0);
 397
 398         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 399         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 400         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 401                 for (i = 0; i < SK_TIMEOUT; i++) {
 402                         DELAY(1);
 403                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 404                             XM_MMUCMD_PHYDATARDY)
 405                                 break;
 406                 }
 407
 408                 if (i == SK_TIMEOUT) {
 409                         if_printf(&sc_if->arpcom.ac_if,
 410                                   "phy failed to come ready\n");
 411                         return(0);
 412                 }
 413         }
 414         DELAY(1);
 415         return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
 416 }
 417
 418 static int
 419 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 420 {
 421         int i;
 422
 423         DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
 424
 425         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 426         for (i = 0; i < SK_TIMEOUT; i++) {
 427                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 428                         break;
 429         }
 430
 431         if (i == SK_TIMEOUT) {
 432                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 433                 return(ETIMEDOUT);
 434         }
 435
 436         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 437         for (i = 0; i < SK_TIMEOUT; i++) {
 438                 DELAY(1);
 439                 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
 440                         break;
 441         }
 442
 443         if (i == SK_TIMEOUT)
 444                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 445         return(0);
 446 }
 447
 448 static void
 449 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
 450 {
 451         struct mii_data *mii;
 452
 453         mii = device_get_softc(sc_if->sk_miibus);
 454         DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
 455
 456         /*
 457          * If this is a GMII PHY, manually set the XMAC's
 458          * duplex mode accordingly.
 459          */
 460         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 461                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 462                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 463                 else
 464                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 465         }
 466 }
 467
 468 static int
 469 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
 470 {
 471         uint16_t val;
 472         int i;
 473
 474         if (phy != 0 ||
 475             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 476              sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
 477                 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
 478                              phy, reg));
 479                 return(0);
 480         }
 481
 482         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 483                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 484
 485         for (i = 0; i < SK_TIMEOUT; i++) {
 486                 DELAY(1);
 487                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 488                 if (val & YU_SMICR_READ_VALID)
 489                         break;
 490         }
 491
 492         if (i == SK_TIMEOUT) {
 493                 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
 494                 return(0);
 495         }
 496
 497         DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
 498                      SK_TIMEOUT));
 499
 500         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 501
 502         DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
 503                      phy, reg, val));
 504
 505         return(val);
 506 }
 507
 508 static int
 509 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
 510 {
 511         int i;
 512
 513         DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
 514                      phy, reg, val));
 515
 516         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 517         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 518                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 519
 520         for (i = 0; i < SK_TIMEOUT; i++) {
 521                 DELAY(1);
 522                 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
 523                         break;
 524         }
 525
 526         if (i == SK_TIMEOUT)
 527                 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
 528
 529         return(0);
 530 }
 531
 532 static void
 533 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
 534 {
 535         DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
 536                      SK_YU_READ_2(sc_if, YUKON_GPCR)));
 537 }
 538
 539 #define HASH_BITS       6
 540
 541 static uint32_t
 542 sk_xmac_hash(caddr_t addr)
 543 {
 544         uint32_t crc;
 545
 546         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 547         return (~crc & ((1 << HASH_BITS) - 1));
 548 }
 549
 550 static uint32_t
 551 sk_yukon_hash(caddr_t addr)
 552 {
 553         uint32_t crc;
 554
 555         crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
 556         return (crc & ((1 << HASH_BITS) - 1));
 557 }
 558
 559 static void
 560 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
 561 {
 562         int base;
 563
 564         base = XM_RXFILT_ENTRY(slot);
 565
 566         SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
 567         SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
 568         SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
 569 }
 570
 571 static void
 572 sk_setmulti(struct sk_if_softc *sc_if)
 573 {
 574         struct sk_softc *sc = sc_if->sk_softc;
 575         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 576         uint32_t hashes[2] = { 0, 0 };
 577         int h = 0, i;
 578         struct ifmultiaddr *ifma;
 579         uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
 580
 581         /* First, zot all the existing filters. */
 582         switch(sc->sk_type) {
 583         case SK_GENESIS:
 584                 for (i = 1; i < XM_RXFILT_MAX; i++)
 585                         sk_setfilt(sc_if, (caddr_t)&dummy, i);
 586
 587                 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
 588                 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
 589                 break;
 590         case SK_YUKON:
 591         case SK_YUKON_LITE:
 592         case SK_YUKON_LP:
 593                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
 594                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
 595                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
 596                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
 597                 break;
 598         }
 599
 600         /* Now program new ones. */
 601         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 602                 hashes[0] = 0xFFFFFFFF;
 603                 hashes[1] = 0xFFFFFFFF;
 604         } else {
 605                 i = 1;
 606                 /* First find the tail of the list. */
 607                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 608                     ifma_link) {
 609                         caddr_t maddr;
 610
 611                         if (ifma->ifma_addr->sa_family != AF_LINK)
 612                                 continue;
 613
 614                         maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
 615
 616                         /*
 617                          * Program the first XM_RXFILT_MAX multicast groups
 618                          * into the perfect filter. For all others,
 619                          * use the hash table.
 620                          */
 621                         if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
 622                                 sk_setfilt(sc_if, maddr, i);
 623                                 i++;
 624                                 continue;
 625                         }
 626
 627                         switch(sc->sk_type) {
 628                         case SK_GENESIS:
 629                                 h = sk_xmac_hash(maddr);
 630                                 break;
 631
 632                         case SK_YUKON:
 633                         case SK_YUKON_LITE:
 634                         case SK_YUKON_LP:
 635                                 h = sk_yukon_hash(maddr);
 636                                 break;
 637                         }
 638                         if (h < 32)
 639                                 hashes[0] |= (1 << h);
 640                         else
 641                                 hashes[1] |= (1 << (h - 32));
 642                 }
 643         }
 644
 645         switch(sc->sk_type) {
 646         case SK_GENESIS:
 647                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
 648                                XM_MODE_RX_USE_PERFECT);
 649                 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 650                 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 651                 break;
 652         case SK_YUKON:
 653         case SK_YUKON_LITE:
 654         case SK_YUKON_LP:
 655                 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 656                 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 657                 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 658                 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 659                 break;
 660         }
 661 }
 662
 663 static void
 664 sk_setpromisc(struct sk_if_softc *sc_if)
 665 {
 666         struct sk_softc *sc = sc_if->sk_softc;
 667         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 668
 669         switch(sc->sk_type) {
 670         case SK_GENESIS:
 671                 if (ifp->if_flags & IFF_PROMISC)
 672                         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 673                 else
 674                         SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
 675                 break;
 676         case SK_YUKON:
 677         case SK_YUKON_LITE:
 678         case SK_YUKON_LP:
 679                 if (ifp->if_flags & IFF_PROMISC) {
 680                         SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
 681                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 682                 } else {
 683                         SK_YU_SETBIT_2(sc_if, YUKON_RCR,
 684                             YU_RCR_UFLEN | YU_RCR_MUFLEN);
 685                 }
 686                 break;
 687         }
 688 }
 689
 690 static int
 691 sk_init_rx_ring(struct sk_if_softc *sc_if)
 692 {
 693         struct sk_chain_data *cd = &sc_if->sk_cdata;
 694         struct sk_ring_data *rd = &sc_if->sk_rdata;
 695         int i, nexti, error;
 696
 697         bzero(rd->sk_rx_ring, SK_RX_RING_SIZE);
 698
 699         for (i = 0; i < SK_RX_RING_CNT; i++) {
 700                 bus_addr_t paddr;
 701
 702                 if (i == (SK_RX_RING_CNT - 1))
 703                         nexti = 0;
 704                 else
 705                         nexti = i + 1;
 706                 paddr = rd->sk_rx_ring_paddr +
 707                         (nexti * sizeof(struct sk_rx_desc));
 708
 709                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
 710                 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
 711                 rd->sk_rx_ring[i].sk_csum2_start =
 712                         htole16(ETHER_HDR_LEN + sizeof(struct ip));
 713
 714                 error = sk_newbuf(sc_if, i, 1);
 715                 if (error) {
 716                         if_printf(&sc_if->arpcom.ac_if,
 717                                   "failed alloc of %dth mbuf\n", i);
 718                         return error;
 719                 }
 720         }
 721
 722         cd->sk_rx_prod = 0;
 723         cd->sk_rx_cons = 0;
 724
 725         return (0);
 726 }
 727
 728 static int
 729 sk_init_tx_ring(struct sk_if_softc *sc_if)
 730 {
 731         struct sk_ring_data *rd = &sc_if->sk_rdata;
 732         int i, nexti;
 733
 734         bzero(rd->sk_tx_ring, SK_TX_RING_SIZE);
 735
 736         for (i = 0; i < SK_TX_RING_CNT; i++) {
 737                 bus_addr_t paddr;
 738
 739                 if (i == (SK_TX_RING_CNT - 1))
 740                         nexti = 0;
 741                 else
 742                         nexti = i + 1;
 743                 paddr = rd->sk_tx_ring_paddr +
 744                         (nexti * sizeof(struct sk_tx_desc));
 745
 746                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
 747         }
 748
 749         sc_if->sk_cdata.sk_tx_prod = 0;
 750         sc_if->sk_cdata.sk_tx_cons = 0;
 751         sc_if->sk_cdata.sk_tx_cnt = 0;
 752
 753         return (0);
 754 }
 755
 756 static int
 757 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
 758 {
 759         struct sk_jpool_entry *entry;
 760         struct mbuf *m_new = NULL;
 761         struct sk_rx_desc *r;
 762         bus_addr_t paddr;
 763
 764         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 765
 766         MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 767         if (m_new == NULL)
 768                 return ENOBUFS;
 769
 770         /* Allocate the jumbo buffer */
 771         entry = sk_jalloc(sc_if);
 772         if (entry == NULL) {
 773                 m_freem(m_new);
 774                 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
 775                     "dropped!\n", sc_if->arpcom.ac_if.if_xname));
 776                 return ENOBUFS;
 777         }
 778
 779         m_new->m_ext.ext_arg = entry;
 780         m_new->m_ext.ext_buf = entry->buf;
 781         m_new->m_ext.ext_free = sk_jfree;
 782         m_new->m_ext.ext_ref = sk_jref;
 783         m_new->m_ext.ext_size = SK_JLEN;
 784
 785         m_new->m_flags |= M_EXT;
 786
 787         m_new->m_data = m_new->m_ext.ext_buf;
 788         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 789
 790         paddr = entry->paddr;
 791
 792         /*
 793          * Adjust alignment so packet payload begins on a
 794          * longword boundary. Mandatory for Alpha, useful on
 795          * x86 too.
 796          */
 797         m_adj(m_new, ETHER_ALIGN);
 798         paddr += ETHER_ALIGN;
 799
 800         sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
 801
 802         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 803         r->sk_data_lo = htole32(SK_ADDR_LO(paddr));
 804         r->sk_data_hi = htole32(SK_ADDR_HI(paddr));
 805         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 806
 807         return 0;
 808 }
 809
 810 static int
 811 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
 812 {
 813         struct mbuf *m_new = NULL;
 814         struct sk_chain_data *cd = &sc_if->sk_cdata;
 815         struct sk_rx_desc *r;
 816         bus_dma_segment_t seg;
 817         bus_dmamap_t map;
 818         int error, nseg;
 819
 820         KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
 821
 822         m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 823         if (m_new == NULL)
 824                 return ENOBUFS;
 825
 826         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 827
 828         /*
 829          * Adjust alignment so packet payload begins on a
 830          * longword boundary. Mandatory for Alpha, useful on
 831          * x86 too.
 832          */
 833         m_adj(m_new, ETHER_ALIGN);
 834
 835         error = bus_dmamap_load_mbuf_segment(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
 836                         m_new, &seg, 1, &nseg, BUS_DMA_NOWAIT);
 837         if (error) {
 838                 m_freem(m_new);
 839                 if (wait) {
 840                         if_printf(&sc_if->arpcom.ac_if,
 841                                   "could not map RX mbuf\n");
 842                 }
 843                 return error;
 844         }
 845
 846         /* Unload originally mapped mbuf */
 847         if (cd->sk_rx_mbuf[idx] != NULL) {
 848                 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[idx],
 849                                 BUS_DMASYNC_POSTREAD);
 850                 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
 851         }
 852
 853         /* Switch DMA map with tmp DMA map */
 854         map = cd->sk_rx_dmap_tmp;
 855         cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
 856         cd->sk_rx_dmap[idx] = map;
 857
 858         cd->sk_rx_mbuf[idx] = m_new;
 859
 860         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 861         r->sk_data_lo = htole32(SK_ADDR_LO(seg.ds_addr));
 862         r->sk_data_hi = htole32(SK_ADDR_HI(seg.ds_addr));
 863         r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
 864
 865         return 0;
 866 }
 867
 868 /*
 869  * Allocate a jumbo buffer.
 870  */
 871 struct sk_jpool_entry *
 872 sk_jalloc(struct sk_if_softc *sc_if)
 873 {
 874         struct sk_chain_data *cd = &sc_if->sk_cdata;
 875         struct sk_jpool_entry *entry;
 876
 877         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 878
 879         entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
 880         if (entry != NULL) {
 881                 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
 882                 entry->inuse = 1;
 883         } else {
 884                 DPRINTF(("no free jumbo buffer\n"));
 885         }
 886
 887         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 888         return entry;
 889 }
 890
 891 /*
 892  * Release a jumbo buffer.
 893  */
 894 void
 895 sk_jfree(void *arg)
 896 {
 897         struct sk_jpool_entry *entry = arg;
 898         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 899
 900         if (&cd->sk_jpool_ent[entry->slot] != entry)
 901                 panic("%s: free wrong jumbo buffer\n", __func__);
 902         else if (entry->inuse == 0)
 903                 panic("%s: jumbo buffer already freed\n", __func__);
 904
 905         lwkt_serialize_enter(&cd->sk_jpool_serializer);
 906
 907         atomic_subtract_int(&entry->inuse, 1);
 908         if (entry->inuse == 0)
 909                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
 910
 911         lwkt_serialize_exit(&cd->sk_jpool_serializer);
 912 }
 913
 914 static void
 915 sk_jref(void *arg)
 916 {
 917         struct sk_jpool_entry *entry = arg;
 918         struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
 919
 920         if (&cd->sk_jpool_ent[entry->slot] != entry)
 921                 panic("%s: free wrong jumbo buffer\n", __func__);
 922         else if (entry->inuse == 0)
 923                 panic("%s: jumbo buffer already freed\n", __func__);
 924
 925         atomic_add_int(&entry->inuse, 1);
 926 }
 927
 928 /*
 929  * Set media options.
 930  */
 931 static int
 932 sk_ifmedia_upd(struct ifnet *ifp)
 933 {
 934         struct sk_if_softc *sc_if = ifp->if_softc;
 935         struct mii_data *mii;
 936
 937         mii = device_get_softc(sc_if->sk_miibus);
 938         sk_init(sc_if);
 939         mii_mediachg(mii);
 940
 941         return(0);
 942 }
 943
 944 /*
 945  * Report current media status.
 946  */
 947 static void
 948 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 949 {
 950         struct sk_if_softc *sc_if;
 951         struct mii_data *mii;
 952
 953         sc_if = ifp->if_softc;
 954         mii = device_get_softc(sc_if->sk_miibus);
 955
 956         mii_pollstat(mii);
 957         ifmr->ifm_active = mii->mii_media_active;
 958         ifmr->ifm_status = mii->mii_media_status;
 959 }
 960
 961 static int
 962 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 963 {
 964         struct sk_if_softc *sc_if = ifp->if_softc;
 965         struct ifreq *ifr = (struct ifreq *)data;
 966         struct mii_data *mii;
 967         int error = 0;
 968
 969         ASSERT_SERIALIZED(ifp->if_serializer);
 970
 971         switch(command) {
 972         case SIOCSIFMTU:
 973                 if (ifr->ifr_mtu > SK_JUMBO_MTU)
 974                         error = EINVAL;
 975                 else {
 976                         ifp->if_mtu = ifr->ifr_mtu;
 977                         ifp->if_flags &= ~IFF_RUNNING;
 978                         sk_init(sc_if);
 979                 }
 980                 break;
 981         case SIOCSIFFLAGS:
 982                 if (ifp->if_flags & IFF_UP) {
 983                         if (ifp->if_flags & IFF_RUNNING) {
 984                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
 985                                     & IFF_PROMISC) {
 986                                         sk_setpromisc(sc_if);
 987                                         sk_setmulti(sc_if);
 988                                 }
 989                         } else
 990                                 sk_init(sc_if);
 991                 } else {
 992                         if (ifp->if_flags & IFF_RUNNING)
 993                                 sk_stop(sc_if);
 994                 }
 995                 sc_if->sk_if_flags = ifp->if_flags;
 996                 break;
 997         case SIOCADDMULTI:
 998         case SIOCDELMULTI:
 999                 sk_setmulti(sc_if);
1000                 break;
1001         case SIOCGIFMEDIA:
1002         case SIOCSIFMEDIA:
1003                 mii = device_get_softc(sc_if->sk_miibus);
1004                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1005                 break;
1006         default:
1007                 error = ether_ioctl(ifp, command, data);
1008                 break;
1009         }
1010
1011         return(error);
1012 }
1013
1014 /*
1015  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1016  * IDs against our list and return a device name if we find a match.
1017  */
1018 static int
1019 skc_probe(device_t dev)
1020 {
1021         const struct skc_type *t;
1022         uint16_t vid, did;
1023
1024         vid = pci_get_vendor(dev);
1025         did = pci_get_device(dev);
1026
1027         /*
1028          * Only attach to rev.2 of the Linksys EG1032 adapter.
1029          * Rev.3 is supported by re(4).
1030          */
1031         if (vid == PCI_VENDOR_LINKSYS &&
1032             did == PCI_PRODUCT_LINKSYS_EG1032 &&
1033             pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1034                 return ENXIO;
1035
1036         for (t = skc_devs; t->skc_name != NULL; t++) {
1037                 if (vid == t->skc_vid && did == t->skc_did) {
1038                         device_set_desc(dev, t->skc_name);
1039                         return 0;
1040                 }
1041         }
1042         return ENXIO;
1043 }
1044
1045 /*
1046  * Force the GEnesis into reset, then bring it out of reset.
1047  */
1048 static void
1049 sk_reset(struct sk_softc *sc)
1050 {
1051         DPRINTFN(2, ("sk_reset\n"));
1052
1053         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1054         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1055         if (SK_IS_YUKON(sc))
1056                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1057
1058         DELAY(1000);
1059         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1060         DELAY(2);
1061         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1062         if (SK_IS_YUKON(sc))
1063                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1064
1065         DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1066         DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1067                      CSR_READ_2(sc, SK_LINK_CTRL)));
1068
1069         if (SK_IS_GENESIS(sc)) {
1070                 /* Configure packet arbiter */
1071                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1072                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1073                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1074                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1075                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1076         }
1077
1078         /* Enable RAM interface */
1079         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1080
1081         /*
1082          * Configure interrupt moderation. The moderation timer
1083          * defers interrupts specified in the interrupt moderation
1084          * timer mask based on the timeout specified in the interrupt
1085          * moderation timer init register. Each bit in the timer
1086          * register represents one tick, so to specify a timeout in
1087          * microseconds, we have to multiply by the correct number of
1088          * ticks-per-microsecond.
1089          */
1090         KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0);
1091         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime));
1092         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1093             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1094         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1095 }
1096
1097 static int
1098 sk_probe(device_t dev)
1099 {
1100         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1101         const char *revstr = "", *name = NULL;
1102         char devname[80];
1103
1104         switch (sc->sk_type) {
1105         case SK_GENESIS:
1106                 name = "SysKonnect GEnesis";
1107                 break;
1108         case SK_YUKON:
1109                 name = "Marvell Yukon";
1110                 break;
1111         case SK_YUKON_LITE:
1112                 name = "Marvell Yukon Lite";
1113                 switch (sc->sk_rev) {
1114                 case SK_YUKON_LITE_REV_A0:
1115                         revstr = " rev.A0";
1116                         break;
1117                 case SK_YUKON_LITE_REV_A1:
1118                         revstr = " rev.A1";
1119                         break;
1120                 case SK_YUKON_LITE_REV_A3:
1121                         revstr = " rev.A3";
1122                         break;
1123                 }
1124                 break;
1125         case SK_YUKON_LP:
1126                 name = "Marvell Yukon LP";
1127                 break;
1128         default:
1129                 return ENXIO;
1130         }
1131
1132         ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1133                  name, revstr, sc->sk_rev);
1134         device_set_desc_copy(dev, devname);
1135         return 0;
1136 }
1137
1138 /*
1139  * Each XMAC chip is attached as a separate logical IP interface.
1140  * Single port cards will have only one logical interface of course.
1141  */
1142 static int
1143 sk_attach(device_t dev)
1144 {
1145         struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1146         struct sk_if_softc *sc_if = device_get_softc(dev);
1147         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1148         int i, error, if_attached = 0;
1149
1150         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1151
1152         sc_if->sk_port = *(int *)device_get_ivars(dev);
1153         KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1154
1155         sc_if->sk_softc = sc;
1156         sc->sk_if[sc_if->sk_port] = sc_if;
1157
1158         kfree(device_get_ivars(dev), M_DEVBUF);
1159         device_set_ivars(dev, NULL);
1160
1161         if (sc_if->sk_port == SK_PORT_A)
1162                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1163         if (sc_if->sk_port == SK_PORT_B)
1164                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1165
1166         DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1167
1168         /*
1169          * Get station address for this interface. Note that
1170          * dual port cards actually come with three station
1171          * addresses: one for each port, plus an extra. The
1172          * extra one is used by the SysKonnect driver software
1173          * as a 'virtual' station address for when both ports
1174          * are operating in failover mode. Currently we don't
1175          * use this extra address.
1176          */
1177         for (i = 0; i < ETHER_ADDR_LEN; i++) {
1178                 /* XXX */
1179                 sc_if->arpcom.ac_enaddr[i] =
1180                     sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1181         }
1182
1183         /*
1184          * Set up RAM buffer addresses. The NIC will have a certain
1185          * amount of SRAM on it, somewhere between 512K and 2MB. We
1186          * need to divide this up a) between the transmitter and
1187          * receiver and b) between the two XMACs, if this is a
1188          * dual port NIC. Our algorithm is to divide up the memory
1189          * evenly so that everyone gets a fair share.
1190          */
1191         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1192                 uint32_t chunk, val;
1193
1194                 chunk = sc->sk_ramsize / 2;
1195                 val = sc->sk_rboff / sizeof(uint64_t);
1196                 sc_if->sk_rx_ramstart = val;
1197                 val += (chunk / sizeof(uint64_t));
1198                 sc_if->sk_rx_ramend = val - 1;
1199                 sc_if->sk_tx_ramstart = val;
1200                 val += (chunk / sizeof(uint64_t));
1201                 sc_if->sk_tx_ramend = val - 1;
1202         } else {
1203                 uint32_t chunk, val;
1204
1205                 chunk = sc->sk_ramsize / 4;
1206                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1207                     sizeof(uint64_t);
1208                 sc_if->sk_rx_ramstart = val;
1209                 val += (chunk / sizeof(uint64_t));
1210                 sc_if->sk_rx_ramend = val - 1;
1211                 sc_if->sk_tx_ramstart = val;
1212                 val += (chunk / sizeof(uint64_t));
1213                 sc_if->sk_tx_ramend = val - 1;
1214         }
1215
1216         DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1217                      "           tx_ramstart=%#x tx_ramend=%#x\n",
1218                      sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1219                      sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1220
1221         /* Read and save PHY type */
1222         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1223
1224         /* Set PHY address */
1225         if (SK_IS_GENESIS(sc)) {
1226                 switch (sc_if->sk_phytype) {
1227                 case SK_PHYTYPE_XMAC:
1228                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1229                         break;
1230                 case SK_PHYTYPE_BCOM:
1231                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1232                         break;
1233                 default:
1234                         device_printf(dev, "unsupported PHY type: %d\n",
1235                             sc_if->sk_phytype);
1236                         error = ENXIO;
1237                         goto fail;
1238                 }
1239         }
1240
1241         if (SK_IS_YUKON(sc)) {
1242                 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1243                     sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1244                         /* not initialized, punt */
1245                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1246                         sc->sk_coppertype = 1;
1247                 }
1248
1249                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1250
1251                 if (!(sc->sk_coppertype))
1252                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1253         }
1254
1255         error = sk_dma_alloc(dev);
1256         if (error)
1257                 goto fail;
1258
1259         ifp->if_softc = sc_if;
1260         ifp->if_mtu = ETHERMTU;
1261         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1262         ifp->if_ioctl = sk_ioctl;
1263         ifp->if_start = sk_start;
1264         ifp->if_watchdog = sk_watchdog;
1265         ifp->if_init = sk_init;
1266         ifp->if_baudrate = 1000000000;
1267         ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1268         ifq_set_ready(&ifp->if_snd);
1269
1270         ifp->if_capabilities = IFCAP_VLAN_MTU;
1271
1272         /* Don't use jumbo buffers by default */
1273         sc_if->sk_use_jumbo = 0;
1274
1275         /*
1276          * Call MI attach routines.
1277          *
1278          * NOTE:
1279          * This must be done before following sk_init_xxx(), in which
1280          * if_multiaddrs will be used.
1281          */
1282         ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1283         if_attached = 1;
1284
1285         /*
1286          * Do miibus setup.
1287          */
1288         switch (sc->sk_type) {
1289         case SK_GENESIS:
1290                 sk_init_xmac(sc_if);
1291                 break;
1292         case SK_YUKON:
1293         case SK_YUKON_LITE:
1294         case SK_YUKON_LP:
1295                 sk_init_yukon(sc_if);
1296                 break;
1297         default:
1298                 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1299                 error = ENXIO;
1300                 goto fail;
1301         }
1302
1303         DPRINTFN(2, ("sk_attach: 1\n"));
1304
1305         error = mii_phy_probe(dev, &sc_if->sk_miibus,
1306                               sk_ifmedia_upd, sk_ifmedia_sts);
1307         if (error) {
1308                 device_printf(dev, "no PHY found!\n");
1309                 goto fail;
1310         }
1311
1312         callout_init(&sc_if->sk_tick_timer);
1313
1314         DPRINTFN(2, ("sk_attach: end\n"));
1315         return 0;
1316 fail:
1317         if (if_attached)
1318                 ether_ifdetach(ifp);
1319         sk_detach(dev);
1320         sc->sk_if[sc_if->sk_port] = NULL;
1321         return error;
1322 }
1323
1324 /*
1325  * Attach the interface. Allocate softc structures, do ifmedia
1326  * setup and ethernet/BPF attach.
1327  */
1328 static int
1329 skc_attach(device_t dev)
1330 {
1331         struct sk_softc *sc = device_get_softc(dev);
1332         uint8_t skrs;
1333         int *port;
1334         int error, cpuid;
1335
1336         DPRINTFN(2, ("begin skc_attach\n"));
1337
1338         sc->sk_dev = dev;
1339         lwkt_serialize_init(&sc->sk_serializer);
1340
1341 #ifndef BURN_BRIDGES
1342         /*
1343          * Handle power management nonsense.
1344          */
1345         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1346                 uint32_t iobase, membase, irq;
1347
1348                 /* Save important PCI config data. */
1349                 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1350                 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1351                 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1352
1353                 /* Reset the power state. */
1354                 device_printf(dev, "chip is in D%d power mode "
1355                               "-- setting to D0\n", pci_get_powerstate(dev));
1356
1357                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1358
1359                 /* Restore PCI config data. */
1360                 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1361                 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1362                 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1363         }
1364 #endif  /* BURN_BRIDGES */
1365
1366         /*
1367          * Map control/status registers.
1368          */
1369         pci_enable_busmaster(dev);
1370
1371         sc->sk_res_rid = SK_PCI_LOMEM;
1372         sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1373                                             &sc->sk_res_rid, RF_ACTIVE);
1374         if (sc->sk_res == NULL) {
1375                 device_printf(dev, "couldn't map memory\n");
1376                 error = ENXIO;
1377                 goto fail;
1378         }
1379         sc->sk_btag = rman_get_bustag(sc->sk_res);
1380         sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1381
1382         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1383         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1384
1385         /* Bail out here if chip is not recognized */
1386         if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1387                 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1388                 error = ENXIO;
1389                 goto fail;
1390         }
1391
1392         DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1393
1394         /* Allocate interrupt */
1395         sc->sk_irq_rid = 0;
1396         sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1397                                             RF_SHAREABLE | RF_ACTIVE);
1398         if (sc->sk_irq == NULL) {
1399                 device_printf(dev, "couldn't map interrupt\n");
1400                 error = ENXIO;
1401                 goto fail;
1402         }
1403
1404         switch (sc->sk_type) {
1405         case SK_GENESIS:
1406                 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1407                 break;
1408         default:
1409                 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1410                 break;
1411         }
1412         sc->sk_imtime = skc_imtime;
1413
1414         /* Reset the adapter. */
1415         sk_reset(sc);
1416
1417         skrs = sk_win_read_1(sc, SK_EPROM0);
1418         if (SK_IS_GENESIS(sc)) {
1419                 /* Read and save RAM size and RAMbuffer offset */
1420                 switch(skrs) {
1421                 case SK_RAMSIZE_512K_64:
1422                         sc->sk_ramsize = 0x80000;
1423                         sc->sk_rboff = SK_RBOFF_0;
1424                         break;
1425                 case SK_RAMSIZE_1024K_64:
1426                         sc->sk_ramsize = 0x100000;
1427                         sc->sk_rboff = SK_RBOFF_80000;
1428                         break;
1429                 case SK_RAMSIZE_1024K_128:
1430                         sc->sk_ramsize = 0x100000;
1431                         sc->sk_rboff = SK_RBOFF_0;
1432                         break;
1433                 case SK_RAMSIZE_2048K_128:
1434                         sc->sk_ramsize = 0x200000;
1435                         sc->sk_rboff = SK_RBOFF_0;
1436                         break;
1437                 default:
1438                         device_printf(dev, "unknown ram size: %d\n", skrs);
1439                         error = ENXIO;
1440                         goto fail;
1441                 }
1442         } else {
1443                 if (skrs == 0x00)
1444                         sc->sk_ramsize = 0x20000;
1445                 else
1446                         sc->sk_ramsize = skrs * (1<<12);
1447                 sc->sk_rboff = SK_RBOFF_0;
1448         }
1449
1450         DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1451                      sc->sk_ramsize, sc->sk_ramsize / 1024,
1452                      sc->sk_rboff));
1453
1454         /* Read and save physical media type */
1455         sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1456
1457         if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1458                 sc->sk_coppertype = 1;
1459         else
1460                 sc->sk_coppertype = 0;
1461
1462         /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1463         if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1464                 uint32_t flashaddr;
1465                 uint8_t testbyte;
1466
1467                 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1468
1469                 /* Test Flash-Address Register */
1470                 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1471                 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1472
1473                 if (testbyte != 0) {
1474                         /* This is a Yukon Lite Rev A0 */
1475                         sc->sk_type = SK_YUKON_LITE;
1476                         sc->sk_rev = SK_YUKON_LITE_REV_A0;
1477                         /* Restore Flash-Address Register */
1478                         sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1479                 }
1480         }
1481
1482         /*
1483          * Create sysctl nodes.
1484          */
1485         sysctl_ctx_init(&sc->sk_sysctl_ctx);
1486         sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx,
1487                                              SYSCTL_STATIC_CHILDREN(_hw),
1488                                              OID_AUTO,
1489                                              device_get_nameunit(dev),
1490                                              CTLFLAG_RD, 0, "");
1491         if (sc->sk_sysctl_tree == NULL) {
1492                 device_printf(dev, "can't add sysctl node\n");
1493                 error = ENXIO;
1494                 goto fail;
1495         }
1496         SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx,
1497                         SYSCTL_CHILDREN(sc->sk_sysctl_tree),
1498                         OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW,
1499                         sc, 0, skc_sysctl_imtime, "I",
1500                         "Interrupt moderation time (usec).");
1501
1502         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1503         port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1504         *port = SK_PORT_A;
1505         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1506
1507         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1508                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1509                 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1510                 *port = SK_PORT_B;
1511                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1512         }
1513
1514         /* Turn on the 'driver is loaded' LED. */
1515         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1516
1517         bus_generic_attach(dev);
1518
1519         error = bus_setup_intr(dev, sc->sk_irq, INTR_MPSAFE, sk_intr, sc,
1520                                &sc->sk_intrhand, &sc->sk_serializer);
1521         if (error) {
1522                 device_printf(dev, "couldn't set up irq\n");
1523                 goto fail;
1524         }
1525
1526         cpuid = ithread_cpuid(rman_get_start(sc->sk_irq));
1527         KKASSERT(cpuid >= 0 && cpuid < ncpus);
1528
1529         if (sc->sk_if[0] != NULL)
1530                 sc->sk_if[0]->arpcom.ac_if.if_cpuid = cpuid;
1531         if (sc->sk_if[1] != NULL)
1532                 sc->sk_if[1]->arpcom.ac_if.if_cpuid = cpuid;
1533
1534         return 0;
1535 fail:
1536         skc_detach(dev);
1537         return error;
1538 }
1539
1540 static int
1541 sk_detach(device_t dev)
1542 {
1543         struct sk_if_softc *sc_if = device_get_softc(dev);
1544
1545         if (device_is_attached(dev)) {
1546                 struct sk_softc *sc = sc_if->sk_softc;
1547                 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1548
1549                 lwkt_serialize_enter(ifp->if_serializer);
1550
1551                 if (sc->sk_intrhand != NULL) {
1552                         if (sc->sk_if[SK_PORT_A] != NULL)
1553                                 sk_stop(sc->sk_if[SK_PORT_A]);
1554                         if (sc->sk_if[SK_PORT_B] != NULL)
1555                                 sk_stop(sc->sk_if[SK_PORT_B]);
1556
1557                         bus_teardown_intr(sc->sk_dev, sc->sk_irq,
1558                                           sc->sk_intrhand);
1559                         sc->sk_intrhand = NULL;
1560                 }
1561
1562                 lwkt_serialize_exit(ifp->if_serializer);
1563
1564                 ether_ifdetach(ifp);
1565         }
1566
1567         if (sc_if->sk_miibus != NULL)
1568                 device_delete_child(dev, sc_if->sk_miibus);
1569
1570         sk_dma_free(dev);
1571         return 0;
1572 }
1573
1574 static int
1575 skc_detach(device_t dev)
1576 {
1577         struct sk_softc *sc = device_get_softc(dev);
1578         int *port;
1579
1580 #ifdef INVARIANTS
1581         if (device_is_attached(dev)) {
1582                 KASSERT(sc->sk_intrhand == NULL,
1583                         ("intr has not been torn down yet"));
1584         }
1585 #endif
1586
1587         if (sc->sk_devs[SK_PORT_A] != NULL) {
1588                 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1589                 if (port != NULL) {
1590                         kfree(port, M_DEVBUF);
1591                         device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1592                 }
1593                 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1594         }
1595         if (sc->sk_devs[SK_PORT_B] != NULL) {
1596                 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1597                 if (port != NULL) {
1598                         kfree(port, M_DEVBUF);
1599                         device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1600                 }
1601                 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1602         }
1603
1604         if (sc->sk_irq != NULL) {
1605                 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1606                                      sc->sk_irq);
1607         }
1608         if (sc->sk_res != NULL) {
1609                 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1610                                      sc->sk_res);
1611         }
1612
1613         if (sc->sk_sysctl_tree != NULL)
1614                 sysctl_ctx_free(&sc->sk_sysctl_ctx);
1615
1616         return 0;
1617 }
1618
1619 static int
1620 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head0, uint32_t *txidx)
1621 {
1622         struct sk_chain_data *cd = &sc_if->sk_cdata;
1623         struct sk_ring_data *rd = &sc_if->sk_rdata;
1624         struct sk_tx_desc *f = NULL;
1625         uint32_t frag, cur, sk_ctl;
1626         bus_dma_segment_t segs[SK_NTXSEG];
1627         bus_dmamap_t map;
1628         int i, error, maxsegs, nsegs;
1629
1630         DPRINTFN(2, ("sk_encap\n"));
1631
1632         maxsegs = SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - SK_NDESC_RESERVE;
1633         KASSERT(maxsegs >= SK_NDESC_SPARE, ("not enough spare TX desc\n"));
1634         if (maxsegs > SK_NTXSEG)
1635                 maxsegs = SK_NTXSEG;
1636
1637         cur = frag = *txidx;
1638
1639 #ifdef SK_DEBUG
1640         if (skdebug >= 2)
1641                 sk_dump_mbuf(*m_head0);
1642 #endif
1643
1644         map = cd->sk_tx_dmap[*txidx];
1645
1646         error = bus_dmamap_load_mbuf_defrag(cd->sk_tx_dtag, map, m_head0,
1647                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1648         if (error) {
1649                 m_freem(*m_head0);
1650                 *m_head0 = NULL;
1651                 return error;
1652         }
1653
1654         DPRINTFN(2, ("sk_encap: nsegs=%d\n", nsegs));
1655
1656         /* Sync the DMA map. */
1657         bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1658
1659         for (i = 0; i < nsegs; i++) {
1660                 f = &rd->sk_tx_ring[frag];
1661                 f->sk_data_lo = htole32(SK_ADDR_LO(segs[i].ds_addr));
1662                 f->sk_data_hi = htole32(SK_ADDR_HI(segs[i].ds_addr));
1663                 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1664                 if (i == 0)
1665                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
1666                 else
1667                         sk_ctl |= SK_TXCTL_OWN;
1668                 f->sk_ctl = htole32(sk_ctl);
1669                 cur = frag;
1670                 SK_INC(frag, SK_TX_RING_CNT);
1671         }
1672
1673         cd->sk_tx_mbuf[cur] = *m_head0;
1674         /* Switch DMA map */
1675         cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1676         cd->sk_tx_dmap[cur] = map;
1677
1678         rd->sk_tx_ring[cur].sk_ctl |=
1679                 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1680         rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1681
1682         sc_if->sk_cdata.sk_tx_cnt += nsegs;
1683
1684 #ifdef SK_DEBUG
1685         if (skdebug >= 2) {
1686                 struct sk_tx_desc *desc;
1687                 uint32_t idx;
1688
1689                 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1690                         desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1691                         sk_dump_txdesc(desc, idx);
1692                 }
1693         }
1694 #endif
1695
1696         *txidx = frag;
1697
1698         DPRINTFN(2, ("sk_encap: completed successfully\n"));
1699
1700         return (0);
1701 }
1702
1703 static void
1704 sk_start(struct ifnet *ifp)
1705 {
1706         struct sk_if_softc *sc_if = ifp->if_softc;
1707         struct sk_softc *sc = sc_if->sk_softc;
1708         uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1709         int trans = 0;
1710
1711         DPRINTFN(2, ("sk_start\n"));
1712
1713         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1714                 return;
1715
1716         while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1717                 struct mbuf *m_head;
1718
1719                 if (SK_IS_OACTIVE(sc_if)) {
1720                         ifp->if_flags |= IFF_OACTIVE;
1721                         break;
1722                 }
1723
1724                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1725                 if (m_head == NULL)
1726                         break;
1727
1728                 /*
1729                  * Pack the data into the transmit ring. If we
1730                  * don't have room, set the OACTIVE flag and wait
1731                  * for the NIC to drain the ring.
1732                  */
1733                 if (sk_encap(sc_if, &m_head, &idx)) {
1734                         if (sc_if->sk_cdata.sk_tx_cnt == 0) {
1735                                 continue;
1736                         } else {
1737                                 ifp->if_flags |= IFF_OACTIVE;
1738                                 break;
1739                         }
1740                 }
1741
1742                 trans = 1;
1743                 BPF_MTAP(ifp, m_head);
1744         }
1745         if (!trans)
1746                 return;
1747
1748         /* Transmit */
1749         if (idx != sc_if->sk_cdata.sk_tx_prod) {
1750                 sc_if->sk_cdata.sk_tx_prod = idx;
1751                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1752
1753                 /* Set a timeout in case the chip goes out to lunch. */
1754                 ifp->if_timer = 5;
1755         }
1756 }
1757
1758 static void
1759 sk_watchdog(struct ifnet *ifp)
1760 {
1761         struct sk_if_softc *sc_if = ifp->if_softc;
1762
1763         ASSERT_SERIALIZED(ifp->if_serializer);
1764         /*
1765          * Reclaim first as there is a possibility of losing Tx completion
1766          * interrupts.
1767          */
1768         sk_txeof(sc_if);
1769         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1770                 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1771                 ifp->if_oerrors++;
1772                 ifp->if_flags &= ~IFF_RUNNING;
1773                 sk_init(sc_if);
1774         }
1775 }
1776
1777 static void
1778 skc_shutdown(device_t dev)
1779 {
1780         struct sk_softc *sc = device_get_softc(dev);
1781
1782         DPRINTFN(2, ("sk_shutdown\n"));
1783
1784         lwkt_serialize_enter(&sc->sk_serializer);
1785
1786         /* Turn off the 'driver is loaded' LED. */
1787         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1788
1789         /*
1790          * Reset the GEnesis controller. Doing this should also
1791          * assert the resets on the attached XMAC(s).
1792          */
1793         sk_reset(sc);
1794
1795         lwkt_serialize_exit(&sc->sk_serializer);
1796 }
1797
1798 static __inline int
1799 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1800 {
1801         if (sc->sk_type == SK_GENESIS) {
1802                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1803                     XM_RXSTAT_BYTES(stat) != len)
1804                         return (0);
1805         } else {
1806                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1807                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1808                     YU_RXSTAT_JABBER)) != 0 ||
1809                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1810                     YU_RXSTAT_BYTES(stat) != len)
1811                         return (0);
1812         }
1813
1814         return (1);
1815 }
1816
1817 static void
1818 sk_rxeof(struct sk_if_softc *sc_if)
1819 {
1820         struct sk_softc *sc = sc_if->sk_softc;
1821         struct ifnet *ifp = &sc_if->arpcom.ac_if;
1822         struct sk_chain_data *cd = &sc_if->sk_cdata;
1823         struct sk_ring_data *rd = &sc_if->sk_rdata;
1824         int i, reap, max_frmlen;
1825
1826         DPRINTFN(2, ("sk_rxeof\n"));
1827
1828         i = cd->sk_rx_prod;
1829
1830         if (sc_if->sk_use_jumbo)
1831                 max_frmlen = SK_JUMBO_FRAMELEN;
1832         else
1833                 max_frmlen = ETHER_MAX_LEN;
1834
1835         reap = 0;
1836         for (;;) {
1837                 struct sk_rx_desc *cur_desc;
1838                 uint32_t rxstat, sk_ctl;
1839 #ifdef SK_RXCSUM
1840                 uint16_t csum1, csum2;
1841 #endif
1842                 int cur, total_len;
1843                 struct mbuf *m;
1844
1845                 cur = i;
1846                 cur_desc = &rd->sk_rx_ring[cur];
1847
1848                 sk_ctl = le32toh(cur_desc->sk_ctl);
1849                 if (sk_ctl & SK_RXCTL_OWN) {
1850                         /* Invalidate the descriptor -- it's not ready yet */
1851                         cd->sk_rx_prod = cur;
1852                         break;
1853                 }
1854
1855                 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1856                 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1857
1858 #ifdef SK_RXCSUM
1859                 csum1 = le16toh(cur_desc->sk_csum1);
1860                 csum2 = le16toh(cur_desc->sk_csum2);
1861 #endif
1862
1863                 m = cd->sk_rx_mbuf[cur];
1864
1865                 /*
1866                  * Bump 'i' here, so we can keep going, even if the current
1867                  * RX descriptor reaping fails later.  'i' shoult NOT be used
1868                  * in the following processing any more.
1869                  */
1870                 SK_INC(i, SK_RX_RING_CNT);
1871                 reap = 1;
1872
1873                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1874                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1875                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1876                     total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1877                     sk_rxvalid(sc, rxstat, total_len) == 0) {
1878                         ifp->if_ierrors++;
1879                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1880                         continue;
1881                 }
1882
1883                 /*
1884                  * Try to allocate a new RX buffer. If that fails,
1885                  * copy the packet to mbufs and put the RX buffer
1886                  * back in the ring so it can be re-used. If
1887                  * allocating mbufs fails, then we have to drop
1888                  * the packet.
1889                  */
1890                 if (sk_newbuf(sc_if, cur, 0)) {
1891                         ifp->if_ierrors++;
1892                         cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1893                         continue;
1894                 } else {
1895                         m->m_pkthdr.rcvif = ifp;
1896                         m->m_pkthdr.len = m->m_len = total_len;
1897                 }
1898
1899 #ifdef SK_RXCSUM
1900                 sk_rxcsum(ifp, m, csum1, csum2);
1901 #endif
1902
1903                 ifp->if_ipackets++;
1904                 ifp->if_input(ifp, m);
1905         }
1906 }
1907
1908 #ifdef SK_RXCSUM
1909 static void
1910 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1911           const uint16_t csum1, const uint16_t csum2)
1912 {
1913         struct ether_header *eh;
1914         struct ip *ip;
1915         uint8_t *pp;
1916         int hlen, len, plen;
1917         uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1918
1919         pp = mtod(m, uint8_t *);
1920         plen = m->m_pkthdr.len;
1921         if (plen < sizeof(*eh))
1922                 return;
1923         eh = (struct ether_header *)pp;
1924         iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1925
1926         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1927                 uint16_t *xp = (uint16_t *)pp;
1928
1929                 xp = (uint16_t *)pp;
1930                 if (xp[1] != htons(ETHERTYPE_IP))
1931                         return;
1932                 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1933                 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1934                 xp = (uint16_t *)(pp + sizeof(struct ip));
1935                 iph_csum = in_addword(iph_csum, xp[0]);
1936                 iph_csum = in_addword(iph_csum, xp[1]);
1937                 pp += EVL_ENCAPLEN;
1938         } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1939                 return;
1940         }
1941
1942         pp += sizeof(*eh);
1943         plen -= sizeof(*eh);
1944
1945         ip = (struct ip *)pp;
1946
1947         if (ip->ip_v != IPVERSION)
1948                 return;
1949
1950         hlen = ip->ip_hl << 2;
1951         if (hlen < sizeof(struct ip))
1952                 return;
1953         if (hlen > ntohs(ip->ip_len))
1954                 return;
1955
1956         /* Don't deal with truncated or padded packets. */
1957         if (plen != ntohs(ip->ip_len))
1958                 return;
1959
1960         len = hlen - sizeof(struct ip);
1961         if (len > 0) {
1962                 uint16_t *p;
1963
1964                 p = (uint16_t *)(ip + 1);
1965                 ipo_csum = 0;
1966                 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1967                         ipo_csum = in_addword(ipo_csum, *p);
1968                 iph_csum = in_addword(iph_csum, ipo_csum);
1969                 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1970         } else {
1971                 ipd_csum = csum2;
1972         }
1973
1974         if (iph_csum != 0xffff)
1975                 return;
1976         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1977
1978         if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1979                 return;                 /* ip frag, we're done for now */
1980
1981         pp += hlen;
1982
1983         /* Only know checksum protocol for udp/tcp */
1984         if (ip->ip_p == IPPROTO_UDP) {
1985                 struct udphdr *uh = (struct udphdr *)pp;
1986
1987                 if (uh->uh_sum == 0)    /* udp with no checksum */
1988                         return;
1989         } else if (ip->ip_p != IPPROTO_TCP) {
1990                 return;
1991         }
1992
1993         csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1994             htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1995         if (csum == 0xffff) {
1996                 m->m_pkthdr.csum_data = csum;
1997                 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1998         }
1999 }
2000 #endif
2001
2002 static void
2003 sk_txeof(struct sk_if_softc *sc_if)
2004 {
2005         struct sk_chain_data *cd = &sc_if->sk_cdata;
2006         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2007         uint32_t idx;
2008         int reap = 0;
2009
2010         DPRINTFN(2, ("sk_txeof\n"));
2011
2012         /*
2013          * Go through our tx ring and free mbufs for those
2014          * frames that have been sent.
2015          */
2016         idx = cd->sk_tx_cons;
2017         while (idx != cd->sk_tx_prod) {
2018                 struct sk_tx_desc *cur_tx;
2019                 uint32_t sk_ctl;
2020
2021                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2022                 sk_ctl = le32toh(cur_tx->sk_ctl);
2023 #ifdef SK_DEBUG
2024                 if (skdebug >= 2)
2025                         sk_dump_txdesc(cur_tx, idx);
2026 #endif
2027                 if (sk_ctl & SK_TXCTL_OWN)
2028                         break;
2029                 if (sk_ctl & SK_TXCTL_LASTFRAG)
2030                         ifp->if_opackets++;
2031                 if (cd->sk_tx_mbuf[idx] != NULL) {
2032                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2033                         m_freem(cd->sk_tx_mbuf[idx]);
2034                         cd->sk_tx_mbuf[idx] = NULL;
2035                 }
2036                 sc_if->sk_cdata.sk_tx_cnt--;
2037                 reap = 1;
2038                 SK_INC(idx, SK_TX_RING_CNT);
2039         }
2040
2041         if (!SK_IS_OACTIVE(sc_if))
2042                 ifp->if_flags &= ~IFF_OACTIVE;
2043
2044         if (sc_if->sk_cdata.sk_tx_cnt == 0)
2045                 ifp->if_timer = 0;
2046
2047         sc_if->sk_cdata.sk_tx_cons = idx;
2048 }
2049
2050 static void
2051 sk_tick(void *xsc_if)
2052 {
2053         struct sk_if_softc *sc_if = xsc_if;
2054         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2055         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2056         int i;
2057
2058         DPRINTFN(2, ("sk_tick\n"));
2059
2060         lwkt_serialize_enter(ifp->if_serializer);
2061
2062         if ((ifp->if_flags & IFF_UP) == 0) {
2063                 lwkt_serialize_exit(ifp->if_serializer);
2064                 return;
2065         }
2066
2067         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2068                 sk_intr_bcom(sc_if);
2069                 lwkt_serialize_exit(ifp->if_serializer);
2070                 return;
2071         }
2072
2073         /*
2074          * According to SysKonnect, the correct way to verify that
2075          * the link has come back up is to poll bit 0 of the GPIO
2076          * register three times. This pin has the signal from the
2077          * link sync pin connected to it; if we read the same link
2078          * state 3 times in a row, we know the link is up.
2079          */
2080         for (i = 0; i < 3; i++) {
2081                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2082                         break;
2083         }
2084
2085         if (i != 3) {
2086                 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2087                 lwkt_serialize_exit(ifp->if_serializer);
2088                 return;
2089         }
2090
2091         /* Turn the GP0 interrupt back on. */
2092         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2093         SK_XM_READ_2(sc_if, XM_ISR);
2094         mii_tick(mii);
2095         callout_stop(&sc_if->sk_tick_timer);
2096         lwkt_serialize_exit(ifp->if_serializer);
2097 }
2098
2099 static void
2100 sk_yukon_tick(void *xsc_if)
2101 {
2102         struct sk_if_softc *sc_if = xsc_if;
2103         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2104         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2105
2106         lwkt_serialize_enter(ifp->if_serializer);
2107         mii_tick(mii);
2108         callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2109         lwkt_serialize_exit(ifp->if_serializer);
2110 }
2111
2112 static void
2113 sk_intr_bcom(struct sk_if_softc *sc_if)
2114 {
2115         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2116         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2117         int status;
2118
2119         DPRINTFN(2, ("sk_intr_bcom\n"));
2120
2121         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2122
2123         /*
2124          * Read the PHY interrupt register to make sure
2125          * we clear any pending interrupts.
2126          */
2127         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2128
2129         if ((ifp->if_flags & IFF_RUNNING) == 0) {
2130                 sk_init_xmac(sc_if);
2131                 return;
2132         }
2133
2134         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2135                 int lstat;
2136
2137                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2138                     BRGPHY_MII_AUXSTS);
2139
2140                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2141                         mii_mediachg(mii);
2142                         /* Turn off the link LED. */
2143                         SK_IF_WRITE_1(sc_if, 0,
2144                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
2145                         sc_if->sk_link = 0;
2146                 } else if (status & BRGPHY_ISR_LNK_CHG) {
2147                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2148                             BRGPHY_MII_IMR, 0xFF00);
2149                         mii_tick(mii);
2150                         sc_if->sk_link = 1;
2151                         /* Turn on the link LED. */
2152                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2153                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2154                             SK_LINKLED_BLINK_OFF);
2155                 } else {
2156                         mii_tick(mii);
2157                         callout_reset(&sc_if->sk_tick_timer, hz,
2158                                       sk_tick, sc_if);
2159                 }
2160         }
2161
2162         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2163 }
2164
2165 static void
2166 sk_intr_xmac(struct sk_if_softc *sc_if)
2167 {
2168         uint16_t status;
2169
2170         status = SK_XM_READ_2(sc_if, XM_ISR);
2171         DPRINTFN(2, ("sk_intr_xmac\n"));
2172
2173         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2174             (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2175                 if (status & XM_ISR_GP0_SET)
2176                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2177
2178                 callout_reset(&sc_if->sk_tick_timer, hz,
2179                               sk_tick, sc_if);
2180         }
2181
2182         if (status & XM_IMR_TX_UNDERRUN)
2183                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2184
2185         if (status & XM_IMR_RX_OVERRUN)
2186                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2187 }
2188
2189 static void
2190 sk_intr_yukon(struct sk_if_softc *sc_if)
2191 {
2192         uint8_t status;
2193
2194         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2195         /* RX overrun */
2196         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2197                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2198                     SK_RFCTL_RX_FIFO_OVER);
2199         }
2200         /* TX underrun */
2201         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2202                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2203                     SK_TFCTL_TX_FIFO_UNDER);
2204         }
2205
2206         DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2207 }
2208
2209 static void
2210 sk_intr(void *xsc)
2211 {
2212         struct sk_softc *sc = xsc;
2213         struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2214         struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2215         struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2216         uint32_t status;
2217
2218         ASSERT_SERIALIZED(&sc->sk_serializer);
2219
2220         status = CSR_READ_4(sc, SK_ISSR);
2221         if (status == 0 || status == 0xffffffff)
2222                 return;
2223
2224         if (sc_if0 != NULL)
2225                 ifp0 = &sc_if0->arpcom.ac_if;
2226         if (sc_if1 != NULL)
2227                 ifp1 = &sc_if1->arpcom.ac_if;
2228
2229         for (; (status &= sc->sk_intrmask) != 0;) {
2230                 /* Handle receive interrupts first. */
2231                 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2232                         sk_rxeof(sc_if0);
2233                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2234                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2235                 }
2236                 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2237                         sk_rxeof(sc_if1);
2238                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2239                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2240                 }
2241
2242                 /* Then transmit interrupts. */
2243                 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2244                         sk_txeof(sc_if0);
2245                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2246                             SK_TXBMU_CLR_IRQ_EOF);
2247                 }
2248                 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2249                         sk_txeof(sc_if1);
2250                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2251                             SK_TXBMU_CLR_IRQ_EOF);
2252                 }
2253
2254                 /* Then MAC interrupts. */
2255                 if (sc_if0 && (status & SK_ISR_MAC1) &&
2256                     (ifp0->if_flags & IFF_RUNNING)) {
2257                         if (SK_IS_GENESIS(sc))
2258                                 sk_intr_xmac(sc_if0);
2259                         else
2260                                 sk_intr_yukon(sc_if0);
2261                 }
2262
2263                 if (sc_if1 && (status & SK_ISR_MAC2) &&
2264                     (ifp1->if_flags & IFF_RUNNING)) {
2265                         if (SK_IS_GENESIS(sc))
2266                                 sk_intr_xmac(sc_if1);
2267                         else
2268                                 sk_intr_yukon(sc_if1);
2269                 }
2270
2271                 if (status & SK_ISR_EXTERNAL_REG) {
2272                         if (sc_if0 != NULL &&
2273                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2274                                 sk_intr_bcom(sc_if0);
2275
2276                         if (sc_if1 != NULL &&
2277                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2278                                 sk_intr_bcom(sc_if1);
2279                 }
2280                 status = CSR_READ_4(sc, SK_ISSR);
2281         }
2282
2283         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2284
2285         if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2286                 if_devstart(ifp0);
2287         if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2288                 if_devstart(ifp1);
2289 }
2290
2291 static void
2292 sk_init_xmac(struct sk_if_softc *sc_if)
2293 {
2294         struct sk_softc *sc = sc_if->sk_softc;
2295         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2296         static const struct sk_bcom_hack bhack[] = {
2297         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2298         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2299         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2300         { 0, 0 } };
2301
2302         DPRINTFN(2, ("sk_init_xmac\n"));
2303
2304         /* Unreset the XMAC. */
2305         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2306         DELAY(1000);
2307
2308         /* Reset the XMAC's internal state. */
2309         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2310
2311         /* Save the XMAC II revision */
2312         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2313
2314         /*
2315          * Perform additional initialization for external PHYs,
2316          * namely for the 1000baseT cards that use the XMAC's
2317          * GMII mode.
2318          */
2319         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2320                 int i = 0;
2321                 uint32_t val;
2322
2323                 /* Take PHY out of reset. */
2324                 val = sk_win_read_4(sc, SK_GPIO);
2325                 if (sc_if->sk_port == SK_PORT_A)
2326                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2327                 else
2328                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2329                 sk_win_write_4(sc, SK_GPIO, val);
2330
2331                 /* Enable GMII mode on the XMAC. */
2332                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2333
2334                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2335                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2336                 DELAY(10000);
2337                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2338                     BRGPHY_MII_IMR, 0xFFF0);
2339
2340                 /*
2341                  * Early versions of the BCM5400 apparently have
2342                  * a bug that requires them to have their reserved
2343                  * registers initialized to some magic values. I don't
2344                  * know what the numbers do, I'm just the messenger.
2345                  */
2346                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2347                     == 0x6041) {
2348                         while(bhack[i].reg) {
2349                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2350                                     bhack[i].reg, bhack[i].val);
2351                                 i++;
2352                         }
2353                 }
2354         }
2355
2356         /* Set station address */
2357         SK_XM_WRITE_2(sc_if, XM_PAR0,
2358             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2359         SK_XM_WRITE_2(sc_if, XM_PAR1,
2360             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2361         SK_XM_WRITE_2(sc_if, XM_PAR2,
2362             *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2363         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2364
2365         if (ifp->if_flags & IFF_BROADCAST)
2366                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2367         else
2368                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2369
2370         /* We don't need the FCS appended to the packet. */
2371         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2372
2373         /* We want short frames padded to 60 bytes. */
2374         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2375
2376         /*
2377          * Enable the reception of all error frames. This is
2378          * a necessary evil due to the design of the XMAC. The
2379          * XMAC's receive FIFO is only 8K in size, however jumbo
2380          * frames can be up to 9000 bytes in length. When bad
2381          * frame filtering is enabled, the XMAC's RX FIFO operates
2382          * in 'store and forward' mode. For this to work, the
2383          * entire frame has to fit into the FIFO, but that means
2384          * that jumbo frames larger than 8192 bytes will be
2385          * truncated. Disabling all bad frame filtering causes
2386          * the RX FIFO to operate in streaming mode, in which
2387          * case the XMAC will start transfering frames out of the
2388          * RX FIFO as soon as the FIFO threshold is reached.
2389          */
2390         if (sc_if->sk_use_jumbo) {
2391                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2392                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2393                     XM_MODE_RX_INRANGELEN);
2394         }
2395
2396         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2397
2398         /*
2399          * Bump up the transmit threshold. This helps hold off transmit
2400          * underruns when we're blasting traffic from both ports at once.
2401          */
2402         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2403
2404         /* Set promiscuous mode */
2405         sk_setpromisc(sc_if);
2406
2407         /* Set multicast filter */
2408         sk_setmulti(sc_if);
2409
2410         /* Clear and enable interrupts */
2411         SK_XM_READ_2(sc_if, XM_ISR);
2412         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2413                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2414         else
2415                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2416
2417         /* Configure MAC arbiter */
2418         switch(sc_if->sk_xmac_rev) {
2419         case XM_XMAC_REV_B2:
2420                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2421                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2422                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2423                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2424                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2425                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2426                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2427                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2428                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2429                 break;
2430         case XM_XMAC_REV_C1:
2431                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2432                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2433                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2434                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2435                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2436                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2437                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2438                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2439                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2440                 break;
2441         default:
2442                 break;
2443         }
2444         sk_win_write_2(sc, SK_MACARB_CTL,
2445             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2446
2447         sc_if->sk_link = 1;
2448 }
2449
2450 static void
2451 sk_init_yukon(struct sk_if_softc *sc_if)
2452 {
2453         uint32_t phy, v;
2454         uint16_t reg;
2455         struct sk_softc *sc;
2456         int i;
2457
2458         sc = sc_if->sk_softc;
2459
2460         DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2461                      CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2462
2463         if (sc->sk_type == SK_YUKON_LITE &&
2464             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2465                 /*
2466                  * Workaround code for COMA mode, set PHY reset.
2467                  * Otherwise it will not correctly take chip out of
2468                  * powerdown (coma)
2469                  */
2470                 v = sk_win_read_4(sc, SK_GPIO);
2471                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2472                 sk_win_write_4(sc, SK_GPIO, v);
2473         }
2474
2475         DPRINTFN(6, ("sk_init_yukon: 1\n"));
2476
2477         /* GMAC and GPHY Reset */
2478         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2479         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2480         DELAY(1000);
2481
2482         DPRINTFN(6, ("sk_init_yukon: 2\n"));
2483
2484         if (sc->sk_type == SK_YUKON_LITE &&
2485             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2486                 /*
2487                  * Workaround code for COMA mode, clear PHY reset
2488                  */
2489                 v = sk_win_read_4(sc, SK_GPIO);
2490                 v |= SK_GPIO_DIR9;
2491                 v &= ~SK_GPIO_DAT9;
2492                 sk_win_write_4(sc, SK_GPIO, v);
2493         }
2494
2495         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2496                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2497
2498         if (sc->sk_coppertype)
2499                 phy |= SK_GPHY_COPPER;
2500         else
2501                 phy |= SK_GPHY_FIBER;
2502
2503         DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2504
2505         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2506         DELAY(1000);
2507         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2508         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2509                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2510
2511         DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2512                      SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2513
2514         DPRINTFN(6, ("sk_init_yukon: 3\n"));
2515
2516         /* unused read of the interrupt source register */
2517         DPRINTFN(6, ("sk_init_yukon: 4\n"));
2518         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2519
2520         DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2521         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2522         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2523
2524         /* MIB Counter Clear Mode set */
2525         reg |= YU_PAR_MIB_CLR;
2526         DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2527         DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2528         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2529
2530         /* MIB Counter Clear Mode clear */
2531         DPRINTFN(6, ("sk_init_yukon: 5\n"));
2532         reg &= ~YU_PAR_MIB_CLR;
2533         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2534
2535         /* receive control reg */
2536         DPRINTFN(6, ("sk_init_yukon: 7\n"));
2537         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2538
2539         /* transmit parameter register */
2540         DPRINTFN(6, ("sk_init_yukon: 8\n"));
2541         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2542                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2543
2544         /* serial mode register */
2545         DPRINTFN(6, ("sk_init_yukon: 9\n"));
2546         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2547         if (sc_if->sk_use_jumbo)
2548                 reg |= YU_SMR_MFL_JUMBO;
2549         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2550
2551         DPRINTFN(6, ("sk_init_yukon: 10\n"));
2552         /* Setup Yukon's address */
2553         for (i = 0; i < 3; i++) {
2554                 /* Write Source Address 1 (unicast filter) */
2555                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2556                               sc_if->arpcom.ac_enaddr[i * 2] |
2557                               sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2558         }
2559
2560         for (i = 0; i < 3; i++) {
2561                 reg = sk_win_read_2(sc_if->sk_softc,
2562                                     SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2563                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2564         }
2565
2566         /* Set promiscuous mode */
2567         sk_setpromisc(sc_if);
2568
2569         /* Set multicast filter */
2570         DPRINTFN(6, ("sk_init_yukon: 11\n"));
2571         sk_setmulti(sc_if);
2572
2573         /* enable interrupt mask for counter overflows */
2574         DPRINTFN(6, ("sk_init_yukon: 12\n"));
2575         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2576         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2577         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2578
2579         /* Configure RX MAC FIFO Flush Mask */
2580         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2581             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2582             YU_RXSTAT_JABBER;
2583         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2584
2585         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2586         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2587                 v = SK_TFCTL_OPERATION_ON;
2588         else
2589                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2590         /* Configure RX MAC FIFO */
2591         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2592         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2593
2594         /* Increase flush threshould to 64 bytes */
2595         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2596             SK_RFCTL_FIFO_THRESHOLD + 1);
2597
2598         /* Configure TX MAC FIFO */
2599         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2600         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2601
2602         DPRINTFN(6, ("sk_init_yukon: end\n"));
2603 }
2604
2605 /*
2606  * Note that to properly initialize any part of the GEnesis chip,
2607  * you first have to take it out of reset mode.
2608  */
2609 static void
2610 sk_init(void *xsc_if)
2611 {
2612         struct sk_if_softc *sc_if = xsc_if;
2613         struct sk_softc *sc = sc_if->sk_softc;
2614         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2615         struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2616
2617         DPRINTFN(2, ("sk_init\n"));
2618
2619         ASSERT_SERIALIZED(ifp->if_serializer);
2620
2621         if (ifp->if_flags & IFF_RUNNING)
2622                 return;
2623
2624         /* Cancel pending I/O and free all RX/TX buffers. */
2625         sk_stop(sc_if);
2626
2627         /*
2628          * NOTE: Change sk_use_jumbo after sk_stop(),
2629          *       but before real initialization.
2630          */
2631         if (ifp->if_mtu > ETHER_MAX_LEN)
2632                 sc_if->sk_use_jumbo = 1;
2633         else
2634                 sc_if->sk_use_jumbo = 0;
2635         DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2636
2637         if (SK_IS_GENESIS(sc)) {
2638                 /* Configure LINK_SYNC LED */
2639                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2640                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2641                         SK_LINKLED_LINKSYNC_ON);
2642
2643                 /* Configure RX LED */
2644                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2645                         SK_RXLEDCTL_COUNTER_START);
2646
2647                 /* Configure TX LED */
2648                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2649                         SK_TXLEDCTL_COUNTER_START);
2650         }
2651
2652         /*
2653          * Configure descriptor poll timer
2654          *
2655          * SK-NET GENESIS data sheet says that possibility of losing Start
2656          * transmit command due to CPU/cache related interim storage problems
2657          * under certain conditions. The document recommends a polling
2658          * mechanism to send a Start transmit command to initiate transfer
2659          * of ready descriptors regulary. To cope with this issue sk(4) now
2660          * enables descriptor poll timer to initiate descriptor processing
2661          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2662          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2663          * command instead of waiting for next descriptor polling time.
2664          * The same rule may apply to Rx side too but it seems that is not
2665          * needed at the moment.
2666          * Since sk(4) uses descriptor polling as a last resort there is no
2667          * need to set smaller polling time than maximum allowable one.
2668          */
2669         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2670
2671         /* Configure I2C registers */
2672
2673         /* Configure XMAC(s) */
2674         switch (sc->sk_type) {
2675         case SK_GENESIS:
2676                 sk_init_xmac(sc_if);
2677                 break;
2678         case SK_YUKON:
2679         case SK_YUKON_LITE:
2680         case SK_YUKON_LP:
2681                 sk_init_yukon(sc_if);
2682                 break;
2683         }
2684         mii_mediachg(mii);
2685
2686         if (SK_IS_GENESIS(sc)) {
2687                 /* Configure MAC FIFOs */
2688                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2689                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2690                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2691
2692                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2693                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2694                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2695         }
2696
2697         /* Configure transmit arbiter(s) */
2698         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2699             SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2700
2701         /* Configure RAMbuffers */
2702         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2703         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2704         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2705         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2706         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2707         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2708
2709         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2710         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2711         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2712         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2713         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2714         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2715         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2716
2717         /* Configure BMUs */
2718         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2719         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2720                       SK_ADDR_LO(sc_if->sk_rdata.sk_rx_ring_paddr));
2721         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
2722                       SK_ADDR_HI(sc_if->sk_rdata.sk_rx_ring_paddr));
2723
2724         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2725         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2726                       SK_ADDR_LO(sc_if->sk_rdata.sk_tx_ring_paddr));
2727         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
2728                       SK_ADDR_HI(sc_if->sk_rdata.sk_tx_ring_paddr));
2729
2730         /* Init descriptors */
2731         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2732                 if_printf(ifp, "initialization failed: "
2733                           "no memory for rx buffers\n");
2734                 sk_stop(sc_if);
2735                 return;
2736         }
2737
2738         if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2739                 if_printf(ifp, "initialization failed: "
2740                           "no memory for tx buffers\n");
2741                 sk_stop(sc_if);
2742                 return;
2743         }
2744
2745         /* Configure interrupt handling */
2746         CSR_READ_4(sc, SK_ISSR);
2747         if (sc_if->sk_port == SK_PORT_A)
2748                 sc->sk_intrmask |= SK_INTRS1;
2749         else
2750                 sc->sk_intrmask |= SK_INTRS2;
2751
2752         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2753
2754         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2755
2756         /* Start BMUs. */
2757         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2758
2759         if (SK_IS_GENESIS(sc)) {
2760                 /* Enable XMACs TX and RX state machines */
2761                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2762                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2763                                XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2764         }
2765
2766         if (SK_IS_YUKON(sc)) {
2767                 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2768                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2769 #if 0
2770                 /* XXX disable 100Mbps and full duplex mode? */
2771                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2772 #endif
2773                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2774         }
2775
2776         /* Activate descriptor polling timer */
2777         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2778         /* Start transfer of Tx descriptors */
2779         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2780
2781         ifp->if_flags |= IFF_RUNNING;
2782         ifp->if_flags &= ~IFF_OACTIVE;
2783
2784         if (SK_IS_YUKON(sc))
2785                 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2786 }
2787
2788 static void
2789 sk_stop(struct sk_if_softc *sc_if)
2790 {
2791         struct sk_softc *sc = sc_if->sk_softc;
2792         struct ifnet *ifp = &sc_if->arpcom.ac_if;
2793         struct sk_chain_data *cd = &sc_if->sk_cdata;
2794         uint32_t val;
2795         int i;
2796
2797         ASSERT_SERIALIZED(ifp->if_serializer);
2798
2799         DPRINTFN(2, ("sk_stop\n"));
2800
2801         callout_stop(&sc_if->sk_tick_timer);
2802
2803         ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2804
2805         /* Stop Tx descriptor polling timer */
2806         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2807
2808         /* Stop transfer of Tx descriptors */
2809         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2810         for (i = 0; i < SK_TIMEOUT; i++) {
2811                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2812                 if (!(val & SK_TXBMU_TX_STOP))
2813                         break;
2814                 DELAY(1);
2815         }
2816         if (i == SK_TIMEOUT)
2817                 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2818
2819         /* Stop transfer of Rx descriptors */
2820         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2821         for (i = 0; i < SK_TIMEOUT; i++) {
2822                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2823                 if (!(val & SK_RXBMU_RX_STOP))
2824                         break;
2825                 DELAY(1);
2826         }
2827         if (i == SK_TIMEOUT)
2828                 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2829
2830         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2831                 /* Put PHY back into reset. */
2832                 val = sk_win_read_4(sc, SK_GPIO);
2833                 if (sc_if->sk_port == SK_PORT_A) {
2834                         val |= SK_GPIO_DIR0;
2835                         val &= ~SK_GPIO_DAT0;
2836                 } else {
2837                         val |= SK_GPIO_DIR2;
2838                         val &= ~SK_GPIO_DAT2;
2839                 }
2840                 sk_win_write_4(sc, SK_GPIO, val);
2841         }
2842
2843         /* Turn off various components of this interface. */
2844         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2845         switch (sc->sk_type) {
2846         case SK_GENESIS:
2847                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2848                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2849                 break;
2850         case SK_YUKON:
2851         case SK_YUKON_LITE:
2852         case SK_YUKON_LP:
2853                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2854                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2855                 break;
2856         }
2857         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2858         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2859         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2860         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2861             SK_RBCTL_RESET | SK_RBCTL_OFF);
2862         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2863         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2864         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2865         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2866         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2867
2868         /* Disable interrupts */
2869         if (sc_if->sk_port == SK_PORT_A)
2870                 sc->sk_intrmask &= ~SK_INTRS1;
2871         else
2872                 sc->sk_intrmask &= ~SK_INTRS2;
2873         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2874
2875         SK_XM_READ_2(sc_if, XM_ISR);
2876         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2877
2878         /* Free RX and TX mbufs still in the queues. */
2879         for (i = 0; i < SK_RX_RING_CNT; i++) {
2880                 if (cd->sk_rx_mbuf[i] != NULL) {
2881                         if (!sc_if->sk_use_jumbo) {
2882                                 bus_dmamap_unload(cd->sk_rx_dtag,
2883                                                   cd->sk_rx_dmap[i]);
2884                         }
2885                         m_freem(cd->sk_rx_mbuf[i]);
2886                         cd->sk_rx_mbuf[i] = NULL;
2887                 }
2888         }
2889         for (i = 0; i < SK_TX_RING_CNT; i++) {
2890                 if (cd->sk_tx_mbuf[i] != NULL) {
2891                         bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2892                         m_freem(cd->sk_tx_mbuf[i]);
2893                         cd->sk_tx_mbuf[i] = NULL;
2894                 }
2895         }
2896 }
2897
2898 #ifdef SK_DEBUG
2899 static void
2900 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2901 {
2902 #define DESC_PRINT(X)                                   \
2903         if (X)                                  \
2904                 kprintf("txdesc[%d]." #X "=%#x\n",      \
2905                        idx, X);
2906
2907         DESC_PRINT(le32toh(desc->sk_ctl));
2908         DESC_PRINT(le32toh(desc->sk_next));
2909         DESC_PRINT(le32toh(desc->sk_data_lo));
2910         DESC_PRINT(le32toh(desc->sk_data_hi));
2911         DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2912         DESC_PRINT(le16toh(desc->sk_rsvd0));
2913         DESC_PRINT(le16toh(desc->sk_csum_startval));
2914         DESC_PRINT(le16toh(desc->sk_csum_startpos));
2915         DESC_PRINT(le16toh(desc->sk_csum_writepos));
2916         DESC_PRINT(le16toh(desc->sk_rsvd1));
2917 #undef PRINT
2918 }
2919
2920 static void
2921 sk_dump_bytes(const char *data, int len)
2922 {
2923         int c, i, j;
2924
2925         for (i = 0; i < len; i += 16) {
2926                 kprintf("%08x  ", i);
2927                 c = len - i;
2928                 if (c > 16) c = 16;
2929
2930                 for (j = 0; j < c; j++) {
2931                         kprintf("%02x ", data[i + j] & 0xff);
2932                         if ((j & 0xf) == 7 && j > 0)
2933                                 kprintf(" ");
2934                 }
2935
2936                 for (; j < 16; j++)
2937                         kprintf("   ");
2938                 kprintf("  ");
2939
2940                 for (j = 0; j < c; j++) {
2941                         int ch = data[i + j] & 0xff;
2942                         kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2943                 }
2944
2945                 kprintf("\n");
2946
2947                 if (c < 16)
2948                         break;
2949         }
2950 }
2951
2952 static void
2953 sk_dump_mbuf(struct mbuf *m)
2954 {
2955         int count = m->m_pkthdr.len;
2956
2957         kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2958
2959         while (count > 0 && m) {
2960                 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2961                        m, m->m_data, m->m_len);
2962                 sk_dump_bytes(mtod(m, char *), m->m_len);
2963
2964                 count -= m->m_len;
2965                 m = m->m_next;
2966         }
2967 }
2968 #endif
2969
2970 /*
2971  * Allocate jumbo buffer storage. The SysKonnect adapters support
2972  * "jumbograms" (9K frames), although SysKonnect doesn't currently
2973  * use them in their drivers. In order for us to use them, we need
2974  * large 9K receive buffers, however standard mbuf clusters are only
2975  * 2048 bytes in size. Consequently, we need to allocate and manage
2976  * our own jumbo buffer pool. Fortunately, this does not require an
2977  * excessive amount of additional code.
2978  */
2979 static int
2980 sk_jpool_alloc(device_t dev)
2981 {
2982         struct sk_if_softc *sc_if = device_get_softc(dev);
2983         struct sk_chain_data *cd = &sc_if->sk_cdata;
2984         bus_dmamem_t dmem;
2985         bus_addr_t paddr;
2986         caddr_t buf;
2987         int error, i;
2988
2989         lwkt_serialize_init(&cd->sk_jpool_serializer);
2990
2991         error = bus_dmamem_coherent(cd->sk_buf_dtag, PAGE_SIZE /* XXX */, 0,
2992                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2993                                     SK_JMEM, BUS_DMA_WAITOK, &dmem);
2994         if (error) {
2995                 device_printf(dev, "can't allocate jumbo frame pool\n");
2996                 return error;
2997         }
2998         cd->sk_jpool_dtag = dmem.dmem_tag;
2999         cd->sk_jpool_dmap = dmem.dmem_map;
3000         cd->sk_jpool = dmem.dmem_addr;
3001         paddr = dmem.dmem_busaddr;
3002
3003         SLIST_INIT(&cd->sk_jpool_free_ent);
3004         buf = cd->sk_jpool;
3005
3006         /*
3007          * Now divide it up into SK_JLEN pieces.
3008          */
3009         for (i = 0; i < SK_JSLOTS; i++) {
3010                 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
3011
3012                 entry->sc_if = sc_if;
3013                 entry->inuse = 0;
3014                 entry->slot = i;
3015                 entry->buf = buf;
3016                 entry->paddr = paddr;
3017
3018                 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3019
3020                 buf += SK_JLEN;
3021                 paddr += SK_JLEN;
3022         }
3023         return 0;
3024 }
3025
3026 static void
3027 sk_jpool_free(struct sk_if_softc *sc_if)
3028 {
3029         struct sk_chain_data *cd = &sc_if->sk_cdata;
3030
3031         if (cd->sk_jpool_dtag != NULL) {
3032                 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3033                 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3034                                 cd->sk_jpool_dmap);
3035                 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3036                 cd->sk_jpool_dtag = NULL;
3037         }
3038 }
3039
3040 static int
3041 sk_dma_alloc(device_t dev)
3042 {
3043         struct sk_if_softc *sc_if = device_get_softc(dev);
3044         struct sk_chain_data *cd = &sc_if->sk_cdata;
3045         struct sk_ring_data *rd = &sc_if->sk_rdata;
3046         bus_dmamem_t dmem;
3047         int i, j, error;
3048
3049         /* Create parent DMA tag */
3050         error = bus_dma_tag_create(NULL, 1, 0,
3051                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3052                                    NULL, NULL,
3053                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3054                                    BUS_SPACE_MAXSIZE_32BIT,
3055                                    0, &sc_if->sk_parent_dtag);
3056         if (error) {
3057                 device_printf(dev, "can't create parent DMA tag\n");
3058                 return error;
3059         }
3060
3061         /* Create top level ring DMA tag */
3062         error = bus_dma_tag_create(sc_if->sk_parent_dtag,
3063                                    1, SK_RING_BOUNDARY,
3064                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3065                                    NULL, NULL,
3066                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3067                                    BUS_SPACE_MAXSIZE_32BIT,
3068                                    0, &rd->sk_ring_dtag);
3069         if (error) {
3070                 device_printf(dev, "can't create ring DMA tag\n");
3071                 return error;
3072         }
3073
3074         /* Create top level buffer DMA tag */
3075         error = bus_dma_tag_create(sc_if->sk_parent_dtag, 1, 0,
3076                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3077                                    NULL, NULL,
3078                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3079                                    BUS_SPACE_MAXSIZE_32BIT,
3080                                    0, &cd->sk_buf_dtag);
3081         if (error) {
3082                 device_printf(dev, "can't create buf DMA tag\n");
3083                 return error;
3084         }
3085
3086         /* Allocate the TX descriptor queue. */
3087         error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3088                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3089                                     SK_TX_RING_SIZE,
3090                                     BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3091         if (error) {
3092                 device_printf(dev, "can't allocate TX ring\n");
3093                 return error;
3094         }
3095         rd->sk_tx_ring_dtag = dmem.dmem_tag;
3096         rd->sk_tx_ring_dmap = dmem.dmem_map;
3097         rd->sk_tx_ring = dmem.dmem_addr;
3098         rd->sk_tx_ring_paddr = dmem.dmem_busaddr;
3099
3100         /* Allocate the RX descriptor queue. */
3101         error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3102                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3103                                     SK_RX_RING_SIZE,
3104                                     BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3105         if (error) {
3106                 device_printf(dev, "can't allocate TX ring\n");
3107                 return error;
3108         }
3109         rd->sk_rx_ring_dtag = dmem.dmem_tag;
3110         rd->sk_rx_ring_dmap = dmem.dmem_map;
3111         rd->sk_rx_ring = dmem.dmem_addr;
3112         rd->sk_rx_ring_paddr = dmem.dmem_busaddr;
3113
3114         /* Try to allocate memory for jumbo buffers. */
3115         error = sk_jpool_alloc(dev);
3116         if (error) {
3117                 device_printf(dev, "jumbo buffer allocation failed\n");
3118                 return error;
3119         }
3120
3121         /* Create DMA tag for TX. */
3122         error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3123                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3124                                    NULL, NULL,
3125                                    SK_JLEN, SK_NTXSEG, SK_JLEN,
3126                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3127                                    BUS_DMA_ONEBPAGE,
3128                                    &cd->sk_tx_dtag);
3129         if (error) {
3130                 device_printf(dev, "can't create TX DMA tag\n");
3131                 return error;
3132         }
3133
3134         /* Create DMA maps for TX. */
3135         for (i = 0; i < SK_TX_RING_CNT; i++) {
3136                 error = bus_dmamap_create(cd->sk_tx_dtag,
3137                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3138                                           &cd->sk_tx_dmap[i]);
3139                 if (error) {
3140                         device_printf(dev, "can't create %dth TX DMA map\n", i);
3141
3142                         for (j = 0; j < i; ++j) {
3143                                 bus_dmamap_destroy(cd->sk_tx_dtag,
3144                                                    cd->sk_tx_dmap[i]);
3145                         }
3146                         bus_dma_tag_destroy(cd->sk_tx_dtag);
3147                         cd->sk_tx_dtag = NULL;
3148                         return error;
3149                 }
3150         }
3151
3152         /* Create DMA tag for RX. */
3153         error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3154                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3155                                    NULL, NULL,
3156                                    MCLBYTES, 1, MCLBYTES,
3157                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3158                                    &cd->sk_rx_dtag);
3159         if (error) {
3160                 device_printf(dev, "can't create RX DMA tag\n");
3161                 return error;
3162         }
3163
3164         /* Create a spare RX DMA map. */
3165         error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3166                                   &cd->sk_rx_dmap_tmp);
3167         if (error) {
3168                 device_printf(dev, "can't create spare RX DMA map\n");
3169                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3170                 cd->sk_rx_dtag = NULL;
3171                 return error;
3172         }
3173
3174         /* Create DMA maps for RX. */
3175         for (i = 0; i < SK_RX_RING_CNT; ++i) {
3176                 error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3177                                           &cd->sk_rx_dmap[i]);
3178                 if (error) {
3179                         device_printf(dev, "can't create %dth RX DMA map\n", i);
3180
3181                         for (j = 0; j < i; ++j) {
3182                                 bus_dmamap_destroy(cd->sk_rx_dtag,
3183                                                    cd->sk_rx_dmap[i]);
3184                         }
3185                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3186                         bus_dma_tag_destroy(cd->sk_rx_dtag);
3187                         cd->sk_rx_dtag = NULL;
3188                         return error;
3189                 }
3190         }
3191         return 0;
3192 }
3193
3194 static void
3195 sk_dma_free(device_t dev)
3196 {
3197         struct sk_if_softc *sc_if = device_get_softc(dev);
3198         struct sk_chain_data *cd = &sc_if->sk_cdata;
3199         struct sk_ring_data *rd = &sc_if->sk_rdata;
3200         int i;
3201
3202         if (cd->sk_tx_dtag != NULL) {
3203                 for (i = 0; i < SK_TX_RING_CNT; ++i) {
3204                         KASSERT(cd->sk_tx_mbuf[i] == NULL,
3205                                 ("sk_stop() is not called before %s()",
3206                                  __func__));
3207                         bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3208                 }
3209                 bus_dma_tag_destroy(cd->sk_tx_dtag);
3210         }
3211
3212         if (cd->sk_rx_dtag != NULL) {
3213                 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3214                         KASSERT(cd->sk_rx_mbuf[i] == NULL,
3215                                 ("sk_stop() is not called before %s()",
3216                                  __func__));
3217                         bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3218                 }
3219                 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3220                 bus_dma_tag_destroy(cd->sk_rx_dtag);
3221         }
3222
3223         sk_jpool_free(sc_if);
3224
3225         if (rd->sk_rx_ring_dtag != NULL) {
3226                 bus_dmamap_unload(rd->sk_rx_ring_dtag, rd->sk_rx_ring_dmap);
3227                 bus_dmamem_free(rd->sk_rx_ring_dtag, rd->sk_rx_ring,
3228                                 rd->sk_rx_ring_dmap);
3229                 bus_dma_tag_destroy(rd->sk_rx_ring_dtag);
3230         }
3231
3232         if (rd->sk_tx_ring_dtag != NULL) {
3233                 bus_dmamap_unload(rd->sk_tx_ring_dtag, rd->sk_tx_ring_dmap);
3234                 bus_dmamem_free(rd->sk_tx_ring_dtag, rd->sk_tx_ring,
3235                                 rd->sk_tx_ring_dmap);
3236                 bus_dma_tag_destroy(rd->sk_tx_ring_dtag);
3237         }
3238
3239         if (rd->sk_ring_dtag != NULL)
3240                 bus_dma_tag_destroy(rd->sk_ring_dtag);
3241         if (cd->sk_buf_dtag != NULL)
3242                 bus_dma_tag_destroy(cd->sk_buf_dtag);
3243         if (sc_if->sk_parent_dtag != NULL)
3244                 bus_dma_tag_destroy(sc_if->sk_parent_dtag);
3245 }
3246
3247 static int
3248 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)
3249 {
3250         struct sk_softc *sc = arg1;
3251         struct lwkt_serialize *slize = &sc->sk_serializer;
3252         int error = 0, v;
3253
3254         lwkt_serialize_enter(slize);
3255
3256         v = sc->sk_imtime;
3257         error = sysctl_handle_int(oidp, &v, 0, req);
3258         if (error || req->newptr == NULL)
3259                 goto back;
3260         if (v <= 0) {
3261                 error = EINVAL;
3262                 goto back;
3263         }
3264
3265         if (sc->sk_imtime != v) {
3266                 sc->sk_imtime = v;
3267                 sk_win_write_4(sc, SK_IMTIMERINIT,
3268                                SK_IM_USECS(sc, sc->sk_imtime));
3269
3270                 /*
3271                  * Force interrupt moderation timer to
3272                  * reload new value.
3273                  */
3274                 sk_win_write_4(sc, SK_IMTIMER, 0);
3275         }
3276 back:
3277         lwkt_serialize_exit(slize);
3278         return error;
3279 }