2 * Copyright (c) 2008 The DragonFly Project. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
14 * 3. Neither the name of The DragonFly Project nor the names of its
15 * contributors may be used to endorse or promote products derived
16 * from this software without specific, prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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31 * from: vector.s, 386BSD 0.1 unknown origin
32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
33 * $DragonFly: src/sys/platform/pc64/icu/icu_vector.s,v 1.1 2008/08/29 17:07:16 dillon Exp $
36 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
39 #include "opt_auto_eoi.h"
41 #include <machine/asmacros.h>
42 #include <machine/lock.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/segments.h>
46 #include <machine_base/icu/icu.h>
47 #include <machine_base/icu/icu_ipl.h>
49 #include <bus/isa/i386/isa.h>
53 #define ICU_EOI 0x20 /* XXX - define elsewhere */
55 #define IRQ_LBIT(irq_num) (1 << (irq_num))
56 #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
57 #define IRQ_BYTE(irq_num) ((irq_num) >> 3)
60 #define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
64 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
65 OUTB_ICU1 ; /* ... to clear in service bit */ \
74 * The data sheet says no auto-EOI on slave, but it sometimes works.
76 #define ENABLE_ICU1_AND_2 ENABLE_ICU1
78 #define ENABLE_ICU1_AND_2 \
79 movb $ICU_EOI,%al ; /* as above */ \
80 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
81 OUTB_ICU1 ; /* ... then first icu (if !AUTO_EOI_1) */ \
88 #define ICU_PUSH_FRAME \
89 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \
90 movl $0,TF_XFLAGS(%rsp) ; \
91 movl $0,TF_TRAPNO(%rsp) ; \
92 movl $0,TF_ADDR(%rsp) ; \
93 movl $0,TF_FLAGS(%rsp) ; \
94 movl $0,TF_ERR(%rsp) ; \
97 #define MASK_IRQ(icu, irq_num) \
99 movb icu_imen + IRQ_BYTE(irq_num),%al ; \
100 orb $IRQ_BIT(irq_num),%al ; \
101 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \
102 outb %al,$icu+ICU_IMR_OFFSET ; \
105 #define UNMASK_IRQ(icu, irq_num) \
109 movb icu_imen + IRQ_BYTE(irq_num),%al ; \
110 andb $~IRQ_BIT(irq_num),%al ; \
111 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \
112 outb %al,$icu+ICU_IMR_OFFSET ; \
117 * Interrupt call handlers run in the following sequence:
119 * - Push the trap frame required by doreti.
120 * - Mask the interrupt and reenable its source.
121 * - If we cannot take the interrupt set its ipending bit and
123 * - If we can take the interrupt clear its ipending bit,
124 * call the handler, then unmask the interrupt and doreti.
126 * YYY can cache gd base pointer instead of using hidden %fs
130 #define INTR_HANDLER(irq_num, icu, enable_icus) \
133 IDTVEC(icu_intr##irq_num) ; \
135 FAKE_MCOUNT(TF_RIP(%rsp)) ; \
136 MASK_IRQ(icu, irq_num) ; \
138 movq PCPU(curthread),%rbx ; \
139 testl $-1,TD_NEST_COUNT(%rbx) ; \
141 testl $-1,TD_CRITCOUNT(%rbx) ; \
144 /* set pending bit and return, leave interrupt masked */ \
146 orq $IRQ_LBIT(irq_num),PCPU_E8(ipending,%edx) ; \
147 orl $RQF_INTPEND, PCPU(reqflags) ; \
150 /* clear pending bit, run handler */ \
152 andq $~IRQ_LBIT(irq_num),PCPU_E8(ipending,%edx) ; \
154 movq %rsp,%rdi ; /* rdi = call argument */ \
155 incl TD_CRITCOUNT(%rbx) ; \
157 call ithread_fast_handler ; /* returns 0 to unmask int */ \
158 decl TD_CRITCOUNT(%rbx) ; \
159 addq $8,%rsp ; /* intr frame -> trap frame */ \
160 UNMASK_IRQ(icu, irq_num) ; \
166 INTR_HANDLER(0, IO_ICU1, ENABLE_ICU1)
167 INTR_HANDLER(1, IO_ICU1, ENABLE_ICU1)
168 INTR_HANDLER(2, IO_ICU1, ENABLE_ICU1)
169 INTR_HANDLER(3, IO_ICU1, ENABLE_ICU1)
170 INTR_HANDLER(4, IO_ICU1, ENABLE_ICU1)
171 INTR_HANDLER(5, IO_ICU1, ENABLE_ICU1)
172 INTR_HANDLER(6, IO_ICU1, ENABLE_ICU1)
173 INTR_HANDLER(7, IO_ICU1, ENABLE_ICU1)
174 INTR_HANDLER(8, IO_ICU2, ENABLE_ICU1_AND_2)
175 INTR_HANDLER(9, IO_ICU2, ENABLE_ICU1_AND_2)
176 INTR_HANDLER(10, IO_ICU2, ENABLE_ICU1_AND_2)
177 INTR_HANDLER(11, IO_ICU2, ENABLE_ICU1_AND_2)
178 INTR_HANDLER(12, IO_ICU2, ENABLE_ICU1_AND_2)
179 INTR_HANDLER(13, IO_ICU2, ENABLE_ICU1_AND_2)
180 INTR_HANDLER(14, IO_ICU2, ENABLE_ICU1_AND_2)
181 INTR_HANDLER(15, IO_ICU2, ENABLE_ICU1_AND_2)