2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/i386/isa/pcibus.c,v 1.57.2.11 2002/11/13 21:40:40 peter Exp $
27 * $DragonFly: src/sys/bus/pci/i386/pcibus.c,v 1.2 2003/06/17 04:28:37 dillon Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <pci/pcivar.h>
37 #include <pci/pcireg.h>
38 #include <i386/isa/pcibus.h>
39 #include <machine/pci_cfgreg.h>
40 #include <machine/md_var.h>
46 static devclass_t pcib_devclass;
49 nexus_pcib_is_host_bridge(pcicfgregs *cfg,
50 u_int32_t id, u_int8_t class, u_int8_t subclass,
54 static u_int8_t pxb[4]; /* hack for 450nx */
60 s = "Intel 824?? host to PCI bridge";
61 /* XXX This is a guess */
62 /* *busnum = pci_cfgread(cfg, 0x41, 1); */
66 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
69 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
72 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
75 s = "Intel 82443LX (440 LX) host to PCI bridge";
78 s = "Intel 82443BX (440 BX) host to PCI bridge";
81 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
84 s = "Intel 82443MX host to PCI bridge";
87 s = "Intel 82443GX host to PCI bridge";
90 s = "Intel 82443GX host to AGP bridge";
93 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
96 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
97 *busnum = pci_cfgread(cfg, 0x4a, 1);
101 * For the 450nx chipset, there is a whole bundle of
102 * things pretending to be host bridges. The MIOC will
103 * be seen first and isn't really a pci bridge (the
104 * actual busses are attached to the PXB's). We need to
105 * read the registers of the MIOC to figure out the
106 * bus numbers for the PXB channels.
108 * Since the MIOC doesn't have a pci bus attached, we
109 * pretend it wasn't there.
111 pxb[0] = pci_cfgread(cfg, 0xd0, 1); /* BUSNO[0] */
112 pxb[1] = pci_cfgread(cfg, 0xd1, 1) + 1; /* SUBA[0]+1 */
113 pxb[2] = pci_cfgread(cfg, 0xd3, 1); /* BUSNO[1] */
114 pxb[3] = pci_cfgread(cfg, 0xd4, 1) + 1; /* SUBA[1]+1 */
119 s = "Intel 82454NX PXB#0, Bus#A";
123 s = "Intel 82454NX PXB#0, Bus#B";
127 s = "Intel 82454NX PXB#1, Bus#A";
131 s = "Intel 82454NX PXB#1, Bus#B";
137 s = "Intel 82845 Host to PCI bridge";
140 /* AMD -- vendor 0x1022 */
142 s = "AMD Elan SC520 host to PCI bridge";
144 init_AMD_Elan_sc520();
146 printf("*** WARNING: kernel option CPU_ELAN missing");
147 printf("-- timekeeping may be wrong\n");
151 s = "AMD-751 host to PCI bridge";
154 s = "AMD-761 host to PCI bridge";
157 /* SiS -- vendor 0x1039 */
168 s = "SiS 5591 host to PCI bridge";
171 s = "SiS 5591 host to AGP bridge";
174 /* VLSI -- vendor 0x1004 */
176 s = "VLSI 82C592 Host to PCI bridge";
179 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
180 /* totally. Please let me know if anything wrong. -F */
181 /* XXX need info on the MVP3 -- any takers? */
183 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
186 /* AcerLabs -- vendor 0x10b9 */
187 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
188 /* id is '10b9" but the register always shows "10b9". -Foxfair */
190 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
193 /* OPTi -- vendor 0x1045 */
195 s = "OPTi 82C822 host to PCI Bridge";
198 /* ServerWorks -- vendor 0x1166 */
200 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
201 *busnum = pci_cfgread(cfg, 0x44, 1);
207 s = "ServerWorks host to PCI bridge";
208 *busnum = pci_cfgread(cfg, 0x44, 1);
212 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
213 *busnum = pci_cfgread(cfg, 0x44, 1);
217 s = "ServerWorks CIOB30 host to PCI bridge";
218 *busnum = pci_cfgread(cfg, 0x44, 1);
221 /* XXX unknown chipset, but working */
225 s = "ServerWorks host to PCI bridge(unknown chipset)";
226 *busnum = pci_cfgread(cfg, 0x44, 1);
229 /* Integrated Micro Solutions -- vendor 0x10e0 */
231 s = "Integrated Micro Solutions VL Bridge";
235 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
236 s = "Host to PCI bridge";
244 * Scan the first pci bus for host-pci bridges and add pcib instances
245 * to the nexus for each bridge.
248 nexus_pcib_identify(driver_t *driver, device_t parent)
257 if (pci_cfgregopen() == 0)
262 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
264 hdrtype = pci_cfgread(&probe, PCIR_HEADERTYPE, 1);
265 if (hdrtype & PCIM_MFDEV && (!found_orion || hdrtype != 0xff) )
270 probe.func <= pcifunchigh;
273 * Read the IDs and class from the device.
276 u_int8_t class, subclass, busnum;
280 id = pci_cfgread(&probe, PCIR_DEVVENDOR, 4);
283 class = pci_cfgread(&probe, PCIR_CLASS, 1);
284 subclass = pci_cfgread(&probe, PCIR_SUBCLASS, 1);
286 s = nexus_pcib_is_host_bridge(&probe, id,
291 * Add at priority 100 to make sure we
292 * go after any motherboard resources
294 child = BUS_ADD_CHILD(parent, 100,
296 device_set_desc(child, s);
298 if (id == 0x12258086)
300 if (id == 0x84c48086)
305 if (found824xx && probe.bus == 0) {
311 * Make sure we add at least one bridge since some old
312 * hardware doesn't actually have a host-pci bridge device.
313 * Note that pci_cfgregopen() thinks we have PCI devices..
318 "nexus_pcib_identify: no bridge found, adding pcib0 anyway\n");
319 BUS_ADD_CHILD(parent, 100, "pcib", 0);
324 nexus_pcib_probe(device_t dev)
326 if (pci_cfgregopen() != 0) {
327 device_add_child(dev, "pci", device_get_unit(dev));
333 /* route interrupt */
336 nexus_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
338 return(pci_cfgintr(pci_get_bus(dev), pci_get_slot(dev), pin));
341 static device_method_t nexus_pcib_methods[] = {
342 /* Device interface */
343 DEVMETHOD(device_identify, nexus_pcib_identify),
344 DEVMETHOD(device_probe, nexus_pcib_probe),
345 DEVMETHOD(device_attach, bus_generic_attach),
346 DEVMETHOD(device_shutdown, bus_generic_shutdown),
347 DEVMETHOD(device_suspend, bus_generic_suspend),
348 DEVMETHOD(device_resume, bus_generic_resume),
351 DEVMETHOD(bus_print_child, bus_generic_print_child),
352 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
353 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
354 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
355 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
356 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
357 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
360 DEVMETHOD(pci_route_interrupt, nexus_pcib_route_interrupt),
364 static driver_t nexus_pcib_driver = {
370 DRIVER_MODULE(pcib, nexus, nexus_pcib_driver, pcib_devclass, 0, 0);