2 * Copyright 1996 Massachusetts Institute of Technology
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
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16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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29 * From: wd82371reg.h,v 1.3 1997/02/22 09:44:15 peter Exp $
30 * $FreeBSD: src/sys/pci/ide_pcireg.h,v 1.2 1999/08/28 00:50:47 peter Exp $
31 * $DragonFly: src/sys/bus/pci/Attic/ide_pcireg.h,v 1.2 2003/06/17 04:28:56 dillon Exp $
34 #ifndef _PCI_IDEPCIREG_H_
35 #define _PCI_IDEPCIREG_H_ 1
37 /* Ports are for controller 0. Add SFF8038_CTLR_1 for controller 1. */
38 #define SFF8038_CTLR_1 8
40 /* Contents of BMICOM register */
42 #define BMICOM_READ_WRITE 0x0008 /* false = read, true = write */
43 #define BMICOM_STOP_START 0x0001 /* false = stop, true = start */
45 /* Contents of BMISTA register */
47 #define BMISTA_SIMPLEX 0x0080 /* 1 = controller cannot DMA on both
48 channels simultaneously */
49 #define BMISTA_DMA1CAP 0x0040 /* true = drive 1 can DMA */
50 #define BMISTA_DMA0CAP 0x0020 /* true = drive 0 can DMA */
51 #define BMISTA_INTERRUPT 0x0004
52 #define BMISTA_DMA_ERROR 0x0002
53 #define BMISTA_DMA_ACTIVE 0x0001
55 #define BMIDTP_PORT 4 /* use outl */
62 #define PRD_EOT_BIT 0x80000000
64 #endif /* _PCI_IDEPCIREG_H_ */