1 /* $FreeBSD: src/sys/dev/mii/e1000phyreg.h,v 1.1.2.1 2001/04/21 16:13:09 mjacob Exp $ */
2 /* $DragonFly: src/sys/dev/netif/mii_layer/e1000phyreg.h,v 1.2 2003/06/17 04:28:28 dillon Exp $ */
4 * Principal Author: Parag Patel
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Additonal Copyright (c) 2001 by Traakan Software under same licence.
31 * Secondary Author: Matthew Jacob
35 * Marvell E1000 PHY registers
38 #define E1000_MAX_REG_ADDRESS 0x1F
40 #define E1000_CR 0x00 /* control register */
41 #define E1000_CR_SPEED_SELECT_MSB 0x0040
42 #define E1000_CR_COLL_TEST_ENABLE 0x0080
43 #define E1000_CR_FULL_DUPLEX 0x0100
44 #define E1000_CR_RESTART_AUTO_NEG 0x0200
45 #define E1000_CR_ISOLATE 0x0400
46 #define E1000_CR_POWER_DOWN 0x0800
47 #define E1000_CR_AUTO_NEG_ENABLE 0x1000
48 #define E1000_CR_SPEED_SELECT_LSB 0x2000
49 #define E1000_CR_LOOPBACK 0x4000
50 #define E1000_CR_RESET 0x8000
52 #define E1000_CR_SPEED_1000 0x0040
53 #define E1000_CR_SPEED_100 0x2000
54 #define E1000_CR_SPEED_10 0x0000
56 #define E1000_SR 0x01 /* status register */
57 #define E1000_SR_EXTENDED 0x0001
58 #define E1000_SR_JABBER_DETECT 0x0002
59 #define E1000_SR_LINK_STATUS 0x0004
60 #define E1000_SR_AUTO_NEG 0x0008
61 #define E1000_SR_REMOTE_FAULT 0x0010
62 #define E1000_SR_AUTO_NEG_COMPLETE 0x0020
63 #define E1000_SR_PREAMBLE_SUPPRESS 0x0040
64 #define E1000_SR_EXTENDED_STATUS 0x0100
65 #define E1000_SR_100T2 0x0200
66 #define E1000_SR_100T2_FD 0x0400
67 #define E1000_SR_10T 0x0800
68 #define E1000_SR_10T_FD 0x1000
69 #define E1000_SR_100TX 0x2000
70 #define E1000_SR_100TX_FD 0x4000
71 #define E1000_SR_100T4 0x8000
73 #define E1000_ID1 0x02 /* ID register 1 */
74 #define E1000_ID2 0x03 /* ID register 2 */
75 #define E1000_ID_88E1000 0x01410C50
76 #define E1000_ID_88E1000S 0x01410C40
77 #define E1000_ID_MASK 0xFFFFFFF0
79 #define E1000_AR 0x04 /* autonegotiation advertise reg */
80 #define E1000_AR_SELECTOR_FIELD 0x0001
81 #define E1000_AR_10T 0x0020
82 #define E1000_AR_10T_FD 0x0040
83 #define E1000_AR_100TX 0x0080
84 #define E1000_AR_100TX_FD 0x0100
85 #define E1000_AR_100T4 0x0200
86 #define E1000_AR_PAUSE 0x0400
87 #define E1000_AR_ASM_DIR 0x0800
88 #define E1000_AR_REMOTE_FAULT 0x2000
89 #define E1000_AR_NEXT_PAGE 0x8000
90 #define E1000_AR_SPEED_MASK 0x01E0
92 #define E1000_LPAR 0x05 /* autoneg link partner abilities reg */
93 #define E1000_LPAR_SELECTOR_FIELD 0x0001
94 #define E1000_LPAR_10T 0x0020
95 #define E1000_LPAR_10T_FD 0x0040
96 #define E1000_LPAR_100TX 0x0080
97 #define E1000_LPAR_100TX_FD 0x0100
98 #define E1000_LPAR_100T4 0x0200
99 #define E1000_LPAR_PAUSE 0x0400
100 #define E1000_LPAR_ASM_DIR 0x0800
101 #define E1000_LPAR_REMOTE_FAULT 0x2000
102 #define E1000_LPAR_ACKNOWLEDGE 0x4000
103 #define E1000_LPAR_NEXT_PAGE 0x8000
105 #define E1000_ER 0x06 /* autoneg expansion reg */
106 #define E1000_ER_LP_NWAY 0x0001
107 #define E1000_ER_PAGE_RXD 0x0002
108 #define E1000_ER_NEXT_PAGE 0x0004
109 #define E1000_ER_LP_NEXT_PAGE 0x0008
110 #define E1000_ER_PAR_DETECT_FAULT 0x0100
112 #define E1000_NPTX 0x07 /* autoneg next page TX */
113 #define E1000_NPTX_MSG_CODE_FIELD 0x0001
114 #define E1000_NPTX_TOGGLE 0x0800
115 #define E1000_NPTX_ACKNOWLDGE2 0x1000
116 #define E1000_NPTX_MSG_PAGE 0x2000
117 #define E1000_NPTX_NEXT_PAGE 0x8000
119 #define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */
120 #define E1000_RNPR_MSG_CODE_FIELD 0x0001
121 #define E1000_RNPR_TOGGLE 0x0800
122 #define E1000_RNPR_ACKNOWLDGE2 0x1000
123 #define E1000_RNPR_MSG_PAGE 0x2000
124 #define E1000_RNPR_ACKNOWLDGE 0x4000
125 #define E1000_RNPR_NEXT_PAGE 0x8000
127 #define E1000_1GCR 0x09 /* 1000T (1G) control reg */
128 #define E1000_1GCR_ASYM_PAUSE 0x0080
129 #define E1000_1GCR_1000T 0x0100
130 #define E1000_1GCR_1000T_FD 0x0200
131 #define E1000_1GCR_REPEATER_DTE 0x0400
132 #define E1000_1GCR_MS_VALUE 0x0800
133 #define E1000_1GCR_MS_ENABLE 0x1000
134 #define E1000_1GCR_TEST_MODE_NORMAL 0x0000
135 #define E1000_1GCR_TEST_MODE_1 0x2000
136 #define E1000_1GCR_TEST_MODE_2 0x4000
137 #define E1000_1GCR_TEST_MODE_3 0x6000
138 #define E1000_1GCR_TEST_MODE_4 0x8000
139 #define E1000_1GCR_SPEED_MASK 0x0300
141 #define E1000_1GSR 0x0A /* 1000T (1G) status reg */
142 #define E1000_1GSR_IDLE_ERROR_CNT 0x0000
143 #define E1000_1GSR_ASYM_PAUSE_DIR 0x0100
144 #define E1000_1GSR_LP 0x0400
145 #define E1000_1GSR_LP_FD 0x0800
146 #define E1000_1GSR_REMOTE_RX_STATUS 0x1000
147 #define E1000_1GSR_LOCAL_RX_STATUS 0x2000
148 #define E1000_1GSR_MS_CONFIG_RES 0x4000
149 #define E1000_1GSR_MS_CONFIG_FAULT 0x8000
151 #define E1000_ESR 0x0F /* IEEE extended status reg */
152 #define E1000_ESR_1000T 0x1000
153 #define E1000_ESR_1000T_FD 0x2000
154 #define E1000_ESR_1000X 0x4000
155 #define E1000_ESR_1000X_FD 0x8000
157 #define E1000_TX_POLARITY_MASK 0x0100
158 #define E1000_TX_NORMAL_POLARITY 0
160 #define E1000_AUTO_POLARITY_DISABLE 0x0010
162 #define E1000_SCR 0x10 /* special control register */
163 #define E1000_SCR_JABBER_DISABLE 0x0001
164 #define E1000_SCR_POLARITY_REVERSAL 0x0002
165 #define E1000_SCR_SQE_TEST 0x0004
166 #define E1000_SCR_INT_FIFO_DISABLE 0x0008
167 #define E1000_SCR_CLK125_DISABLE 0x0010
168 #define E1000_SCR_MDI_MANUAL_MODE 0x0000
169 #define E1000_SCR_MDIX_MANUAL_MODE 0x0020
170 #define E1000_SCR_AUTO_X_1000T 0x0040
171 #define E1000_SCR_AUTO_X_MODE 0x0060
172 #define E1000_SCR_10BT_EXT_ENABLE 0x0080
173 #define E1000_SCR_MII_5BIT_ENABLE 0x0100
174 #define E1000_SCR_SCRAMBLER_DISABLE 0x0200
175 #define E1000_SCR_FORCE_LINK_GOOD 0x0400
176 #define E1000_SCR_ASSERT_CRS_ON_TX 0x0800
177 #define E1000_SCR_RX_FIFO_DEPTH_6 0x0000
178 #define E1000_SCR_RX_FIFO_DEPTH_8 0x1000
179 #define E1000_SCR_RX_FIFO_DEPTH_10 0x2000
180 #define E1000_SCR_RX_FIFO_DEPTH_12 0x3000
181 #define E1000_SCR_TX_FIFO_DEPTH_6 0x0000
182 #define E1000_SCR_TX_FIFO_DEPTH_8 0x4000
183 #define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
184 #define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
186 #define E1000_SSR 0x11 /* special status register */
187 #define E1000_SSR_JABBER 0x0001
188 #define E1000_SSR_REV_POLARITY 0x0002
189 #define E1000_SSR_MDIX 0x0020
190 #define E1000_SSR_LINK 0x0400
191 #define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
192 #define E1000_SSR_PAGE_RCVD 0x1000
193 #define E1000_SSR_DUPLEX 0x2000
194 #define E1000_SSR_SPEED 0xC000
195 #define E1000_SSR_10MBS 0x0000
196 #define E1000_SSR_100MBS 0x4000
197 #define E1000_SSR_1000MBS 0x8000
199 #define E1000_IER 0x12 /* interrupt enable reg */
200 #define E1000_IER_JABBER 0x0001
201 #define E1000_IER_POLARITY_CHANGE 0x0002
202 #define E1000_IER_MDIX_CHANGE 0x0040
203 #define E1000_IER_FIFO_OVER_UNDERUN 0x0080
204 #define E1000_IER_FALSE_CARRIER 0x0100
205 #define E1000_IER_SYMBOL_ERROR 0x0200
206 #define E1000_IER_LINK_STAT_CHANGE 0x0400
207 #define E1000_IER_AUTO_NEG_COMPLETE 0x0800
208 #define E1000_IER_PAGE_RECEIVED 0x1000
209 #define E1000_IER_DUPLEX_CHANGED 0x2000
210 #define E1000_IER_SPEED_CHANGED 0x4000
211 #define E1000_IER_AUTO_NEG_ERR 0x8000
213 #define E1000_ISR 0x13 /* interrupt status reg */
214 #define E1000_ISR_JABBER 0x0001
215 #define E1000_ISR_POLARITY_CHANGE 0x0002
216 #define E1000_ISR_MDIX_CHANGE 0x0040
217 #define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
218 #define E1000_ISR_FALSE_CARRIER 0x0100
219 #define E1000_ISR_SYMBOL_ERROR 0x0200
220 #define E1000_ISR_LINK_STAT_CHANGE 0x0400
221 #define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
222 #define E1000_ISR_PAGE_RECEIVED 0x1000
223 #define E1000_ISR_DUPLEX_CHANGED 0x2000
224 #define E1000_ISR_SPEED_CHANGED 0x4000
225 #define E1000_ISR_AUTO_NEG_ERR 0x8000
227 #define E1000_ESCR 0x14 /* extended special control reg */
228 #define E1000_ESCR_FIBER_LOOPBACK 0x4000
229 #define E1000_ESCR_DOWN_NO_IDLE 0x8000
230 #define E1000_ESCR_TX_CLK_2_5 0x0060
231 #define E1000_ESCR_TX_CLK_25 0x0070
232 #define E1000_ESCR_TX_CLK_0 0x0000
234 #define E1000_RECR 0x15 /* RX error counter reg */
236 #define E1000_LCR 0x18 /* LED control reg */
237 #define E1000_LCR_LED_TX 0x0001
238 #define E1000_LCR_LED_RX 0x0002
239 #define E1000_LCR_LED_DUPLEX 0x0004
240 #define E1000_LCR_LINK 0x0008
241 #define E1000_LCR_BLINK_42MS 0x0000
242 #define E1000_LCR_BLINK_84MS 0x0100
243 #define E1000_LCR_BLINK_170MS 0x0200
244 #define E1000_LCR_BLINK_340MS 0x0300
245 #define E1000_LCR_BLINK_670MS 0x0400
246 #define E1000_LCR_PULSE_OFF 0x0000
247 #define E1000_LCR_PULSE_21_42MS 0x1000
248 #define E1000_LCR_PULSE_42_84MS 0x2000
249 #define E1000_LCR_PULSE_84_170MS 0x3000
250 #define E1000_LCR_PULSE_170_340MS 0x4000
251 #define E1000_LCR_PULSE_340_670MS 0x5000
252 #define E1000_LCR_PULSE_670_13S 0x6000
253 #define E1000_LCR_PULSE_13_26S 0x7000