2 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * capi/iavc/iavc_card.c
26 * The AVM ISDN controllers' card specific support routines.
28 * $FreeBSD: src/sys/i4b/capi/iavc/iavc_card.c,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
29 * $DragonFly: src/sys/net/i4b/capi/iavc/iavc_card.c,v 1.3 2003/08/07 21:17:24 dillon Exp $
33 #include "use_i4bcapi.h"
36 #if (NIAVC > 0) && (NI4BCAPI > 0)
38 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
42 #include <sys/socket.h>
45 #include <machine/clock.h>
47 #include <machine/bus.h>
48 #include <machine/resource.h>
52 #include <machine/i4b_debug.h>
53 #include <machine/i4b_ioctl.h>
54 #include <machine/i4b_trace.h>
56 #include "../../include/i4b_global.h"
57 #include "../../include/i4b_l3l4.h"
58 #include "../../include/i4b_mbuf.h"
64 // AVM B1 (active BRI, PIO mode)
67 int b1_detect(iavc_softc_t *sc)
69 if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) ||
70 (iavc_read_port(sc, B1_OUTSTAT) & 0xfc))
73 b1io_outp(sc, B1_INSTAT, 0x02);
74 b1io_outp(sc, B1_OUTSTAT, 0x02);
75 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 ||
76 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2)
79 b1io_outp(sc, B1_INSTAT, 0x00);
80 b1io_outp(sc, B1_OUTSTAT, 0x00);
81 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) ||
82 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe))
85 return (0); /* found */
88 void b1_disable_irq(iavc_softc_t *sc)
90 b1io_outp(sc, B1_INSTAT, 0x00);
93 void b1_reset(iavc_softc_t *sc)
95 b1io_outp(sc, B1_RESET, 0);
98 b1io_outp(sc, B1_RESET, 1);
101 b1io_outp(sc, B1_RESET, 0);
106 // Newer PCI-based B1's, and T1's, supports DMA
109 int b1dma_detect(iavc_softc_t *sc)
111 AMCC_WRITE(sc, AMCC_MCSR, 0);
113 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
115 AMCC_WRITE(sc, AMCC_MCSR, 0);
118 AMCC_WRITE(sc, AMCC_RXLEN, 0);
119 AMCC_WRITE(sc, AMCC_TXLEN, 0);
121 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
123 if (AMCC_READ(sc, AMCC_INTCSR) != 0)
126 AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
127 AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
128 if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
129 (AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
132 AMCC_WRITE(sc, AMCC_RXPTR, 0);
133 AMCC_WRITE(sc, AMCC_TXPTR, 0);
134 if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
135 (AMCC_READ(sc, AMCC_TXPTR) != 0))
138 iavc_write_port(sc, 0x10, 0x00);
139 iavc_write_port(sc, 0x07, 0x00);
141 iavc_write_port(sc, 0x02, 0x02);
142 iavc_write_port(sc, 0x03, 0x02);
144 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
145 (iavc_read_port(sc, 0x03) != 0x03))
148 iavc_write_port(sc, 0x02, 0x00);
149 iavc_write_port(sc, 0x03, 0x00);
151 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
152 (iavc_read_port(sc, 0x03) != 0x01))
155 return (0); /* found */
158 void b1dma_reset(iavc_softc_t *sc)
163 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
164 AMCC_WRITE(sc, AMCC_MCSR, 0);
165 AMCC_WRITE(sc, AMCC_RXLEN, 0);
166 AMCC_WRITE(sc, AMCC_TXLEN, 0);
168 iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */
169 iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */
173 AMCC_WRITE(sc, AMCC_MCSR, 0);
175 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
177 AMCC_WRITE(sc, AMCC_MCSR, 0);
182 // AVM T1 (active PRI)
185 /* XXX how do these differ from b1io_{read,write}_reg()? XXX */
187 static int b1dma_tx_empty(int iobase)
188 { return inb(iobase + 3) & 1; }
190 static int b1dma_rx_full(int iobase)
191 { return inb(iobase + 2) & 1; }
193 static int b1dma_tolink(iavc_softc_t *sc, void *buf, int len)
196 char *s = (char*) buf;
199 while (!b1dma_tx_empty(sc->sc_iobase) && spin < 100000)
201 if (!b1dma_tx_empty(sc->sc_iobase))
203 t1io_outp(sc, 1, *s++);
208 static int b1dma_fromlink(iavc_softc_t *sc, void *buf, int len)
211 char *s = (char*) buf;
214 while (!b1dma_rx_full(sc->sc_iobase) && spin < 100000)
216 if (!b1dma_rx_full(sc->sc_iobase))
218 *s++ = t1io_inp(sc, 0);
223 static int WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val)
226 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
227 b1dma_tolink(sc, ®, 4) == 0) {
229 return b1dma_tolink(sc, &tmp, 4);
234 static u_int8_t ReadReg(iavc_softc_t *sc, u_int32_t reg)
237 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
238 b1dma_tolink(sc, ®, 4) == 0) {
240 if (b1dma_fromlink(sc, &tmp, 4) == 0)
241 return (u_int8_t) tmp;
246 int t1_detect(iavc_softc_t *sc)
248 int ret = b1dma_detect(sc);
251 if ((WriteReg(sc, 0x80001000, 0x11) != 0) ||
252 (WriteReg(sc, 0x80101000, 0x22) != 0) ||
253 (WriteReg(sc, 0x80201000, 0x33) != 0) ||
254 (WriteReg(sc, 0x80301000, 0x44) != 0))
257 if ((ReadReg(sc, 0x80001000) != 0x11) ||
258 (ReadReg(sc, 0x80101000) != 0x22) ||
259 (ReadReg(sc, 0x80201000) != 0x33) ||
260 (ReadReg(sc, 0x80301000) != 0x44))
263 if ((WriteReg(sc, 0x80001000, 0x55) != 0) ||
264 (WriteReg(sc, 0x80101000, 0x66) != 0) ||
265 (WriteReg(sc, 0x80201000, 0x77) != 0) ||
266 (WriteReg(sc, 0x80301000, 0x88) != 0))
269 if ((ReadReg(sc, 0x80001000) != 0x55) ||
270 (ReadReg(sc, 0x80101000) != 0x66) ||
271 (ReadReg(sc, 0x80201000) != 0x77) ||
272 (ReadReg(sc, 0x80301000) != 0x88))
275 return 0; /* found */
278 void t1_disable_irq(iavc_softc_t *sc)
280 iavc_write_port(sc, T1_IRQMASTER, 0x00);
283 void t1_reset(iavc_softc_t *sc)
286 iavc_write_port(sc, B1_INSTAT, 0x00);
287 iavc_write_port(sc, B1_OUTSTAT, 0x00);
288 iavc_write_port(sc, T1_IRQMASTER, 0x00);
289 iavc_write_port(sc, T1_RESETBOARD, 0x0f);