sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id$
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.4 2003/08/07 21:17:25 dillon Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi2.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI2 > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55
  56 #include <machine/bus.h>
  57 #include <sys/bus.h>
  58 #include <sys/rman.h>
  59
  60 #include <bus/pci/pcireg.h>
  61 #include <bus/pci/pcivar.h>
  62
  63 #include <sys/socket.h>
  64 #include <net/if.h>
  65
  66 #include <net/i4b/include/machine/i4b_debug.h>
  67 #include <net/i4b/include/machine/i4b_ioctl.h>
  68 #include <net/i4b/include/machine/i4b_trace.h>
  69
  70 #include "../../include/i4b_global.h"
  71 #include "../../include/i4b_mbuf.h"
  72
  73 #include "../i4b_l1.h"
  74 #include "../isic/i4b_isic.h"
  75 /*#include "../isic/i4b_isac.h"*/
  76 #include "../isic/i4b_hscx.h"
  77
  78 #include "i4b_ifpi2_ext.h"
  79 #include "i4b_ifpi2_isacsx.h"
  80
  81 #define PCI_AVMA1_VID 0x1244
  82 #define PCI_AVMA1_V2_DID 0x0e00
  83
  84 /* prototypes */
  85 static void avma1pp2_disable(device_t);
  86
  87 static void avma1pp2_intr(void *);
  88 static void hscx_write_reg(int, u_int, struct l1_softc *);
  89 static u_char hscx_read_reg(int, struct l1_softc *);
  90 static u_int hscx_read_reg_int(int, struct l1_softc *);
  91 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  92 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  93 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  94 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  95 static void avma1pp2_init_linktab(struct l1_softc *);
  96 static void avma1pp2_bchannel_setup(int, int, int, int);
  97 static void avma1pp2_bchannel_start(int, int);
  98 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
  99 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
 100 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
 101 static isdn_link_t * avma1pp2_ret_linktab(int, int);
 102 static int avma1pp2_pci_probe(device_t);
 103 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 104 int avma1pp2_attach_avma1pp(device_t);
 105 static void ifpi2_isacsx_intr(struct l1_softc *sc);
 106
 107 static device_method_t avma1pp2_pci_methods[] = {
 108         /* Device interface */
 109         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 110         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 111         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 112
 113         /* bus interface */
 114         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 115         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 116
 117         { 0, 0 }
 118 };
 119
 120 static driver_t avma1pp2_pci_driver = {
 121         "ifpi2-",
 122         avma1pp2_pci_methods,
 123         sizeof(struct l1_softc)
 124 };
 125
 126 static devclass_t avma1pp2_pci_devclass;
 127
 128 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
 129
 130 /* jump table for multiplex routines */
 131
 132 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 133         avma1pp2_ret_linktab,
 134         avma1pp2_set_linktab,
 135         ifpi2_mph_command_req,
 136         ifpi2_ph_data_req,
 137         ifpi2_ph_activate_req,
 138 };
 139
 140 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 141
 142 /*---------------------------------------------------------------------------*
 143  *      AVM PCI Fritz!Card V. 2 special registers
 144  *---------------------------------------------------------------------------*/
 145
 146 /*
 147  *      AVM PCI Status Latch 0 read only bits
 148  */
 149 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 150 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 151 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 152 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 153 /* actually active high */
 154 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 155
 156 /*
 157  *      AVM PCI Status Latch 0 read only bits
 158  */
 159 #define ASL_TIMERRESET          0x04
 160 #define ASL_ENABLE_INT          0x08
 161
 162 /*
 163  * "HSCX" status bits
 164  */
 165 #define  HSCX_STAT_RME          0x01
 166 #define  HSCX_STAT_RDO          0x10
 167 #define  HSCX_STAT_CRCVFRRAB    0x0E
 168 #define  HSCX_STAT_CRCVFR       0x06
 169 #define  HSCX_STAT_RML_MASK     0x3f00
 170
 171 /*
 172  * "HSCX" interrupt bits
 173  */
 174 #define  HSCX_INT_XPR           0x80
 175 #define  HSCX_INT_XDU           0x40
 176 #define  HSCX_INT_RPR           0x20
 177 #define  HSCX_INT_MASK          0xE0
 178
 179 /*
 180  * "HSCX" command bits
 181  */
 182 #define  HSCX_CMD_XRS           0x80
 183 #define  HSCX_CMD_XME           0x01
 184 #define  HSCX_CMD_RRS           0x20
 185 #define  HSCX_CMD_XML_MASK      0x3f00
 186
 187 /* "HSCX" mode bits */
 188 #define HSCX_MODE_ITF_FLG       0x01
 189 #define HSCX_MODE_TRANS         0x02
 190
 191 /* offsets to various registers in the ASIC, evidently */
 192 #define  STAT0_OFFSET           0x02
 193
 194 #define  HSCX_FIFO1             0x10
 195 #define  HSCX_FIFO2             0x18
 196
 197 #define  HSCX_STAT1             0x14
 198 #define  HSCX_STAT2             0x1c
 199
 200 #define  ISACSX_INDEX           0x04
 201 #define  ISACSX_DATA            0x08
 202
 203 /*
 204  * Commands and parameters are sent to the "HSCX" as a long, but the
 205  * fields are handled as bytes.
 206  *
 207  * The long contains:
 208  *      (prot << 16)|(txl << 8)|cmd
 209  *
 210  * where:
 211  *      prot = protocol to use
 212  *      txl = transmit length
 213  *      cmd = the command to be executed
 214  *
 215  * The fields are defined as u_char in struct l1_softc.
 216  *
 217  * Macro to coalesce the byte fields into a u_int
 218  */
 219 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 220                                         | (sc->avma1pp_prot << 16))
 221
 222 /*
 223  * to prevent deactivating the "HSCX" when both channels are active we
 224  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 225  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 226  * It is set high to allow room for new flags.
 227  */
 228 #define HSCX_AVMA1PP_ACTIVE     0x1000
 229
 230 /*---------------------------------------------------------------------------*
 231  *      AVM read fifo routines
 232  *---------------------------------------------------------------------------*/
 233
 234 static void
 235 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 236 {
 237         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 238         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 239         int i;
 240
 241         switch (what) {
 242                 case ISIC_WHAT_ISAC:
 243                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 244                         /* evidently each byte must be read as a long */
 245                         for (i = 0; i < size; i++)
 246                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 247                         break;
 248                 case ISIC_WHAT_HSCXA:
 249                         hscx_read_fifo(0, buf, size, sc);
 250                         break;
 251                 case ISIC_WHAT_HSCXB:
 252                         hscx_read_fifo(1, buf, size, sc);
 253                         break;
 254         }
 255 }
 256
 257 static void
 258 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 259 {
 260         u_int32_t *ip;
 261         size_t cnt;
 262         int dataoff;
 263         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 264         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 265
 266         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 267
 268         ip = (u_int32_t *)buf;
 269         cnt = 0;
 270         /* what if len isn't a multiple of sizeof(int) and buf is */
 271         /* too small ???? */
 272         while (cnt < len)
 273         {
 274                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 275                 cnt += 4;
 276         }
 277 }
 278
 279 /*---------------------------------------------------------------------------*
 280  *      AVM write fifo routines
 281  *---------------------------------------------------------------------------*/
 282 static void
 283 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 284 {
 285         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 286         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 287         int i;
 288
 289         switch (what) {
 290                 case ISIC_WHAT_ISAC:
 291                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 292                         /* evidently each byte must written as a long */
 293                         for (i = 0; i < size; i++)
 294                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 295                         break;
 296                 case ISIC_WHAT_HSCXA:
 297                         hscx_write_fifo(0, buf, size, sc);
 298                         break;
 299                 case ISIC_WHAT_HSCXB:
 300                         hscx_write_fifo(1, buf, size, sc);
 301                         break;
 302         }
 303 }
 304
 305 static void
 306 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 307 {
 308         u_int32_t *ip;
 309         size_t cnt;
 310         int dataoff;
 311         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 312         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 313         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 314
 315         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 316
 317         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 318         sc->avma1pp_txl = 0;
 319         if (Bchan->out_mbuf_cur == NULL)
 320         {
 321           if (Bchan->bprot != BPROT_NONE)
 322                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 323         }
 324         if (len != sc->sc_bfifolen)
 325                 sc->avma1pp_txl = len;
 326
 327         cnt = 0; /* borrow cnt */
 328         AVMA1PPSETCMDLONG(cnt);
 329         hscx_write_reg(chan, cnt, sc);
 330
 331         ip = (u_int32_t *)buf;
 332         cnt = 0;
 333         while (cnt < len)
 334         {
 335                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 336                 ip++;
 337                 cnt += 4;
 338         }
 339 }
 340
 341 /*---------------------------------------------------------------------------*
 342  *      AVM write register routines
 343  *---------------------------------------------------------------------------*/
 344
 345 static void
 346 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 347 {
 348         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 349         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 350
 351         switch (what) {
 352                 case ISIC_WHAT_ISAC:
 353                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 354                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 355                         break;
 356                 case ISIC_WHAT_HSCXA:
 357                         hscx_write_reg(0, data, sc);
 358                         break;
 359                 case ISIC_WHAT_HSCXB:
 360                         hscx_write_reg(1, data, sc);
 361                         break;
 362         }
 363 }
 364
 365 static void
 366 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 367 {
 368         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 369         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 370         u_int off;
 371
 372         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 373
 374         bus_space_write_4(btag, bhandle, off, val);
 375 }
 376
 377 /*---------------------------------------------------------------------------*
 378  *      AVM read register routines
 379  *---------------------------------------------------------------------------*/
 380 static u_int8_t
 381 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 382 {
 383         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 384         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 385         u_int8_t val;
 386
 387         switch (what) {
 388                 case ISIC_WHAT_ISAC:
 389                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 390                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 391                         return(val);
 392                 case ISIC_WHAT_HSCXA:
 393                         return hscx_read_reg(0, sc);
 394                 case ISIC_WHAT_HSCXB:
 395                         return hscx_read_reg(1, sc);
 396         }
 397         return 0;
 398 }
 399
 400 static u_char
 401 hscx_read_reg(int chan, struct l1_softc *sc)
 402 {
 403         return(hscx_read_reg_int(chan, sc) & 0xff);
 404 }
 405
 406 /*
 407  * need to be able to return an int because the RBCH is in the 2nd
 408  * byte.
 409  */
 410 static u_int
 411 hscx_read_reg_int(int chan, struct l1_softc *sc)
 412 {
 413         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 414         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 415         u_int off;
 416
 417         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 418         return(bus_space_read_4(btag, bhandle, off));
 419 }
 420
 421 /*---------------------------------------------------------------------------*
 422  *      avma1pp2_probe - probe for a card
 423  *---------------------------------------------------------------------------*/
 424 static int
 425 avma1pp2_pci_probe(dev)
 426         device_t                dev;
 427 {
 428         u_int16_t               did, vid;
 429
 430         vid = pci_get_vendor(dev);
 431         did = pci_get_device(dev);
 432
 433         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 434                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 435                 return(0);
 436         }
 437
 438         return(ENXIO);
 439 }
 440
 441 /*---------------------------------------------------------------------------*
 442  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 443  *---------------------------------------------------------------------------*/
 444 int
 445 avma1pp2_attach_avma1pp(device_t dev)
 446 {
 447         struct l1_softc *sc;
 448         u_int v;
 449         int unit, error = 0;
 450         int s;
 451         u_int16_t did, vid;
 452         void *ih = 0;
 453         bus_space_handle_t bhandle;
 454         bus_space_tag_t btag;
 455         l1_bchan_state_t *chan;
 456
 457         s = splimp();
 458
 459         vid = pci_get_vendor(dev);
 460         did = pci_get_device(dev);
 461         sc = device_get_softc(dev);
 462         unit = device_get_unit(dev);
 463         bzero(sc, sizeof(struct l1_softc));
 464
 465         /* probably not really required */
 466         if(unit > IFPI2_MAXUNIT) {
 467                 printf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 468                 splx(s);
 469                 return(ENXIO);
 470         }
 471
 472         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 473                 printf("ifpi2-%d: unknown device!?\n", unit);
 474                 goto fail;
 475         }
 476
 477         ifpi2_scp[unit] = sc;
 478
 479         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 480         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 481                 &sc->sc_resources.io_rid[0],
 482                 0, ~0, 1, RF_ACTIVE);
 483
 484         if (sc->sc_resources.io_base[0] == NULL) {
 485                 printf("ifpi2-%d: couldn't map IO port\n", unit);
 486                 error = ENXIO;
 487                 goto fail;
 488         }
 489
 490         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 491         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 492
 493         /* Allocate interrupt */
 494         sc->sc_resources.irq_rid = 0;
 495         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 496                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 497
 498         if (sc->sc_resources.irq == NULL) {
 499                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 500                 printf("ifpi2-%d: couldn't map interrupt\n", unit);
 501                 error = ENXIO;
 502                 goto fail;
 503         }
 504
 505         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET, avma1pp2_intr, sc, &ih);
 506
 507         if (error) {
 508                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 509                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 510                 printf("ifpi2-%d: couldn't set up irq\n", unit);
 511                 goto fail;
 512         }
 513
 514         sc->sc_unit = unit;
 515
 516         /* end of new-bus stuff */
 517
 518         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 519
 520         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 521         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 522
 523         /* setup access routines */
 524
 525         sc->clearirq = NULL;
 526         sc->readreg = avma1pp2_read_reg;
 527         sc->writereg = avma1pp2_write_reg;
 528
 529         sc->readfifo = avma1pp2_read_fifo;
 530         sc->writefifo = avma1pp2_write_fifo;
 531
 532         /* setup card type */
 533
 534         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 535
 536         /* setup IOM bus type */
 537
 538         sc->sc_bustyp = BUS_TYPE_IOM2;
 539
 540         /* set up some other miscellaneous things */
 541         sc->sc_ipac = 0;
 542         sc->sc_bfifolen = HSCX_FIFO_LEN;
 543
 544         /* reset the card */
 545         /* the Linux driver does this to clear any pending ISAC interrupts */
 546         v = 0;
 547         v = ISAC_READ(I_RMODED);
 548 #ifdef AVMA1PCI_V2_DEBUG
 549         printf("avma1pp2_attach: I_MODED %x...", v);
 550 #endif
 551         v = ISAC_READ(I_ISTAD);
 552 #ifdef AVMA1PCI_V2_DEBUG
 553         printf("avma1pp2_attach: I_ISTAD %x...", v);
 554 #endif
 555         v = ISAC_READ(I_ISTA);
 556 #ifdef AVMA1PCI_V2_DEBUG
 557         printf("avma1pp2_attach: I_ISTA %x...", v);
 558 #endif
 559         ISAC_WRITE(I_MASKD, 0xff);
 560         ISAC_WRITE(I_MASK, 0xff);
 561         /* the Linux driver does this to clear any pending HSCX interrupts */
 562         v = hscx_read_reg_int(0, sc);
 563 #ifdef AVMA1PCI_V2_DEBUG
 564         printf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 565 #endif
 566         v = hscx_read_reg_int(1, sc);
 567 #ifdef AVMA1PCI_V2_DEBUG
 568         printf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 569 #endif
 570
 571         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 572         DELAY(SEC_DELAY/100); /* 10 ms */
 573         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 574         DELAY(SEC_DELAY/100); /* 10 ms */
 575
 576    /* from here to the end would normally be done in isic_pciattach */
 577
 578          printf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 579
 580         /* init the ISAC */
 581         ifpi2_isacsx_init(sc);
 582
 583 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 584         /* Init the channel mutexes */
 585         chan = &sc->sc_chan[HSCX_CH_A];
 586         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
 587         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
 588         chan = &sc->sc_chan[HSCX_CH_B];
 589         mtx_init(&chan->rx_queue.ifq_mtx, "i4b_avma1pp2_rx", MTX_DEF);
 590         mtx_init(&chan->tx_queue.ifq_mtx, "i4b_avma1pp2_tx", MTX_DEF);
 591 #endif
 592
 593         /* init the "HSCX" */
 594         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 595
 596         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 597
 598         /* can't use the normal B-Channel stuff */
 599         avma1pp2_init_linktab(sc);
 600
 601         /* set trace level */
 602
 603         sc->sc_trace = TRACE_OFF;
 604
 605         sc->sc_state = ISAC_IDLE;
 606
 607         sc->sc_ibuf = NULL;
 608         sc->sc_ib = NULL;
 609         sc->sc_ilen = 0;
 610
 611         sc->sc_obuf = NULL;
 612         sc->sc_op = NULL;
 613         sc->sc_ol = 0;
 614         sc->sc_freeflag = 0;
 615
 616         sc->sc_obuf2 = NULL;
 617         sc->sc_freeflag2 = 0;
 618
 619 #if defined(__FreeBSD__) && __FreeBSD__ >=3
 620         callout_handle_init(&sc->sc_T3_callout);
 621         callout_handle_init(&sc->sc_T4_callout);
 622 #endif
 623
 624         /* init higher protocol layers */
 625
 626         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 627
 628   fail:
 629         splx(s);
 630         return(error);
 631 }
 632
 633 /*
 634  * this is the real interrupt routine
 635  */
 636 static void
 637 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 638 {
 639         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 640         int activity = -1;
 641         u_int param = 0;
 642
 643         NDBGL1(L1_H_IRQ, "%#x", stat);
 644
 645         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 646         {
 647                 chan->stat_XDU++;
 648                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 649                 /* abort the transmission */
 650                 sc->avma1pp_txl = 0;
 651                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 652                 AVMA1PPSETCMDLONG(param);
 653                 hscx_write_reg(h_chan, param, sc);
 654                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 655                 AVMA1PPSETCMDLONG(param);
 656                 hscx_write_reg(h_chan, param, sc);
 657
 658                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 659                 {
 660                         i4b_Bfreembuf(chan->out_mbuf_head);
 661                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 662                 }
 663         }
 664
 665         /*
 666          * The following is based on examination of the Linux driver.
 667          *
 668          * The logic here is different than with a "real" HSCX; all kinds
 669          * of information (interrupt/status bits) are in stat.
 670          *              HSCX_INT_RPR indicates a receive interrupt
 671          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 672          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 673          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 674          *                      CRC/framing errors are only reported in this state.
 675          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 676          *                                      CRC/framing error
 677          */
 678
 679         if(stat & HSCX_INT_RPR)
 680         {
 681                 int fifo_data_len;
 682                 int error = 0;
 683                 /* always have to read the FIFO, so use a scratch buffer */
 684                 u_char scrbuf[HSCX_FIFO_LEN];
 685
 686                 if(stat & HSCX_STAT_RDO)
 687                 {
 688                         chan->stat_RDO++;
 689                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 690                         error++;
 691                 }
 692
 693                 /*
 694                  * check whether we're receiving data for an inactive B-channel
 695                  * and discard it. This appears to happen for telephony when
 696                  * both B-channels are active and one is deactivated. Since
 697                  * it is not really possible to deactivate the channel in that
 698                  * case (the ASIC seems to deactivate _both_ channels), the
 699                  * "deactivated" channel keeps receiving data which can lead
 700                  * to exhaustion of mbufs and a kernel panic.
 701                  *
 702                  * This is a hack, but it's the only solution I can think of
 703                  * without having the documentation for the ASIC.
 704                  * GJ - 28 Nov 1999
 705                  */
 706                  if (chan->state == HSCX_IDLE)
 707                  {
 708                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 709                         error++;
 710                  }
 711
 712                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 713
 714                 if(fifo_data_len == 0)
 715                         fifo_data_len = sc->sc_bfifolen;
 716
 717                 /* ALWAYS read data from HSCX fifo */
 718
 719                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 720                 chan->rxcount += fifo_data_len;
 721
 722                 /* all error conditions checked, now decide and take action */
 723
 724                 if(error == 0)
 725                 {
 726                         if(chan->in_mbuf == NULL)
 727                         {
 728                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 729                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 730                                 chan->in_cbptr = chan->in_mbuf->m_data;
 731                                 chan->in_len = 0;
 732                         }
 733
 734                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 735                         {
 736                                 /* OK to copy the data */
 737                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 738                                 chan->in_cbptr += fifo_data_len;
 739                                 chan->in_len += fifo_data_len;
 740
 741                                 /* setup mbuf data length */
 742
 743                                 chan->in_mbuf->m_len = chan->in_len;
 744                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 745
 746                                 if(sc->sc_trace & TRACE_B_RX)
 747                                 {
 748                                         i4b_trace_hdr_t hdr;
 749                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 750                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 751                                         hdr.dir = FROM_NT;
 752                                         hdr.count = ++sc->sc_trace_bcount;
 753                                         MICROTIME(hdr.time);
 754                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 755                                 }
 756
 757                                 if (stat & HSCX_STAT_RME)
 758                                 {
 759                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 760                                   {
 761                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 762                                          activity = ACT_RX;
 763
 764                                          /* mark buffer ptr as unused */
 765
 766                                          chan->in_mbuf = NULL;
 767                                          chan->in_cbptr = NULL;
 768                                          chan->in_len = 0;
 769                                   }
 770                                   else
 771                                   {
 772                                                 chan->stat_CRC++;
 773                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 774                                           if (chan->in_mbuf != NULL)
 775                                           {
 776                                                   i4b_Bfreembuf(chan->in_mbuf);
 777                                                   chan->in_mbuf = NULL;
 778                                                   chan->in_cbptr = NULL;
 779                                                   chan->in_len = 0;
 780                                           }
 781                                   }
 782                                 }
 783                         } /* END enough space in mbuf */
 784                         else
 785                         {
 786                                  if(chan->bprot == BPROT_NONE)
 787                                  {
 788                                           /* setup mbuf data length */
 789
 790                                           chan->in_mbuf->m_len = chan->in_len;
 791                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 792
 793                                           if(sc->sc_trace & TRACE_B_RX)
 794                                           {
 795                                                         i4b_trace_hdr_t hdr;
 796                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 797                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 798                                                         hdr.dir = FROM_NT;
 799                                                         hdr.count = ++sc->sc_trace_bcount;
 800                                                         MICROTIME(hdr.time);
 801                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 802                                                 }
 803
 804                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 805                                                  activity = ACT_RX;
 806
 807                                           /* move rx'd data to rx queue */
 808
 809 #if defined (__FreeBSD__) && __FreeBSD__ > 4
 810                                           (void) IF_HANDOFF(&chan->rx_queue, chan->in_mbuf, NULL);
 811 #else
 812                                           if(!(IF_QFULL(&chan->rx_queue)))
 813                                           {
 814                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 815                                           }
 816                                           else
 817                                           {
 818                                                 i4b_Bfreembuf(chan->in_mbuf);
 819                                           }
 820 #endif
 821                                           /* signal upper layer that data are available */
 822                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 823
 824                                           /* alloc new buffer */
 825
 826                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 827                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 828
 829                                           /* setup new data ptr */
 830
 831                                           chan->in_cbptr = chan->in_mbuf->m_data;
 832
 833                                           /* OK to copy the data */
 834                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 835
 836                                           chan->in_cbptr += fifo_data_len;
 837                                           chan->in_len = fifo_data_len;
 838
 839                                           chan->rxcount += fifo_data_len;
 840                                         }
 841                                  else
 842                                         {
 843                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 844                                           chan->in_cbptr = chan->in_mbuf->m_data;
 845                                           chan->in_len = 0;
 846                                         }
 847                           }
 848                 } /* if(error == 0) */
 849                 else
 850                 {
 851                         /* land here for RDO */
 852                         if (chan->in_mbuf != NULL)
 853                         {
 854                                 i4b_Bfreembuf(chan->in_mbuf);
 855                                 chan->in_mbuf = NULL;
 856                                 chan->in_cbptr = NULL;
 857                                 chan->in_len = 0;
 858                         }
 859                         sc->avma1pp_txl = 0;
 860                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 861                         AVMA1PPSETCMDLONG(param);
 862                         hscx_write_reg(h_chan, param, sc);
 863                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 864                         AVMA1PPSETCMDLONG(param);
 865                         hscx_write_reg(h_chan, param, sc);
 866                 }
 867         }
 868
 869
 870         /* transmit fifo empty, new data can be written to fifo */
 871
 872         if(stat & HSCX_INT_XPR)
 873         {
 874                 /*
 875                  * for a description what is going on here, please have
 876                  * a look at isic_bchannel_start() in i4b_bchan.c !
 877                  */
 878
 879                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 880
 881                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 882                 {
 883                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 884
 885                         if(chan->out_mbuf_head == NULL)
 886                         {
 887                                 chan->state &= ~HSCX_TX_ACTIVE;
 888                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 889                         }
 890                         else
 891                         {
 892                                 chan->state |= HSCX_TX_ACTIVE;
 893                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 894                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 895                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 896
 897                                 if(sc->sc_trace & TRACE_B_TX)
 898                                 {
 899                                         i4b_trace_hdr_t hdr;
 900                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 901                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 902                                         hdr.dir = FROM_TE;
 903                                         hdr.count = ++sc->sc_trace_bcount;
 904                                         MICROTIME(hdr.time);
 905                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 906                                 }
 907
 908                                 if(chan->bprot == BPROT_NONE)
 909                                 {
 910                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 911                                                 activity = ACT_TX;
 912                                 }
 913                                 else
 914                                 {
 915                                         activity = ACT_TX;
 916                                 }
 917                         }
 918                 }
 919
 920                 avma1pp2_hscx_fifo(chan, sc);
 921         }
 922
 923         /* call timeout handling routine */
 924
 925         if(activity == ACT_RX || activity == ACT_TX)
 926                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 927 }
 928
 929 /*
 930  * this is the main routine which checks each channel and then calls
 931  * the real interrupt routine as appropriate
 932  */
 933 static void
 934 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 935 {
 936         u_int stat;
 937
 938         /* has to be a u_int because the byte count is in the 2nd byte */
 939         stat = hscx_read_reg_int(0, sc);
 940         if (stat & HSCX_INT_MASK)
 941           avma1pp2_hscx_intr(0, stat, sc);
 942         stat = hscx_read_reg_int(1, sc);
 943         if (stat & HSCX_INT_MASK)
 944           avma1pp2_hscx_intr(1, stat, sc);
 945 }
 946
 947 static void
 948 avma1pp2_disable(device_t dev)
 949 {
 950         struct l1_softc *sc = device_get_softc(dev);
 951         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 952         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 953
 954         /* could still be wrong, but it seems to help */
 955         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 956 }
 957
 958 static void
 959 avma1pp2_intr(void *xsc)
 960 {
 961         u_char stat;
 962         struct l1_softc *sc;
 963         bus_space_handle_t bhandle;
 964         bus_space_tag_t btag;
 965
 966         sc = xsc;
 967         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 968         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 969
 970         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 971         NDBGL1(L1_H_IRQ, "stat %x", stat);
 972         /* was there an interrupt from this card ? */
 973         if ((stat & ASL_IRQ_Pending) == 0)
 974                 return; /* no */
 975         /* For slow machines loop as long as an interrupt is active */
 976         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 977         {
 978                 /* interrupts are high active */
 979                 if (stat & ASL_IRQ_TIMER)
 980                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 981                 if (stat & ASL_IRQ_HSCX)
 982                 {
 983                         NDBGL1(L1_H_IRQ, "HSCX");
 984                         avma1pp2_hscx_int_handler(sc);
 985                 }
 986                 if (stat & ASL_IRQ_ISAC)
 987                 {
 988                        NDBGL1(L1_H_IRQ, "ISAC");
 989                        ifpi2_isacsx_intr(sc);
 990                 }
 991                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 992                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 993
 994         }
 995 }
 996
 997 static void
 998 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 999 {
1000         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1001         u_int param = 0;
1002
1003         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1004                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1005
1006         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
1007
1008         if (activate == 0)
1009         {
1010                 /* only deactivate if both channels are idle */
1011                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1012                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1013                 {
1014                         return;
1015                 }
1016                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1017                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1018                 AVMA1PPSETCMDLONG(param);
1019                 hscx_write_reg(h_chan, param, sc);
1020                 return;
1021         }
1022         if(chan->bprot == BPROT_RHDLC)
1023         {
1024                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1025
1026                 /* HDLC Frames, transparent mode 0 */
1027                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1028                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1029                 AVMA1PPSETCMDLONG(param);
1030                 hscx_write_reg(h_chan, param, sc);
1031                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1032                 AVMA1PPSETCMDLONG(param);
1033                 hscx_write_reg(h_chan, param, sc);
1034                 sc->avma1pp_cmd = 0;
1035         }
1036         else
1037         {
1038                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1039
1040                 /* Raw Telephony, extended transparent mode 1 */
1041                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1042                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1043                 AVMA1PPSETCMDLONG(param);
1044                 hscx_write_reg(h_chan, param, sc);
1045                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1046                 AVMA1PPSETCMDLONG(param);
1047                 hscx_write_reg(h_chan, param, sc);
1048                 sc->avma1pp_cmd = 0;
1049         }
1050 }
1051
1052 static void
1053 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1054 {
1055 #ifdef __FreeBSD__
1056         struct l1_softc *sc = ifpi2_scp[unit];
1057 #else
1058         struct l1_softc *sc = isic_find_sc(unit);
1059 #endif
1060         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1061
1062         int s = SPLI4B();
1063
1064         if(activate == 0)
1065         {
1066                 /* deactivation */
1067                 chan->state = HSCX_IDLE;
1068                 avma1pp2_hscx_init(sc, h_chan, activate);
1069         }
1070
1071         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1072                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1073
1074         /* general part */
1075
1076         chan->unit = sc->sc_unit;       /* unit number */
1077         chan->channel = h_chan;         /* B channel */
1078         chan->bprot = bprot;            /* B channel protocol */
1079         chan->state = HSCX_IDLE;        /* B channel state */
1080
1081         /* receiver part */
1082
1083         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1084
1085         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1086
1087         chan->rxcount = 0;              /* reset rx counter */
1088
1089         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1090
1091         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1092         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1093         chan->in_len = 0;               /* reset mbuf data len */
1094
1095         /* transmitter part */
1096
1097         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1098
1099         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1100
1101         chan->txcount = 0;              /* reset tx counter */
1102
1103         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1104
1105         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1106         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1107         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1108         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1109
1110         if(activate != 0)
1111         {
1112                 /* activation */
1113                 avma1pp2_hscx_init(sc, h_chan, activate);
1114                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1115         }
1116
1117         splx(s);
1118 }
1119
1120 static void
1121 avma1pp2_bchannel_start(int unit, int h_chan)
1122 {
1123 #ifdef __FreeBSD__
1124         struct l1_softc *sc = ifpi2_scp[unit];
1125 #else
1126         struct l1_softc *sc = isic_find_sc(unit);
1127 #endif
1128         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1129         int s;
1130         int activity = -1;
1131
1132         s = SPLI4B();                           /* enter critical section */
1133         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1134         {
1135                 splx(s);
1136                 return;                         /* yes, leave */
1137         }
1138
1139         /* get next mbuf from queue */
1140
1141         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1142
1143         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1144         {
1145                 splx(s);                        /* leave critical section */
1146                 return;                         /* yes, exit */
1147         }
1148
1149         /* init current mbuf values */
1150
1151         chan->out_mbuf_cur = chan->out_mbuf_head;
1152         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1153         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1154
1155         /* activity indicator for timeout handling */
1156
1157         if(chan->bprot == BPROT_NONE)
1158         {
1159                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1160                         activity = ACT_TX;
1161         }
1162         else
1163         {
1164                 activity = ACT_TX;
1165         }
1166
1167         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1168
1169         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1170         {
1171                 i4b_trace_hdr_t hdr;
1172                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1173                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1174                 hdr.dir = FROM_TE;
1175                 hdr.count = ++sc->sc_trace_bcount;
1176                 MICROTIME(hdr.time);
1177                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1178         }
1179
1180         avma1pp2_hscx_fifo(chan, sc);
1181
1182         /* call timeout handling routine */
1183
1184         if(activity == ACT_RX || activity == ACT_TX)
1185                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1186
1187         splx(s);
1188 }
1189
1190 /*---------------------------------------------------------------------------*
1191  *      return the address of isic drivers linktab
1192  *---------------------------------------------------------------------------*/
1193 static isdn_link_t *
1194 avma1pp2_ret_linktab(int unit, int channel)
1195 {
1196 #ifdef __FreeBSD__
1197         struct l1_softc *sc = ifpi2_scp[unit];
1198 #else
1199         struct l1_softc *sc = isic_find_sc(unit);
1200 #endif
1201         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1202
1203         return(&chan->isic_isdn_linktab);
1204 }
1205
1206 /*---------------------------------------------------------------------------*
1207  *      set the driver linktab in the b channel softc
1208  *---------------------------------------------------------------------------*/
1209 static void
1210 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1211 {
1212 #ifdef __FreeBSD__
1213         struct l1_softc *sc = ifpi2_scp[unit];
1214 #else
1215         struct l1_softc *sc = isic_find_sc(unit);
1216 #endif
1217         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1218
1219         chan->isic_drvr_linktab = dlt;
1220 }
1221
1222
1223 /*---------------------------------------------------------------------------*
1224  *      initialize our local linktab
1225  *---------------------------------------------------------------------------*/
1226 static void
1227 avma1pp2_init_linktab(struct l1_softc *sc)
1228 {
1229         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1230         isdn_link_t *lt = &chan->isic_isdn_linktab;
1231
1232         /* make sure the hardware driver is known to layer 4 */
1233         /* avoid overwriting if already set */
1234         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1235         {
1236                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1237                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1238         }
1239
1240         /* local setup */
1241         lt->unit = sc->sc_unit;
1242         lt->channel = HSCX_CH_A;
1243         lt->bch_config = avma1pp2_bchannel_setup;
1244         lt->bch_tx_start = avma1pp2_bchannel_start;
1245         lt->bch_stat = avma1pp2_bchannel_stat;
1246         lt->tx_queue = &chan->tx_queue;
1247
1248         /* used by non-HDLC data transfers, i.e. telephony drivers */
1249         lt->rx_queue = &chan->rx_queue;
1250
1251         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1252         lt->rx_mbuf = &chan->in_mbuf;
1253
1254         chan = &sc->sc_chan[HSCX_CH_B];
1255         lt = &chan->isic_isdn_linktab;
1256
1257         lt->unit = sc->sc_unit;
1258         lt->channel = HSCX_CH_B;
1259         lt->bch_config = avma1pp2_bchannel_setup;
1260         lt->bch_tx_start = avma1pp2_bchannel_start;
1261         lt->bch_stat = avma1pp2_bchannel_stat;
1262         lt->tx_queue = &chan->tx_queue;
1263
1264         /* used by non-HDLC data transfers, i.e. telephony drivers */
1265         lt->rx_queue = &chan->rx_queue;
1266
1267         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1268         lt->rx_mbuf = &chan->in_mbuf;
1269 }
1270
1271 /*
1272  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1273  */
1274 static void
1275 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1276 {
1277 #ifdef __FreeBSD__
1278         struct l1_softc *sc = ifpi2_scp[unit];
1279 #else
1280         struct l1_softc *sc = isic_find_sc(unit);
1281 #endif
1282         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1283         int s;
1284
1285         s = SPLI4B();
1286
1287         bsp->outbytes = chan->txcount;
1288         bsp->inbytes = chan->rxcount;
1289
1290         chan->txcount = 0;
1291         chan->rxcount = 0;
1292
1293         splx(s);
1294 }
1295
1296 /*---------------------------------------------------------------------------*
1297  *      fill HSCX fifo with data from the current mbuf
1298  *      Put this here until it can go into i4b_hscx.c
1299  *---------------------------------------------------------------------------*/
1300 static int
1301 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1302 {
1303         int len;
1304         int nextlen;
1305         int i;
1306         int cmd = 0;
1307         /* using a scratch buffer simplifies writing to the FIFO */
1308         u_char scrbuf[HSCX_FIFO_LEN];
1309
1310         len = 0;
1311
1312         /*
1313          * fill the HSCX tx fifo with data from the current mbuf. if
1314          * current mbuf holds less data than HSCX fifo length, try to
1315          * get the next mbuf from (a possible) mbuf chain. if there is
1316          * not enough data in a single mbuf or in a chain, then this
1317          * is the last mbuf and we tell the HSCX that it has to send
1318          * CRC and closing flag
1319          */
1320
1321         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1322         {
1323                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1324
1325 #ifdef NOTDEF
1326                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1327                         chan->out_mbuf_head,
1328                         chan->out_mbuf_cur,
1329                         chan->out_mbuf_cur_ptr,
1330                         chan->out_mbuf_cur_len,
1331                         len,
1332                         nextlen);
1333 #endif
1334
1335                 cmd |= HSCX_CMDR_XTF;
1336                 /* collect the data in the scratch buffer */
1337                 for (i = 0; i < nextlen; i++)
1338                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1339
1340                 len += nextlen;
1341                 chan->txcount += nextlen;
1342
1343                 chan->out_mbuf_cur_ptr += nextlen;
1344                 chan->out_mbuf_cur_len -= nextlen;
1345
1346                 if(chan->out_mbuf_cur_len == 0)
1347                 {
1348                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1349                         {
1350                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1351                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1352
1353                                 if(sc->sc_trace & TRACE_B_TX)
1354                                 {
1355                                         i4b_trace_hdr_t hdr;
1356                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1357                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1358                                         hdr.dir = FROM_TE;
1359                                         hdr.count = ++sc->sc_trace_bcount;
1360                                         MICROTIME(hdr.time);
1361                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1362                                 }
1363                         }
1364                         else
1365                         {
1366                                 if (chan->bprot != BPROT_NONE)
1367                                         cmd |= HSCX_CMDR_XME;
1368                                 i4b_Bfreembuf(chan->out_mbuf_head);
1369                                 chan->out_mbuf_head = NULL;
1370                         }
1371                 }
1372         }
1373         /* write what we have from the scratch buf to the HSCX fifo */
1374         if (len != 0)
1375                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1376         return(cmd);
1377 }
1378
1379 /*---------------------------------------------------------------------------*
1380  *      ifpi2 - ISAC interrupt routine
1381  *---------------------------------------------------------------------------*/
1382 static void
1383 ifpi2_isacsx_intr(struct l1_softc *sc)
1384 {
1385         u_char isacsx_irq_stat;
1386
1387         for(;;)
1388         {
1389                 /* get isac irq status */
1390                 /* ISTA tells us whether it was a C/I or HDLC int. */
1391                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1392
1393                 if(isacsx_irq_stat)
1394                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1395                 else
1396                         break;
1397         }
1398
1399         ISAC_WRITE(I_MASKD, 0xff);
1400         ISAC_WRITE(I_MASK, 0xff);
1401
1402         DELAY(100);
1403
1404         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1405         ISAC_WRITE(I_MASK, isacsx_imask);
1406 }
1407
1408 /*---------------------------------------------------------------------------*
1409  *      ifpi2_recover - try to recover from irq lockup
1410  *---------------------------------------------------------------------------*/
1411 void
1412 ifpi2_recover(struct l1_softc *sc)
1413 {
1414         printf("ifpi2_recover %d\n", sc->sc_unit);
1415 #if 0 /* fix me later */
1416         u_char byte;
1417
1418         /* get isac irq status */
1419
1420         byte = ISAC_READ(I_ISTA);
1421
1422         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1423
1424         if(byte & ISACSX_ISTA_EXI)
1425                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1426
1427         if(byte & ISACSX_ISTA_CISQ)
1428         {
1429                 byte = ISAC_READ(I_CIRR);
1430
1431                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1432
1433                 if(byte & ISACSX_CIRR_SQC)
1434                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1435         }
1436
1437         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1438
1439         ISAC_WRITE(I_MASKD, 0xff);
1440         ISAC_WRITE(I_MASK, 0xff);
1441         DELAY(100);
1442         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1443         ISAC_WRITE(I_MASK, isacsx_imask);
1444 #endif
1445 }
1446
1447
1448 #endif /* NIFPI2 > 0 */