2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.29 2006/10/25 20:55:53 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
46 #include <bus/pci/pcivar.h>
50 static void cyrix_timing(struct ata_device *, int, int);
51 static void promise_timing(struct ata_device *, int, int);
52 static void hpt_timing(struct ata_device *, int, int);
53 static int hpt_cable80(struct ata_device *);
56 #define ATAPI_DEVICE(atadev) \
57 ((atadev->unit == ATA_MASTER && \
58 atadev->channel->devices & ATA_ATAPI_MASTER) || \
59 (atadev->unit == ATA_SLAVE && \
60 atadev->channel->devices & ATA_ATAPI_SLAVE))
62 int ata_dma_debug = 0;
65 ata_dmaalloc(struct ata_device *atadev, int flags)
67 struct ata_channel *ch = atadev->channel;
69 if (atadev->dmastate.dmatab != NULL)
72 KKASSERT(ch->dma_mpipe.max_count != 0);
73 if (flags & M_RNOWAIT)
74 atadev->dmastate.dmatab = mpipe_alloc_nowait(&ch->dma_mpipe);
76 atadev->dmastate.dmatab = mpipe_alloc_waitok(&ch->dma_mpipe);
78 if (atadev->dmastate.dmatab != NULL) {
79 KKASSERT(((uintptr_t)atadev->dmastate.dmatab & PAGE_MASK) == 0);
86 ata_dmafree(struct ata_device *atadev)
88 struct ata_channel *ch = atadev->channel;
90 if (atadev->dmastate.dmatab) {
91 mpipe_free(&ch->dma_mpipe, atadev->dmastate.dmatab);
92 atadev->dmastate.dmatab = NULL;
97 ata_dmafreetags(struct ata_channel *ch)
102 ata_dmacreate(struct ata_device *atadev, int apiomode, int mode)
108 ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode)
110 device_t parent = device_get_parent(atadev->channel->dev);
111 int chiptype = atadev->channel->chiptype;
112 int chiprev = pci_get_revid(parent);
113 int channel = atadev->channel->unit;
114 int device = ATA_DEV(atadev->unit);
115 int devno = (channel << 1) + device;
118 /* set our most pessimistic default mode */
119 atadev->mode = ATA_PIO;
121 if (!atadev->channel->r_bmio)
124 /* if simplex controller, only allow DMA on primary channel */
126 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT,
127 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
128 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
129 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
130 ATA_BMSTAT_DMA_SIMPLEX) {
131 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
136 /* DMA engine address alignment is usually 1 word (2 bytes) */
137 atadev->channel->alignment = 0x1;
140 if (udmamode > 2 && !atadev->param->hwres_cblid) {
141 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
147 case 0x27df8086: /* Intel ICH7 ATA */
148 case 0x27c48086: /* Intel ICH7M SATA */
149 case 0x266f8086: /* Intel ICH6 ATA */
150 case 0x26528086: /* Intel ICH6R/RW SATA */
151 case 0x26518086: /* Intel ICH6/W SATA */
152 case 0x24db8086: /* Intel ICH5 */
153 case 0x24d18086: /* Intel ICH5 SATA */
154 case 0x24ca8086: /* Intel ICH4 mobile */
155 case 0x24cb8086: /* Intel ICH4 */
156 case 0x248a8086: /* Intel ICH3 mobile */
157 case 0x248b8086: /* Intel ICH3 */
158 case 0x244a8086: /* Intel ICH2 mobile */
159 case 0x244b8086: /* Intel ICH2 */
161 int32_t mask48, new48;
164 word54 = pci_read_config(parent, 0x54, 2);
165 if (word54 & (0x10 << devno)) {
166 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
167 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
169 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
170 (error) ? "failed" : "success");
172 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
173 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
174 pci_write_config(parent, 0x48,
175 (pci_read_config(parent, 0x48, 4) &
176 ~mask48) | new48, 4);
177 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
178 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
183 /* make sure eventual ATA100 mode from the BIOS is disabled */
184 pci_write_config(parent, 0x54,
185 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
188 case 0x24118086: /* Intel ICH */
189 case 0x76018086: /* Intel ICH */
191 int32_t mask48, new48;
194 word54 = pci_read_config(parent, 0x54, 2);
195 if (word54 & (0x10 << devno)) {
196 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
197 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
199 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
200 (error) ? "failed" : "success");
202 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
203 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
204 pci_write_config(parent, 0x48,
205 (pci_read_config(parent, 0x48, 4) &
206 ~mask48) | new48, 4);
207 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
208 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
213 /* make sure eventual ATA66 mode from the BIOS is disabled */
214 pci_write_config(parent, 0x54,
215 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
218 case 0x71118086: /* Intel PIIX4 */
219 case 0x84CA8086: /* Intel PIIX4 */
220 case 0x71998086: /* Intel PIIX4e */
221 case 0x24218086: /* Intel ICH0 */
223 int32_t mask48, new48;
225 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
226 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
228 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
229 (error) ? "failed" : "success");
231 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
232 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
233 pci_write_config(parent, 0x48,
234 (pci_read_config(parent, 0x48, 4) &
235 ~mask48) | new48, 4);
236 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
240 /* make sure eventual ATA33 mode from the BIOS is disabled */
241 pci_write_config(parent, 0x48,
242 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
245 case 0x70108086: /* Intel PIIX3 */
246 if (wdmamode >= 2 && apiomode >= 4) {
247 int32_t mask40, new40, mask44, new44;
249 /* if SITRE not set doit for both channels */
250 if (!((pci_read_config(parent,0x40,4)>>(channel<<8))&0x4000)) {
251 new40 = pci_read_config(parent, 0x40, 4);
252 new44 = pci_read_config(parent, 0x44, 4);
253 if (!(new40 & 0x00004000)) {
254 new44 &= ~0x0000000f;
255 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
257 if (!(new40 & 0x40000000)) {
258 new44 &= ~0x000000f0;
259 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
262 pci_write_config(parent, 0x40, new40, 4);
263 pci_write_config(parent, 0x44, new44, 4);
265 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
266 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
268 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
269 (error) ? "failed" : "success");
271 if (device == ATA_MASTER) {
289 pci_write_config(parent, 0x40,
290 (pci_read_config(parent, 0x40, 4) & ~mask40)|
292 pci_write_config(parent, 0x44,
293 (pci_read_config(parent, 0x44, 4) & ~mask44)|
295 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
299 /* we could set PIO mode timings, but we assume the BIOS did that */
302 case 0x12308086: /* Intel PIIX */
303 if (wdmamode >= 2 && apiomode >= 4) {
306 word40 = pci_read_config(parent, 0x40, 4);
307 word40 >>= channel * 16;
309 /* Check for timing config usable for DMA on controller */
310 if (!((word40 & 0x3300) == 0x2300 &&
311 ((word40 >> (device ? 4 : 0)) & 1) == 1))
314 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
315 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
317 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
318 (error) ? "failed" : "success");
320 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
326 case 0x522910b9: /* AcerLabs Aladdin IV/V */
327 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
328 if (chiprev < 0xc2 &&
329 atadev->channel->devices & ATA_ATAPI_MASTER &&
330 atadev->channel->devices & ATA_ATAPI_SLAVE) {
331 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
334 #if !defined(NO_ATANG)
335 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4);
337 if (udmamode >= 5 && chiprev >= 0xc4) {
338 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
339 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
341 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
342 (error) ? "failed" : "success");
344 int32_t word54 = pci_read_config(parent, 0x54, 4);
346 pci_write_config(parent, 0x4b,
347 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
348 word54 &= ~(0x000f000f << (devno << 2));
349 word54 |= (0x000f0005 << (devno << 2));
350 pci_write_config(parent, 0x54, word54, 4);
351 pci_write_config(parent, 0x53,
352 pci_read_config(parent, 0x53, 1) | 0x03, 1);
353 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
357 if (udmamode >= 4 && chiprev >= 0xc2) {
358 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
359 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
361 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
362 (error) ? "failed" : "success");
364 int32_t word54 = pci_read_config(parent, 0x54, 4);
366 pci_write_config(parent, 0x4b,
367 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
368 word54 &= ~(0x000f000f << (devno << 2));
369 word54 |= (0x00080005 << (devno << 2));
370 pci_write_config(parent, 0x54, word54, 4);
371 pci_write_config(parent, 0x53,
372 pci_read_config(parent, 0x53, 1) | 0x03, 1);
373 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
377 if (udmamode >= 2 && chiprev >= 0x20) {
378 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
379 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
381 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
382 (error) ? "failed" : "success");
384 int32_t word54 = pci_read_config(parent, 0x54, 4);
386 word54 &= ~(0x000f000f << (devno << 2));
387 word54 |= (0x000a0005 << (devno << 2));
388 pci_write_config(parent, 0x54, word54, 4);
389 pci_write_config(parent, 0x53,
390 pci_read_config(parent, 0x53, 1) | 0x03, 1);
391 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
392 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
397 /* make sure eventual UDMA mode from the BIOS is disabled */
398 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
399 ~(0x0008 << (devno << 2)), 2);
401 if (wdmamode >= 2 && apiomode >= 4) {
402 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
403 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
405 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
406 (error) ? "failed" : "success");
408 pci_write_config(parent, 0x53,
409 pci_read_config(parent, 0x53, 1) | 0x03, 1);
410 atadev->channel->flags |= ATA_ATAPI_DMA_RO;
411 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
415 pci_write_config(parent, 0x53,
416 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
417 #if !defined(NO_ATANG)
418 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
420 ATA_C_F_SETXFER, ATA_WAIT_READY);
422 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n",
423 (error) ? "failed" : "success",
424 (apiomode >= 0) ? apiomode : 0);
426 int32_t word54 = pci_read_config(parent, 0x54, 4);
429 switch(ATA_PIO0 + apiomode) {
430 case ATA_PIO0: timing = 0x006d0003; break;
431 case ATA_PIO1: timing = 0x00580002; break;
432 case ATA_PIO2: timing = 0x00440001; break;
433 case ATA_PIO3: timing = 0x00330001; break;
434 case ATA_PIO4: timing = 0x00310001; break;
435 default: timing = 0x006d0003; break;
437 pci_write_config(parent, 0x58 + (channel << 2), timing, 4);
438 word54 &= ~(0x000f000f << (devno << 2));
439 word54 |= (0x00000004 << (devno << 2));
440 pci_write_config(parent, 0x54, word54, 4);
441 atadev->mode = ATA_PIO0 + apiomode;
447 case 0x31491106: /* VIA 8237 SATA part */
449 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
451 ATA_C_F_SETXFER, ATA_WAIT_READY);
453 ata_prtdev(atadev, "%s setting UDMA%d on VIA chip\n",
454 (error) ? "failed" : "success", udmamode);
456 ata_dmacreate(atadev, apiomode, ATA_UDMA + udmamode);
460 /* we could set PIO mode timings, but we assume the BIOS did that */
463 case 0x01bc10de: /* NVIDIA nForce1 */
464 case 0x006510de: /* NVIDIA nForce2 */
465 case 0x00d510de: /* NVIDIA nForce3 */
466 case 0x00e310de: /* NVIDIA nForce3 PRO S1 */
467 case 0x00e510de: /* NVIDIA nForce3 PRO */
468 case 0x74691022: /* AMD 8111 */
469 case 0x74411022: /* AMD 768 */
470 case 0x74111022: /* AMD 766 */
471 case 0x74091022: /* AMD 756 */
472 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
474 int via_modes[][7] = {
475 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
476 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
477 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
478 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
479 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
484 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
485 ata_find_dev(parent, 0x31771106, 0) || /* 8235 */
486 ata_find_dev(parent, 0x31491106, 0)) { /* 8237 */
487 udmamode = imin(udmamode, 6);
488 reg_val = via_modes[3];
490 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
491 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
492 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
493 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
494 udmamode = imin(udmamode, 5);
495 reg_val = via_modes[2];
497 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
498 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
499 udmamode = imin(udmamode, 4);
500 reg_val = via_modes[1];
502 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
503 udmamode = imin(udmamode, 2);
504 reg_val = via_modes[1];
506 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
507 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
508 udmamode = imin(udmamode, 2);
509 reg_val = via_modes[0];
511 else if (chiptype == 0x74691022 || /* AMD 8111 */
512 chiptype == 0x74411022 || /* AMD 768 */
513 chiptype == 0x74111022) { /* AMD 766 */
514 udmamode = imin(udmamode, 5);
515 reg_val = via_modes[4];
518 else if (chiptype == 0x74091022) { /* AMD 756 */
519 udmamode = imin(udmamode, 4);
520 reg_val = via_modes[4];
523 else if (chiptype == 0x01bc10de) { /* nForce1 */
524 udmamode = imin(udmamode, 5);
525 reg_val = via_modes[4];
526 #if !defined(NO_ATANG)
531 else if (chiptype == 0x006510de || /* nForce2 */
532 chiptype == 0x00d510de || /* nForce3 */
533 chiptype == 0x00e310de || /* nForce3 PRO S1 */
534 chiptype == 0x00e510de) { /* nForce3 PRO */
535 udmamode = imin(udmamode, 6);
536 reg_val = via_modes[4];
537 #if !defined(NO_ATANG)
548 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
549 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
551 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
552 (error) ? "failed" : "success", chip);
554 pci_write_config(parent, reg_off, reg_val[6], 1);
555 pci_write_config(parent, reg_off - 8, 0x20, 1);
556 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
561 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
562 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
564 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
565 (error) ? "failed" : "success", chip);
567 pci_write_config(parent, reg_off, reg_val[5], 1);
568 pci_write_config(parent, reg_off - 8, 0x20, 1);
569 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
574 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
575 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
577 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
578 (error) ? "failed" : "success", chip);
580 pci_write_config(parent, reg_off, reg_val[4], 1);
581 pci_write_config(parent, reg_off - 8, 0x20, 1);
582 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
587 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
588 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
590 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
591 (error) ? "failed" : "success", chip);
593 pci_write_config(parent, reg_off, reg_val[2], 1);
594 pci_write_config(parent, reg_off - 8, 0x20, 1);
595 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
599 if (wdmamode >= 2 && apiomode >= 4) {
600 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
601 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
603 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
604 (error) ? "failed" : "success", chip);
606 pci_write_config(parent, reg_off, 0x0b, 1);
607 pci_write_config(parent, reg_off - 8, 0x20, 1);
608 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
612 pci_write_config(parent, reg_off, 0x8b, 1);
615 pci_write_config(parent, reg_off - 8, 0xa8, 1);
618 pci_write_config(parent, reg_off - 8, 0x65, 1);
621 pci_write_config(parent, reg_off - 8, 0x42, 1);
624 pci_write_config(parent, reg_off - 8, 0x22, 1);
627 pci_write_config(parent, reg_off - 8, 0x20, 1);
633 case 0x55131039: /* SiS 5591 */
634 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
635 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
636 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
637 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
638 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
639 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
640 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
641 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
642 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
643 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
644 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
645 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
646 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
647 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
648 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
649 int8_t reg = 0x40 + (devno << 1);
650 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
653 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
654 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
656 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
657 (error) ? "failed" : "success");
659 pci_write_config(parent, reg, val | 0x8000, 2);
660 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
665 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
666 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
668 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
669 (error) ? "failed" : "success");
671 pci_write_config(parent, reg, val | 0x9000, 2);
672 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
677 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
678 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
680 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
681 (error) ? "failed" : "success");
683 pci_write_config(parent, reg, val | 0xb000, 2);
684 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
688 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
689 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
690 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
691 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
692 int8_t reg = 0x40 + (devno << 1);
693 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
696 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
697 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
699 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
700 (error) ? "failed" : "success");
702 pci_write_config(parent, reg, val | 0x9000, 2);
703 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
708 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
709 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
711 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
712 (error) ? "failed" : "success");
714 pci_write_config(parent, reg, val | 0xa000, 2);
715 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
719 } else if (udmamode >= 2 && chiprev > 0xc1) {
720 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
721 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
723 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
724 (error) ? "failed" : "success");
726 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
727 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
731 if (wdmamode >=2 && apiomode >= 4) {
732 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
733 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
735 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
736 (error) ? "failed" : "success");
738 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
739 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
743 /* we could set PIO mode timings, but we assume the BIOS did that */
746 case 0x35121095: /* SiI 3512 SATA controller */
747 /* EXPERIMENTAL! Works with FN85 AMD 64 3200+ motherboard */
749 case 0x31241095: /* SiI 3124 SATA controller */
750 case 0x31141095: /* SiI 3114 SATA controller */
751 case 0x31121095: /* SiI 3112 SATA controller */
752 case 0x06801095: /* SiI 0680 ATA133 controller */
754 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10);
755 u_int8_t uval = pci_read_config(parent, ureg, 1);
756 u_int8_t mreg = channel ? 0x84 : 0x80;
757 u_int8_t mask = device ? 0x30 : 0x03;
758 u_int8_t mode = pci_read_config(parent, mreg, 1);
760 /* enable UDMA mode */
761 pci_write_config(parent, mreg,
762 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
764 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
765 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
767 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
768 (error) ? "failed" : "success");
770 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x01, 1);
771 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
776 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
777 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
779 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
780 (error) ? "failed" : "success");
782 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x02, 1);
783 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
788 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
789 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
791 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
792 (error) ? "failed" : "success");
794 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x03, 1);
795 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
800 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
801 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
803 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
804 (error) ? "failed" : "success");
806 pci_write_config(parent, ureg, (uval & ~0x3f) | 0x07, 1);
807 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
812 /* disable UDMA mode and enable WDMA mode */
813 pci_write_config(parent, mreg,
814 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
815 if (wdmamode >= 2 && apiomode >= 4) {
816 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
817 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
819 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
820 (error) ? "failed" : "success");
822 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
823 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
828 /* restore PIO mode */
829 pci_write_config(parent, mreg, mode, 1);
831 /* we could set PIO mode timings, but we assume the BIOS did that */
834 case 0x06491095: /* CMD 649 ATA100 controller */
838 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
839 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
841 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
842 (error) ? "failed" : "success");
844 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
845 umode &= ~(device ? 0xca : 0x35);
846 umode |= (device ? 0x0a : 0x05);
847 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
848 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
854 case 0x06481095: /* CMD 648 ATA66 controller */
858 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
859 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
861 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
862 (error) ? "failed" : "success");
864 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
865 umode &= ~(device ? 0xca : 0x35);
866 umode |= (device ? 0x4a : 0x15);
867 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
868 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
875 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
876 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
878 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
879 (error) ? "failed" : "success");
881 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1);
882 umode &= ~(device ? 0xca : 0x35);
883 umode |= (device ? 0x42 : 0x11);
884 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1);
885 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
889 /* make sure eventual UDMA mode from the BIOS is disabled */
890 pci_write_config(parent, channel ? 0x7b : 0x73,
891 pci_read_config(parent, channel ? 0x7b : 0x73, 1)&
892 #if !defined(NO_ATANG)
893 ~(device ? 0xca : 0x53), 1);
895 ~(device ? 0xca : 0x35), 1);
899 case 0x06461095: /* CMD 646 ATA controller */
900 if (wdmamode >= 2 && apiomode >= 4) {
901 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
902 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
904 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
905 error ? "failed" : "success");
907 int32_t offset = (devno < 3) ? (devno << 1) : 7;
909 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
910 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
914 /* we could set PIO mode timings, but we assume the BIOS did that */
917 case 0xc6931080: /* Cypress 82c693 ATA controller */
918 if (wdmamode >= 2 && apiomode >= 4) {
919 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
920 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
922 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
923 error ? "failed" : "success");
925 pci_write_config(atadev->channel->dev,
926 channel ? 0x4e:0x4c, 0x2020, 2);
927 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
931 /* we could set PIO mode timings, but we assume the BIOS did that */
934 case 0x01021078: /* Cyrix 5530 ATA33 controller */
935 atadev->channel->alignment = 0xf; /* DMA engine requires 16 byte alignment */
937 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
938 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
940 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
941 (error) ? "failed" : "success");
943 cyrix_timing(atadev, devno, ATA_UDMA2);
944 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
948 if (wdmamode >= 2 && apiomode >= 4) {
949 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
950 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
952 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
953 (error) ? "failed" : "success");
955 cyrix_timing(atadev, devno, ATA_WDMA2);
956 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
960 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
961 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
964 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
965 (error) ? "failed" : "success",
966 ata_mode2str(ATA_PIO0 + apiomode));
967 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode);
968 atadev->mode = ATA_PIO0 + apiomode;
971 #if !defined(NO_ATANG)
972 case 0x02131166: /* ServerWorks CSB6 ATA 100 controller (chan 0+1) */
974 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
975 #if !defined(NO_ATANG)
976 if (udmamode >= 5 && (chiptype == 0x02131166 ||
977 (chiptype == 0x02121166 &&
980 if (udmamode >= 5 && chiprev >= 0x92) {
982 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
983 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
985 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
986 (error) ? "failed" : "success");
990 pci_write_config(parent, 0x54,
991 pci_read_config(parent, 0x54, 1) |
993 reg56 = pci_read_config(parent, 0x56, 2);
994 reg56 &= ~(0xf << (devno * 4));
995 reg56 |= (0x5 << (devno * 4));
996 pci_write_config(parent, 0x56, reg56, 2);
997 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1001 #if !defined(NO_ATANG)
1003 case 0x02171166: /* Server Works CSB6 ATA 66 controller chan 2 */
1005 if (udmamode >= 4) {
1006 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1007 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1009 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
1010 (error) ? "failed" : "success");
1014 pci_write_config(parent, 0x54,
1015 pci_read_config(parent, 0x54, 1) |
1016 (0x01 << devno), 1);
1017 reg56 = pci_read_config(parent, 0x56, 2);
1018 reg56 &= ~(0xf << (devno * 4));
1019 reg56 |= (0x4 << (devno * 4));
1020 pci_write_config(parent, 0x56, reg56, 2);
1021 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1027 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
1028 if (udmamode >= 2) {
1029 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1030 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1032 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
1033 (error) ? "failed" : "success");
1037 pci_write_config(parent, 0x54,
1038 pci_read_config(parent, 0x54, 1) |
1039 (0x01 << devno), 1);
1040 reg56 = pci_read_config(parent, 0x56, 2);
1041 reg56 &= ~(0xf << (devno * 4));
1042 reg56 |= (0x2 << (devno * 4));
1043 pci_write_config(parent, 0x56, reg56, 2);
1044 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1048 if (wdmamode >= 2 && apiomode >= 4) {
1049 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1050 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1052 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
1053 (error) ? "failed" : "success");
1055 int offset = devno ^ 0x01; /* (chan*2) + (dev==ATA_MASTER)*/
1056 int word44 = pci_read_config(parent, 0x44, 4);
1058 pci_write_config(parent, 0x54,
1059 pci_read_config(parent, 0x54, 1) &
1060 ~(0x01 << devno), 1);
1061 word44 &= ~(0xff << (offset << 8));
1062 word44 |= (0x20 << (offset << 8));
1063 pci_write_config(parent, 0x44, 0x20, 4);
1064 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1068 /* we could set PIO mode timings, but we assume the BIOS did that */
1071 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
1072 case 0x5275105a: /* Promise TX2 ATA133 controllers */
1073 case 0x6269105a: /* Promise TX2 ATA133 controllers */
1074 case 0x7275105a: /* Promise TX2 ATA133 controllers */
1075 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1076 if (udmamode >= 6 &&
1077 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1078 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1079 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1081 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
1082 (error) ? "failed" : "success");
1084 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1090 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
1091 case 0x6268105a: /* Promise TX2 ATA100 controllers */
1092 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1093 if (udmamode >= 5 &&
1094 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1095 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1096 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1098 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1099 (error) ? "failed" : "success");
1101 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1105 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
1106 if (udmamode >= 4 &&
1107 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
1108 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1109 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1111 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1112 (error) ? "failed" : "success");
1114 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1118 if (udmamode >= 2) {
1119 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1120 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1122 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
1123 (error) ? "failed" : "success");
1125 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1129 if (wdmamode >= 2 && apiomode >= 4) {
1130 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1131 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1133 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1134 (error) ? "failed" : "success");
1136 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1142 case 0x0d30105a: /* Promise OEM ATA100 controllers */
1143 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
1144 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 &&
1145 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1146 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1147 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1149 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1150 (error) ? "failed" : "success");
1152 promise_timing(atadev, devno, ATA_UDMA5);
1153 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1159 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1160 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1161 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 &&
1162 !(pci_read_config(parent, 0x50, 2)&(channel ? 1<<11 : 1<<10))){
1163 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1164 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1166 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1167 (error) ? "failed" : "success");
1169 promise_timing(atadev, devno, ATA_UDMA4);
1170 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1176 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1177 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1178 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1179 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1181 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1182 (error) ? "failed" : "success");
1184 promise_timing(atadev, devno, ATA_UDMA2);
1185 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1189 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1190 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1191 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1193 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1194 (error) ? "failed" : "success");
1196 promise_timing(atadev, devno, ATA_WDMA2);
1197 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1201 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1202 ATA_PIO0 + apiomode,
1203 ATA_C_F_SETXFER, ATA_WAIT_READY);
1205 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1206 (error) ? "failed" : "success",
1207 (apiomode >= 0) ? apiomode : 0);
1208 promise_timing(atadev, devno, ATA_PIO0 + apiomode);
1209 atadev->mode = ATA_PIO0 + apiomode;
1212 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1213 case 0x00051103: /* HighPoint HPT372 controllers */
1214 case 0x00081103: /* HighPoint HPT374 controllers */
1215 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) &&
1216 ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1217 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1218 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1219 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1220 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1222 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1223 (error) ? "failed" : "success");
1225 hpt_timing(atadev, devno, ATA_UDMA6);
1226 ata_dmacreate(atadev, apiomode, ATA_UDMA6);
1230 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) &&
1231 ((chiptype == 0x00041103 && chiprev >= 0x03) ||
1232 (chiptype == 0x00051103 && chiprev >= 0x01) ||
1233 (chiptype == 0x00081103 && chiprev >= 0x07))) {
1234 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1235 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1237 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1238 (error) ? "failed" : "success");
1240 hpt_timing(atadev, devno, ATA_UDMA5);
1241 ata_dmacreate(atadev, apiomode, ATA_UDMA5);
1245 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) {
1246 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1247 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1249 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1250 (error) ? "failed" : "success");
1252 hpt_timing(atadev, devno, ATA_UDMA4);
1253 ata_dmacreate(atadev, apiomode, ATA_UDMA4);
1257 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) {
1258 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1259 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1261 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1262 (error) ? "failed" : "success");
1264 hpt_timing(atadev, devno, ATA_UDMA2);
1265 ata_dmacreate(atadev, apiomode, ATA_UDMA2);
1269 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) {
1270 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1271 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1273 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1274 (error) ? "failed" : "success");
1276 hpt_timing(atadev, devno, ATA_WDMA2);
1277 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1281 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1282 ATA_PIO0 + apiomode,
1283 ATA_C_F_SETXFER, ATA_WAIT_READY);
1285 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1286 (error) ? "failed" : "success",
1287 (apiomode >= 0) ? apiomode : 0);
1288 hpt_timing(atadev, devno, ATA_PIO0 + apiomode);
1289 atadev->mode = ATA_PIO0 + apiomode;
1292 case 0x000116ca: /* Cenatek Rocket Drive controller */
1293 if (wdmamode >= 0 &&
1294 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1295 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER)))
1296 ata_dmacreate(atadev, apiomode, ATA_DMA);
1298 atadev->mode = ATA_PIO;
1301 default: /* unknown controller chip */
1302 /* better not try generic DMA on ATAPI devices it almost never works */
1303 if (ATAPI_DEVICE(atadev))
1306 /* if controller says its setup for DMA take the easy way out */
1307 /* the downside is we dont know what DMA mode we are in */
1308 if ((udmamode >= 0 || wdmamode >= 2) &&
1309 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) &
1310 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) {
1311 ata_dmacreate(atadev, apiomode, ATA_DMA);
1315 /* well, we have no support for this, but try anyways */
1316 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) {
1317 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1318 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1320 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1321 (error) ? "failed" : "success");
1323 ata_dmacreate(atadev, apiomode, ATA_WDMA2);
1328 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1329 ATA_C_F_SETXFER, ATA_WAIT_READY);
1331 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1332 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1334 atadev->mode = ATA_PIO0 + apiomode;
1337 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1338 atadev->mode = ATA_PIO;
1343 ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count)
1345 struct ata_channel *ch = atadev->channel;
1346 struct ata_dmastate *ds = &atadev->dmastate;
1347 u_int32_t dma_count, dma_base;
1350 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1351 ata_prtdev(atadev, "non aligned DMA transfer attempted\n");
1356 ata_prtdev(atadev, "zero length DMA transfer attempted\n");
1360 dma_base = vtophys(data);
1361 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1366 ds->dmatab[i].base = dma_base;
1367 ds->dmatab[i].count = (dma_count & 0xffff);
1369 if (i >= ATA_DMA_ENTRIES) {
1370 ata_prtdev(atadev, "too many segments in DMA table\n");
1373 dma_base = vtophys(data);
1374 dma_count = imin(count, PAGE_SIZE);
1375 data += imin(count, PAGE_SIZE);
1376 count -= imin(count, PAGE_SIZE);
1378 ds->dmatab[i].base = dma_base;
1379 ds->dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1384 ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir)
1386 struct ata_channel *ch = atadev->channel;
1387 struct ata_dmastate *ds = &atadev->dmastate;
1389 ch->flags |= ATA_DMA_ACTIVE;
1390 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(ds->dmatab));
1391 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1392 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1393 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1394 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1395 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1396 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1401 ata_dmadone(struct ata_device *atadev)
1403 struct ata_channel *ch;
1404 struct ata_dmastate *ds;
1407 ch = atadev->channel;
1408 ds = &atadev->dmastate;
1410 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1411 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1412 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1413 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1414 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1415 ch->flags &= ~ATA_DMA_ACTIVE;
1417 return error & ATA_BMSTAT_MASK;
1421 ata_dmastatus(struct ata_channel *ch)
1423 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1427 cyrix_timing(struct ata_device *atadev, int devno, int mode)
1429 u_int32_t reg20 = 0x0000e132;
1430 u_int32_t reg24 = 0x00017771;
1433 case ATA_PIO0: reg20 = 0x0000e132; break;
1434 case ATA_PIO1: reg20 = 0x00018121; break;
1435 case ATA_PIO2: reg20 = 0x00024020; break;
1436 case ATA_PIO3: reg20 = 0x00032010; break;
1437 case ATA_PIO4: reg20 = 0x00040010; break;
1438 case ATA_WDMA2: reg24 = 0x00002020; break;
1439 case ATA_UDMA2: reg24 = 0x00911030; break;
1441 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20);
1442 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24);
1446 promise_timing(struct ata_device *atadev, int devno, int mode)
1448 u_int32_t timing = 0;
1449 /* XXX: Endianess */
1450 struct promise_timing {
1452 u_int8_t prefetch:1;
1463 u_int8_t reserved:8;
1464 } *t = (struct promise_timing*)&timing;
1466 t->iordy = 1; t->iordyp = 1;
1467 if (mode >= ATA_DMA) {
1468 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1471 switch (atadev->channel->chiptype) {
1472 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1475 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1476 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1477 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1478 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1479 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1480 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1481 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1485 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1486 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1487 case 0x0d30105a: /* Promise OEM ATA 100 */
1490 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1491 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1492 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1493 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1494 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1495 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1496 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1497 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1498 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1502 pci_write_config(device_get_parent(atadev->channel->dev),
1503 0x60 + (devno<<2), timing, 4);
1507 hpt_timing(struct ata_device *atadev, int devno, int mode)
1509 device_t parent = device_get_parent(atadev->channel->dev);
1510 u_int32_t chiptype = atadev->channel->chiptype;
1511 int chiprev = pci_get_revid(parent);
1514 if (chiptype == 0x00081103 && chiprev >= 0x07) {
1515 switch (mode) { /* HPT374 */
1516 case ATA_PIO0: timing = 0x0ac1f48a; break;
1517 case ATA_PIO1: timing = 0x0ac1f465; break;
1518 case ATA_PIO2: timing = 0x0a81f454; break;
1519 case ATA_PIO3: timing = 0x0a81f443; break;
1520 case ATA_PIO4: timing = 0x0a81f442; break;
1521 case ATA_WDMA2: timing = 0x22808242; break;
1522 case ATA_UDMA2: timing = 0x120c8242; break;
1523 case ATA_UDMA4: timing = 0x12ac8242; break;
1524 case ATA_UDMA5: timing = 0x12848242; break;
1525 case ATA_UDMA6: timing = 0x12808242; break;
1526 default: timing = 0x0d029d5e;
1529 else if ((chiptype == 0x00041103 && chiprev >= 0x05) ||
1530 (chiptype == 0x00051103 && chiprev >= 0x01)) {
1531 switch (mode) { /* HPT372 */
1532 case ATA_PIO0: timing = 0x0d029d5e; break;
1533 case ATA_PIO1: timing = 0x0d029d26; break;
1534 case ATA_PIO2: timing = 0x0c829ca6; break;
1535 case ATA_PIO3: timing = 0x0c829c84; break;
1536 case ATA_PIO4: timing = 0x0c829c62; break;
1537 case ATA_WDMA2: timing = 0x2c829262; break;
1538 case ATA_UDMA2: timing = 0x1c91dc62; break;
1539 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1540 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1541 case ATA_UDMA6: timing = 0x1c81dc62; break;
1542 default: timing = 0x0d029d5e;
1545 else if (chiptype == 0x00041103 && chiprev >= 0x03) {
1546 switch (mode) { /* HPT370 */
1547 case ATA_PIO0: timing = 0x06914e57; break;
1548 case ATA_PIO1: timing = 0x06914e43; break;
1549 case ATA_PIO2: timing = 0x06514e33; break;
1550 case ATA_PIO3: timing = 0x06514e22; break;
1551 case ATA_PIO4: timing = 0x06514e21; break;
1552 case ATA_WDMA2: timing = 0x26514e21; break;
1553 case ATA_UDMA2: timing = 0x16494e31; break;
1554 case ATA_UDMA4: timing = 0x16454e31; break;
1555 case ATA_UDMA5: timing = 0x16454e31; break;
1556 default: timing = 0x06514e57;
1558 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1560 else { /* HPT36[68] */
1561 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1562 case 0x85: /* 25Mhz */
1564 case ATA_PIO0: timing = 0x40d08585; break;
1565 case ATA_PIO1: timing = 0x40d08572; break;
1566 case ATA_PIO2: timing = 0x40ca8542; break;
1567 case ATA_PIO3: timing = 0x40ca8532; break;
1568 case ATA_PIO4: timing = 0x40ca8521; break;
1569 case ATA_WDMA2: timing = 0x20ca8521; break;
1570 case ATA_UDMA2: timing = 0x10cf8521; break;
1571 case ATA_UDMA4: timing = 0x10c98521; break;
1572 default: timing = 0x01208585;
1576 case 0xa7: /* 33MHz */
1578 case ATA_PIO0: timing = 0x40d0a7aa; break;
1579 case ATA_PIO1: timing = 0x40d0a7a3; break;
1580 case ATA_PIO2: timing = 0x40d0a753; break;
1581 case ATA_PIO3: timing = 0x40c8a742; break;
1582 case ATA_PIO4: timing = 0x40c8a731; break;
1583 case ATA_WDMA2: timing = 0x20c8a731; break;
1584 case ATA_UDMA2: timing = 0x10caa731; break;
1585 case ATA_UDMA4: timing = 0x10c9a731; break;
1586 default: timing = 0x0120a7a7;
1589 case 0xd9: /* 40Mhz */
1591 case ATA_PIO0: timing = 0x4018d9d9; break;
1592 case ATA_PIO1: timing = 0x4010d9c7; break;
1593 case ATA_PIO2: timing = 0x4010d997; break;
1594 case ATA_PIO3: timing = 0x4010d974; break;
1595 case ATA_PIO4: timing = 0x4008d963; break;
1596 case ATA_WDMA2: timing = 0x2008d943; break;
1597 case ATA_UDMA2: timing = 0x100bd943; break;
1598 case ATA_UDMA4: timing = 0x100fd943; break;
1599 default: timing = 0x0120d9d9;
1603 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1607 hpt_cable80(struct ata_device *atadev)
1609 device_t parent = device_get_parent(atadev->channel->dev);
1610 u_int8_t reg, val, res;
1612 if (atadev->channel->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1613 reg = atadev->channel->unit ? 0x57 : 0x53;
1614 val = pci_read_config(parent, reg, 1);
1615 pci_write_config(parent, reg, val | 0x80, 1);
1619 val = pci_read_config(parent, reg, 1);
1620 pci_write_config(parent, reg, val & 0xfe, 1);
1622 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x01 : 0x02);
1623 pci_write_config(parent, reg, val, 1);