sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 /*
  37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  38  *
  39  * Written by Bill Paul <wpaul@windriver.com>
  40  * Senior Engineer, Wind River Systems
  41  */
  42
  43 /*
  44  * The Broadcom BCM5700 is based on technology originally developed by
  45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  49  * frames, highly configurable RX filtering, and 16 RX and TX queues
  50  * (which, along with RX filter rules, can be used for QOS applications).
  51  * Other features, such as TCP segmentation, may be available as part
  52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  53  * firmware images can be stored in hardware and need not be compiled
  54  * into the driver.
  55  *
  56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  58  *
  59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  61  * does not support external SSRAM.
  62  *
  63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  64  * brand name, which is functionally similar but lacks PCI-X support.
  65  *
  66  * Without external SSRAM, you can only have at most 4 TX rings,
  67  * and the use of the mini RX ring is disabled. This seems to imply
  68  * that these features are simply not available on the BCM5701. As a
  69  * result, this driver does not implement any support for the mini RX
  70  * ring.
  71  */
  72
  73 #include "opt_polling.h"
  74
  75 #include <sys/param.h>
  76 #include <sys/bus.h>
  77 #include <sys/endian.h>
  78 #include <sys/kernel.h>
  79 #include <sys/ktr.h>
  80 #include <sys/interrupt.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99 #include <net/vlan/if_vlan_ether.h>
 100
 101 #include <dev/netif/mii_layer/mii.h>
 102 #include <dev/netif/mii_layer/miivar.h>
 103 #include <dev/netif/mii_layer/brgphyreg.h>
 104
 105 #include <bus/pci/pcidevs.h>
 106 #include <bus/pci/pcireg.h>
 107 #include <bus/pci/pcivar.h>
 108
 109 #include <dev/netif/bge/if_bgereg.h>
 110
 111 /* "device miibus" required.  See GENERIC if you get errors here. */
 112 #include "miibus_if.h"
 113
 114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 115 #define BGE_MIN_FRAME           60
 116
 117 static const struct bge_type bge_devs[] = {
 118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 119                 "3COM 3C996 Gigabit Ethernet" },
 120
 121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 122                 "Alteon BCM5700 Gigabit Ethernet" },
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 124                 "Alteon BCM5701 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 127                 "Altima AC1000 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 129                 "Altima AC1002 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 131                 "Altima AC9100 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 134                 "Apple BCM5701 Gigabit Ethernet" },
 135
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 141                 "Broadcom BCM5702 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 143                 "Broadcom BCM5702X Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 145                 "Broadcom BCM5702 Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 149                 "Broadcom BCM5703X Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 151                 "Broadcom BCM5703 Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 159                 "Broadcom BCM5705 Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 161                 "Broadcom BCM5705F Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 163                 "Broadcom BCM5705K Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 165                 "Broadcom BCM5705M Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 169                 "Broadcom BCM5714C Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 171                 "Broadcom BCM5714S Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 173                 "Broadcom BCM5715 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 175                 "Broadcom BCM5715S Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 177                 "Broadcom BCM5720 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 179                 "Broadcom BCM5721 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 181                 "Broadcom BCM5722 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
 183                 "Broadcom BCM5723 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
 215                 "Broadcom BCM5761 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
 217                 "Broadcom BCM5761E Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
 219                 "Broadcom BCM5761S Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
 221                 "Broadcom BCM5761SE Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
 223                 "Broadcom BCM5764 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 225                 "Broadcom BCM5780 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 227                 "Broadcom BCM5780S Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 229                 "Broadcom BCM5781 Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 231                 "Broadcom BCM5782 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
 233                 "Broadcom BCM5784 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
 235                 "Broadcom BCM5785F Gigabit Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
 237                 "Broadcom BCM5785G Gigabit Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 239                 "Broadcom BCM5786 Gigabit Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 241                 "Broadcom BCM5787 Gigabit Ethernet" },
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 243                 "Broadcom BCM5787F Gigabit Ethernet" },
 244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 245                 "Broadcom BCM5787M Gigabit Ethernet" },
 246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 247                 "Broadcom BCM5788 Gigabit Ethernet" },
 248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 249                 "Broadcom BCM5789 Gigabit Ethernet" },
 250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 251                 "Broadcom BCM5901 Fast Ethernet" },
 252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 253                 "Broadcom BCM5901A2 Fast Ethernet" },
 254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 255                 "Broadcom BCM5903M Fast Ethernet" },
 256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 257                 "Broadcom BCM5906 Fast Ethernet"},
 258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 259                 "Broadcom BCM5906M Fast Ethernet"},
 260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
 261                 "Broadcom BCM57760 Gigabit Ethernet"},
 262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
 263                 "Broadcom BCM57780 Gigabit Ethernet"},
 264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
 265                 "Broadcom BCM57788 Gigabit Ethernet"},
 266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
 267                 "Broadcom BCM57790 Gigabit Ethernet"},
 268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 269                 "SysKonnect Gigabit Ethernet" },
 270
 271         { 0, 0, NULL }
 272 };
 273
 274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 280
 281 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 282
 283 static int      bge_probe(device_t);
 284 static int      bge_attach(device_t);
 285 static int      bge_detach(device_t);
 286 static void     bge_txeof(struct bge_softc *);
 287 static void     bge_rxeof(struct bge_softc *);
 288
 289 static void     bge_tick(void *);
 290 static void     bge_stats_update(struct bge_softc *);
 291 static void     bge_stats_update_regs(struct bge_softc *);
 292 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 293
 294 #ifdef DEVICE_POLLING
 295 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 296 #endif
 297 static void     bge_intr(void *);
 298 static void     bge_enable_intr(struct bge_softc *);
 299 static void     bge_disable_intr(struct bge_softc *);
 300 static void     bge_start(struct ifnet *);
 301 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 302 static void     bge_init(void *);
 303 static void     bge_stop(struct bge_softc *);
 304 static void     bge_watchdog(struct ifnet *);
 305 static void     bge_shutdown(device_t);
 306 static int      bge_suspend(device_t);
 307 static int      bge_resume(device_t);
 308 static int      bge_ifmedia_upd(struct ifnet *);
 309 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 310
 311 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 312 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 313
 314 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 315 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 316
 317 static void     bge_setmulti(struct bge_softc *);
 318 static void     bge_setpromisc(struct bge_softc *);
 319
 320 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 321 static void     bge_free_jumbo_mem(struct bge_softc *);
 322 static struct bge_jslot
 323                 *bge_jalloc(struct bge_softc *);
 324 static void     bge_jfree(void *);
 325 static void     bge_jref(void *);
 326 static int      bge_newbuf_std(struct bge_softc *, int, int);
 327 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
 328 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
 329 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
 330 static int      bge_init_rx_ring_std(struct bge_softc *);
 331 static void     bge_free_rx_ring_std(struct bge_softc *);
 332 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 333 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 334 static void     bge_free_tx_ring(struct bge_softc *);
 335 static int      bge_init_tx_ring(struct bge_softc *);
 336
 337 static int      bge_chipinit(struct bge_softc *);
 338 static int      bge_blockinit(struct bge_softc *);
 339
 340 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 341 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 342 #ifdef notdef
 343 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 344 #endif
 345 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 346 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 347 static void     bge_writembx(struct bge_softc *, int, int);
 348
 349 static int      bge_miibus_readreg(device_t, int, int);
 350 static int      bge_miibus_writereg(device_t, int, int, int);
 351 static void     bge_miibus_statchg(device_t);
 352 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 353 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 354 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 355
 356 static void     bge_reset(struct bge_softc *);
 357
 358 static int      bge_dma_alloc(struct bge_softc *);
 359 static void     bge_dma_free(struct bge_softc *);
 360 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 361                                     bus_dma_tag_t *, bus_dmamap_t *,
 362                                     void **, bus_addr_t *);
 363 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 364
 365 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 366 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 367 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 368 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 369
 370 static void     bge_coal_change(struct bge_softc *);
 371 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 372 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 373 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 374 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 375 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 376
 377 /*
 378  * Set following tunable to 1 for some IBM blade servers with the DNLK
 379  * switch module. Auto negotiation is broken for those configurations.
 380  */
 381 static int      bge_fake_autoneg = 0;
 382 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 383
 384 /* Interrupt moderation control variables. */
 385 static int      bge_rx_coal_ticks = 100;        /* usec */
 386 static int      bge_tx_coal_ticks = 1023;       /* usec */
 387 static int      bge_rx_max_coal_bds = 80;
 388 static int      bge_tx_max_coal_bds = 128;
 389
 390 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 391 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 392 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 393 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 394
 395 #if !defined(KTR_IF_BGE)
 396 #define KTR_IF_BGE      KTR_ALL
 397 #endif
 398 KTR_INFO_MASTER(if_bge);
 399 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
 400 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
 401 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
 402 #define logif(name)     KTR_LOG(if_bge_ ## name)
 403
 404 static device_method_t bge_methods[] = {
 405         /* Device interface */
 406         DEVMETHOD(device_probe,         bge_probe),
 407         DEVMETHOD(device_attach,        bge_attach),
 408         DEVMETHOD(device_detach,        bge_detach),
 409         DEVMETHOD(device_shutdown,      bge_shutdown),
 410         DEVMETHOD(device_suspend,       bge_suspend),
 411         DEVMETHOD(device_resume,        bge_resume),
 412
 413         /* bus interface */
 414         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 415         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 416
 417         /* MII interface */
 418         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 419         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 420         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 421
 422         { 0, 0 }
 423 };
 424
 425 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 426 static devclass_t bge_devclass;
 427
 428 DECLARE_DUMMY_MODULE(if_bge);
 429 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
 430 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
 431
 432 static uint32_t
 433 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 434 {
 435         device_t dev = sc->bge_dev;
 436         uint32_t val;
 437
 438         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 439         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 440         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 441         return (val);
 442 }
 443
 444 static void
 445 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 446 {
 447         device_t dev = sc->bge_dev;
 448
 449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 450         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 451         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 452 }
 453
 454 #ifdef notdef
 455 static uint32_t
 456 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 457 {
 458         device_t dev = sc->bge_dev;
 459
 460         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 461         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 462 }
 463 #endif
 464
 465 static void
 466 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 467 {
 468         device_t dev = sc->bge_dev;
 469
 470         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 471         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 472 }
 473
 474 static void
 475 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 476 {
 477         CSR_WRITE_4(sc, off, val);
 478 }
 479
 480 static void
 481 bge_writembx(struct bge_softc *sc, int off, int val)
 482 {
 483         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 484                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 485
 486         CSR_WRITE_4(sc, off, val);
 487 }
 488
 489 static uint8_t
 490 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 491 {
 492         uint32_t access, byte = 0;
 493         int i;
 494
 495         /* Lock. */
 496         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 497         for (i = 0; i < 8000; i++) {
 498                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 499                         break;
 500                 DELAY(20);
 501         }
 502         if (i == 8000)
 503                 return (1);
 504
 505         /* Enable access. */
 506         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 508
 509         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 510         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 511         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 512                 DELAY(10);
 513                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 514                         DELAY(10);
 515                         break;
 516                 }
 517         }
 518
 519         if (i == BGE_TIMEOUT * 10) {
 520                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 521                 return (1);
 522         }
 523
 524         /* Get result. */
 525         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 526
 527         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 528
 529         /* Disable access. */
 530         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 531
 532         /* Unlock. */
 533         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 534         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 535
 536         return (0);
 537 }
 538
 539 /*
 540  * Read a sequence of bytes from NVRAM.
 541  */
 542 static int
 543 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 544 {
 545         int err = 0, i;
 546         uint8_t byte = 0;
 547
 548         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 549                 return (1);
 550
 551         for (i = 0; i < cnt; i++) {
 552                 err = bge_nvram_getbyte(sc, off + i, &byte);
 553                 if (err)
 554                         break;
 555                 *(dest + i) = byte;
 556         }
 557
 558         return (err ? 1 : 0);
 559 }
 560
 561 /*
 562  * Read a byte of data stored in the EEPROM at address 'addr.' The
 563  * BCM570x supports both the traditional bitbang interface and an
 564  * auto access interface for reading the EEPROM. We use the auto
 565  * access method.
 566  */
 567 static uint8_t
 568 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 569 {
 570         int i;
 571         uint32_t byte = 0;
 572
 573         /*
 574          * Enable use of auto EEPROM access so we can avoid
 575          * having to use the bitbang method.
 576          */
 577         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 578
 579         /* Reset the EEPROM, load the clock period. */
 580         CSR_WRITE_4(sc, BGE_EE_ADDR,
 581             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 582         DELAY(20);
 583
 584         /* Issue the read EEPROM command. */
 585         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 586
 587         /* Wait for completion */
 588         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 589                 DELAY(10);
 590                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 591                         break;
 592         }
 593
 594         if (i == BGE_TIMEOUT) {
 595                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 596                 return(1);
 597         }
 598
 599         /* Get result. */
 600         byte = CSR_READ_4(sc, BGE_EE_DATA);
 601
 602         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 603
 604         return(0);
 605 }
 606
 607 /*
 608  * Read a sequence of bytes from the EEPROM.
 609  */
 610 static int
 611 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 612 {
 613         size_t i;
 614         int err;
 615         uint8_t byte;
 616
 617         for (byte = 0, err = 0, i = 0; i < len; i++) {
 618                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 619                 if (err)
 620                         break;
 621                 *(dest + i) = byte;
 622         }
 623
 624         return(err ? 1 : 0);
 625 }
 626
 627 static int
 628 bge_miibus_readreg(device_t dev, int phy, int reg)
 629 {
 630         struct bge_softc *sc = device_get_softc(dev);
 631         struct ifnet *ifp = &sc->arpcom.ac_if;
 632         uint32_t val, autopoll;
 633         int i;
 634
 635         /*
 636          * Broadcom's own driver always assumes the internal
 637          * PHY is at GMII address 1. On some chips, the PHY responds
 638          * to accesses at all addresses, which could cause us to
 639          * bogusly attach the PHY 32 times at probe type. Always
 640          * restricting the lookup to address 1 is simpler than
 641          * trying to figure out which chips revisions should be
 642          * special-cased.
 643          */
 644         if (phy != 1)
 645                 return(0);
 646
 647         /* Reading with autopolling on may trigger PCI errors */
 648         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 649         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 650                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 651                 DELAY(40);
 652         }
 653
 654         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 655             BGE_MIPHY(phy)|BGE_MIREG(reg));
 656
 657         for (i = 0; i < BGE_TIMEOUT; i++) {
 658                 DELAY(10);
 659                 val = CSR_READ_4(sc, BGE_MI_COMM);
 660                 if (!(val & BGE_MICOMM_BUSY))
 661                         break;
 662         }
 663
 664         if (i == BGE_TIMEOUT) {
 665                 if_printf(ifp, "PHY read timed out "
 666                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 667                 val = 0;
 668                 goto done;
 669         }
 670
 671         DELAY(5);
 672         val = CSR_READ_4(sc, BGE_MI_COMM);
 673
 674 done:
 675         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 677                 DELAY(40);
 678         }
 679
 680         if (val & BGE_MICOMM_READFAIL)
 681                 return(0);
 682
 683         return(val & 0xFFFF);
 684 }
 685
 686 static int
 687 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 688 {
 689         struct bge_softc *sc = device_get_softc(dev);
 690         uint32_t autopoll;
 691         int i;
 692
 693         /*
 694          * See the related comment in bge_miibus_readreg()
 695          */
 696         if (phy != 1)
 697                 return(0);
 698
 699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 701                return(0);
 702
 703         /* Reading with autopolling on may trigger PCI errors */
 704         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 705         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 706                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 707                 DELAY(40);
 708         }
 709
 710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 711             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 712
 713         for (i = 0; i < BGE_TIMEOUT; i++) {
 714                 DELAY(10);
 715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 716                         DELAY(5);
 717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 718                         break;
 719                 }
 720         }
 721
 722         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 723                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 724                 DELAY(40);
 725         }
 726
 727         if (i == BGE_TIMEOUT) {
 728                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 729                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 730                 return(0);
 731         }
 732
 733         return(0);
 734 }
 735
 736 static void
 737 bge_miibus_statchg(device_t dev)
 738 {
 739         struct bge_softc *sc;
 740         struct mii_data *mii;
 741
 742         sc = device_get_softc(dev);
 743         mii = device_get_softc(sc->bge_miibus);
 744
 745         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 746         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 747             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 748                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 749         } else {
 750                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 751         }
 752
 753         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 754                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 755         } else {
 756                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 757         }
 758 }
 759
 760 /*
 761  * Memory management for jumbo frames.
 762  */
 763 static int
 764 bge_alloc_jumbo_mem(struct bge_softc *sc)
 765 {
 766         struct ifnet *ifp = &sc->arpcom.ac_if;
 767         struct bge_jslot *entry;
 768         uint8_t *ptr;
 769         bus_addr_t paddr;
 770         int i, error;
 771
 772         /*
 773          * Create tag for jumbo mbufs.
 774          * This is really a bit of a kludge. We allocate a special
 775          * jumbo buffer pool which (thanks to the way our DMA
 776          * memory allocation works) will consist of contiguous
 777          * pages. This means that even though a jumbo buffer might
 778          * be larger than a page size, we don't really need to
 779          * map it into more than one DMA segment. However, the
 780          * default mbuf tag will result in multi-segment mappings,
 781          * so we have to create a special jumbo mbuf tag that
 782          * lets us get away with mapping the jumbo buffers as
 783          * a single segment. I think eventually the driver should
 784          * be changed so that it uses ordinary mbufs and cluster
 785          * buffers, i.e. jumbo frames can span multiple DMA
 786          * descriptors. But that's a project for another day.
 787          */
 788
 789         /*
 790          * Create DMA stuffs for jumbo RX ring.
 791          */
 792         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 793                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 794                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 795                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
 796                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 797         if (error) {
 798                 if_printf(ifp, "could not create jumbo RX ring\n");
 799                 return error;
 800         }
 801
 802         /*
 803          * Create DMA stuffs for jumbo buffer block.
 804          */
 805         error = bge_dma_block_alloc(sc, BGE_JMEM,
 806                                     &sc->bge_cdata.bge_jumbo_tag,
 807                                     &sc->bge_cdata.bge_jumbo_map,
 808                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 809                                     &paddr);
 810         if (error) {
 811                 if_printf(ifp, "could not create jumbo buffer\n");
 812                 return error;
 813         }
 814
 815         SLIST_INIT(&sc->bge_jfree_listhead);
 816
 817         /*
 818          * Now divide it up into 9K pieces and save the addresses
 819          * in an array. Note that we play an evil trick here by using
 820          * the first few bytes in the buffer to hold the the address
 821          * of the softc structure for this interface. This is because
 822          * bge_jfree() needs it, but it is called by the mbuf management
 823          * code which will not pass it to us explicitly.
 824          */
 825         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 826                 entry = &sc->bge_cdata.bge_jslots[i];
 827                 entry->bge_sc = sc;
 828                 entry->bge_buf = ptr;
 829                 entry->bge_paddr = paddr;
 830                 entry->bge_inuse = 0;
 831                 entry->bge_slot = i;
 832                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 833
 834                 ptr += BGE_JLEN;
 835                 paddr += BGE_JLEN;
 836         }
 837         return 0;
 838 }
 839
 840 static void
 841 bge_free_jumbo_mem(struct bge_softc *sc)
 842 {
 843         /* Destroy jumbo RX ring. */
 844         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 845                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 846                            sc->bge_ldata.bge_rx_jumbo_ring);
 847
 848         /* Destroy jumbo buffer block. */
 849         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 850                            sc->bge_cdata.bge_jumbo_map,
 851                            sc->bge_ldata.bge_jumbo_buf);
 852 }
 853
 854 /*
 855  * Allocate a jumbo buffer.
 856  */
 857 static struct bge_jslot *
 858 bge_jalloc(struct bge_softc *sc)
 859 {
 860         struct bge_jslot *entry;
 861
 862         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 863         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 864         if (entry) {
 865                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 866                 entry->bge_inuse = 1;
 867         } else {
 868                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 869         }
 870         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 871         return(entry);
 872 }
 873
 874 /*
 875  * Adjust usage count on a jumbo buffer.
 876  */
 877 static void
 878 bge_jref(void *arg)
 879 {
 880         struct bge_jslot *entry = (struct bge_jslot *)arg;
 881         struct bge_softc *sc = entry->bge_sc;
 882
 883         if (sc == NULL)
 884                 panic("bge_jref: can't find softc pointer!");
 885
 886         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 887                 panic("bge_jref: asked to reference buffer "
 888                     "that we don't manage!");
 889         } else if (entry->bge_inuse == 0) {
 890                 panic("bge_jref: buffer already free!");
 891         } else {
 892                 atomic_add_int(&entry->bge_inuse, 1);
 893         }
 894 }
 895
 896 /*
 897  * Release a jumbo buffer.
 898  */
 899 static void
 900 bge_jfree(void *arg)
 901 {
 902         struct bge_jslot *entry = (struct bge_jslot *)arg;
 903         struct bge_softc *sc = entry->bge_sc;
 904
 905         if (sc == NULL)
 906                 panic("bge_jfree: can't find softc pointer!");
 907
 908         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 909                 panic("bge_jfree: asked to free buffer that we don't manage!");
 910         } else if (entry->bge_inuse == 0) {
 911                 panic("bge_jfree: buffer already free!");
 912         } else {
 913                 /*
 914                  * Possible MP race to 0, use the serializer.  The atomic insn
 915                  * is still needed for races against bge_jref().
 916                  */
 917                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 918                 atomic_subtract_int(&entry->bge_inuse, 1);
 919                 if (entry->bge_inuse == 0) {
 920                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 921                                           entry, jslot_link);
 922                 }
 923                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 924         }
 925 }
 926
 927
 928 /*
 929  * Intialize a standard receive ring descriptor.
 930  */
 931 static int
 932 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 933 {
 934         struct mbuf *m_new = NULL;
 935         bus_dma_segment_t seg;
 936         bus_dmamap_t map;
 937         int error, nsegs;
 938
 939         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 940         if (m_new == NULL)
 941                 return ENOBUFS;
 942         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 943
 944         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 945                 m_adj(m_new, ETHER_ALIGN);
 946
 947         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 948                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 949                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 950         if (error) {
 951                 m_freem(m_new);
 952                 return error;
 953         }
 954
 955         if (!init) {
 956                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 957                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 958                                 BUS_DMASYNC_POSTREAD);
 959                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 960                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 961         }
 962
 963         map = sc->bge_cdata.bge_rx_tmpmap;
 964         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 965         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 966
 967         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 968         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 969
 970         bge_setup_rxdesc_std(sc, i);
 971         return 0;
 972 }
 973
 974 static void
 975 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 976 {
 977         struct bge_rxchain *rc;
 978         struct bge_rx_bd *r;
 979
 980         rc = &sc->bge_cdata.bge_rx_std_chain[i];
 981         r = &sc->bge_ldata.bge_rx_std_ring[i];
 982
 983         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
 984         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
 985         r->bge_len = rc->bge_mbuf->m_len;
 986         r->bge_idx = i;
 987         r->bge_flags = BGE_RXBDFLAG_END;
 988 }
 989
 990 /*
 991  * Initialize a jumbo receive ring descriptor. This allocates
 992  * a jumbo buffer from the pool managed internally by the driver.
 993  */
 994 static int
 995 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
 996 {
 997         struct mbuf *m_new = NULL;
 998         struct bge_jslot *buf;
 999         bus_addr_t paddr;
1000
1001         /* Allocate the mbuf. */
1002         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1003         if (m_new == NULL)
1004                 return ENOBUFS;
1005
1006         /* Allocate the jumbo buffer */
1007         buf = bge_jalloc(sc);
1008         if (buf == NULL) {
1009                 m_freem(m_new);
1010                 return ENOBUFS;
1011         }
1012
1013         /* Attach the buffer to the mbuf. */
1014         m_new->m_ext.ext_arg = buf;
1015         m_new->m_ext.ext_buf = buf->bge_buf;
1016         m_new->m_ext.ext_free = bge_jfree;
1017         m_new->m_ext.ext_ref = bge_jref;
1018         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1019
1020         m_new->m_flags |= M_EXT;
1021
1022         m_new->m_data = m_new->m_ext.ext_buf;
1023         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1024
1025         paddr = buf->bge_paddr;
1026         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1027                 m_adj(m_new, ETHER_ALIGN);
1028                 paddr += ETHER_ALIGN;
1029         }
1030
1031         /* Save necessary information */
1032         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1033         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1034
1035         /* Set up the descriptor. */
1036         bge_setup_rxdesc_jumbo(sc, i);
1037         return 0;
1038 }
1039
1040 static void
1041 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1042 {
1043         struct bge_rx_bd *r;
1044         struct bge_rxchain *rc;
1045
1046         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1047         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1048
1049         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1050         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1051         r->bge_len = rc->bge_mbuf->m_len;
1052         r->bge_idx = i;
1053         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1054 }
1055
1056 static int
1057 bge_init_rx_ring_std(struct bge_softc *sc)
1058 {
1059         int i, error;
1060
1061         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1062                 error = bge_newbuf_std(sc, i, 1);
1063                 if (error)
1064                         return error;
1065         };
1066
1067         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1068         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1069
1070         return(0);
1071 }
1072
1073 static void
1074 bge_free_rx_ring_std(struct bge_softc *sc)
1075 {
1076         int i;
1077
1078         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1079                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1080
1081                 if (rc->bge_mbuf != NULL) {
1082                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1083                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1084                         m_freem(rc->bge_mbuf);
1085                         rc->bge_mbuf = NULL;
1086                 }
1087                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1088                     sizeof(struct bge_rx_bd));
1089         }
1090 }
1091
1092 static int
1093 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1094 {
1095         struct bge_rcb *rcb;
1096         int i, error;
1097
1098         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1099                 error = bge_newbuf_jumbo(sc, i, 1);
1100                 if (error)
1101                         return error;
1102         };
1103
1104         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1105
1106         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1107         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1108         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1109
1110         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1111
1112         return(0);
1113 }
1114
1115 static void
1116 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1117 {
1118         int i;
1119
1120         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1121                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1122
1123                 if (rc->bge_mbuf != NULL) {
1124                         m_freem(rc->bge_mbuf);
1125                         rc->bge_mbuf = NULL;
1126                 }
1127                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1128                     sizeof(struct bge_rx_bd));
1129         }
1130 }
1131
1132 static void
1133 bge_free_tx_ring(struct bge_softc *sc)
1134 {
1135         int i;
1136
1137         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1138                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1139                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1140                                           sc->bge_cdata.bge_tx_dmamap[i]);
1141                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1142                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1143                 }
1144                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1145                     sizeof(struct bge_tx_bd));
1146         }
1147 }
1148
1149 static int
1150 bge_init_tx_ring(struct bge_softc *sc)
1151 {
1152         sc->bge_txcnt = 0;
1153         sc->bge_tx_saved_considx = 0;
1154         sc->bge_tx_prodidx = 0;
1155
1156         /* Initialize transmit producer index for host-memory send ring. */
1157         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1158
1159         /* 5700 b2 errata */
1160         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1161                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1162
1163         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1164         /* 5700 b2 errata */
1165         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1166                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1167
1168         return(0);
1169 }
1170
1171 static void
1172 bge_setmulti(struct bge_softc *sc)
1173 {
1174         struct ifnet *ifp;
1175         struct ifmultiaddr *ifma;
1176         uint32_t hashes[4] = { 0, 0, 0, 0 };
1177         int h, i;
1178
1179         ifp = &sc->arpcom.ac_if;
1180
1181         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1182                 for (i = 0; i < 4; i++)
1183                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1184                 return;
1185         }
1186
1187         /* First, zot all the existing filters. */
1188         for (i = 0; i < 4; i++)
1189                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1190
1191         /* Now program new ones. */
1192         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1193                 if (ifma->ifma_addr->sa_family != AF_LINK)
1194                         continue;
1195                 h = ether_crc32_le(
1196                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1197                     ETHER_ADDR_LEN) & 0x7f;
1198                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1199         }
1200
1201         for (i = 0; i < 4; i++)
1202                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1203 }
1204
1205 /*
1206  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1207  * self-test results.
1208  */
1209 static int
1210 bge_chipinit(struct bge_softc *sc)
1211 {
1212         int i;
1213         uint32_t dma_rw_ctl;
1214         uint16_t val;
1215
1216         /* Set endian type before we access any non-PCI registers. */
1217         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1218
1219         /* Clear the MAC control register */
1220         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1221
1222         /*
1223          * Clear the MAC statistics block in the NIC's
1224          * internal memory.
1225          */
1226         for (i = BGE_STATS_BLOCK;
1227             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1228                 BGE_MEMWIN_WRITE(sc, i, 0);
1229
1230         for (i = BGE_STATUS_BLOCK;
1231             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1232                 BGE_MEMWIN_WRITE(sc, i, 0);
1233
1234         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1235                 /*
1236                  * Fix data corruption caused by non-qword write with WB.
1237                  * Fix master abort in PCI mode.
1238                  * Fix PCI latency timer.
1239                  */
1240                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1241                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1242                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1243         }
1244
1245         /* Set up the PCI DMA control register. */
1246         if (sc->bge_flags & BGE_FLAG_PCIE) {
1247                 /* PCI Express */
1248                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1249                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1250                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1251         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1252                 /* PCI-X bus */
1253                 if (BGE_IS_5714_FAMILY(sc)) {
1254                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1255                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1256                         /* XXX magic values, Broadcom-supplied Linux driver */
1257                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1258                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1259                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1260                         } else {
1261                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1262                         }
1263                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1264                         /*
1265                          * In the BCM5703, the DMA read watermark should
1266                          * be set to less than or equal to the maximum
1267                          * memory read byte count of the PCI-X command
1268                          * register.
1269                          */
1270                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1271                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1272                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1273                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1274                         /*
1275                          * The 5704 uses a different encoding of read/write
1276                          * watermarks.
1277                          */
1278                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1279                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1280                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1281                 } else {
1282                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1283                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1284                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1285                             (0x0F);
1286                 }
1287
1288                 /*
1289                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1290                  * for hardware bugs.
1291                  */
1292                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1293                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1294                         uint32_t tmp;
1295
1296                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1297                         if (tmp == 0x6 || tmp == 0x7)
1298                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1299                 }
1300         } else {
1301                 /* Conventional PCI bus */
1302                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1303                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1304                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1305                     (0x0F);
1306         }
1307
1308         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1309             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1310             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1311                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1312         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1313
1314         /*
1315          * Set up general mode register.
1316          */
1317         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1318             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1319             BGE_MODECTL_TX_NO_PHDR_CSUM);
1320
1321         /*
1322          * BCM5701 B5 have a bug causing data corruption when using
1323          * 64-bit DMA reads, which can be terminated early and then
1324          * completed later as 32-bit accesses, in combination with
1325          * certain bridges.
1326          */
1327         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1328             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1329                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1330
1331         /*
1332          * Disable memory write invalidate.  Apparently it is not supported
1333          * properly by these devices.
1334          */
1335         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1336
1337         /* Set the timer prescaler (always 66Mhz) */
1338         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1339
1340         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1341                 DELAY(40);      /* XXX */
1342
1343                 /* Put PHY into ready state */
1344                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1345                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1346                 DELAY(40);
1347         }
1348
1349         return(0);
1350 }
1351
1352 static int
1353 bge_blockinit(struct bge_softc *sc)
1354 {
1355         struct bge_rcb *rcb;
1356         bus_size_t vrcb;
1357         bge_hostaddr taddr;
1358         uint32_t val;
1359         int i;
1360
1361         /*
1362          * Initialize the memory window pointer register so that
1363          * we can access the first 32K of internal NIC RAM. This will
1364          * allow us to set up the TX send ring RCBs and the RX return
1365          * ring RCBs, plus other things which live in NIC memory.
1366          */
1367         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1368
1369         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1370
1371         if (!BGE_IS_5705_PLUS(sc)) {
1372                 /* Configure mbuf memory pool */
1373                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1374                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1375                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1376                 else
1377                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1378
1379                 /* Configure DMA resource pool */
1380                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1381                     BGE_DMA_DESCRIPTORS);
1382                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1383         }
1384
1385         /* Configure mbuf pool watermarks */
1386         if (!BGE_IS_5705_PLUS(sc)) {
1387                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1388                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1389                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1390         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1391                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1392                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1393                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1394         } else {
1395                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1396                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1397                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1398         }
1399
1400         /* Configure DMA resource watermarks */
1401         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1402         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1403
1404         /* Enable buffer manager */
1405         if (!BGE_IS_5705_PLUS(sc)) {
1406                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1407                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1408
1409                 /* Poll for buffer manager start indication */
1410                 for (i = 0; i < BGE_TIMEOUT; i++) {
1411                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1412                                 break;
1413                         DELAY(10);
1414                 }
1415
1416                 if (i == BGE_TIMEOUT) {
1417                         if_printf(&sc->arpcom.ac_if,
1418                                   "buffer manager failed to start\n");
1419                         return(ENXIO);
1420                 }
1421         }
1422
1423         /* Enable flow-through queues */
1424         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1425         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1426
1427         /* Wait until queue initialization is complete */
1428         for (i = 0; i < BGE_TIMEOUT; i++) {
1429                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1430                         break;
1431                 DELAY(10);
1432         }
1433
1434         if (i == BGE_TIMEOUT) {
1435                 if_printf(&sc->arpcom.ac_if,
1436                           "flow-through queue init failed\n");
1437                 return(ENXIO);
1438         }
1439
1440         /* Initialize the standard RX ring control block */
1441         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1442         rcb->bge_hostaddr.bge_addr_lo =
1443             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1444         rcb->bge_hostaddr.bge_addr_hi =
1445             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1446         if (BGE_IS_5705_PLUS(sc))
1447                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1448         else
1449                 rcb->bge_maxlen_flags =
1450                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1451         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1452         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1453         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1454         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1455         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1456
1457         /*
1458          * Initialize the jumbo RX ring control block
1459          * We set the 'ring disabled' bit in the flags
1460          * field until we're actually ready to start
1461          * using this ring (i.e. once we set the MTU
1462          * high enough to require it).
1463          */
1464         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1465                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1466
1467                 rcb->bge_hostaddr.bge_addr_lo =
1468                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1469                 rcb->bge_hostaddr.bge_addr_hi =
1470                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1471                 rcb->bge_maxlen_flags =
1472                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1473                     BGE_RCB_FLAG_RING_DISABLED);
1474                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1475                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1476                     rcb->bge_hostaddr.bge_addr_hi);
1477                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1478                     rcb->bge_hostaddr.bge_addr_lo);
1479                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1480                     rcb->bge_maxlen_flags);
1481                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1482
1483                 /* Set up dummy disabled mini ring RCB */
1484                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1485                 rcb->bge_maxlen_flags =
1486                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1487                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1488                     rcb->bge_maxlen_flags);
1489         }
1490
1491         /*
1492          * Set the BD ring replentish thresholds. The recommended
1493          * values are 1/8th the number of descriptors allocated to
1494          * each ring.
1495          */
1496         if (BGE_IS_5705_PLUS(sc))
1497                 val = 8;
1498         else
1499                 val = BGE_STD_RX_RING_CNT / 8;
1500         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1501         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1502                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1503                     BGE_JUMBO_RX_RING_CNT/8);
1504         }
1505
1506         /*
1507          * Disable all unused send rings by setting the 'ring disabled'
1508          * bit in the flags field of all the TX send ring control blocks.
1509          * These are located in NIC memory.
1510          */
1511         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1512         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1513                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1514                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1515                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1516                 vrcb += sizeof(struct bge_rcb);
1517         }
1518
1519         /* Configure TX RCB 0 (we use only the first ring) */
1520         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1521         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1522         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1523         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1524         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1525             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1526         if (!BGE_IS_5705_PLUS(sc)) {
1527                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1528                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1529         }
1530
1531         /* Disable all unused RX return rings */
1532         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1533         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1534                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1535                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1536                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1537                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1538                     BGE_RCB_FLAG_RING_DISABLED));
1539                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1540                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1541                     (i * (sizeof(uint64_t))), 0);
1542                 vrcb += sizeof(struct bge_rcb);
1543         }
1544
1545         /* Initialize RX ring indexes */
1546         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1547         if (BGE_IS_JUMBO_CAPABLE(sc))
1548                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1549         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1550
1551         /*
1552          * Set up RX return ring 0
1553          * Note that the NIC address for RX return rings is 0x00000000.
1554          * The return rings live entirely within the host, so the
1555          * nicaddr field in the RCB isn't used.
1556          */
1557         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1558         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1559         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1560         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1561         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1562         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1563             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1564
1565         /* Set random backoff seed for TX */
1566         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1567             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1568             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1569             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1570             BGE_TX_BACKOFF_SEED_MASK);
1571
1572         /* Set inter-packet gap */
1573         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1574
1575         /*
1576          * Specify which ring to use for packets that don't match
1577          * any RX rules.
1578          */
1579         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1580
1581         /*
1582          * Configure number of RX lists. One interrupt distribution
1583          * list, sixteen active lists, one bad frames class.
1584          */
1585         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1586
1587         /* Inialize RX list placement stats mask. */
1588         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1589         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1590
1591         /* Disable host coalescing until we get it set up */
1592         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1593
1594         /* Poll to make sure it's shut down. */
1595         for (i = 0; i < BGE_TIMEOUT; i++) {
1596                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1597                         break;
1598                 DELAY(10);
1599         }
1600
1601         if (i == BGE_TIMEOUT) {
1602                 if_printf(&sc->arpcom.ac_if,
1603                           "host coalescing engine failed to idle\n");
1604                 return(ENXIO);
1605         }
1606
1607         /* Set up host coalescing defaults */
1608         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1609         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1610         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1611         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1612         if (!BGE_IS_5705_PLUS(sc)) {
1613                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1614                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1615         }
1616         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1617         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1618
1619         /* Set up address of statistics block */
1620         if (!BGE_IS_5705_PLUS(sc)) {
1621                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1622                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1623                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1624                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1625
1626                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1627                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1628                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1629         }
1630
1631         /* Set up address of status block */
1632         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1633             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1634         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1635             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1636         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1637         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1638
1639         /*
1640          * Set up status block partail update size.
1641          *
1642          * Because only single TX ring, RX produce ring and Rx return ring
1643          * are used, ask device to update only minimum part of status block
1644          * except for BCM5700 AX/BX, whose status block partial update size
1645          * can't be configured.
1646          */
1647         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1648             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1649                 /* XXX Actually reserved on BCM5700 AX/BX */
1650                 val = BGE_STATBLKSZ_FULL;
1651         } else {
1652                 val = BGE_STATBLKSZ_32BYTE;
1653         }
1654
1655         /* Turn on host coalescing state machine */
1656         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1657
1658         /* Turn on RX BD completion state machine and enable attentions */
1659         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1660             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1661
1662         /* Turn on RX list placement state machine */
1663         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1664
1665         /* Turn on RX list selector state machine. */
1666         if (!BGE_IS_5705_PLUS(sc))
1667                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1668
1669         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1670             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1671             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1672             BGE_MACMODE_FRMHDR_DMA_ENB;
1673
1674         if (sc->bge_flags & BGE_FLAG_TBI)
1675                 val |= BGE_PORTMODE_TBI;
1676         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1677                 val |= BGE_PORTMODE_GMII;
1678         else
1679                 val |= BGE_PORTMODE_MII;
1680
1681         /* Turn on DMA, clear stats */
1682         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1683
1684         /* Set misc. local control, enable interrupts on attentions */
1685         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1686
1687 #ifdef notdef
1688         /* Assert GPIO pins for PHY reset */
1689         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1690             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1691         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1692             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1693 #endif
1694
1695         /* Turn on DMA completion state machine */
1696         if (!BGE_IS_5705_PLUS(sc))
1697                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1698
1699         /* Turn on write DMA state machine */
1700         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1701         if (BGE_IS_5755_PLUS(sc)) {
1702                 /* Enable host coalescing bug fix. */
1703                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1704         }
1705         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1706         DELAY(40);
1707
1708         /* Turn on read DMA state machine */
1709         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1710         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1711             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1712             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1713                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1714                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1715                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1716         if (sc->bge_flags & BGE_FLAG_PCIE)
1717                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1718         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1719         DELAY(40);
1720
1721         /* Turn on RX data completion state machine */
1722         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1723
1724         /* Turn on RX BD initiator state machine */
1725         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1726
1727         /* Turn on RX data and RX BD initiator state machine */
1728         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1729
1730         /* Turn on Mbuf cluster free state machine */
1731         if (!BGE_IS_5705_PLUS(sc))
1732                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1733
1734         /* Turn on send BD completion state machine */
1735         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1736
1737         /* Turn on send data completion state machine */
1738         val = BGE_SDCMODE_ENABLE;
1739         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1740                 val |= BGE_SDCMODE_CDELAY;
1741         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1742
1743         /* Turn on send data initiator state machine */
1744         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1745
1746         /* Turn on send BD initiator state machine */
1747         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1748
1749         /* Turn on send BD selector state machine */
1750         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1751
1752         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1753         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1754             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1755
1756         /* ack/clear link change events */
1757         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1758             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1759             BGE_MACSTAT_LINK_CHANGED);
1760         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1761
1762         /* Enable PHY auto polling (for MII/GMII only) */
1763         if (sc->bge_flags & BGE_FLAG_TBI) {
1764                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1765         } else {
1766                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1767                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1768                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1769                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1770                             BGE_EVTENB_MI_INTERRUPT);
1771                 }
1772         }
1773
1774         /*
1775          * Clear any pending link state attention.
1776          * Otherwise some link state change events may be lost until attention
1777          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1778          * It's not necessary on newer BCM chips - perhaps enabling link
1779          * state change attentions implies clearing pending attention.
1780          */
1781         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1782             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1783             BGE_MACSTAT_LINK_CHANGED);
1784
1785         /* Enable link state change attentions. */
1786         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1787
1788         return(0);
1789 }
1790
1791 /*
1792  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1793  * against our list and return its name if we find a match. Note
1794  * that since the Broadcom controller contains VPD support, we
1795  * can get the device name string from the controller itself instead
1796  * of the compiled-in string. This is a little slow, but it guarantees
1797  * we'll always announce the right product name.
1798  */
1799 static int
1800 bge_probe(device_t dev)
1801 {
1802         const struct bge_type *t;
1803         uint16_t product, vendor;
1804
1805         product = pci_get_device(dev);
1806         vendor = pci_get_vendor(dev);
1807
1808         for (t = bge_devs; t->bge_name != NULL; t++) {
1809                 if (vendor == t->bge_vid && product == t->bge_did)
1810                         break;
1811         }
1812         if (t->bge_name == NULL)
1813                 return(ENXIO);
1814
1815         device_set_desc(dev, t->bge_name);
1816         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1817                 struct bge_softc *sc = device_get_softc(dev);
1818                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1819         }
1820         return(0);
1821 }
1822
1823 static int
1824 bge_attach(device_t dev)
1825 {
1826         struct ifnet *ifp;
1827         struct bge_softc *sc;
1828         uint32_t hwcfg = 0;
1829         int error = 0, rid;
1830         uint8_t ether_addr[ETHER_ADDR_LEN];
1831
1832         sc = device_get_softc(dev);
1833         sc->bge_dev = dev;
1834         callout_init(&sc->bge_stat_timer);
1835         lwkt_serialize_init(&sc->bge_jslot_serializer);
1836
1837 #ifndef BURN_BRIDGES
1838         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1839                 uint32_t irq, mem;
1840
1841                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1842                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1843
1844                 device_printf(dev, "chip is in D%d power mode "
1845                     "-- setting to D0\n", pci_get_powerstate(dev));
1846
1847                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1848
1849                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1850                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1851         }
1852 #endif  /* !BURN_BRIDGE */
1853
1854         /*
1855          * Map control/status registers.
1856          */
1857         pci_enable_busmaster(dev);
1858
1859         rid = BGE_PCI_BAR0;
1860         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1861             RF_ACTIVE);
1862
1863         if (sc->bge_res == NULL) {
1864                 device_printf(dev, "couldn't map memory\n");
1865                 return ENXIO;
1866         }
1867
1868         sc->bge_btag = rman_get_bustag(sc->bge_res);
1869         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1870
1871         /* Save various chip information */
1872         sc->bge_chipid =
1873             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1874             BGE_PCIMISCCTL_ASICREV_SHIFT;
1875         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1876                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1877         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1878         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1879
1880         /* Save chipset family. */
1881         switch (sc->bge_asicrev) {
1882         case BGE_ASICREV_BCM5755:
1883         case BGE_ASICREV_BCM5761:
1884         case BGE_ASICREV_BCM5784:
1885         case BGE_ASICREV_BCM5785:
1886         case BGE_ASICREV_BCM5787:
1887         case BGE_ASICREV_BCM57780:
1888             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1889                 BGE_FLAG_5705_PLUS;
1890             break;
1891
1892         case BGE_ASICREV_BCM5700:
1893         case BGE_ASICREV_BCM5701:
1894         case BGE_ASICREV_BCM5703:
1895         case BGE_ASICREV_BCM5704:
1896                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1897                 break;
1898
1899         case BGE_ASICREV_BCM5714_A0:
1900         case BGE_ASICREV_BCM5780:
1901         case BGE_ASICREV_BCM5714:
1902                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1903                 /* Fall through */
1904
1905         case BGE_ASICREV_BCM5750:
1906         case BGE_ASICREV_BCM5752:
1907         case BGE_ASICREV_BCM5906:
1908                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1909                 /* Fall through */
1910
1911         case BGE_ASICREV_BCM5705:
1912                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1913                 break;
1914         }
1915
1916         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1917                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1918
1919         /*
1920          * Set various quirk flags.
1921          */
1922
1923         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1924         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1925             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1926              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1927               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1928             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1929                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1930
1931         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1932             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1933                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1934
1935         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1936             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1937                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1938
1939         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1940                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1941
1942         if (BGE_IS_5705_PLUS(sc)) {
1943                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1944                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1945                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1946                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1947                         uint32_t product = pci_get_device(dev);
1948
1949                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1950                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1951                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1952                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1953                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1954                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1955                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1956                 }
1957         }
1958
1959         /* Allocate interrupt */
1960         rid = 0;
1961
1962         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1963             RF_SHAREABLE | RF_ACTIVE);
1964
1965         if (sc->bge_irq == NULL) {
1966                 device_printf(dev, "couldn't map interrupt\n");
1967                 error = ENXIO;
1968                 goto fail;
1969         }
1970
1971         /*
1972          * Check if this is a PCI-X or PCI Express device.
1973          */
1974         if (BGE_IS_5705_PLUS(sc)) {
1975                 if (pci_is_pcie(dev)) {
1976                         sc->bge_flags |= BGE_FLAG_PCIE;
1977                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1978                 }
1979         } else {
1980                 /*
1981                  * Check if the device is in PCI-X Mode.
1982                  * (This bit is not valid on PCI Express controllers.)
1983                  */
1984                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1985                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
1986                         sc->bge_flags |= BGE_FLAG_PCIX;
1987                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
1988                 }
1989         }
1990
1991         device_printf(dev, "CHIP ID 0x%08x; "
1992                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1993                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1994                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1995                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1996                         "PCI-E" : "PCI"));
1997
1998         /*
1999          * All controllers that are not 5755 or higher have 4GB
2000          * boundary DMA bug.
2001          * Whenever an address crosses a multiple of the 4GB boundary
2002          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2003          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2004          * state machine will lockup and cause the device to hang.
2005          */
2006         if (BGE_IS_5755_PLUS(sc) == 0)
2007                 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
2008
2009         /*
2010          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2011          * not actually a MAC controller bug but an issue with the embedded
2012          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2013          */
2014         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2015                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2016
2017         ifp = &sc->arpcom.ac_if;
2018         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2019
2020         /* Try to reset the chip. */
2021         bge_reset(sc);
2022
2023         if (bge_chipinit(sc)) {
2024                 device_printf(dev, "chip initialization failed\n");
2025                 error = ENXIO;
2026                 goto fail;
2027         }
2028
2029         /*
2030          * Get station address
2031          */
2032         error = bge_get_eaddr(sc, ether_addr);
2033         if (error) {
2034                 device_printf(dev, "failed to read station address\n");
2035                 goto fail;
2036         }
2037
2038         /* 5705/5750 limits RX return ring to 512 entries. */
2039         if (BGE_IS_5705_PLUS(sc))
2040                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2041         else
2042                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2043
2044         error = bge_dma_alloc(sc);
2045         if (error)
2046                 goto fail;
2047
2048         /* Set default tuneable values. */
2049         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2050         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2051         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2052         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2053         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2054
2055         /* Set up ifnet structure */
2056         ifp->if_softc = sc;
2057         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2058         ifp->if_ioctl = bge_ioctl;
2059         ifp->if_start = bge_start;
2060 #ifdef DEVICE_POLLING
2061         ifp->if_poll = bge_poll;
2062 #endif
2063         ifp->if_watchdog = bge_watchdog;
2064         ifp->if_init = bge_init;
2065         ifp->if_mtu = ETHERMTU;
2066         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2067         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2068         ifq_set_ready(&ifp->if_snd);
2069
2070         /*
2071          * 5700 B0 chips do not support checksumming correctly due
2072          * to hardware bugs.
2073          */
2074         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2075                 ifp->if_capabilities |= IFCAP_HWCSUM;
2076                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2077         }
2078         ifp->if_capenable = ifp->if_capabilities;
2079
2080         /*
2081          * Figure out what sort of media we have by checking the
2082          * hardware config word in the first 32k of NIC internal memory,
2083          * or fall back to examining the EEPROM if necessary.
2084          * Note: on some BCM5700 cards, this value appears to be unset.
2085          * If that's the case, we have to rely on identifying the NIC
2086          * by its PCI subsystem ID, as we do below for the SysKonnect
2087          * SK-9D41.
2088          */
2089         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2090                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2091         else {
2092                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2093                                     sizeof(hwcfg))) {
2094                         device_printf(dev, "failed to read EEPROM\n");
2095                         error = ENXIO;
2096                         goto fail;
2097                 }
2098                 hwcfg = ntohl(hwcfg);
2099         }
2100
2101         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2102         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2103             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2104                 if (BGE_IS_5714_FAMILY(sc))
2105                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2106                 else
2107                         sc->bge_flags |= BGE_FLAG_TBI;
2108         }
2109
2110         if (sc->bge_flags & BGE_FLAG_TBI) {
2111                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2112                     bge_ifmedia_upd, bge_ifmedia_sts);
2113                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2114                 ifmedia_add(&sc->bge_ifmedia,
2115                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2116                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2117                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2118                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2119         } else {
2120                 /*
2121                  * Do transceiver setup.
2122                  */
2123                 if (mii_phy_probe(dev, &sc->bge_miibus,
2124                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2125                         device_printf(dev, "MII without any PHY!\n");
2126                         error = ENXIO;
2127                         goto fail;
2128                 }
2129         }
2130
2131         /*
2132          * When using the BCM5701 in PCI-X mode, data corruption has
2133          * been observed in the first few bytes of some received packets.
2134          * Aligning the packet buffer in memory eliminates the corruption.
2135          * Unfortunately, this misaligns the packet payloads.  On platforms
2136          * which do not support unaligned accesses, we will realign the
2137          * payloads by copying the received packets.
2138          */
2139         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2140             (sc->bge_flags & BGE_FLAG_PCIX))
2141                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2142
2143         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2144             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2145                 sc->bge_link_upd = bge_bcm5700_link_upd;
2146                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2147         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2148                 sc->bge_link_upd = bge_tbi_link_upd;
2149                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2150         } else {
2151                 sc->bge_link_upd = bge_copper_link_upd;
2152                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2153         }
2154
2155         /*
2156          * Create sysctl nodes.
2157          */
2158         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2159         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2160                                               SYSCTL_STATIC_CHILDREN(_hw),
2161                                               OID_AUTO,
2162                                               device_get_nameunit(dev),
2163                                               CTLFLAG_RD, 0, "");
2164         if (sc->bge_sysctl_tree == NULL) {
2165                 device_printf(dev, "can't add sysctl node\n");
2166                 error = ENXIO;
2167                 goto fail;
2168         }
2169
2170         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2171                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2172                         OID_AUTO, "rx_coal_ticks",
2173                         CTLTYPE_INT | CTLFLAG_RW,
2174                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2175                         "Receive coalescing ticks (usec).");
2176         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2177                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2178                         OID_AUTO, "tx_coal_ticks",
2179                         CTLTYPE_INT | CTLFLAG_RW,
2180                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2181                         "Transmit coalescing ticks (usec).");
2182         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2183                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2184                         OID_AUTO, "rx_max_coal_bds",
2185                         CTLTYPE_INT | CTLFLAG_RW,
2186                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2187                         "Receive max coalesced BD count.");
2188         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2189                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2190                         OID_AUTO, "tx_max_coal_bds",
2191                         CTLTYPE_INT | CTLFLAG_RW,
2192                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2193                         "Transmit max coalesced BD count.");
2194
2195         if (sc->bge_flags & BGE_FLAG_PCIE) {
2196                 /*
2197                  * A common design characteristic for many Broadcom
2198                  * client controllers is that they only support a
2199                  * single outstanding DMA read operation on the PCIe
2200                  * bus. This means that it will take twice as long to
2201                  * fetch a TX frame that is split into header and
2202                  * payload buffers as it does to fetch a single,
2203                  * contiguous TX frame (2 reads vs. 1 read). For these
2204                  * controllers, coalescing buffers to reduce the number
2205                  * of memory reads is effective way to get maximum
2206                  * performance(about 940Mbps).  Without collapsing TX
2207                  * buffers the maximum TCP bulk transfer performance
2208                  * is about 850Mbps. However forcing coalescing mbufs
2209                  * consumes a lot of CPU cycles, so leave it off by
2210                  * default.
2211                  */
2212                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2213                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2214                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2215                                &sc->bge_force_defrag, 0,
2216                                "Force defragment on TX path");
2217         }
2218
2219         /*
2220          * Call MI attach routine.
2221          */
2222         ether_ifattach(ifp, ether_addr, NULL);
2223
2224         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2225                                bge_intr, sc, &sc->bge_intrhand,
2226                                ifp->if_serializer);
2227         if (error) {
2228                 ether_ifdetach(ifp);
2229                 device_printf(dev, "couldn't set up irq\n");
2230                 goto fail;
2231         }
2232
2233         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2234         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2235
2236         return(0);
2237 fail:
2238         bge_detach(dev);
2239         return(error);
2240 }
2241
2242 static int
2243 bge_detach(device_t dev)
2244 {
2245         struct bge_softc *sc = device_get_softc(dev);
2246
2247         if (device_is_attached(dev)) {
2248                 struct ifnet *ifp = &sc->arpcom.ac_if;
2249
2250                 lwkt_serialize_enter(ifp->if_serializer);
2251                 bge_stop(sc);
2252                 bge_reset(sc);
2253                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2254                 lwkt_serialize_exit(ifp->if_serializer);
2255
2256                 ether_ifdetach(ifp);
2257         }
2258
2259         if (sc->bge_flags & BGE_FLAG_TBI)
2260                 ifmedia_removeall(&sc->bge_ifmedia);
2261         if (sc->bge_miibus)
2262                 device_delete_child(dev, sc->bge_miibus);
2263         bus_generic_detach(dev);
2264
2265         if (sc->bge_irq != NULL)
2266                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2267
2268         if (sc->bge_res != NULL)
2269                 bus_release_resource(dev, SYS_RES_MEMORY,
2270                     BGE_PCI_BAR0, sc->bge_res);
2271
2272         if (sc->bge_sysctl_tree != NULL)
2273                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2274
2275         bge_dma_free(sc);
2276
2277         return 0;
2278 }
2279
2280 static void
2281 bge_reset(struct bge_softc *sc)
2282 {
2283         device_t dev;
2284         uint32_t cachesize, command, pcistate, reset;
2285         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2286         int i, val = 0;
2287
2288         dev = sc->bge_dev;
2289
2290         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2291             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2292                 if (sc->bge_flags & BGE_FLAG_PCIE)
2293                         write_op = bge_writemem_direct;
2294                 else
2295                         write_op = bge_writemem_ind;
2296         } else {
2297                 write_op = bge_writereg_ind;
2298         }
2299
2300         /* Save some important PCI state. */
2301         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2302         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2303         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2304
2305         pci_write_config(dev, BGE_PCI_MISC_CTL,
2306             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2307             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2308
2309         /* Disable fastboot on controllers that support it. */
2310         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2311             BGE_IS_5755_PLUS(sc)) {
2312                 if (bootverbose)
2313                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2314                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2315         }
2316
2317         /*
2318          * Write the magic number to SRAM at offset 0xB50.
2319          * When firmware finishes its initialization it will
2320          * write ~BGE_MAGIC_NUMBER to the same location.
2321          */
2322         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2323
2324         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2325
2326         /* XXX: Broadcom Linux driver. */
2327         if (sc->bge_flags & BGE_FLAG_PCIE) {
2328                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2329                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2330                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2331                         /* Prevent PCIE link training during global reset */
2332                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2333                         reset |= (1<<29);
2334                 }
2335         }
2336
2337         /*
2338          * Set GPHY Power Down Override to leave GPHY
2339          * powered up in D0 uninitialized.
2340          */
2341         if (BGE_IS_5705_PLUS(sc))
2342                 reset |= 0x04000000;
2343
2344         /* Issue global reset */
2345         write_op(sc, BGE_MISC_CFG, reset);
2346
2347         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2348                 uint32_t status, ctrl;
2349
2350                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2351                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2352                     status | BGE_VCPU_STATUS_DRV_RESET);
2353                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2354                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2355                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2356         }
2357
2358         DELAY(1000);
2359
2360         /* XXX: Broadcom Linux driver. */
2361         if (sc->bge_flags & BGE_FLAG_PCIE) {
2362                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2363                         uint32_t v;
2364
2365                         DELAY(500000); /* wait for link training to complete */
2366                         v = pci_read_config(dev, 0xc4, 4);
2367                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2368                 }
2369                 /*
2370                  * Set PCIE max payload size to 128 bytes and
2371                  * clear error status.
2372                  */
2373                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2374         }
2375
2376         /* Reset some of the PCI state that got zapped by reset */
2377         pci_write_config(dev, BGE_PCI_MISC_CTL,
2378             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2379             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2380         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2381         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2382         write_op(sc, BGE_MISC_CFG, (65 << 1));
2383
2384         /*
2385          * Disable PCI-X relaxed ordering to ensure status block update
2386          * comes first then packet buffer DMA. Otherwise driver may
2387          * read stale status block.
2388          */
2389         if (sc->bge_flags & BGE_FLAG_PCIX) {
2390                 uint16_t devctl;
2391
2392                 devctl = pci_read_config(dev,
2393                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2394                 devctl &= ~PCIXM_COMMAND_ERO;
2395                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2396                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2397                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2398                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2399                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2400                             PCIXM_COMMAND_MAX_READ);
2401                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2402                 }
2403                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2404                     devctl, 2);
2405         }
2406
2407         /* Enable memory arbiter. */
2408         if (BGE_IS_5714_FAMILY(sc)) {
2409                 uint32_t val;
2410
2411                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2412                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2413         } else {
2414                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2415         }
2416
2417         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2418                 for (i = 0; i < BGE_TIMEOUT; i++) {
2419                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2420                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2421                                 break;
2422                         DELAY(100);
2423                 }
2424                 if (i == BGE_TIMEOUT) {
2425                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2426                         return;
2427                 }
2428         } else {
2429                 /*
2430                  * Poll until we see the 1's complement of the magic number.
2431                  * This indicates that the firmware initialization
2432                  * is complete.
2433                  */
2434                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2435                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2436                         if (val == ~BGE_MAGIC_NUMBER)
2437                                 break;
2438                         DELAY(10);
2439                 }
2440                 if (i == BGE_FIRMWARE_TIMEOUT) {
2441                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2442                                   "timed out, found 0x%08x\n", val);
2443                         return;
2444                 }
2445         }
2446
2447         /*
2448          * XXX Wait for the value of the PCISTATE register to
2449          * return to its original pre-reset state. This is a
2450          * fairly good indicator of reset completion. If we don't
2451          * wait for the reset to fully complete, trying to read
2452          * from the device's non-PCI registers may yield garbage
2453          * results.
2454          */
2455         for (i = 0; i < BGE_TIMEOUT; i++) {
2456                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2457                         break;
2458                 DELAY(10);
2459         }
2460
2461         if (sc->bge_flags & BGE_FLAG_PCIE) {
2462                 reset = bge_readmem_ind(sc, 0x7c00);
2463                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2464         }
2465
2466         /* Fix up byte swapping */
2467         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2468             BGE_MODECTL_BYTESWAP_DATA);
2469
2470         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2471
2472         /*
2473          * The 5704 in TBI mode apparently needs some special
2474          * adjustment to insure the SERDES drive level is set
2475          * to 1.2V.
2476          */
2477         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2478             (sc->bge_flags & BGE_FLAG_TBI)) {
2479                 uint32_t serdescfg;
2480
2481                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2482                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2483                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2484         }
2485
2486         /* XXX: Broadcom Linux driver. */
2487         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2488             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2489                 uint32_t v;
2490
2491                 v = CSR_READ_4(sc, 0x7c00);
2492                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2493         }
2494
2495         DELAY(10000);
2496 }
2497
2498 /*
2499  * Frame reception handling. This is called if there's a frame
2500  * on the receive return list.
2501  *
2502  * Note: we have to be able to handle two possibilities here:
2503  * 1) the frame is from the jumbo recieve ring
2504  * 2) the frame is from the standard receive ring
2505  */
2506
2507 static void
2508 bge_rxeof(struct bge_softc *sc)
2509 {
2510         struct ifnet *ifp;
2511         int stdcnt = 0, jumbocnt = 0;
2512
2513         if (sc->bge_rx_saved_considx ==
2514             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2515                 return;
2516
2517         ifp = &sc->arpcom.ac_if;
2518
2519         while (sc->bge_rx_saved_considx !=
2520                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2521                 struct bge_rx_bd        *cur_rx;
2522                 uint32_t                rxidx;
2523                 struct mbuf             *m = NULL;
2524                 uint16_t                vlan_tag = 0;
2525                 int                     have_tag = 0;
2526
2527                 cur_rx =
2528             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2529
2530                 rxidx = cur_rx->bge_idx;
2531                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2532                 logif(rx_pkt);
2533
2534                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2535                         have_tag = 1;
2536                         vlan_tag = cur_rx->bge_vlan_tag;
2537                 }
2538
2539                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2540                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2541                         jumbocnt++;
2542
2543                         if (rxidx != sc->bge_jumbo) {
2544                                 ifp->if_ierrors++;
2545                                 if_printf(ifp, "sw jumbo index(%d) "
2546                                     "and hw jumbo index(%d) mismatch, drop!\n",
2547                                     sc->bge_jumbo, rxidx);
2548                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2549                                 continue;
2550                         }
2551
2552                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2553                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2554                                 ifp->if_ierrors++;
2555                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2556                                 continue;
2557                         }
2558                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2559                                 ifp->if_ierrors++;
2560                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2561                                 continue;
2562                         }
2563                 } else {
2564                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2565                         stdcnt++;
2566
2567                         if (rxidx != sc->bge_std) {
2568                                 ifp->if_ierrors++;
2569                                 if_printf(ifp, "sw std index(%d) "
2570                                     "and hw std index(%d) mismatch, drop!\n",
2571                                     sc->bge_std, rxidx);
2572                                 bge_setup_rxdesc_std(sc, rxidx);
2573                                 continue;
2574                         }
2575
2576                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2577                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2578                                 ifp->if_ierrors++;
2579                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2580                                 continue;
2581                         }
2582                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2583                                 ifp->if_ierrors++;
2584                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2585                                 continue;
2586                         }
2587                 }
2588
2589                 ifp->if_ipackets++;
2590 #if !defined(__i386__) && !defined(__x86_64__)
2591                 /*
2592                  * The x86 allows unaligned accesses, but for other
2593                  * platforms we must make sure the payload is aligned.
2594                  */
2595                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2596                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2597                             cur_rx->bge_len);
2598                         m->m_data += ETHER_ALIGN;
2599                 }
2600 #endif
2601                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2602                 m->m_pkthdr.rcvif = ifp;
2603
2604                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2605                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2606                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2607                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2608                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2609                         }
2610                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2611                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2612                                 m->m_pkthdr.csum_data =
2613                                         cur_rx->bge_tcp_udp_csum;
2614                                 m->m_pkthdr.csum_flags |=
2615                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2616                         }
2617                 }
2618
2619                 /*
2620                  * If we received a packet with a vlan tag, pass it
2621                  * to vlan_input() instead of ether_input().
2622                  */
2623                 if (have_tag) {
2624                         m->m_flags |= M_VLANTAG;
2625                         m->m_pkthdr.ether_vlantag = vlan_tag;
2626                         have_tag = vlan_tag = 0;
2627                 }
2628                 ifp->if_input(ifp, m);
2629         }
2630
2631         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2632         if (stdcnt)
2633                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2634         if (jumbocnt)
2635                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2636 }
2637
2638 static void
2639 bge_txeof(struct bge_softc *sc)
2640 {
2641         struct bge_tx_bd *cur_tx = NULL;
2642         struct ifnet *ifp;
2643
2644         if (sc->bge_tx_saved_considx ==
2645             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2646                 return;
2647
2648         ifp = &sc->arpcom.ac_if;
2649
2650         /*
2651          * Go through our tx ring and free mbufs for those
2652          * frames that have been sent.
2653          */
2654         while (sc->bge_tx_saved_considx !=
2655                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2656                 uint32_t idx = 0;
2657
2658                 idx = sc->bge_tx_saved_considx;
2659                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2660                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2661                         ifp->if_opackets++;
2662                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2663                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2664                             sc->bge_cdata.bge_tx_dmamap[idx]);
2665                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2666                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2667                 }
2668                 sc->bge_txcnt--;
2669                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2670                 logif(tx_pkt);
2671         }
2672
2673         if (cur_tx != NULL &&
2674             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2675             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2676                 ifp->if_flags &= ~IFF_OACTIVE;
2677
2678         if (sc->bge_txcnt == 0)
2679                 ifp->if_timer = 0;
2680
2681         if (!ifq_is_empty(&ifp->if_snd))
2682                 if_devstart(ifp);
2683 }
2684
2685 #ifdef DEVICE_POLLING
2686
2687 static void
2688 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2689 {
2690         struct bge_softc *sc = ifp->if_softc;
2691         uint32_t status;
2692
2693         switch(cmd) {
2694         case POLL_REGISTER:
2695                 bge_disable_intr(sc);
2696                 break;
2697         case POLL_DEREGISTER:
2698                 bge_enable_intr(sc);
2699                 break;
2700         case POLL_AND_CHECK_STATUS:
2701                 /*
2702                  * Process link state changes.
2703                  */
2704                 status = CSR_READ_4(sc, BGE_MAC_STS);
2705                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2706                         sc->bge_link_evt = 0;
2707                         sc->bge_link_upd(sc, status);
2708                 }
2709                 /* fall through */
2710         case POLL_ONLY:
2711                 if (ifp->if_flags & IFF_RUNNING) {
2712                         bge_rxeof(sc);
2713                         bge_txeof(sc);
2714                 }
2715                 break;
2716         }
2717 }
2718
2719 #endif
2720
2721 static void
2722 bge_intr(void *xsc)
2723 {
2724         struct bge_softc *sc = xsc;
2725         struct ifnet *ifp = &sc->arpcom.ac_if;
2726         uint32_t status;
2727
2728         logif(intr);
2729
2730         /*
2731          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2732          * disable interrupts by writing nonzero like we used to, since with
2733          * our current organization this just gives complications and
2734          * pessimizations for re-enabling interrupts.  We used to have races
2735          * instead of the necessary complications.  Disabling interrupts
2736          * would just reduce the chance of a status update while we are
2737          * running (by switching to the interrupt-mode coalescence
2738          * parameters), but this chance is already very low so it is more
2739          * efficient to get another interrupt than prevent it.
2740          *
2741          * We do the ack first to ensure another interrupt if there is a
2742          * status update after the ack.  We don't check for the status
2743          * changing later because it is more efficient to get another
2744          * interrupt than prevent it, not quite as above (not checking is
2745          * a smaller optimization than not toggling the interrupt enable,
2746          * since checking doesn't involve PCI accesses and toggling require
2747          * the status check).  So toggling would probably be a pessimization
2748          * even with MSI.  It would only be needed for using a task queue.
2749          */
2750         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2751
2752         /*
2753          * Process link state changes.
2754          */
2755         status = CSR_READ_4(sc, BGE_MAC_STS);
2756         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2757                 sc->bge_link_evt = 0;
2758                 sc->bge_link_upd(sc, status);
2759         }
2760
2761         if (ifp->if_flags & IFF_RUNNING) {
2762                 /* Check RX return ring producer/consumer */
2763                 bge_rxeof(sc);
2764
2765                 /* Check TX ring producer/consumer */
2766                 bge_txeof(sc);
2767         }
2768
2769         if (sc->bge_coal_chg)
2770                 bge_coal_change(sc);
2771 }
2772
2773 static void
2774 bge_tick(void *xsc)
2775 {
2776         struct bge_softc *sc = xsc;
2777         struct ifnet *ifp = &sc->arpcom.ac_if;
2778
2779         lwkt_serialize_enter(ifp->if_serializer);
2780
2781         if (BGE_IS_5705_PLUS(sc))
2782                 bge_stats_update_regs(sc);
2783         else
2784                 bge_stats_update(sc);
2785
2786         if (sc->bge_flags & BGE_FLAG_TBI) {
2787                 /*
2788                  * Since in TBI mode auto-polling can't be used we should poll
2789                  * link status manually. Here we register pending link event
2790                  * and trigger interrupt.
2791                  */
2792                 sc->bge_link_evt++;
2793                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2794         } else if (!sc->bge_link) {
2795                 mii_tick(device_get_softc(sc->bge_miibus));
2796         }
2797
2798         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2799
2800         lwkt_serialize_exit(ifp->if_serializer);
2801 }
2802
2803 static void
2804 bge_stats_update_regs(struct bge_softc *sc)
2805 {
2806         struct ifnet *ifp = &sc->arpcom.ac_if;
2807         struct bge_mac_stats_regs stats;
2808         uint32_t *s;
2809         int i;
2810
2811         s = (uint32_t *)&stats;
2812         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2813                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2814                 s++;
2815         }
2816
2817         ifp->if_collisions +=
2818            (stats.dot3StatsSingleCollisionFrames +
2819            stats.dot3StatsMultipleCollisionFrames +
2820            stats.dot3StatsExcessiveCollisions +
2821            stats.dot3StatsLateCollisions) -
2822            ifp->if_collisions;
2823 }
2824
2825 static void
2826 bge_stats_update(struct bge_softc *sc)
2827 {
2828         struct ifnet *ifp = &sc->arpcom.ac_if;
2829         bus_size_t stats;
2830
2831         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2832
2833 #define READ_STAT(sc, stats, stat)      \
2834         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2835
2836         ifp->if_collisions +=
2837            (READ_STAT(sc, stats,
2838                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2839             READ_STAT(sc, stats,
2840                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2841             READ_STAT(sc, stats,
2842                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2843             READ_STAT(sc, stats,
2844                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2845            ifp->if_collisions;
2846
2847 #undef READ_STAT
2848
2849 #ifdef notdef
2850         ifp->if_collisions +=
2851            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2852            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2853            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2854            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2855            ifp->if_collisions;
2856 #endif
2857 }
2858
2859 /*
2860  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2861  * pointers to descriptors.
2862  */
2863 static int
2864 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2865 {
2866         struct bge_tx_bd *d = NULL;
2867         uint16_t csum_flags = 0;
2868         bus_dma_segment_t segs[BGE_NSEG_NEW];
2869         bus_dmamap_t map;
2870         int error, maxsegs, nsegs, idx, i;
2871         struct mbuf *m_head = *m_head0;
2872
2873         if (m_head->m_pkthdr.csum_flags) {
2874                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2875                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2876                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2877                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2878                 if (m_head->m_flags & M_LASTFRAG)
2879                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2880                 else if (m_head->m_flags & M_FRAG)
2881                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2882         }
2883
2884         idx = *txidx;
2885         map = sc->bge_cdata.bge_tx_dmamap[idx];
2886
2887         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2888         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2889                 ("not enough segments %d", maxsegs));
2890
2891         if (maxsegs > BGE_NSEG_NEW)
2892                 maxsegs = BGE_NSEG_NEW;
2893
2894         /*
2895          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2896          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2897          * but when such padded frames employ the bge IP/TCP checksum
2898          * offload, the hardware checksum assist gives incorrect results
2899          * (possibly from incorporating its own padding into the UDP/TCP
2900          * checksum; who knows).  If we pad such runts with zeros, the
2901          * onboard checksum comes out correct.
2902          */
2903         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2904             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2905                 error = m_devpad(m_head, BGE_MIN_FRAME);
2906                 if (error)
2907                         goto back;
2908         }
2909
2910         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
2911             m_head->m_next != NULL) {
2912                 struct mbuf *m_new;
2913
2914                 /*
2915                  * Forcefully defragment mbuf chain to overcome hardware
2916                  * limitation which only support a single outstanding
2917                  * DMA read operation.  If it fails, keep moving on using
2918                  * the original mbuf chain.
2919                  */
2920                 m_new = m_defrag(m_head, MB_DONTWAIT);
2921                 if (m_new != NULL)
2922                         *m_head0 = m_head = m_new;
2923         }
2924
2925         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2926                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2927         if (error)
2928                 goto back;
2929
2930         m_head = *m_head0;
2931         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2932
2933         for (i = 0; ; i++) {
2934                 d = &sc->bge_ldata.bge_tx_ring[idx];
2935
2936                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2937                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2938                 d->bge_len = segs[i].ds_len;
2939                 d->bge_flags = csum_flags;
2940
2941                 if (i == nsegs - 1)
2942                         break;
2943                 BGE_INC(idx, BGE_TX_RING_CNT);
2944         }
2945         /* Mark the last segment as end of packet... */
2946         d->bge_flags |= BGE_TXBDFLAG_END;
2947
2948         /* Set vlan tag to the first segment of the packet. */
2949         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2950         if (m_head->m_flags & M_VLANTAG) {
2951                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2952                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2953         } else {
2954                 d->bge_vlan_tag = 0;
2955         }
2956
2957         /*
2958          * Insure that the map for this transmission is placed at
2959          * the array index of the last descriptor in this chain.
2960          */
2961         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2962         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2963         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2964         sc->bge_txcnt += nsegs;
2965
2966         BGE_INC(idx, BGE_TX_RING_CNT);
2967         *txidx = idx;
2968 back:
2969         if (error) {
2970                 m_freem(*m_head0);
2971                 *m_head0 = NULL;
2972         }
2973         return error;
2974 }
2975
2976 /*
2977  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2978  * to the mbuf data regions directly in the transmit descriptors.
2979  */
2980 static void
2981 bge_start(struct ifnet *ifp)
2982 {
2983         struct bge_softc *sc = ifp->if_softc;
2984         struct mbuf *m_head = NULL;
2985         uint32_t prodidx;
2986         int need_trans;
2987
2988         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2989                 return;
2990
2991         prodidx = sc->bge_tx_prodidx;
2992
2993         need_trans = 0;
2994         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2995                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2996                 if (m_head == NULL)
2997                         break;
2998
2999                 /*
3000                  * XXX
3001                  * The code inside the if() block is never reached since we
3002                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3003                  * requests to checksum TCP/UDP in a fragmented packet.
3004                  *
3005                  * XXX
3006                  * safety overkill.  If this is a fragmented packet chain
3007                  * with delayed TCP/UDP checksums, then only encapsulate
3008                  * it if we have enough descriptors to handle the entire
3009                  * chain at once.
3010                  * (paranoia -- may not actually be needed)
3011                  */
3012                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3013                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3014                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3015                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3016                                 ifp->if_flags |= IFF_OACTIVE;
3017                                 ifq_prepend(&ifp->if_snd, m_head);
3018                                 break;
3019                         }
3020                 }
3021
3022                 /*
3023                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3024                  * descriptors of the end of the ring.  Also make
3025                  * sure there are BGE_NSEG_SPARE descriptors for
3026                  * jumbo buffers' defragmentation.
3027                  */
3028                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3029                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3030                         ifp->if_flags |= IFF_OACTIVE;
3031                         ifq_prepend(&ifp->if_snd, m_head);
3032                         break;
3033                 }
3034
3035                 /*
3036                  * Pack the data into the transmit ring. If we
3037                  * don't have room, set the OACTIVE flag and wait
3038                  * for the NIC to drain the ring.
3039                  */
3040                 if (bge_encap(sc, &m_head, &prodidx)) {
3041                         ifp->if_flags |= IFF_OACTIVE;
3042                         ifp->if_oerrors++;
3043                         break;
3044                 }
3045                 need_trans = 1;
3046
3047                 ETHER_BPF_MTAP(ifp, m_head);
3048         }
3049
3050         if (!need_trans)
3051                 return;
3052
3053         /* Transmit */
3054         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3055         /* 5700 b2 errata */
3056         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3057                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3058
3059         sc->bge_tx_prodidx = prodidx;
3060
3061         /*
3062          * Set a timeout in case the chip goes out to lunch.
3063          */
3064         ifp->if_timer = 5;
3065 }
3066
3067 static void
3068 bge_init(void *xsc)
3069 {
3070         struct bge_softc *sc = xsc;
3071         struct ifnet *ifp = &sc->arpcom.ac_if;
3072         uint16_t *m;
3073
3074         ASSERT_SERIALIZED(ifp->if_serializer);
3075
3076         if (ifp->if_flags & IFF_RUNNING)
3077                 return;
3078
3079         /* Cancel pending I/O and flush buffers. */
3080         bge_stop(sc);
3081         bge_reset(sc);
3082         bge_chipinit(sc);
3083
3084         /*
3085          * Init the various state machines, ring
3086          * control blocks and firmware.
3087          */
3088         if (bge_blockinit(sc)) {
3089                 if_printf(ifp, "initialization failure\n");
3090                 bge_stop(sc);
3091                 return;
3092         }
3093
3094         /* Specify MTU. */
3095         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3096             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3097
3098         /* Load our MAC address. */
3099         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3100         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3101         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3102
3103         /* Enable or disable promiscuous mode as needed. */
3104         bge_setpromisc(sc);
3105
3106         /* Program multicast filter. */
3107         bge_setmulti(sc);
3108
3109         /* Init RX ring. */
3110         if (bge_init_rx_ring_std(sc)) {
3111                 if_printf(ifp, "RX ring initialization failed\n");
3112                 bge_stop(sc);
3113                 return;
3114         }
3115
3116         /*
3117          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3118          * memory to insure that the chip has in fact read the first
3119          * entry of the ring.
3120          */
3121         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3122                 uint32_t                v, i;
3123                 for (i = 0; i < 10; i++) {
3124                         DELAY(20);
3125                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3126                         if (v == (MCLBYTES - ETHER_ALIGN))
3127                                 break;
3128                 }
3129                 if (i == 10)
3130                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3131         }
3132
3133         /* Init jumbo RX ring. */
3134         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3135                 if (bge_init_rx_ring_jumbo(sc)) {
3136                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3137                         bge_stop(sc);
3138                         return;
3139                 }
3140         }
3141
3142         /* Init our RX return ring index */
3143         sc->bge_rx_saved_considx = 0;
3144
3145         /* Init TX ring. */
3146         bge_init_tx_ring(sc);
3147
3148         /* Turn on transmitter */
3149         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3150
3151         /* Turn on receiver */
3152         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3153
3154         /* Tell firmware we're alive. */
3155         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3156
3157         /* Enable host interrupts if polling(4) is not enabled. */
3158         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3159 #ifdef DEVICE_POLLING
3160         if (ifp->if_flags & IFF_POLLING)
3161                 bge_disable_intr(sc);
3162         else
3163 #endif
3164         bge_enable_intr(sc);
3165
3166         bge_ifmedia_upd(ifp);
3167
3168         ifp->if_flags |= IFF_RUNNING;
3169         ifp->if_flags &= ~IFF_OACTIVE;
3170
3171         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3172 }
3173
3174 /*
3175  * Set media options.
3176  */
3177 static int
3178 bge_ifmedia_upd(struct ifnet *ifp)
3179 {
3180         struct bge_softc *sc = ifp->if_softc;
3181
3182         /* If this is a 1000baseX NIC, enable the TBI port. */
3183         if (sc->bge_flags & BGE_FLAG_TBI) {
3184                 struct ifmedia *ifm = &sc->bge_ifmedia;
3185
3186                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3187                         return(EINVAL);
3188
3189                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3190                 case IFM_AUTO:
3191                         /*
3192                          * The BCM5704 ASIC appears to have a special
3193                          * mechanism for programming the autoneg
3194                          * advertisement registers in TBI mode.
3195                          */
3196                         if (!bge_fake_autoneg &&
3197                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3198                                 uint32_t sgdig;
3199
3200                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3201                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3202                                 sgdig |= BGE_SGDIGCFG_AUTO |
3203                                          BGE_SGDIGCFG_PAUSE_CAP |
3204                                          BGE_SGDIGCFG_ASYM_PAUSE;
3205                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3206                                             sgdig | BGE_SGDIGCFG_SEND);
3207                                 DELAY(5);
3208                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3209                         }
3210                         break;
3211                 case IFM_1000_SX:
3212                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3213                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3214                                     BGE_MACMODE_HALF_DUPLEX);
3215                         } else {
3216                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3217                                     BGE_MACMODE_HALF_DUPLEX);
3218                         }
3219                         break;
3220                 default:
3221                         return(EINVAL);
3222                 }
3223         } else {
3224                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3225
3226                 sc->bge_link_evt++;
3227                 sc->bge_link = 0;
3228                 if (mii->mii_instance) {
3229                         struct mii_softc *miisc;
3230
3231                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3232                                 mii_phy_reset(miisc);
3233                 }
3234                 mii_mediachg(mii);
3235         }
3236         return(0);
3237 }
3238
3239 /*
3240  * Report current media status.
3241  */
3242 static void
3243 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3244 {
3245         struct bge_softc *sc = ifp->if_softc;
3246
3247         if (sc->bge_flags & BGE_FLAG_TBI) {
3248                 ifmr->ifm_status = IFM_AVALID;
3249                 ifmr->ifm_active = IFM_ETHER;
3250                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3251                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3252                         ifmr->ifm_status |= IFM_ACTIVE;
3253                 } else {
3254                         ifmr->ifm_active |= IFM_NONE;
3255                         return;
3256                 }
3257
3258                 ifmr->ifm_active |= IFM_1000_SX;
3259                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3260                         ifmr->ifm_active |= IFM_HDX;
3261                 else
3262                         ifmr->ifm_active |= IFM_FDX;
3263         } else {
3264                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3265
3266                 mii_pollstat(mii);
3267                 ifmr->ifm_active = mii->mii_media_active;
3268                 ifmr->ifm_status = mii->mii_media_status;
3269         }
3270 }
3271
3272 static int
3273 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3274 {
3275         struct bge_softc *sc = ifp->if_softc;
3276         struct ifreq *ifr = (struct ifreq *)data;
3277         int mask, error = 0;
3278
3279         ASSERT_SERIALIZED(ifp->if_serializer);
3280
3281         switch (command) {
3282         case SIOCSIFMTU:
3283                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3284                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3285                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3286                         error = EINVAL;
3287                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3288                         ifp->if_mtu = ifr->ifr_mtu;
3289                         ifp->if_flags &= ~IFF_RUNNING;
3290                         bge_init(sc);
3291                 }
3292                 break;
3293         case SIOCSIFFLAGS:
3294                 if (ifp->if_flags & IFF_UP) {
3295                         if (ifp->if_flags & IFF_RUNNING) {
3296                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3297
3298                                 /*
3299                                  * If only the state of the PROMISC flag
3300                                  * changed, then just use the 'set promisc
3301                                  * mode' command instead of reinitializing
3302                                  * the entire NIC. Doing a full re-init
3303                                  * means reloading the firmware and waiting
3304                                  * for it to start up, which may take a
3305                                  * second or two.  Similarly for ALLMULTI.
3306                                  */
3307                                 if (mask & IFF_PROMISC)
3308                                         bge_setpromisc(sc);
3309                                 if (mask & IFF_ALLMULTI)
3310                                         bge_setmulti(sc);
3311                         } else {
3312                                 bge_init(sc);
3313                         }
3314                 } else {
3315                         if (ifp->if_flags & IFF_RUNNING)
3316                                 bge_stop(sc);
3317                 }
3318                 sc->bge_if_flags = ifp->if_flags;
3319                 break;
3320         case SIOCADDMULTI:
3321         case SIOCDELMULTI:
3322                 if (ifp->if_flags & IFF_RUNNING)
3323                         bge_setmulti(sc);
3324                 break;
3325         case SIOCSIFMEDIA:
3326         case SIOCGIFMEDIA:
3327                 if (sc->bge_flags & BGE_FLAG_TBI) {
3328                         error = ifmedia_ioctl(ifp, ifr,
3329                             &sc->bge_ifmedia, command);
3330                 } else {
3331                         struct mii_data *mii;
3332
3333                         mii = device_get_softc(sc->bge_miibus);
3334                         error = ifmedia_ioctl(ifp, ifr,
3335                                               &mii->mii_media, command);
3336                 }
3337                 break;
3338         case SIOCSIFCAP:
3339                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3340                 if (mask & IFCAP_HWCSUM) {
3341                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3342                         if (IFCAP_HWCSUM & ifp->if_capenable)
3343                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3344                         else
3345                                 ifp->if_hwassist = 0;
3346                 }
3347                 break;
3348         default:
3349                 error = ether_ioctl(ifp, command, data);
3350                 break;
3351         }
3352         return error;
3353 }
3354
3355 static void
3356 bge_watchdog(struct ifnet *ifp)
3357 {
3358         struct bge_softc *sc = ifp->if_softc;
3359
3360         if_printf(ifp, "watchdog timeout -- resetting\n");
3361
3362         ifp->if_flags &= ~IFF_RUNNING;
3363         bge_init(sc);
3364
3365         ifp->if_oerrors++;
3366
3367         if (!ifq_is_empty(&ifp->if_snd))
3368                 if_devstart(ifp);
3369 }
3370
3371 /*
3372  * Stop the adapter and free any mbufs allocated to the
3373  * RX and TX lists.
3374  */
3375 static void
3376 bge_stop(struct bge_softc *sc)
3377 {
3378         struct ifnet *ifp = &sc->arpcom.ac_if;
3379
3380         ASSERT_SERIALIZED(ifp->if_serializer);
3381
3382         callout_stop(&sc->bge_stat_timer);
3383
3384         /*
3385          * Disable all of the receiver blocks
3386          */
3387         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3388         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3389         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3390         if (!BGE_IS_5705_PLUS(sc))
3391                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3392         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3393         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3394         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3395
3396         /*
3397          * Disable all of the transmit blocks
3398          */
3399         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3400         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3401         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3402         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3403         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3404         if (!BGE_IS_5705_PLUS(sc))
3405                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3406         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3407
3408         /*
3409          * Shut down all of the memory managers and related
3410          * state machines.
3411          */
3412         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3413         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3414         if (!BGE_IS_5705_PLUS(sc))
3415                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3416         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3417         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3418         if (!BGE_IS_5705_PLUS(sc)) {
3419                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3420                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3421         }
3422
3423         /* Disable host interrupts. */
3424         bge_disable_intr(sc);
3425
3426         /*
3427          * Tell firmware we're shutting down.
3428          */
3429         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3430
3431         /* Free the RX lists. */
3432         bge_free_rx_ring_std(sc);
3433
3434         /* Free jumbo RX list. */
3435         if (BGE_IS_JUMBO_CAPABLE(sc))
3436                 bge_free_rx_ring_jumbo(sc);
3437
3438         /* Free TX buffers. */
3439         bge_free_tx_ring(sc);
3440
3441         sc->bge_link = 0;
3442         sc->bge_coal_chg = 0;
3443
3444         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3445
3446         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3447         ifp->if_timer = 0;
3448 }
3449
3450 /*
3451  * Stop all chip I/O so that the kernel's probe routines don't
3452  * get confused by errant DMAs when rebooting.
3453  */
3454 static void
3455 bge_shutdown(device_t dev)
3456 {
3457         struct bge_softc *sc = device_get_softc(dev);
3458         struct ifnet *ifp = &sc->arpcom.ac_if;
3459
3460         lwkt_serialize_enter(ifp->if_serializer);
3461         bge_stop(sc);
3462         bge_reset(sc);
3463         lwkt_serialize_exit(ifp->if_serializer);
3464 }
3465
3466 static int
3467 bge_suspend(device_t dev)
3468 {
3469         struct bge_softc *sc = device_get_softc(dev);
3470         struct ifnet *ifp = &sc->arpcom.ac_if;
3471
3472         lwkt_serialize_enter(ifp->if_serializer);
3473         bge_stop(sc);
3474         lwkt_serialize_exit(ifp->if_serializer);
3475
3476         return 0;
3477 }
3478
3479 static int
3480 bge_resume(device_t dev)
3481 {
3482         struct bge_softc *sc = device_get_softc(dev);
3483         struct ifnet *ifp = &sc->arpcom.ac_if;
3484
3485         lwkt_serialize_enter(ifp->if_serializer);
3486
3487         if (ifp->if_flags & IFF_UP) {
3488                 bge_init(sc);
3489
3490                 if (!ifq_is_empty(&ifp->if_snd))
3491                         if_devstart(ifp);
3492         }
3493
3494         lwkt_serialize_exit(ifp->if_serializer);
3495
3496         return 0;
3497 }
3498
3499 static void
3500 bge_setpromisc(struct bge_softc *sc)
3501 {
3502         struct ifnet *ifp = &sc->arpcom.ac_if;
3503
3504         if (ifp->if_flags & IFF_PROMISC)
3505                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3506         else
3507                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3508 }
3509
3510 static void
3511 bge_dma_free(struct bge_softc *sc)
3512 {
3513         int i;
3514
3515         /* Destroy RX mbuf DMA stuffs. */
3516         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3517                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3518                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3519                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3520                 }
3521                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3522                                    sc->bge_cdata.bge_rx_tmpmap);
3523                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3524         }
3525
3526         /* Destroy TX mbuf DMA stuffs. */
3527         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3528                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3529                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3530                             sc->bge_cdata.bge_tx_dmamap[i]);
3531                 }
3532                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3533         }
3534
3535         /* Destroy standard RX ring */
3536         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3537                            sc->bge_cdata.bge_rx_std_ring_map,
3538                            sc->bge_ldata.bge_rx_std_ring);
3539
3540         if (BGE_IS_JUMBO_CAPABLE(sc))
3541                 bge_free_jumbo_mem(sc);
3542
3543         /* Destroy RX return ring */
3544         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3545                            sc->bge_cdata.bge_rx_return_ring_map,
3546                            sc->bge_ldata.bge_rx_return_ring);
3547
3548         /* Destroy TX ring */
3549         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3550                            sc->bge_cdata.bge_tx_ring_map,
3551                            sc->bge_ldata.bge_tx_ring);
3552
3553         /* Destroy status block */
3554         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3555                            sc->bge_cdata.bge_status_map,
3556                            sc->bge_ldata.bge_status_block);
3557
3558         /* Destroy statistics block */
3559         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3560                            sc->bge_cdata.bge_stats_map,
3561                            sc->bge_ldata.bge_stats);
3562
3563         /* Destroy the parent tag */
3564         if (sc->bge_cdata.bge_parent_tag != NULL)
3565                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3566 }
3567
3568 static int
3569 bge_dma_alloc(struct bge_softc *sc)
3570 {
3571         struct ifnet *ifp = &sc->arpcom.ac_if;
3572         int i, error;
3573         bus_addr_t lowaddr;
3574         bus_size_t boundary;
3575
3576         boundary = 0;
3577         if (sc->bge_flags & BGE_FLAG_BOUNDARY_4G)
3578                 boundary = BGE_DMA_BOUNDARY_4G;
3579
3580         lowaddr = BUS_SPACE_MAXADDR;
3581         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3582                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3583
3584         /*
3585          * Allocate the parent bus DMA tag appropriate for PCI.
3586          */
3587         error = bus_dma_tag_create(NULL, 1, boundary,
3588                                    lowaddr, BUS_SPACE_MAXADDR,
3589                                    NULL, NULL,
3590                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3591                                    BUS_SPACE_MAXSIZE_32BIT,
3592                                    0, &sc->bge_cdata.bge_parent_tag);
3593         if (error) {
3594                 if_printf(ifp, "could not allocate parent dma tag\n");
3595                 return error;
3596         }
3597
3598         /*
3599          * Create DMA tag and maps for RX mbufs.
3600          */
3601         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3602                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3603                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3604                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3605                                    &sc->bge_cdata.bge_rx_mtag);
3606         if (error) {
3607                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3608                 return error;
3609         }
3610
3611         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3612                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3613         if (error) {
3614                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3615                 sc->bge_cdata.bge_rx_mtag = NULL;
3616                 return error;
3617         }
3618
3619         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3620                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3621                                           BUS_DMA_WAITOK,
3622                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3623                 if (error) {
3624                         int j;
3625
3626                         for (j = 0; j < i; ++j) {
3627                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3628                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3629                         }
3630                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3631                         sc->bge_cdata.bge_rx_mtag = NULL;
3632
3633                         if_printf(ifp, "could not create DMA map for RX\n");
3634                         return error;
3635                 }
3636         }
3637
3638         /*
3639          * Create DMA tag and maps for TX mbufs.
3640          */
3641         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3642                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3643                                    NULL, NULL,
3644                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3645                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3646                                    BUS_DMA_ONEBPAGE,
3647                                    &sc->bge_cdata.bge_tx_mtag);
3648         if (error) {
3649                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3650                 return error;
3651         }
3652
3653         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3654                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3655                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3656                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3657                 if (error) {
3658                         int j;
3659
3660                         for (j = 0; j < i; ++j) {
3661                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3662                                         sc->bge_cdata.bge_tx_dmamap[j]);
3663                         }
3664                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3665                         sc->bge_cdata.bge_tx_mtag = NULL;
3666
3667                         if_printf(ifp, "could not create DMA map for TX\n");
3668                         return error;
3669                 }
3670         }
3671
3672         /*
3673          * Create DMA stuffs for standard RX ring.
3674          */
3675         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3676                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3677                                     &sc->bge_cdata.bge_rx_std_ring_map,
3678                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3679                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3680         if (error) {
3681                 if_printf(ifp, "could not create std RX ring\n");
3682                 return error;
3683         }
3684
3685         /*
3686          * Create jumbo buffer pool.
3687          */
3688         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3689                 error = bge_alloc_jumbo_mem(sc);
3690                 if (error) {
3691                         if_printf(ifp, "could not create jumbo buffer pool\n");
3692                         return error;
3693                 }
3694         }
3695
3696         /*
3697          * Create DMA stuffs for RX return ring.
3698          */
3699         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3700                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3701                                     &sc->bge_cdata.bge_rx_return_ring_map,
3702                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3703                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3704         if (error) {
3705                 if_printf(ifp, "could not create RX ret ring\n");
3706                 return error;
3707         }
3708
3709         /*
3710          * Create DMA stuffs for TX ring.
3711          */
3712         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3713                                     &sc->bge_cdata.bge_tx_ring_tag,
3714                                     &sc->bge_cdata.bge_tx_ring_map,
3715                                     (void *)&sc->bge_ldata.bge_tx_ring,
3716                                     &sc->bge_ldata.bge_tx_ring_paddr);
3717         if (error) {
3718                 if_printf(ifp, "could not create TX ring\n");
3719                 return error;
3720         }
3721
3722         /*
3723          * Create DMA stuffs for status block.
3724          */
3725         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3726                                     &sc->bge_cdata.bge_status_tag,
3727                                     &sc->bge_cdata.bge_status_map,
3728                                     (void *)&sc->bge_ldata.bge_status_block,
3729                                     &sc->bge_ldata.bge_status_block_paddr);
3730         if (error) {
3731                 if_printf(ifp, "could not create status block\n");
3732                 return error;
3733         }
3734
3735         /*
3736          * Create DMA stuffs for statistics block.
3737          */
3738         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3739                                     &sc->bge_cdata.bge_stats_tag,
3740                                     &sc->bge_cdata.bge_stats_map,
3741                                     (void *)&sc->bge_ldata.bge_stats,
3742                                     &sc->bge_ldata.bge_stats_paddr);
3743         if (error) {
3744                 if_printf(ifp, "could not create stats block\n");
3745                 return error;
3746         }
3747         return 0;
3748 }
3749
3750 static int
3751 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3752                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3753 {
3754         bus_dmamem_t dmem;
3755         int error;
3756
3757         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3758                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3759                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3760         if (error)
3761                 return error;
3762
3763         *tag = dmem.dmem_tag;
3764         *map = dmem.dmem_map;
3765         *addr = dmem.dmem_addr;
3766         *paddr = dmem.dmem_busaddr;
3767
3768         return 0;
3769 }
3770
3771 static void
3772 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3773 {
3774         if (tag != NULL) {
3775                 bus_dmamap_unload(tag, map);
3776                 bus_dmamem_free(tag, addr, map);
3777                 bus_dma_tag_destroy(tag);
3778         }
3779 }
3780
3781 /*
3782  * Grrr. The link status word in the status block does
3783  * not work correctly on the BCM5700 rev AX and BX chips,
3784  * according to all available information. Hence, we have
3785  * to enable MII interrupts in order to properly obtain
3786  * async link changes. Unfortunately, this also means that
3787  * we have to read the MAC status register to detect link
3788  * changes, thereby adding an additional register access to
3789  * the interrupt handler.
3790  *
3791  * XXX: perhaps link state detection procedure used for
3792  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3793  */
3794 static void
3795 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3796 {
3797         struct ifnet *ifp = &sc->arpcom.ac_if;
3798         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3799
3800         mii_pollstat(mii);
3801
3802         if (!sc->bge_link &&
3803             (mii->mii_media_status & IFM_ACTIVE) &&
3804             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3805                 sc->bge_link++;
3806                 if (bootverbose)
3807                         if_printf(ifp, "link UP\n");
3808         } else if (sc->bge_link &&
3809             (!(mii->mii_media_status & IFM_ACTIVE) ||
3810             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3811                 sc->bge_link = 0;
3812                 if (bootverbose)
3813                         if_printf(ifp, "link DOWN\n");
3814         }
3815
3816         /* Clear the interrupt. */
3817         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3818         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3819         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3820 }
3821
3822 static void
3823 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3824 {
3825         struct ifnet *ifp = &sc->arpcom.ac_if;
3826
3827 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3828
3829         /*
3830          * Sometimes PCS encoding errors are detected in
3831          * TBI mode (on fiber NICs), and for some reason
3832          * the chip will signal them as link changes.
3833          * If we get a link change event, but the 'PCS
3834          * encoding error' bit in the MAC status register
3835          * is set, don't bother doing a link check.
3836          * This avoids spurious "gigabit link up" messages
3837          * that sometimes appear on fiber NICs during
3838          * periods of heavy traffic.
3839          */
3840         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3841                 if (!sc->bge_link) {
3842                         sc->bge_link++;
3843                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3844                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3845                                     BGE_MACMODE_TBI_SEND_CFGS);
3846                         }
3847                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3848
3849                         if (bootverbose)
3850                                 if_printf(ifp, "link UP\n");
3851
3852                         ifp->if_link_state = LINK_STATE_UP;
3853                         if_link_state_change(ifp);
3854                 }
3855         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3856                 if (sc->bge_link) {
3857                         sc->bge_link = 0;
3858
3859                         if (bootverbose)
3860                                 if_printf(ifp, "link DOWN\n");
3861
3862                         ifp->if_link_state = LINK_STATE_DOWN;
3863                         if_link_state_change(ifp);
3864                 }
3865         }
3866
3867 #undef PCS_ENCODE_ERR
3868
3869         /* Clear the attention. */
3870         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3871             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3872             BGE_MACSTAT_LINK_CHANGED);
3873 }
3874
3875 static void
3876 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3877 {
3878         /*
3879          * Check that the AUTOPOLL bit is set before
3880          * processing the event as a real link change.
3881          * Turning AUTOPOLL on and off in the MII read/write
3882          * functions will often trigger a link status
3883          * interrupt for no reason.
3884          */
3885         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3886                 struct ifnet *ifp = &sc->arpcom.ac_if;
3887                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3888
3889                 mii_pollstat(mii);
3890
3891                 if (!sc->bge_link &&
3892                     (mii->mii_media_status & IFM_ACTIVE) &&
3893                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3894                         sc->bge_link++;
3895                         if (bootverbose)
3896                                 if_printf(ifp, "link UP\n");
3897                 } else if (sc->bge_link &&
3898                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3899                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3900                         sc->bge_link = 0;
3901                         if (bootverbose)
3902                                 if_printf(ifp, "link DOWN\n");
3903                 }
3904         }
3905
3906         /* Clear the attention. */
3907         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3908             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3909             BGE_MACSTAT_LINK_CHANGED);
3910 }
3911
3912 static int
3913 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3914 {
3915         struct bge_softc *sc = arg1;
3916
3917         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3918                                    &sc->bge_rx_coal_ticks,
3919                                    BGE_RX_COAL_TICKS_CHG);
3920 }
3921
3922 static int
3923 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3924 {
3925         struct bge_softc *sc = arg1;
3926
3927         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3928                                    &sc->bge_tx_coal_ticks,
3929                                    BGE_TX_COAL_TICKS_CHG);
3930 }
3931
3932 static int
3933 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3934 {
3935         struct bge_softc *sc = arg1;
3936
3937         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3938                                    &sc->bge_rx_max_coal_bds,
3939                                    BGE_RX_MAX_COAL_BDS_CHG);
3940 }
3941
3942 static int
3943 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3944 {
3945         struct bge_softc *sc = arg1;
3946
3947         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3948                                    &sc->bge_tx_max_coal_bds,
3949                                    BGE_TX_MAX_COAL_BDS_CHG);
3950 }
3951
3952 static int
3953 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3954                     uint32_t coal_chg_mask)
3955 {
3956         struct bge_softc *sc = arg1;
3957         struct ifnet *ifp = &sc->arpcom.ac_if;
3958         int error = 0, v;
3959
3960         lwkt_serialize_enter(ifp->if_serializer);
3961
3962         v = *coal;
3963         error = sysctl_handle_int(oidp, &v, 0, req);
3964         if (!error && req->newptr != NULL) {
3965                 if (v < 0) {
3966                         error = EINVAL;
3967                 } else {
3968                         *coal = v;
3969                         sc->bge_coal_chg |= coal_chg_mask;
3970                 }
3971         }
3972
3973         lwkt_serialize_exit(ifp->if_serializer);
3974         return error;
3975 }
3976
3977 static void
3978 bge_coal_change(struct bge_softc *sc)
3979 {
3980         struct ifnet *ifp = &sc->arpcom.ac_if;
3981         uint32_t val;
3982
3983         ASSERT_SERIALIZED(ifp->if_serializer);
3984
3985         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3986                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3987                             sc->bge_rx_coal_ticks);
3988                 DELAY(10);
3989                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3990
3991                 if (bootverbose) {
3992                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3993                                   sc->bge_rx_coal_ticks);
3994                 }
3995         }
3996
3997         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3998                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3999                             sc->bge_tx_coal_ticks);
4000                 DELAY(10);
4001                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4002
4003                 if (bootverbose) {
4004                         if_printf(ifp, "tx_coal_ticks -> %u\n",
4005                                   sc->bge_tx_coal_ticks);
4006                 }
4007         }
4008
4009         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
4010                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4011                             sc->bge_rx_max_coal_bds);
4012                 DELAY(10);
4013                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4014
4015                 if (bootverbose) {
4016                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
4017                                   sc->bge_rx_max_coal_bds);
4018                 }
4019         }
4020
4021         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
4022                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4023                             sc->bge_tx_max_coal_bds);
4024                 DELAY(10);
4025                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4026
4027                 if (bootverbose) {
4028                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
4029                                   sc->bge_tx_max_coal_bds);
4030                 }
4031         }
4032
4033         sc->bge_coal_chg = 0;
4034 }
4035
4036 static void
4037 bge_enable_intr(struct bge_softc *sc)
4038 {
4039         struct ifnet *ifp = &sc->arpcom.ac_if;
4040
4041         lwkt_serialize_handler_enable(ifp->if_serializer);
4042
4043         /*
4044          * Enable interrupt.
4045          */
4046         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4047
4048         /*
4049          * Unmask the interrupt when we stop polling.
4050          */
4051         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4052
4053         /*
4054          * Trigger another interrupt, since above writing
4055          * to interrupt mailbox0 may acknowledge pending
4056          * interrupt.
4057          */
4058         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4059 }
4060
4061 static void
4062 bge_disable_intr(struct bge_softc *sc)
4063 {
4064         struct ifnet *ifp = &sc->arpcom.ac_if;
4065
4066         /*
4067          * Mask the interrupt when we start polling.
4068          */
4069         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4070
4071         /*
4072          * Acknowledge possible asserted interrupt.
4073          */
4074         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4075
4076         lwkt_serialize_handler_disable(ifp->if_serializer);
4077 }
4078
4079 static int
4080 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4081 {
4082         uint32_t mac_addr;
4083         int ret = 1;
4084
4085         mac_addr = bge_readmem_ind(sc, 0x0c14);
4086         if ((mac_addr >> 16) == 0x484b) {
4087                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4088                 ether_addr[1] = (uint8_t)mac_addr;
4089                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4090                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4091                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4092                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4093                 ether_addr[5] = (uint8_t)mac_addr;
4094                 ret = 0;
4095         }
4096         return ret;
4097 }
4098
4099 static int
4100 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4101 {
4102         int mac_offset = BGE_EE_MAC_OFFSET;
4103
4104         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4105                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4106
4107         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4108 }
4109
4110 static int
4111 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4112 {
4113         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4114                 return 1;
4115
4116         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4117                                ETHER_ADDR_LEN);
4118 }
4119
4120 static int
4121 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4122 {
4123         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4124                 /* NOTE: Order is critical */
4125                 bge_get_eaddr_mem,
4126                 bge_get_eaddr_nvram,
4127                 bge_get_eaddr_eeprom,
4128                 NULL
4129         };
4130         const bge_eaddr_fcn_t *func;
4131
4132         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4133                 if ((*func)(sc, eaddr) == 0)
4134                         break;
4135         }
4136         return (*func == NULL ? ENXIO : 0);
4137 }