2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.41 2005/12/31 14:08:00 sephe Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include "opt_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/socket.h>
72 #include <sys/serialize.h>
73 #include <sys/thread2.h>
76 #include <net/ifq_var.h>
77 #include <net/if_arp.h>
78 #include <net/ethernet.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
84 #include <vm/vm.h> /* for vtophys */
85 #include <vm/pmap.h> /* for vtophys */
86 #include <machine/bus_pio.h>
87 #include <machine/bus_memio.h>
88 #include <machine/bus.h>
89 #include <machine/resource.h>
93 #include <dev/netif/mii_layer/mii.h>
94 #include <dev/netif/mii_layer/miivar.h>
96 #include <bus/pci/pcireg.h>
97 #include <bus/pci/pcivar.h>
101 #include <dev/netif/vr/if_vrreg.h>
103 /* "controller miibus0" required. See GENERIC if you get errors here. */
104 #include "miibus_if.h"
109 * Various supported device vendors/types and their names.
111 static struct vr_type vr_devs[] = {
112 { VIA_VENDORID, VIA_DEVICEID_RHINE,
113 "VIA VT3043 Rhine I 10/100BaseTX" },
114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
115 "VIA VT86C100A Rhine II 10/100BaseTX" },
116 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
117 "VIA VT6102 Rhine II 10/100BaseTX" },
118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
119 "VIA VT6105 Rhine III 10/100BaseTX" },
120 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
121 "VIA VT6105M Rhine III 10/100BaseTX" },
122 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
123 "Delta Electronics Rhine II 10/100BaseTX" },
124 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
125 "Addtron Technology Rhine II 10/100BaseTX" },
129 static int vr_probe(device_t);
130 static int vr_attach(device_t);
131 static int vr_detach(device_t);
133 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *,
135 static int vr_encap(struct vr_softc *, int, struct mbuf * );
137 static void vr_rxeof(struct vr_softc *);
138 static void vr_rxeoc(struct vr_softc *);
139 static void vr_txeof(struct vr_softc *);
140 static void vr_txeoc(struct vr_softc *);
141 static void vr_tick(void *);
142 static void vr_intr(void *);
143 static void vr_start(struct ifnet *);
144 static int vr_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
145 static void vr_init(void *);
146 static void vr_stop(struct vr_softc *);
147 static void vr_watchdog(struct ifnet *);
148 static void vr_shutdown(device_t);
149 static int vr_ifmedia_upd(struct ifnet *);
150 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
153 static void vr_mii_sync(struct vr_softc *);
154 static void vr_mii_send(struct vr_softc *, uint32_t, int);
156 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
157 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
158 static int vr_miibus_readreg(device_t, int, int);
159 static int vr_miibus_writereg(device_t, int, int, int);
160 static void vr_miibus_statchg(device_t);
162 static void vr_setcfg(struct vr_softc *, int);
163 static void vr_setmulti(struct vr_softc *);
164 static void vr_reset(struct vr_softc *);
165 static int vr_list_rx_init(struct vr_softc *);
166 static int vr_list_tx_init(struct vr_softc *);
167 #ifdef DEVICE_POLLING
168 static void vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
172 #define VR_RES SYS_RES_IOPORT
173 #define VR_RID VR_PCI_LOIO
175 #define VR_RES SYS_RES_MEMORY
176 #define VR_RID VR_PCI_LOMEM
179 static device_method_t vr_methods[] = {
180 /* Device interface */
181 DEVMETHOD(device_probe, vr_probe),
182 DEVMETHOD(device_attach, vr_attach),
183 DEVMETHOD(device_detach, vr_detach),
184 DEVMETHOD(device_shutdown, vr_shutdown),
187 DEVMETHOD(bus_print_child, bus_generic_print_child),
188 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
191 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
192 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
193 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
198 static driver_t vr_driver = {
201 sizeof(struct vr_softc)
204 static devclass_t vr_devclass;
206 DECLARE_DUMMY_MODULE(if_vr);
207 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
208 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
210 #define VR_SETBIT(sc, reg, x) \
211 CSR_WRITE_1(sc, reg, \
212 CSR_READ_1(sc, reg) | (x))
214 #define VR_CLRBIT(sc, reg, x) \
215 CSR_WRITE_1(sc, reg, \
216 CSR_READ_1(sc, reg) & ~(x))
218 #define VR_SETBIT16(sc, reg, x) \
219 CSR_WRITE_2(sc, reg, \
220 CSR_READ_2(sc, reg) | (x))
222 #define VR_CLRBIT16(sc, reg, x) \
223 CSR_WRITE_2(sc, reg, \
224 CSR_READ_2(sc, reg) & ~(x))
226 #define VR_SETBIT32(sc, reg, x) \
227 CSR_WRITE_4(sc, reg, \
228 CSR_READ_4(sc, reg) | (x))
230 #define VR_CLRBIT32(sc, reg, x) \
231 CSR_WRITE_4(sc, reg, \
232 CSR_READ_4(sc, reg) & ~(x))
235 CSR_WRITE_1(sc, VR_MIICMD, \
236 CSR_READ_1(sc, VR_MIICMD) | (x))
239 CSR_WRITE_1(sc, VR_MIICMD, \
240 CSR_READ_1(sc, VR_MIICMD) & ~(x))
244 * Sync the PHYs by setting data bit and strobing the clock 32 times.
247 vr_mii_sync(struct vr_softc *sc)
251 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
253 for (i = 0; i < 32; i++) {
254 SIO_SET(VR_MIICMD_CLK);
256 SIO_CLR(VR_MIICMD_CLK);
262 * Clock a series of bits through the MII.
265 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
269 SIO_CLR(VR_MIICMD_CLK);
271 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
273 SIO_SET(VR_MIICMD_DATAIN);
275 SIO_CLR(VR_MIICMD_DATAIN);
277 SIO_CLR(VR_MIICMD_CLK);
279 SIO_SET(VR_MIICMD_CLK);
285 * Read an PHY register through the MII.
288 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame)
293 /* Set up frame for RX. */
294 frame->mii_stdelim = VR_MII_STARTDELIM;
295 frame->mii_opcode = VR_MII_READOP;
296 frame->mii_turnaround = 0;
299 CSR_WRITE_1(sc, VR_MIICMD, 0);
300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
302 /* Turn on data xmit. */
303 SIO_SET(VR_MIICMD_DIR);
307 /* Send command/address info. */
308 vr_mii_send(sc, frame->mii_stdelim, 2);
309 vr_mii_send(sc, frame->mii_opcode, 2);
310 vr_mii_send(sc, frame->mii_phyaddr, 5);
311 vr_mii_send(sc, frame->mii_regaddr, 5);
314 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
316 SIO_SET(VR_MIICMD_CLK);
320 SIO_CLR(VR_MIICMD_DIR);
323 SIO_CLR(VR_MIICMD_CLK);
325 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
326 SIO_SET(VR_MIICMD_CLK);
330 * Now try reading data bits. If the ack failed, we still
331 * need to clock through 16 cycles to keep the PHY(s) in sync.
334 for(i = 0; i < 16; i++) {
335 SIO_CLR(VR_MIICMD_CLK);
337 SIO_SET(VR_MIICMD_CLK);
343 for (i = 0x8000; i; i >>= 1) {
344 SIO_CLR(VR_MIICMD_CLK);
347 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
348 frame->mii_data |= i;
351 SIO_SET(VR_MIICMD_CLK);
356 SIO_CLR(VR_MIICMD_CLK);
358 SIO_SET(VR_MIICMD_CLK);
369 /* Set the PHY address. */
370 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
373 /* Set the register address. */
374 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
375 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
377 for (i = 0; i < 10000; i++) {
378 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
382 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
390 * Write to a PHY register through the MII.
393 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame)
396 CSR_WRITE_1(sc, VR_MIICMD, 0);
397 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
399 /* Set up frame for TX. */
400 frame->mii_stdelim = VR_MII_STARTDELIM;
401 frame->mii_opcode = VR_MII_WRITEOP;
402 frame->mii_turnaround = VR_MII_TURNAROUND;
404 /* Turn on data output. */
405 SIO_SET(VR_MIICMD_DIR);
409 vr_mii_send(sc, frame->mii_stdelim, 2);
410 vr_mii_send(sc, frame->mii_opcode, 2);
411 vr_mii_send(sc, frame->mii_phyaddr, 5);
412 vr_mii_send(sc, frame->mii_regaddr, 5);
413 vr_mii_send(sc, frame->mii_turnaround, 2);
414 vr_mii_send(sc, frame->mii_data, 16);
417 SIO_SET(VR_MIICMD_CLK);
419 SIO_CLR(VR_MIICMD_CLK);
423 SIO_CLR(VR_MIICMD_DIR);
431 /* Set the PHY-adress */
432 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
435 /* Set the register address and data to write. */
436 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
437 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
439 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
441 for (i = 0; i < 10000; i++) {
442 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
451 vr_miibus_readreg(device_t dev, int phy, int reg)
453 struct vr_mii_frame frame;
456 sc = device_get_softc(dev);
458 switch (sc->vr_revid) {
459 case REV_ID_VT6102_APOLLO:
467 bzero(&frame, sizeof(frame));
469 frame.mii_phyaddr = phy;
470 frame.mii_regaddr = reg;
471 vr_mii_readreg(sc, &frame);
473 return(frame.mii_data);
477 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
479 struct vr_mii_frame frame;
482 sc = device_get_softc(dev);
484 switch (sc->vr_revid) {
485 case REV_ID_VT6102_APOLLO:
493 bzero(&frame, sizeof(frame));
495 frame.mii_phyaddr = phy;
496 frame.mii_regaddr = reg;
497 frame.mii_data = data;
499 vr_mii_writereg(sc, &frame);
505 vr_miibus_statchg(device_t dev)
507 struct mii_data *mii;
510 sc = device_get_softc(dev);
511 mii = device_get_softc(sc->vr_miibus);
512 vr_setcfg(sc, mii->mii_media_active);
516 * Program the 64-bit multicast hash filter.
519 vr_setmulti(struct vr_softc *sc)
522 uint32_t hashes[2] = { 0, 0 };
523 struct ifmultiaddr *ifma;
527 ifp = &sc->arpcom.ac_if;
529 rxfilt = CSR_READ_1(sc, VR_RXCFG);
531 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
532 rxfilt |= VR_RXCFG_RX_MULTI;
533 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
534 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
535 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
539 /* First, zero out all the existing hash bits. */
540 CSR_WRITE_4(sc, VR_MAR0, 0);
541 CSR_WRITE_4(sc, VR_MAR1, 0);
543 /* Now program new ones. */
544 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
547 if (ifma->ifma_addr->sa_family != AF_LINK)
550 /* use the lower 6 bits */
552 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
553 ETHER_ADDR_LEN) >> 26) & 0x0000003F;
555 hashes[0] |= (1 << h);
557 hashes[1] |= (1 << (h - 32));
562 rxfilt |= VR_RXCFG_RX_MULTI;
564 rxfilt &= ~VR_RXCFG_RX_MULTI;
566 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
567 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
568 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
572 * In order to fiddle with the
573 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
574 * first have to put the transmit and/or receive logic in the idle state.
577 vr_setcfg(struct vr_softc *sc, int media)
581 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
583 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
586 if ((media & IFM_GMASK) == IFM_FDX)
587 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
589 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
592 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
596 vr_reset(struct vr_softc *sc)
600 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
602 for (i = 0; i < VR_TIMEOUT; i++) {
604 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
607 if (i == VR_TIMEOUT) {
608 struct ifnet *ifp = &sc->arpcom.ac_if;
610 if (sc->vr_revid < REV_ID_VT3065_A) {
611 if_printf(ifp, "reset never completed!\n");
613 /* Use newer force reset command */
614 if_printf(ifp, "Using force reset command.\n");
615 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
619 /* Wait a little while for the chip to get its brains in order. */
624 * Probe for a VIA Rhine chip. Check the PCI vendor and device
625 * IDs against our list and return a device name if we find a match.
628 vr_probe(device_t dev)
633 vid = pci_get_vendor(dev);
634 did = pci_get_device(dev);
636 for (t = vr_devs; t->vr_name != NULL; ++t) {
637 if (vid == t->vr_vid && did == t->vr_did) {
638 device_set_desc(dev, t->vr_name);
647 * Attach the interface. Allocate softc structures, do ifmedia
648 * setup and ethernet/BPF attach.
651 vr_attach(device_t dev)
654 uint8_t eaddr[ETHER_ADDR_LEN];
659 sc = device_get_softc(dev);
660 callout_init(&sc->vr_stat_timer);
663 * Handle power management nonsense.
665 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
666 uint32_t iobase, membase, irq;
668 /* Save important PCI config data. */
669 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
670 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
671 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
673 /* Reset the power state. */
674 device_printf(dev, "chip is in D%d power mode "
675 "-- setting to D0\n", pci_get_powerstate(dev));
676 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
678 /* Restore PCI config data. */
679 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
680 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
681 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
684 pci_enable_busmaster(dev);
686 sc->vr_revid = pci_get_revid(dev);
689 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE);
691 if (sc->vr_res == NULL) {
692 device_printf(dev, "couldn't map ports/memory\n");
696 sc->vr_btag = rman_get_bustag(sc->vr_res);
697 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
699 /* Allocate interrupt */
701 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
702 RF_SHAREABLE | RF_ACTIVE);
704 if (sc->vr_irq == NULL) {
705 device_printf(dev, "couldn't map interrupt\n");
711 * Windows may put the chip in suspend mode when it
712 * shuts down. Be sure to kick it in the head to wake it
715 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
717 ifp = &sc->arpcom.ac_if;
718 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
720 /* Reset the adapter. */
724 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
725 * initialization and disable AUTOPOLL.
727 pci_write_config(dev, VR_PCI_MODE,
728 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4);
729 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
732 * Get station address. The way the Rhine chips work,
733 * you're not allowed to directly access the EEPROM once
734 * they've been programmed a special way. Consequently,
735 * we need to read the node address from the PAR0 and PAR1
738 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
740 for (i = 0; i < ETHER_ADDR_LEN; i++)
741 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
743 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
744 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
746 if (sc->vr_ldata == NULL) {
747 device_printf(dev, "no memory for list buffers!\n");
752 /* Initialize TX buffer */
753 sc->vr_cdata.vr_tx_buf = contigmalloc(VR_TX_BUF_SIZE, M_DEVBUF,
754 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
755 if (sc->vr_cdata.vr_tx_buf == NULL) {
756 device_printf(dev, "can't allocate tx buffer!\n");
761 /* Set various TX indexes to invalid value */
762 sc->vr_cdata.vr_tx_free_idx = -1;
763 sc->vr_cdata.vr_tx_tail_idx = -1;
764 sc->vr_cdata.vr_tx_head_idx = -1;
768 ifp->if_mtu = ETHERMTU;
769 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
770 ifp->if_ioctl = vr_ioctl;
771 ifp->if_start = vr_start;
772 #ifdef DEVICE_POLLING
773 ifp->if_poll = vr_poll;
775 ifp->if_watchdog = vr_watchdog;
776 ifp->if_init = vr_init;
777 ifp->if_baudrate = 10000000;
778 ifq_set_maxlen(&ifp->if_snd, VR_TX_LIST_CNT - 1);
779 ifq_set_ready(&ifp->if_snd);
784 if (mii_phy_probe(dev, &sc->vr_miibus,
785 vr_ifmedia_upd, vr_ifmedia_sts)) {
786 if_printf(ifp, "MII without any phy!\n");
791 /* Call MI attach routine. */
792 ether_ifattach(ifp, eaddr, NULL);
794 error = bus_setup_intr(dev, sc->vr_irq, INTR_NETSAFE,
795 vr_intr, sc, &sc->vr_intrhand,
799 device_printf(dev, "couldn't set up irq\n");
811 vr_detach(device_t dev)
813 struct vr_softc *sc = device_get_softc(dev);
814 struct ifnet *ifp = &sc->arpcom.ac_if;
816 if (device_is_attached(dev)) {
817 lwkt_serialize_enter(ifp->if_serializer);
819 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
820 lwkt_serialize_exit(ifp->if_serializer);
824 if (sc->vr_miibus != NULL)
825 device_delete_child(dev, sc->vr_miibus);
826 bus_generic_detach(dev);
828 if (sc->vr_irq != NULL)
829 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
830 if (sc->vr_res != NULL)
831 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
832 if (sc->vr_ldata != NULL)
833 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
834 if (sc->vr_cdata.vr_tx_buf != NULL)
835 contigfree(sc->vr_cdata.vr_tx_buf, VR_TX_BUF_SIZE, M_DEVBUF);
841 * Initialize the transmit descriptors.
844 vr_list_tx_init(struct vr_softc *sc)
846 struct vr_chain_data *cd;
847 struct vr_list_data *ld;
848 struct vr_chain *tx_chain;
853 tx_chain = cd->vr_tx_chain;
855 for (i = 0; i < VR_TX_LIST_CNT; i++) {
856 tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
857 if (i == (VR_TX_LIST_CNT - 1))
858 tx_chain[i].vr_next_idx = 0;
860 tx_chain[i].vr_next_idx = i + 1;
863 for (i = 0; i < VR_TX_LIST_CNT; ++i) {
867 tx_buf = VR_TX_BUF(sc, i);
868 next_idx = tx_chain[i].vr_next_idx;
870 tx_chain[i].vr_next_desc_paddr =
871 vtophys(tx_chain[next_idx].vr_ptr);
872 tx_chain[i].vr_buf_paddr = vtophys(tx_buf);
875 cd->vr_tx_free_idx = 0;
876 cd->vr_tx_tail_idx = cd->vr_tx_head_idx = -1;
883 * Initialize the RX descriptors and allocate mbufs for them. Note that
884 * we arrange the descriptors in a closed ring, so that the last descriptor
885 * points back to the first.
888 vr_list_rx_init(struct vr_softc *sc)
890 struct vr_chain_data *cd;
891 struct vr_list_data *ld;
897 for (i = 0; i < VR_RX_LIST_CNT; i++) {
898 cd->vr_rx_chain[i].vr_ptr = (struct vr_desc *)&ld->vr_rx_list[i];
899 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
901 if (i == (VR_RX_LIST_CNT - 1))
905 cd->vr_rx_chain[i].vr_nextdesc = &cd->vr_rx_chain[nexti];
906 ld->vr_rx_list[i].vr_next = vtophys(&ld->vr_rx_list[nexti]);
909 cd->vr_rx_head = &cd->vr_rx_chain[0];
915 * Initialize an RX descriptor and attach an MBUF cluster.
916 * Note: the length fields are only 11 bits wide, which means the
917 * largest size we can specify is 2047. This is important because
918 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
919 * overflow the field and make a mess.
922 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m)
924 struct mbuf *m_new = NULL;
927 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
930 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
933 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
934 m_new->m_data = m_new->m_ext.ext_buf;
937 m_adj(m_new, sizeof(uint64_t));
940 c->vr_ptr->vr_status = VR_RXSTAT;
941 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
942 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
948 * A frame has been uploaded: pass the resulting mbuf chain up to
949 * the higher level protocols.
952 vr_rxeof(struct vr_softc *sc)
956 struct vr_chain_onefrag *cur_rx;
960 ifp = &sc->arpcom.ac_if;
962 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
964 struct mbuf *m0 = NULL;
966 cur_rx = sc->vr_cdata.vr_rx_head;
967 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
971 * If an error occurs, update stats, clear the
972 * status word and leave the mbuf cluster in place:
973 * it should simply get re-used next time this descriptor
974 * comes up in the ring.
976 if (rxstat & VR_RXSTAT_RXERR) {
978 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff);
979 if (rxstat & VR_RXSTAT_CRCERR)
980 printf(" crc error");
981 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
982 printf(" frame alignment error\n");
983 if (rxstat & VR_RXSTAT_FIFOOFLOW)
984 printf(" FIFO overflow");
985 if (rxstat & VR_RXSTAT_GIANT)
986 printf(" received giant packet");
987 if (rxstat & VR_RXSTAT_RUNT)
988 printf(" received runt packet");
989 if (rxstat & VR_RXSTAT_BUSERR)
990 printf(" system bus error");
991 if (rxstat & VR_RXSTAT_BUFFERR)
992 printf("rx buffer error");
994 vr_newbuf(sc, cur_rx, m);
998 /* No errors; receive the packet. */
999 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1002 * XXX The VIA Rhine chip includes the CRC with every
1003 * received frame, and there's no way to turn this
1004 * behavior off (at least, I can't find anything in
1005 * the manual that explains how to do it) so we have
1006 * to trim off the CRC manually.
1008 total_len -= ETHER_CRC_LEN;
1010 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1011 total_len + ETHER_ALIGN, 0, ifp, NULL);
1012 vr_newbuf(sc, cur_rx, m);
1017 m_adj(m0, ETHER_ALIGN);
1021 ifp->if_input(ifp, m);
1026 vr_rxeoc(struct vr_softc *sc)
1031 ifp = &sc->arpcom.ac_if;
1035 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1038 /* Wait for receiver to stop */
1040 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1042 ; /* Wait for receiver to stop */
1045 if_printf(ifp, "rx shutdown error!\n");
1046 sc->vr_flags |= VR_F_RESTART;
1052 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1053 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1054 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1058 * A frame was downloaded to the chip. It's safe for us to clean up
1062 vr_txeof(struct vr_softc *sc)
1064 struct vr_chain_data *cd;
1065 struct vr_chain *tx_chain;
1068 ifp = &sc->arpcom.ac_if;
1071 /* Reset the timeout timer; if_txeoc will clear it. */
1075 if (cd->vr_tx_head_idx == -1)
1078 tx_chain = cd->vr_tx_chain;
1081 * Go through our tx list and free mbufs for those
1082 * frames that have been transmitted.
1084 while(tx_chain[cd->vr_tx_head_idx].vr_buf != NULL) {
1085 struct vr_chain *cur_tx;
1089 cur_tx = &tx_chain[cd->vr_tx_head_idx];
1090 txstat = cur_tx->vr_ptr->vr_status;
1092 if ((txstat & VR_TXSTAT_ABRT) ||
1093 (txstat & VR_TXSTAT_UDF)) {
1095 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1097 ; /* Wait for chip to shutdown */
1099 if_printf(ifp, "tx shutdown timeout\n");
1100 sc->vr_flags |= VR_F_RESTART;
1103 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1104 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr));
1108 if (txstat & VR_TXSTAT_OWN)
1111 if (txstat & VR_TXSTAT_ERRSUM) {
1113 if (txstat & VR_TXSTAT_DEFER)
1114 ifp->if_collisions++;
1115 if (txstat & VR_TXSTAT_LATECOLL)
1116 ifp->if_collisions++;
1119 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3;
1122 cur_tx->vr_buf = NULL;
1124 if (cd->vr_tx_head_idx == cd->vr_tx_tail_idx) {
1125 cd->vr_tx_head_idx = -1;
1126 cd->vr_tx_tail_idx = -1;
1130 cd->vr_tx_head_idx = cur_tx->vr_next_idx;
1135 * TX 'end of channel' interrupt handler.
1138 vr_txeoc(struct vr_softc *sc)
1142 ifp = &sc->arpcom.ac_if;
1144 if (sc->vr_cdata.vr_tx_head_idx == -1) {
1145 ifp->if_flags &= ~IFF_OACTIVE;
1146 sc->vr_cdata.vr_tx_tail_idx = -1;
1154 struct vr_softc *sc = xsc;
1155 struct ifnet *ifp = &sc->arpcom.ac_if;
1156 struct mii_data *mii;
1158 lwkt_serialize_enter(ifp->if_serializer);
1160 if (sc->vr_flags & VR_F_RESTART) {
1161 if_printf(&sc->arpcom.ac_if, "restarting\n");
1165 sc->vr_flags &= ~VR_F_RESTART;
1168 mii = device_get_softc(sc->vr_miibus);
1171 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1173 lwkt_serialize_exit(ifp->if_serializer);
1179 struct vr_softc *sc;
1184 ifp = &sc->arpcom.ac_if;
1186 /* Supress unwanted interrupts. */
1187 if (!(ifp->if_flags & IFF_UP)) {
1192 /* Disable interrupts. */
1193 if ((ifp->if_flags & IFF_POLLING) == 0)
1194 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1197 status = CSR_READ_2(sc, VR_ISR);
1199 CSR_WRITE_2(sc, VR_ISR, status);
1201 if ((status & VR_INTRS) == 0)
1204 if (status & VR_ISR_RX_OK)
1207 if (status & VR_ISR_RX_DROPPED) {
1208 if_printf(ifp, "rx packet lost\n");
1212 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1213 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1214 if_printf(ifp, "receive error (%04x)", status);
1215 if (status & VR_ISR_RX_NOBUF)
1216 printf(" no buffers");
1217 if (status & VR_ISR_RX_OFLOW)
1218 printf(" overflow");
1219 if (status & VR_ISR_RX_DROPPED)
1220 printf(" packet lost");
1225 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1231 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1232 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1234 if ((status & VR_ISR_UDFI) ||
1235 (status & VR_ISR_TX_ABRT2) ||
1236 (status & VR_ISR_TX_ABRT)) {
1238 if (sc->vr_cdata.vr_tx_head_idx != -1) {
1239 VR_SETBIT16(sc, VR_COMMAND,
1241 VR_SETBIT16(sc, VR_COMMAND,
1251 /* Re-enable interrupts. */
1252 if ((ifp->if_flags & IFF_POLLING) == 0)
1253 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1255 if (!ifq_is_empty(&ifp->if_snd))
1260 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1261 * pointers to the fragment pointers.
1264 vr_encap(struct vr_softc *sc, int chain_idx, struct mbuf *m_head)
1271 KASSERT(chain_idx >= 0 && chain_idx < VR_TX_LIST_CNT,
1272 ("%s: chain idx(%d) out of range 0-%d",
1273 sc->arpcom.ac_if.if_xname, chain_idx, VR_TX_LIST_CNT));
1276 * The VIA Rhine wants packet buffers to be longword
1277 * aligned, but very often our mbufs aren't. Rather than
1278 * waste time trying to decide when to copy and when not
1279 * to copy, just do it all the time.
1281 tx_buf = VR_TX_BUF(sc, chain_idx);
1282 m_copydata(m_head, 0, m_head->m_pkthdr.len, tx_buf);
1283 len = m_head->m_pkthdr.len;
1286 * The Rhine chip doesn't auto-pad, so we have to make
1287 * sure to pad short frames out to the minimum frame length
1290 if (len < VR_MIN_FRAMELEN) {
1291 bzero(tx_buf + len, VR_MIN_FRAMELEN - len);
1292 len = VR_MIN_FRAMELEN;
1295 c = &sc->vr_cdata.vr_tx_chain[chain_idx];
1299 f->vr_data = c->vr_buf_paddr;
1301 f->vr_ctl |= (VR_TXCTL_TLINK | VR_TXCTL_FIRSTFRAG);
1302 f->vr_ctl |= (VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
1304 f->vr_next = c->vr_next_desc_paddr;
1310 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1311 * to the mbuf data regions directly in the transmit lists. We also save a
1312 * copy of the pointers since the transmit list fragment pointers are
1313 * physical addresses.
1316 vr_start(struct ifnet *ifp)
1318 struct vr_softc *sc;
1319 struct vr_chain_data *cd;
1320 struct vr_chain *tx_chain;
1321 int cur_tx_idx, start_tx_idx, prev_tx_idx;
1323 if (ifp->if_flags & IFF_OACTIVE)
1328 tx_chain = cd->vr_tx_chain;
1330 start_tx_idx = cd->vr_tx_free_idx;
1331 cur_tx_idx = prev_tx_idx = -1;
1333 /* Check for an available queue slot. If there are none, punt. */
1334 if (tx_chain[start_tx_idx].vr_buf != NULL) {
1335 ifp->if_flags |= IFF_OACTIVE;
1339 while(tx_chain[cd->vr_tx_free_idx].vr_buf == NULL) {
1340 struct mbuf *m_head;
1341 struct vr_chain *cur_tx;
1343 m_head = ifq_poll(&ifp->if_snd);
1347 /* Pick a descriptor off the free list. */
1348 cur_tx_idx = cd->vr_tx_free_idx;
1349 cur_tx = &tx_chain[cur_tx_idx];
1351 /* Pack the data into the descriptor. */
1352 if (vr_encap(sc, cur_tx_idx, m_head)) {
1353 ifp->if_flags |= IFF_OACTIVE;
1354 cur_tx_idx = prev_tx_idx;
1358 ifq_dequeue(&ifp->if_snd, m_head);
1361 if (cur_tx_idx != start_tx_idx)
1362 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1364 BPF_MTAP(ifp, m_head);
1367 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1368 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1370 /* Iff everything went OK, we bump up free index. */
1371 prev_tx_idx = cur_tx_idx;
1372 cd->vr_tx_free_idx = cur_tx->vr_next_idx;
1375 /* If there are no frames queued, bail. */
1376 if (cur_tx_idx == -1)
1379 sc->vr_cdata.vr_tx_tail_idx = cur_tx_idx;
1381 if (sc->vr_cdata.vr_tx_head_idx == -1)
1382 sc->vr_cdata.vr_tx_head_idx = start_tx_idx;
1385 * Set a timeout in case the chip goes out to lunch.
1393 struct vr_softc *sc = xsc;
1394 struct ifnet *ifp = &sc->arpcom.ac_if;
1395 struct mii_data *mii;
1398 mii = device_get_softc(sc->vr_miibus);
1400 /* Cancel pending I/O and free all RX/TX buffers. */
1404 /* Set our station address. */
1405 for (i = 0; i < ETHER_ADDR_LEN; i++)
1406 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1409 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1410 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1413 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1414 * so we must set both.
1416 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1417 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1419 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1420 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1422 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1423 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1425 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1426 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1428 /* Init circular RX list. */
1429 if (vr_list_rx_init(sc) == ENOBUFS) {
1431 if_printf(ifp, "initialization failed: no memory for rx buffers\n");
1435 /* Init tx descriptors. */
1436 vr_list_tx_init(sc);
1438 /* If we want promiscuous mode, set the allframes bit. */
1439 if (ifp->if_flags & IFF_PROMISC)
1440 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1442 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1444 /* Set capture broadcast bit to capture broadcast frames. */
1445 if (ifp->if_flags & IFF_BROADCAST)
1446 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1448 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1451 * Program the multicast filter, if necessary.
1456 * Load the address of the RX list.
1458 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1460 /* Enable receiver and transmitter. */
1461 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1462 VR_CMD_TX_ON|VR_CMD_RX_ON|
1465 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1468 * Enable interrupts, unless we are polling.
1470 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1471 if ((ifp->if_flags & IFF_POLLING) == 0)
1472 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1476 ifp->if_flags |= IFF_RUNNING;
1477 ifp->if_flags &= ~IFF_OACTIVE;
1479 callout_reset(&sc->vr_stat_timer, hz, vr_tick, sc);
1483 * Set media options.
1486 vr_ifmedia_upd(struct ifnet *ifp)
1488 struct vr_softc *sc;
1492 if (ifp->if_flags & IFF_UP)
1499 * Report current media status.
1502 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1504 struct vr_softc *sc;
1505 struct mii_data *mii;
1508 mii = device_get_softc(sc->vr_miibus);
1510 ifmr->ifm_active = mii->mii_media_active;
1511 ifmr->ifm_status = mii->mii_media_status;
1515 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1517 struct vr_softc *sc = ifp->if_softc;
1518 struct ifreq *ifr = (struct ifreq *) data;
1519 struct mii_data *mii;
1524 if (ifp->if_flags & IFF_UP) {
1527 if (ifp->if_flags & IFF_RUNNING)
1539 mii = device_get_softc(sc->vr_miibus);
1540 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1543 error = ether_ioctl(ifp, command, data);
1549 #ifdef DEVICE_POLLING
1552 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1554 struct vr_softc *sc = ifp->if_softc;
1558 /* disable interrupts */
1559 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1561 case POLL_DEREGISTER:
1562 /* enable interrupts */
1563 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1573 vr_watchdog(struct ifnet *ifp)
1575 struct vr_softc *sc;
1580 if_printf(ifp, "watchdog timeout\n");
1582 #ifdef DEVICE_POLLING
1583 if (++sc->vr_wdogerrors == 1 && (ifp->if_flags & IFF_POLLING) == 0) {
1584 if_printf(ifp, "ints don't seem to be working, "
1585 "emergency switch to polling\n");
1586 emergency_poll_enable("if_vr");
1587 ether_poll_register(ifp); /* XXX illegal */
1596 if (!ifq_is_empty(&ifp->if_snd))
1601 * Stop the adapter and free any mbufs allocated to the
1605 vr_stop(struct vr_softc *sc)
1610 ifp = &sc->arpcom.ac_if;
1613 callout_stop(&sc->vr_stat_timer);
1615 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1616 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1617 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1618 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1619 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1622 * Free data in the RX lists.
1624 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1625 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1626 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1627 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1630 bzero(&sc->vr_ldata->vr_rx_list, sizeof(sc->vr_ldata->vr_rx_list));
1633 * Reset the TX list buffer pointers.
1635 for (i = 0; i < VR_TX_LIST_CNT; i++)
1636 sc->vr_cdata.vr_tx_chain[i].vr_buf = NULL;
1638 bzero(&sc->vr_ldata->vr_tx_list, sizeof(sc->vr_ldata->vr_tx_list));
1640 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1644 * Stop all chip I/O so that the kernel's probe routines don't
1645 * get confused by errant DMAs when rebooting.
1648 vr_shutdown(device_t dev)
1650 struct vr_softc *sc;
1652 sc = device_get_softc(dev);