sys/dev/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "intel_drv.h"
  29
  30 #include <linux/highmem.h>
  31
  32 typedef uint32_t gtt_pte_t;
  33
  34 /* PPGTT stuff */
  35 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  36
  37 #define GEN6_PDE_VALID                  (1 << 0)
  38 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  39 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  40
  41 #define GEN6_PTE_VALID                  (1 << 0)
  42 #define GEN6_PTE_UNCACHED               (1 << 1)
  43 #define HSW_PTE_UNCACHED                (0)
  44 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  45 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  46 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  47
  48 static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  49                                         dma_addr_t addr,
  50                                         enum i915_cache_level level)
  51 {
  52         gtt_pte_t pte = GEN6_PTE_VALID;
  53         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  54
  55         switch (level) {
  56         case I915_CACHE_LLC_MLC:
  57                 /* Haswell doesn't set L3 this way */
  58                 if (IS_HASWELL(dev))
  59                         pte |= GEN6_PTE_CACHE_LLC;
  60                 else
  61                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  62                 break;
  63         case I915_CACHE_LLC:
  64                 pte |= GEN6_PTE_CACHE_LLC;
  65                 break;
  66         case I915_CACHE_NONE:
  67                 if (IS_HASWELL(dev))
  68                         pte |= HSW_PTE_UNCACHED;
  69                 else
  70                         pte |= GEN6_PTE_UNCACHED;
  71                 break;
  72         default:
  73                 BUG();
  74         }
  75
  76
  77         return pte;
  78 }
  79
  80 /* PPGTT support for Sandybdrige/Gen6 and later */
  81 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
  82                                    unsigned first_entry,
  83                                    unsigned num_entries)
  84 {
  85         gtt_pte_t *pt_vaddr;
  86         gtt_pte_t scratch_pte;
  87         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
  88         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
  89         unsigned last_pte, i;
  90
  91         scratch_pte = gen6_pte_encode(ppgtt->dev,
  92                                       ppgtt->scratch_page_dma_addr,
  93                                       I915_CACHE_LLC);
  94
  95         while (num_entries) {
  96                 last_pte = first_pte + num_entries;
  97                 if (last_pte > I915_PPGTT_PT_ENTRIES)
  98                         last_pte = I915_PPGTT_PT_ENTRIES;
  99
 100                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
 101
 102                 for (i = first_pte; i < last_pte; i++)
 103                         pt_vaddr[i] = scratch_pte;
 104
 105                 kunmap_atomic(pt_vaddr);
 106
 107                 num_entries -= last_pte - first_pte;
 108                 first_pte = 0;
 109                 act_pd++;
 110         }
 111 }
 112
 113 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 114                                       struct sg_table *pages,
 115                                       unsigned first_entry,
 116                                       enum i915_cache_level cache_level)
 117 {
 118         gtt_pte_t *pt_vaddr;
 119         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
 120         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 121         unsigned i, j, m, segment_len;
 122         dma_addr_t page_addr;
 123         struct scatterlist *sg;
 124
 125         /* init sg walking */
 126         sg = pages->sgl;
 127         i = 0;
 128         segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
 129         m = 0;
 130
 131         while (i < pages->nents) {
 132                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
 133
 134                 for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
 135                         page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 136                         pt_vaddr[j] = gen6_pte_encode(ppgtt->dev, page_addr,
 137                                                       cache_level);
 138
 139                         /* grab the next page */
 140                         if (++m == segment_len) {
 141                                 if (++i == pages->nents)
 142                                         break;
 143
 144                                 sg = sg_next(sg);
 145                                 segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
 146                                 m = 0;
 147                         }
 148                 }
 149
 150                 kunmap_atomic(pt_vaddr);
 151
 152                 first_pte = 0;
 153                 act_pd++;
 154         }
 155 }
 156
 157 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 158 {
 159 #if 0
 160         int i;
 161
 162         if (ppgtt->pt_dma_addr) {
 163                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 164                         pci_unmap_page(ppgtt->dev->pdev,
 165                                        ppgtt->pt_dma_addr[i],
 166                                        4096, PCI_DMA_BIDIRECTIONAL);
 167         }
 168
 169         kfree(ppgtt->pt_dma_addr);
 170         for (i = 0; i < ppgtt->num_pd_entries; i++)
 171                 __free_page(ppgtt->pt_pages[i]);
 172         kfree(ppgtt->pt_pages);
 173         kfree(ppgtt);
 174 #endif
 175 }
 176
 177 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 178 {
 179         struct drm_device *dev = ppgtt->dev;
 180         struct drm_i915_private *dev_priv = dev->dev_private;
 181         unsigned first_pd_entry_in_global_pt;
 182         int i;
 183         int ret = -ENOMEM;
 184
 185         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 186          * entries. For aliasing ppgtt support we just steal them at the end for
 187          * now.
 188          */
 189         first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
 190
 191         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 192         ppgtt->clear_range = gen6_ppgtt_clear_range;
 193         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 194         ppgtt->cleanup = gen6_ppgtt_cleanup;
 195         ppgtt->pt_pages = kmalloc(sizeof(vm_page_t) * ppgtt->num_pd_entries,
 196             M_DRM, M_WAITOK | M_ZERO);
 197         if (!ppgtt->pt_pages)
 198                 return -ENOMEM;
 199
 200         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 201                 ppgtt->pt_pages[i] = vm_page_alloc(NULL, 0,
 202                     VM_ALLOC_NORMAL | VM_ALLOC_ZERO);
 203                 if (!ppgtt->pt_pages[i])
 204                         goto err_pt_alloc;
 205         }
 206
 207         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 208
 209         ppgtt->clear_range(ppgtt, 0,
 210                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 211
 212         ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
 213
 214         return 0;
 215
 216 err_pt_alloc:
 217         dev_priv->mm.aliasing_ppgtt = ppgtt;
 218         i915_gem_cleanup_aliasing_ppgtt(dev);
 219
 220         return ret;
 221 }
 222
 223 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 224 {
 225         struct drm_i915_private *dev_priv = dev->dev_private;
 226         struct i915_hw_ppgtt *ppgtt;
 227         int ret;
 228
 229         ppgtt = kmalloc(sizeof(*ppgtt), M_DRM, M_WAITOK | M_ZERO);
 230         if (!ppgtt)
 231                 return -ENOMEM;
 232
 233         ppgtt->dev = dev;
 234
 235         ret = gen6_ppgtt_init(ppgtt);
 236         if (ret)
 237                 kfree(ppgtt, M_DRM);
 238         else
 239                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 240
 241         return ret;
 242 }
 243
 244 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 245 {
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 248
 249         if (!ppgtt)
 250                 return;
 251
 252         ppgtt->cleanup(ppgtt);
 253 }
 254
 255 #if 0
 256 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 257 {
 258         struct drm_i915_private *dev_priv = dev->dev_private;
 259         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 260         vm_page_t m;
 261         int i;
 262
 263         if (!ppgtt)
 264                 return;
 265         dev_priv->mm.aliasing_ppgtt = NULL;
 266
 267         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 268                 m = ppgtt->pt_pages[i];
 269                 if (m != NULL) {
 270                         vm_page_busy_wait(m, FALSE, "i915gem");
 271                         vm_page_unwire(m, 0);
 272                         vm_page_free(m);
 273                 }
 274         }
 275         drm_free(ppgtt->pt_pages, M_DRM);
 276         drm_free(ppgtt, M_DRM);
 277 }
 278 #endif
 279
 280 static void
 281 i915_ppgtt_insert_pages(struct i915_hw_ppgtt *ppgtt, unsigned first_entry,
 282     unsigned num_entries, vm_page_t *pages, enum i915_cache_level cache_level)
 283 {
 284         uint32_t *pt_vaddr;
 285         unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
 286         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 287         unsigned last_pte, i;
 288         dma_addr_t page_addr;
 289
 290         while (num_entries) {
 291                 last_pte = first_pte + num_entries;
 292                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 293                         last_pte = I915_PPGTT_PT_ENTRIES;
 294
 295                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
 296
 297                 for (i = first_pte; i < last_pte; i++) {
 298                         page_addr = VM_PAGE_TO_PHYS(*pages);
 299                         pt_vaddr[i] = gen6_pte_encode(ppgtt->dev, page_addr,
 300                                                  cache_level);
 301
 302                         pages++;
 303                 }
 304
 305                 kunmap_atomic(pt_vaddr);
 306
 307                 num_entries -= last_pte - first_pte;
 308                 first_pte = 0;
 309                 act_pd++;
 310         }
 311 }
 312
 313 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 314                             struct drm_i915_gem_object *obj,
 315                             enum i915_cache_level cache_level)
 316 {
 317         i915_ppgtt_insert_pages(ppgtt, obj->gtt_space->start >> PAGE_SHIFT,
 318             obj->base.size >> PAGE_SHIFT, obj->pages, cache_level);
 319 }
 320
 321 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 322                               struct drm_i915_gem_object *obj)
 323 {
 324         ppgtt->clear_range(ppgtt,
 325                            obj->gtt_space->start >> PAGE_SHIFT,
 326                            obj->base.size >> PAGE_SHIFT);
 327 }
 328
 329 void i915_gem_init_ppgtt(struct drm_device *dev)
 330 {
 331         drm_i915_private_t *dev_priv = dev->dev_private;
 332         uint32_t pd_offset;
 333         struct intel_ring_buffer *ring;
 334         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 335         uint32_t pd_entry, first_pd_entry_in_global_pt;
 336         int i;
 337
 338         if (!dev_priv->mm.aliasing_ppgtt)
 339                 return;
 340
 341         first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
 342         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 343                 vm_paddr_t pt_addr;
 344
 345                 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
 346                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 347                 pd_entry |= GEN6_PDE_VALID;
 348
 349                 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
 350         }
 351         intel_gtt_read_pte(first_pd_entry_in_global_pt);
 352
 353         pd_offset = ppgtt->pd_offset;
 354         pd_offset /= 64; /* in cachelines, */
 355         pd_offset <<= 16;
 356
 357         if (INTEL_INFO(dev)->gen == 6) {
 358                 uint32_t ecochk, gab_ctl, ecobits;
 359
 360                 ecobits = I915_READ(GAC_ECO_BITS);
 361                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 362
 363                 gab_ctl = I915_READ(GAB_CTL);
 364                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 365
 366                 ecochk = I915_READ(GAM_ECOCHK);
 367                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 368                                        ECOCHK_PPGTT_CACHE64B);
 369                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 370         } else if (INTEL_INFO(dev)->gen >= 7) {
 371                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 372                 /* GFX_MODE is per-ring on gen7+ */
 373         }
 374
 375         for_each_ring(ring, dev_priv, i) {
 376                 if (INTEL_INFO(dev)->gen >= 7)
 377                         I915_WRITE(RING_MODE_GEN7(ring),
 378                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 379
 380                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 381                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 382         }
 383 }
 384
 385 extern int intel_iommu_gfx_mapped;
 386 /* Certain Gen5 chipsets require require idling the GPU before
 387  * unmapping anything from the GTT when VT-d is enabled.
 388  */
 389 static inline bool needs_idle_maps(struct drm_device *dev)
 390 {
 391 #ifdef CONFIG_INTEL_IOMMU
 392         /* Query intel_iommu to see if we need the workaround. Presumably that
 393          * was loaded first.
 394          */
 395         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 396                 return true;
 397 #endif
 398         return false;
 399 }
 400
 401 static bool do_idling(struct drm_i915_private *dev_priv)
 402 {
 403         bool ret = dev_priv->mm.interruptible;
 404
 405         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 406                 dev_priv->mm.interruptible = false;
 407                 if (i915_gpu_idle(dev_priv->dev)) {
 408                         DRM_ERROR("Couldn't idle GPU\n");
 409                         /* Wait a bit, in hopes it avoids the hang */
 410                         udelay(10);
 411                 }
 412         }
 413
 414         return ret;
 415 }
 416
 417 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 418 {
 419         if (unlikely(dev_priv->gtt.do_idle_maps))
 420                 dev_priv->mm.interruptible = interruptible;
 421 }
 422
 423 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 424 {
 425         struct drm_i915_private *dev_priv = dev->dev_private;
 426         struct drm_i915_gem_object *obj;
 427
 428         /* First fill our portion of the GTT with scratch pages */
 429         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 430                                       dev_priv->gtt.total / PAGE_SIZE);
 431
 432         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 433                 i915_gem_clflush_object(obj);
 434                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 435         }
 436
 437         i915_gem_chipset_flush(dev);
 438 }
 439
 440 #if 0
 441 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 442 {
 443         if (obj->has_dma_mapping)
 444                 return 0;
 445
 446         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 447                         obj->pages->sgl, obj->pages->nents,
 448                         PCI_DMA_BIDIRECTIONAL))
 449                 return -ENOSPC;
 450
 451         return 0;
 452 }
 453 #endif
 454
 455 /*
 456  * Binds an object into the global gtt with the specified cache level. The object
 457  * will be accessible to the GPU via commands whose operands reference offsets
 458  * within the global GTT as well as accessible by the GPU through the GMADR
 459  * mapped BAR (dev_priv->mm.gtt->gtt).
 460  */
 461 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 462                                      struct sg_table *st,
 463                                      unsigned int first_entry,
 464                                      enum i915_cache_level level)
 465 {
 466 #if 0
 467         struct drm_i915_private *dev_priv = dev->dev_private;
 468         struct scatterlist *sg = st->sgl;
 469         gtt_pte_t __iomem *gtt_entries =
 470                 (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 471         int unused, i = 0;
 472         unsigned int len, m = 0;
 473         dma_addr_t addr;
 474
 475         for_each_sg(st->sgl, sg, st->nents, unused) {
 476                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 477                 for (m = 0; m < len; m++) {
 478                         addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 479                         iowrite32(gen6_pte_encode(dev, addr, level),
 480                                   &gtt_entries[i]);
 481                         i++;
 482                 }
 483         }
 484
 485         /* XXX: This serves as a posting read to make sure that the PTE has
 486          * actually been updated. There is some concern that even though
 487          * registers and PTEs are within the same BAR that they are potentially
 488          * of NUMA access patterns. Therefore, even with the way we assume
 489          * hardware should work, we must keep this posting read for paranoia.
 490          */
 491         if (i != 0)
 492                 WARN_ON(readl(&gtt_entries[i-1])
 493                         != gen6_pte_encode(dev, addr, level));
 494
 495         /* This next bit makes the above posting read even more important. We
 496          * want to flush the TLBs only after we're certain all the PTE updates
 497          * have finished.
 498          */
 499         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 500         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 501 #endif
 502 }
 503
 504 static void gen6_ggtt_clear_range(struct drm_device *dev,
 505                                   unsigned int first_entry,
 506                                   unsigned int num_entries)
 507 {
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         gtt_pte_t scratch_pte;
 510         gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 511         const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
 512         int i;
 513
 514         if (WARN(num_entries > max_entries,
 515                  "First entry = %d; Num entries = %d (max=%d)\n",
 516                  first_entry, num_entries, max_entries))
 517                 num_entries = max_entries;
 518
 519         scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
 520                                       I915_CACHE_LLC);
 521         for (i = 0; i < num_entries; i++)
 522                 iowrite32(scratch_pte, &gtt_base[i]);
 523         readl(gtt_base);
 524 }
 525
 526 static void i915_ggtt_insert_entries(struct drm_device *dev,
 527                                      struct sg_table *st,
 528                                      unsigned int pg_start,
 529                                      enum i915_cache_level cache_level)
 530 {
 531 #if 0
 532         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 533                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 534
 535         intel_gtt_insert_sg_entries(st, pg_start, flags);
 536 #endif
 537 }
 538
 539 static void i915_ggtt_clear_range(struct drm_device *dev,
 540                                   unsigned int first_entry,
 541                                   unsigned int num_entries)
 542 {
 543         intel_gtt_clear_range(first_entry, num_entries);
 544 }
 545
 546 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 547                               enum i915_cache_level cache_level)
 548 {
 549         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 550                         AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 551         intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
 552             obj->base.size >> PAGE_SHIFT, obj->pages, flags);
 553
 554         obj->has_global_gtt_mapping = 1;
 555 }
 556
 557 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 558 {
 559         struct drm_device *dev = obj->base.dev;
 560         struct drm_i915_private *dev_priv = dev->dev_private;
 561
 562         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 563                                       obj->gtt_space->start >> PAGE_SHIFT,
 564                                       obj->base.size >> PAGE_SHIFT);
 565
 566         obj->has_global_gtt_mapping = 0;
 567 }
 568
 569 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 570 {
 571         struct drm_device *dev = obj->base.dev;
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573         bool interruptible;
 574
 575         interruptible = do_idling(dev_priv);
 576
 577 #if 0
 578         if (!obj->has_dma_mapping)
 579                 dma_unmap_sg(&dev->pdev->dev,
 580                              obj->pages->sgl, obj->pages->nents,
 581                              PCI_DMA_BIDIRECTIONAL);
 582 #endif
 583
 584         undo_idling(dev_priv, interruptible);
 585 }
 586
 587 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 588                                   unsigned long color,
 589                                   unsigned long *start,
 590                                   unsigned long *end)
 591 {
 592         if (node->color != color)
 593                 *start += 4096;
 594
 595         if (!list_empty(&node->node_list)) {
 596                 node = list_entry(node->node_list.next,
 597                                   struct drm_mm_node,
 598                                   node_list);
 599                 if (node->allocated && node->color != color)
 600                         *end -= 4096;
 601         }
 602 }
 603 void i915_gem_setup_global_gtt(struct drm_device *dev,
 604                                unsigned long start,
 605                                unsigned long mappable_end,
 606                                unsigned long end)
 607 {
 608         /* Let GEM Manage all of the aperture.
 609          *
 610          * However, leave one page at the end still bound to the scratch page.
 611          * There are a number of places where the hardware apparently prefetches
 612          * past the end of the object, and we've seen multiple hangs with the
 613          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 614          * aperture.  One page should be enough to keep any prefetching inside
 615          * of the aperture.
 616          */
 617         drm_i915_private_t *dev_priv = dev->dev_private;
 618         unsigned long mappable;
 619         int error;
 620
 621         BUG_ON(mappable_end > end);
 622
 623         mappable = min(end, mappable_end) - start;
 624
 625         /* Substract the guard page ... */
 626         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 627         if (!HAS_LLC(dev))
 628                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 629
 630         dev_priv->gtt.start = start;
 631         dev_priv->gtt.mappable_end = mappable_end;
 632         dev_priv->gtt.total = end - start;
 633
 634         /* ... but ensure that we clear the entire range. */
 635         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 636         device_printf(dev->dev,
 637             "taking over the fictitious range 0x%lx-0x%lx\n",
 638             dev->agp->base + start, dev->agp->base + start + mappable);
 639         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 640             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 641 }
 642
 643 static bool
 644 intel_enable_ppgtt(struct drm_device *dev)
 645 {
 646         if (i915_enable_ppgtt >= 0)
 647                 return i915_enable_ppgtt;
 648
 649 #ifdef CONFIG_INTEL_IOMMU
 650         /* Disable ppgtt on SNB if VT-d is on. */
 651         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 652                 return false;
 653 #endif
 654
 655         return true;
 656 }
 657
 658 void i915_gem_init_global_gtt(struct drm_device *dev)
 659 {
 660         struct drm_i915_private *dev_priv = dev->dev_private;
 661         unsigned long gtt_size, mappable_size;
 662         int ret;
 663
 664         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
 665         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 666
 667         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 668                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 669                  * aperture accordingly when using aliasing ppgtt. */
 670                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 671
 672                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 673
 674                 ret = i915_gem_init_aliasing_ppgtt(dev);
 675                 if (ret) {
 676                         DRM_UNLOCK(dev);
 677                         return;
 678                 }
 679         } else {
 680                 /* Let GEM Manage all of the aperture.
 681                  *
 682                  * However, leave one page at the end still bound to the scratch
 683                  * page.  There are a number of places where the hardware
 684                  * apparently prefetches past the end of the object, and we've
 685                  * seen multiple hangs with the GPU head pointer stuck in a
 686                  * batchbuffer bound at the last page of the aperture.  One page
 687                  * should be enough to keep any prefetching inside of the
 688                  * aperture.
 689                  */
 690                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 691         }
 692 }
 693
 694 int i915_gem_gtt_init(struct drm_device *dev)
 695 {
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697
 698         /* On modern platforms we need not worry ourself with the legacy
 699          * hostbridge query stuff. Skip it entirely
 700          */
 701         if (INTEL_INFO(dev)->gen < 6 || 1) {
 702                 dev_priv->mm.gtt = intel_gtt_get();
 703                 if (!dev_priv->mm.gtt) {
 704                         DRM_ERROR("Failed to initialize GTT\n");
 705                         return -ENODEV;
 706                 }
 707
 708                 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev);
 709
 710                 dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 711                 dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 712
 713                 return 0;
 714         }
 715
 716         dev_priv->mm.gtt = kmalloc(sizeof(*dev_priv->mm.gtt), M_DRM, M_WAITOK | M_ZERO);
 717         if (!dev_priv->mm.gtt)
 718                 return -ENOMEM;
 719
 720         /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
 721         DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);
 722         DRM_DEBUG_DRIVER("GMADR size = %dM\n", dev_priv->mm.gtt->gtt_mappable_entries >> 8);
 723         DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);
 724
 725         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 726         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 727
 728         return 0;
 729 }